阅读说明：本技术 半导体器件 (Semiconductor device with a plurality of transistors ) 是由 申乂苑 尹在璇 李昇埈 李钟旻 于 2021-02-02 设计创作，主要内容包括：一种半导体器件包括设置在衬底上的堆叠结构。该堆叠结构包括在与第一方向和第二方向交叉的第三方向上交替堆叠的多个绝缘层和多个电极层。多个沟道结构在第三方向上延伸穿过堆叠结构。第一布线组包括设置在堆叠结构上的多个第一水平布线,所述多个第一水平布线在第一方向上排列并在第二方向上延伸。第二布线组包括设置在堆叠结构上的多个第二水平布线,所述多个第二水平布线在第一方向上排列并在第二方向上延伸。所述多个第一水平布线和所述多个第二水平布线中的每个连接到所述多个沟道结构中的对应一个。第一线识别部设置在第一布线组与第二布线组之间。(A semiconductor device includes a stack structure disposed on a substrate. The stacked structure includes a plurality of insulating layers and a plurality of electrode layers alternately stacked in a third direction crossing the first direction and the second direction. A plurality of channel structures extend through the stacked structure in the third direction. The first wiring group includes a plurality of first horizontal wirings provided on the stacked structure, the plurality of first horizontal wirings being arranged in a first direction and extending in a second direction. The second wiring group includes a plurality of second horizontal wirings provided on the stacked structure, the plurality of second horizontal wirings being aligned in the first direction and extending in the second direction. Each of the plurality of first horizontal wirings and the plurality of second horizontal wirings is connected to a corresponding one of the plurality of channel structures. The first line recognition portion is disposed between the first wiring group and the second wiring group.)

1. A semiconductor device, comprising:

a stacked structure disposed on a substrate, the stacked structure including a plurality of insulating layers and a plurality of electrode layers;

a plurality of channel structures extending through the stacked structure;

a first wiring group including a plurality of first horizontal wirings disposed on the stacked structure, the plurality of first horizontal wirings being arranged in a first direction and extending in a second direction crossing the first direction, each of the plurality of first horizontal wirings being connected to a corresponding one of the plurality of channel structures;

a second wiring group including a plurality of second horizontal wirings disposed on the stacked structure, the plurality of second horizontal wirings being aligned in the first direction and extending in the second direction, each of the plurality of second horizontal wirings being connected to a corresponding one of the plurality of channel structures; and

a first wire identification section provided between the first wiring group and the second wiring group,

wherein the plurality of insulating layers and the plurality of electrode layers are alternately stacked in a third direction crossing the first direction and the second direction, and

wherein each of the plurality of channel structures extends in the third direction.

2. The semiconductor device according to claim 1, wherein the first line identification portion has a horizontal width different from a horizontal width of each of the plurality of first horizontal wirings and the plurality of second horizontal wirings.

3. The semiconductor device according to claim 1, wherein the first line identification portion has a horizontal width in a range of 2 to 20 times a horizontal width of each of the plurality of first horizontal wirings and the plurality of second horizontal wirings.

4. The semiconductor device according to claim 1, wherein the first line identification portion comprises a material which is the same as a material of each of the plurality of first horizontal wirings and the plurality of second horizontal wirings.

5. The semiconductor device according to claim 1, wherein the first line identification portion is insulated from the plurality of channel structures.

6. The semiconductor device according to claim 1, wherein the first line recognition portion is located only in a first overlap region provided between one of the plurality of first horizontal wirings which is closest to the first line recognition portion and one of the plurality of second horizontal wirings which is closest to the first line recognition portion.

7. The semiconductor device of claim 1, further comprising:

a page buffer disposed adjacent to the first wiring group and the second wiring group,

wherein the plurality of first horizontal wirings and the plurality of second horizontal wirings are connected to the page buffer, an

Wherein the first line recognition part is not connected to the page buffer.

8. The semiconductor device of claim 1, further comprising:

a lower horizontal wiring disposed between the substrate and the stacked structure; and

at least one dummy contact plug disposed between the first line recognition part and the lower horizontal wiring, the at least one dummy contact plug passing through the stack structure,

wherein the at least one dummy contact plug is configured to connect the first line recognition part to the lower horizontal wiring.

9. The semiconductor device of claim 1, further comprising:

a third wiring group including a plurality of third horizontal wirings provided on the substrate, the plurality of third horizontal wirings being arranged in the second direction and extending in the first direction, each of the plurality of third horizontal wirings being connected to a corresponding one of the plurality of electrode layers; and

a fourth wiring group including a plurality of fourth horizontal wirings disposed on the substrate,

wherein the plurality of fourth horizontal wirings are arranged in the second direction and extend in the first direction, each of the plurality of fourth horizontal wirings being connected to a corresponding one of the plurality of electrode layers.

10. The semiconductor device of claim 9, further comprising:

a row decoder disposed adjacent to the third wiring group and the fourth wiring group,

wherein the plurality of third horizontal wirings and the plurality of fourth horizontal wirings are connected to the row decoder.

11. The semiconductor device according to claim 10, further comprising a second line identification portion provided between the third wiring group and the fourth wiring group.

12. The semiconductor device according to claim 11, wherein the second line identification section is not connected to the row decoder.

13. The semiconductor device according to claim 11, wherein the second line identification portion has a horizontal width different from a horizontal width of each of the plurality of third horizontal wirings and the plurality of fourth horizontal wirings.

14. The semiconductor device according to claim 11, wherein the second line identification portion comprises a material which is the same as a material of each of the plurality of third horizontal wirings and the plurality of fourth horizontal wirings.

15. The semiconductor device according to claim 11, wherein the second line identification portion is insulated from the plurality of electrode layers.

16. The semiconductor device according to claim 11, wherein the second line recognition portion is located only in a second overlap region provided between one third horizontal wiring line among the plurality of third horizontal wiring lines that is closest to the second line recognition portion and one fourth horizontal wiring line among the plurality of fourth horizontal wiring lines that is closest to the second line recognition portion.

17. A semiconductor device, comprising:

a first wiring group including a plurality of first horizontal wirings provided on a substrate, the plurality of first horizontal wirings being arranged in a first direction and extending in a second direction crossing the first direction;

a second wiring group including a plurality of second horizontal wirings provided on the substrate, the plurality of second horizontal wirings being arranged in the first direction and extending in the second direction; and

a line recognition section provided between the first wiring group and the second wiring group,

wherein the line recognition portion is located in an overlap region provided between one first horizontal wiring line among the plurality of first horizontal wiring lines that is closest to the line recognition portion and one second horizontal wiring line among the plurality of second horizontal wiring lines that is closest to the line recognition portion.

18. The semiconductor device according to claim 17, wherein the line identification portion is located only in the overlap region.

19. The semiconductor device according to claim 17, wherein the line identification portion has a horizontal width different from a horizontal width of each of the plurality of first horizontal wirings and the plurality of second horizontal wirings.

20. A semiconductor device, comprising:

a source line disposed on the substrate;

a stacked structure including a plurality of insulating layers and a plurality of electrode layers disposed on the source line;

a plurality of channel structures passing through the stacked structure and contacting the source line;

a first wiring group including a plurality of first horizontal wirings disposed on the stacked structure, the plurality of first horizontal wirings being arranged in a first direction and extending in a second direction crossing the first direction, each of the plurality of first horizontal wirings being connected to a corresponding one of the plurality of channel structures;

a second wiring group including a plurality of second horizontal wirings disposed on the stacked structure, the plurality of second horizontal wirings being aligned in the first direction and extending in the second direction, each of the plurality of second horizontal wirings being connected to a corresponding one of the plurality of channel structures;

a first wire recognition unit provided between the first wiring group and the second wiring group;

a third wiring group including a plurality of third horizontal wirings provided on the substrate, the plurality of third horizontal wirings being arranged in the second direction and extending in the first direction, each of the plurality of third horizontal wirings being connected to a corresponding one of the plurality of electrode layers; and

a fourth wiring group including a plurality of fourth horizontal wirings provided on the substrate, the plurality of fourth horizontal wirings being arranged in the second direction and extending in the first direction, each of the plurality of fourth horizontal wirings being connected to a corresponding one of the plurality of electrode layers,

wherein the plurality of insulating layers and the plurality of electrode layers are alternately stacked in a third direction crossing the first direction and the second direction, and

wherein each of the plurality of channel structures extends in the third direction.

Technical Field

The present inventive concept relates to a semiconductor device including a line recognition part.

Background

A semiconductor device with high integration may include a plurality of wirings parallel to each other at the same height on a substrate. The increase in the number of wirings makes it difficult to check the position of one wiring selected from among the plurality of wirings. For example, it is difficult to accurately identify the position of one bit line selected from among a plurality of bit lines parallel to each other.

Disclosure of Invention

Exemplary embodiments of the inventive concepts provide a semiconductor device that provides relatively easy recognition of the position of each of a plurality of wirings parallel to each other.

A semiconductor device according to an exemplary embodiment of the inventive concept may include a stack structure disposed on a substrate. The stacked structure includes a plurality of insulating layers and a plurality of electrode layers. A plurality of channel structures extend through the stacked structure. The first wiring group includes a plurality of first horizontal wirings disposed on the stacked structure. The plurality of first horizontal wirings are arranged in a first direction and extend in a second direction intersecting the first direction. Each of the plurality of first horizontal wirings is connected to a corresponding one of the plurality of channel structures. The second wiring group includes a plurality of second horizontal wirings disposed on the stacked structure. The plurality of second horizontal wirings are arranged in the first direction and extend in the second direction. Each of the plurality of second horizontal wirings is connected to a corresponding one of the plurality of channel structures. The first line recognition portion is disposed between the first wiring group and the second wiring group. The plurality of insulating layers and the plurality of electrode layers are alternately stacked in a third direction crossing the first direction and the second direction. Each of the plurality of channel structures extends in a third direction.

A semiconductor device according to an exemplary embodiment of the inventive concept may include a first wiring group including a plurality of first horizontal wirings disposed on a substrate. The plurality of first horizontal wirings are arranged in a first direction and extend in a second direction intersecting the first direction. The second wiring group includes a plurality of second horizontal wirings provided on the substrate. The plurality of second horizontal wirings are arranged in the first direction and extend in the second direction. The line recognition portion is disposed between the first wiring group and the second wiring group. The line recognition portion is located in an overlap region provided between one of the plurality of first horizontal wirings which is closest to the line recognition portion and one of the plurality of second horizontal wirings which is closest to the line recognition portion.

A semiconductor device according to an exemplary embodiment of the inventive concept may include a source line disposed on a substrate. A stacked structure including a plurality of insulating layers and a plurality of electrode layers is disposed on the source line. A plurality of channel structures pass through the stacked structure and contact the source line. The first wiring group includes a plurality of first horizontal wirings disposed on the stacked structure. The plurality of first horizontal wirings are arranged in a first direction and extend in a second direction intersecting the first direction. Each of the plurality of first horizontal wirings is connected to a corresponding one of the plurality of channel structures. The second wiring group includes a plurality of second horizontal wirings disposed on the stacked structure. The plurality of second horizontal wirings are arranged in the first direction and extend in the second direction. Each of the plurality of second horizontal wirings is connected to a corresponding one of the plurality of channel structures. The first line recognition portion is disposed between the first wiring group and the second wiring group. The third wiring group includes a plurality of third horizontal wirings provided on the substrate. The plurality of third horizontal wirings are arranged in the second direction and extend in the first direction. Each of the plurality of third horizontal wirings is connected to a corresponding one of the plurality of electrode layers. The fourth wiring group includes a plurality of fourth horizontal wirings provided on the substrate. The plurality of fourth horizontal wirings are arranged in the second direction and extend in the first direction. Each of the plurality of fourth horizontal wirings is connected to a corresponding one of the plurality of electrode layers. The plurality of insulating layers and the plurality of electrode layers are alternately stacked in a third direction crossing the first direction and the second direction. Each of the plurality of channel structures extends in a third direction.

Drawings

Fig. 1 is a schematic view of a semiconductor device according to an exemplary embodiment of the inventive concept, showing a portion 8 of fig. 2.

Fig. 2 is a schematic view of a semiconductor device according to an exemplary embodiment of the inventive concept.

Fig. 3 to 8 are top views illustrating some elements of fig. 1 according to exemplary embodiments of the inventive concept.

Fig. 9 is a cross-sectional view of a semiconductor device according to an exemplary embodiment of the inventive concept, taken along line 1-1' of fig. 1.

Fig. 10 is a cross-sectional view of a semiconductor device according to an exemplary embodiment of the inventive concept, taken along line 2-2' of fig. 1.

Fig. 11 to 13 are partial views illustrating some elements of the semiconductor device of fig. 9 according to an exemplary embodiment of the inventive concept.

Fig. 14 to 16 are enlarged views respectively illustrating portions 36 to 38 of the semiconductor device of fig. 9 according to exemplary embodiments of the inventive concept.

Fig. 17 and 18 are sectional views of a semiconductor device according to an exemplary embodiment of the inventive concept.

Fig. 19 and 20 are schematic views of a semiconductor device according to an exemplary embodiment of the inventive concept.

Detailed Description

Fig. 1 and 2 are schematic views for describing a semiconductor device according to an exemplary embodiment of the inventive concept. Fig. 1 may be an enlarged view showing a portion 8 of fig. 2 in detail. Fig. 3 to 8 are plan views showing some elements of fig. 1. Fig. 9 is a sectional view taken along line 1-1 'of fig. 1 for describing a semiconductor device according to an exemplary embodiment of the inventive concept, and fig. 10 is a sectional view taken along line 2-2' of fig. 1. Fig. 11 to 13 are partial views showing some elements of fig. 9. Fig. 14 to 16 are enlarged views respectively showing a portion 36 to a portion 38 of fig. 9. Fig. 17 is a sectional view taken along line 3-3 'of fig. 1 for describing a semiconductor device according to an exemplary embodiment of the inventive concept, and fig. 18 is a sectional view taken along line 4-4' of fig. 1. A semiconductor device according to an exemplary embodiment of the inventive concept may include a three-dimensional (3D) flash memory, such as a vertical nand (vnand) flash memory.

Referring to fig. 1, a semiconductor device according to an exemplary embodiment of the inventive concept may include a page buffer 202, a column decoder 204, a row decoder 304, a first wiring group 211 including a plurality of first horizontal wirings B1, a second wiring group 212 including a plurality of second horizontal wirings B2, a plurality of first line recognition portions 255, a third wiring group 313 including a plurality of third horizontal wirings X3, a fourth wiring group 314 including a plurality of fourth horizontal wirings X4, and a plurality of second line recognition portions 356. In an exemplary embodiment, each of the plurality of first line recognition parts 255 and the plurality of second line recognition parts 356 may correspond to a counting pattern or a discriminator. Each of the plurality of first horizontal wirings B1 and the plurality of second horizontal wirings B2 may correspond to a bit line. For example, in an exemplary embodiment, each of the plurality of first line recognition parts 255 may be a bit line count pattern.

The plurality of first horizontal wiring lines B1 and the plurality of second horizontal wiring lines B2 may be disposed in parallel with each other. The plurality of first horizontal wirings B1 and the plurality of second horizontal wirings B2 may be arranged (e.g., spaced apart) in the first direction D1, and may each extend in the second direction D2 crossing the first direction D1. As shown in the exemplary embodiment of fig. 1, the second direction D2 may be perpendicular to the first direction D1. However, exemplary embodiments of the inventive concept are not limited thereto, and the second direction D2 may cross the first direction D1 at various angles.

In an exemplary embodiment, each of the plurality of first horizontal wirings Bl and the plurality of second horizontal wirings B2 may have substantially the same width (e.g., length in the first direction D1). In an exemplary embodiment, the first wiring group 211 may include the number of the first horizontal wirings B1 in the range of about 2 to about 10,000. For example, the first wiring group 211 may include about 2,000 first horizontal wirings B1. The second wiring group 212 may include the number of the second horizontal wirings B2 in the range of about 2 to about 10,000. For example, the second wiring group 212 may include about 2,000 second horizontal wirings B2.

One first line recognition part 255 selected from among the plurality of first line recognition parts 255 may be disposed (e.g., in the first direction D1) between the first wiring group 211 and the second wiring group 212. For example, one first line recognition part 255 selected from among the plurality of first line recognition parts 255 may be disposed (e.g., in the first direction D1) between the plurality of first horizontal wirings B1 and the plurality of second horizontal wirings B2. One first line recognition part 255 selected from among the plurality of first line recognition parts 255 may be disposed in a first overlap region disposed between one first horizontal wiring B1, which is the closest to the one first line recognition part 255, among the plurality of first horizontal wirings B1, and one second horizontal wiring B2, which is the closest to the one first line recognition part 255, among the plurality of second horizontal wirings B2. In an exemplary embodiment, one first line recognition part 255 selected from among the plurality of first line recognition parts 255 may be located only in the first overlap region, and may not protrude outside the first overlap region.

The first and second wiring groups 211 and 212 may be disposed adjacent to the page buffer 202 in the second direction D2. The page buffer 202 may be disposed adjacent to the column decoder 204 in the second direction D2. Each of the plurality of first horizontal wirings B1 and the plurality of second horizontal wirings B2 may be connected to the page buffer 202. As shown in the exemplary embodiment of fig. 1, the plurality of first line recognition parts 255 may not be connected to the page buffer 202.

The first and second wiring groups 211 and 212 may be disposed adjacent to the third and fourth wiring groups 313 and 314 in the first direction D1. The plurality of third horizontal wirings X3 and the plurality of fourth horizontal wirings X4 may be disposed in parallel with each other. The plurality of third horizontal wirings X3 and the plurality of fourth horizontal wirings X4 may be arranged (e.g., spaced apart) in the second direction D2. Each of the plurality of third horizontal wirings X3 and the plurality of fourth horizontal wirings X4 may extend in the first direction D1. In an exemplary embodiment, each of the plurality of third horizontal wirings X3 and the plurality of fourth horizontal wirings X4 may have substantially the same width (e.g., length in the second direction D2).

One second line identification part 356 selected from among the plurality of second line identification parts 356 may be disposed (e.g., in the second direction D2) between the third wiring group 313 and the fourth wiring group 314. For example, one second wire recognition part 356 selected from among the plurality of second wire recognition parts 356 may be disposed (e.g., in the second direction D2) between the plurality of third horizontal wirings X3 and the plurality of fourth horizontal wirings X4. One second line recognition part 356 selected from among the plurality of second line recognition parts 356 may be disposed in a second overlap region between one third horizontal wiring X3 closest to the one second line recognition part 356 among the plurality of third horizontal wirings X3 and one fourth horizontal wiring X4 closest to the one second line recognition part 356 among the plurality of fourth horizontal wirings X4. In an exemplary embodiment, one second line identification part 356 selected from among the plurality of second line identification parts 356 may be located only in the second overlap region, and may not protrude outside the second overlap region.

The third wiring group 313 and the fourth wiring group 314 may be disposed adjacent to the row decoder 304 in the first direction D1. Each of the plurality of third horizontal wirings X3 and the plurality of fourth horizontal wirings X4 may be connected to the row decoder 304. The plurality of second line identification parts 356 may not be connected to the row decoder 304.

Referring to fig. 2, a semiconductor device according to an exemplary embodiment of the inventive concept may include a memory cell array 100, a page buffer 202, a column decoder 204, and a row decoder 304. As shown in the exemplary embodiment of fig. 1, the first wiring group 211, the second wiring group 212, the third wiring group 313, and the fourth wiring group 314 may be disposed in the memory cell array 100.

As shown in the exemplary embodiment of fig. 1-2, the memory cell array 100 may be disposed adjacent to the row decoder 304 in the first direction Dl. The memory cell array 100 may be disposed adjacent to the column decoder 204 in the second direction D2. The page buffer 202 may be disposed (e.g., in the second direction D2) between the memory cell array 100 and the column decoder 204. In an exemplary embodiment, the column decoder 204 may correspond to a Y decoder. The page buffer 202 may include a plurality of sense amplifiers. The row decoder 304 may correspond to an X decoder or a word line decoder.

Referring to the exemplary embodiment of fig. 3 to 8, each of the plurality of first line identifications 255 and the plurality of second line identifications 356 may have a bar shape as shown in fig. 3, a shape including a plurality of blocks as shown in fig. 4, a shape including a combination of a bar shape and a plurality of empty spaces as shown in fig. 5, a shape including a plurality of blocks having a connection portion therebetween for connection as shown in fig. 6 and 7, a chain shape as shown in fig. 8, or various sizes and shapes such as a combination thereof.

Referring to fig. 9, the semiconductor device according to an exemplary embodiment of the inventive concept may include a substrate 51, a lower horizontal wiring 71, a connection electrode layer 73, a support portion 75, a stack structure 85, a plurality of channel structures 99, a first upper insulating layer 103, a second upper insulating layer 105, a third upper insulating layer 106, a plurality of bit plugs (bit plugs) 107, a plurality of first horizontal wirings B1, a plurality of second horizontal wirings B2, and a plurality of first line recognition portions 255. The stack structure 85 may include a plurality of electrode layers 81 and a plurality of insulating layers 83 alternately and repeatedly stacked.

The plurality of electrode layers 81 and the plurality of insulating layers 83 may be alternately stacked in a third direction D3 crossing the first direction D1 and the second direction D2. For example, as shown in the exemplary embodiment of fig. 9, the third direction D3 may be perpendicular to the first direction D1 and the second direction D2, and may be a thickness direction of the substrate 51. Each of the plurality of channel structures 99 may extend in the third direction D3. Each of the plurality of first horizontal wirings B1 and the plurality of second horizontal wirings B2 may be connected to at least one of the corresponding channel structures of the plurality of channel structures 99 via the plurality of bit plugs 107. The plurality of first line recognition parts 255 may not be electrically connected to the plurality of channel structures 99. For example, as shown in the exemplary embodiment of fig. 9, the semiconductor device does not include any bit plugs 107 (e.g., in the third direction D3) disposed between the plurality of first line recognition portions 255 and the plurality of channel structures 99. The plurality of first line recognition portions 255 may be insulated from the plurality of channel structures 99. The first and second upper insulating layers 103 and 105 may be disposed (e.g., in the third direction D3) between the plurality of first line recognition parts 255 and the plurality of channel structures 99.

In an exemplary embodiment, the plurality of first horizontal wirings B1 may have a first pitch Pl. Each of the plurality of first horizontal wirings B1 may have substantially the same first horizontal width W1 (e.g., length in the first direction D1). An interval between the plurality of first horizontal wirings B1 (e.g., a length by which adjacent first horizontal wirings B1 are spaced apart from each other in the first direction D1) may be the first interval D11. The first pitch P1 may be equal to the sum of the first horizontal width W1 and the first spacing D11. The plurality of second horizontal wirings B2 may have a second pitch P2. Each of the plurality of second horizontal wirings B2 may have substantially the same second horizontal width W2 (e.g., length in the first direction D1). An interval between the plurality of second horizontal wirings B2 (e.g., a length by which adjacent second horizontal wirings B2 are spaced apart from each other in the first direction D1) may be the second interval D22. The second pitch P2 may be equal to the sum of the second horizontal width W2 and the second spacing D22. In an exemplary embodiment, the second horizontal width W2 may be substantially the same as the first horizontal width W1. The second pitch P2 may be substantially the same as the first pitch P1. However, the exemplary embodiments of the inventive concept are not limited thereto.

The plurality of first line recognition parts 255 may be disposed at substantially the same height (e.g., a distance from the upper surface of the substrate 51 in the third direction D3) as the plurality of first horizontal wirings B1 and the plurality of second horizontal wirings B2. In an exemplary embodiment, the plurality of first line recognition parts 255, the plurality of first horizontal wirings B1, and the plurality of second horizontal wirings B2 may include the same material, and may be formed substantially simultaneously. Each of the plurality of first line recognition parts 255, the plurality of first horizontal wirings B1, and the plurality of second horizontal wirings B2 may have substantially the same thickness (e.g., length in the third direction D3). In an exemplary embodiment, the plurality of first line recognition parts 255, the plurality of first horizontal wirings B1, and the plurality of second horizontal wirings B2 may include a metal, a metal nitride, a metal oxide, a metal silicide, conductive carbon, polysilicon, or a conductive layer such as a combination thereof. The top surfaces of the plurality of first line recognition parts 255, the plurality of first horizontal wirings B1, and the plurality of second horizontal wirings B2 may be substantially coplanar with each other (e.g., in the third direction D3). Bottom surfaces of the plurality of first line recognition parts 255, the plurality of first horizontal wirings B1, and the plurality of second horizontal wirings B2 may be substantially coplanar with each other (e.g., in the third direction D3).

In an exemplary embodiment, the plurality of first line recognition parts 255 may include a material different from that of the plurality of first horizontal wirings Bl and the plurality of second horizontal wirings B2. In an exemplary embodiment, the plurality of first line recognition parts 255 may include empty spaces. In an exemplary embodiment, the plurality of first line recognition parts 255 and the third upper insulation layer 106 may include the same material, and may be formed at the same time. The plurality of first line recognition parts 255 may include an insulating layer.

Each of the plurality of first line recognition parts 255 may have a third horizontal width W3 (e.g., a length in the first direction D1). As shown in the exemplary embodiment of fig. 9, the third horizontal width W3 may be greater than each of the first horizontal width W1 and the second horizontal width W2. In an exemplary embodiment, the third horizontal width W3 may be in a range of about 2 to about 20 times the size of each of the first horizontal width W1 and the second horizontal width W2. For example, the third horizontal width W3 may be about 300 nm. In an exemplary embodiment, each of the first horizontal width W1 and the second horizontal width W2 may be in a range of about 15nm to about 150 nm. The interval between the side edge of one first line recognition part 255 selected from among the plurality of first line recognition parts 255 and the adjacent side edge of one first horizontal wiring B1 closest to the one first line recognition part 255 among the plurality of first horizontal wirings B1 may be a third interval D31. In an exemplary embodiment, the third interval D31 may be substantially the same as the first interval D11. The interval between the side edge of one first line recognition part 255 selected from among the plurality of first line recognition parts 255 and the adjacent side edge of one second horizontal wiring B2 closest to the one first line recognition part 255 among the plurality of second horizontal wirings B2 may be a fourth interval D32. In an exemplary embodiment, the fourth interval D32 may be substantially the same as the second interval D22. In an exemplary embodiment, the first interval D11, the second interval D22, the third interval D31, and the fourth interval D32 may be substantially the same.

In an exemplary embodiment, the lower horizontal wiring 71 may correspond to a source line or a Common Source Line (CSL). At least one of the plurality of electrode layers 81 adjacent to the lowermost end of the stacked structure 85 and at least one of the plurality of electrode layers 81 adjacent to the uppermost end of the stacked structure 85 may each correspond to a Gate Induced Drain Leakage (GIDL) control line. Some of the plurality of electrode layers 81 may each correspond to a word line or a dummy word line. At least one of the plurality of electrode layers 81 disposed between the GIDL control line and the word line (e.g., in the third direction D3) adjacent to the lowermost end of the stack structure 85 may correspond to a Ground Select Line (GSL). At least one of the plurality of electrode layers 81 adjacent to the uppermost end of the stack structure 85 and disposed between the GIDL control line and the word line (e.g., in the third direction D3) may correspond to a String Selection Line (SSL).

The lower horizontal wiring 71 may be provided on the substrate 51. For example, as shown in the exemplary embodiment of fig. 9, the lower surface of the lower horizontal wiring 71 may directly contact the upper surface of the substrate 51. In an exemplary embodiment, the substrate 51 may include a semiconductor substrate such as a silicon wafer. The lower horizontal wiring 71 may include a single layer or a plurality of layers. In an exemplary embodiment, the lower horizontal wiring 71 may include a metal, a metal nitride, a metal silicide, a metal oxide, conductive carbon, polysilicon, or a combination thereof. For example, the lower horizontal wiring 71 may include a doped polysilicon layer. In an exemplary embodiment, the lower horizontal wiring 71 may be formed by implanting N-type or P-type impurities into the substrate 51. The connection electrode layer 73 and the support portion 75 may be disposed on the lower horizontal wiring 71. The connection electrode layer 73 may be disposed between the lower horizontal wiring 71 and the support portion 75. For example, as shown in the exemplary embodiment of fig. 9, the upper surface of the lower horizontal wiring 71 may directly contact the lower surface of the connection electrode layer 73, and the lower surface of the support portion 75 may directly contact the upper surface of the connection electrode layer 73.

The stack structure 85 may be disposed on the support portion 75. For example, the lower surface of the stack structure 85 may directly contact the upper surface of the support part 75. In an exemplary embodiment, the plurality of electrode layers 81 may include a metal, a metal nitride, a metal silicide, a metal oxide, conductive carbon, polysilicon, or a combination thereof. In an exemplary embodiment, the plurality of insulating layers 83 may include silicon oxide, silicon nitride, silicon oxynitride, silicon boron nitride (SiBN), silicon carbon nitride (SiCN), low-k dielectric, high-k dielectric, or a combination thereof. For example, the plurality of insulating layers 83 may include silicon oxide. Each of the plurality of channel structures 99 may pass through the stack structure 85, the support portion 75, and the connection electrode layer 73, and may extend to the inside of the lower horizontal wiring 71. The plurality of channel structures 99 may contact the lower horizontal wiring 71. For example, as shown in the exemplary embodiment of fig. 9, the lower surfaces of the plurality of channel structures 99 may be at a height (e.g., in the third direction D3) lower than the upper surface of the lower horizontal wiring 71.

The first upper insulating layer 103 may be disposed on the stack structure 85. For example, as shown in the exemplary embodiment of fig. 9, the lower surface of the first upper insulating layer 103 may directly contact the upper surface of the stack structure 85. The second upper insulating layer 105 may be disposed on the first upper insulating layer 103. For example, as shown in the exemplary embodiment of fig. 9, the lower surface of the second upper insulating layer 105 may directly contact the upper surface of the first upper insulating layer 103. A plurality of bit plugs 107 are formed through the second upper insulating layer 105 and the first upper insulating layer 103 to directly contact the lower surfaces of the first and second horizontal wirings B1 and B2 and to directly contact the upper surfaces of the plurality of channel structures 99. The plurality of first horizontal wirings B1, the plurality of second horizontal wirings B2, and the plurality of first line recognition parts 255 may be disposed on the second upper insulating layer 105. For example, as shown in the exemplary embodiment of fig. 9, the lower surfaces of the plurality of first horizontal wirings B1, the plurality of second horizontal wirings B2, and the plurality of first line recognition parts 255 may directly contact the upper surface of the second upper insulating layer 105. A third upper insulating layer 106 covering the plurality of first horizontal wirings B1, the plurality of second horizontal wirings B2, and the plurality of first line recognition parts 255 may be disposed on the second upper insulating layer 105. For example, as shown in the exemplary embodiment of fig. 9, the lower surface of the third upper insulating layer 106 may directly contact the upper surfaces and the side surfaces of the plurality of first horizontal wirings B1, the plurality of second horizontal wirings B2, and the plurality of first line recognition parts 255 and the upper surface of the second upper insulating layer 105.

In an exemplary embodiment, the plurality of bit plugs 107 may include a metal, a metal nitride, a metal silicide, a metal oxide, conductive carbon, polysilicon, or a combination thereof. In an exemplary embodiment, the first, second, and third upper insulating layers 103, 105, and 106 may include silicon oxide, silicon nitride, silicon oxynitride, SiBN, SiCN, a low-k dielectric, a high-k dielectric, or a combination thereof.

Referring to fig. 10, the semiconductor device according to an exemplary embodiment of the inventive concept may include a substrate 51, a lower horizontal wiring 71, a connection electrode layer 73, a support portion 75, a stack structure 85, a plurality of isolation patterns 89, a plurality of channel structures 99, a first upper insulating layer 103, a second upper insulating layer 105, a third upper insulating layer 106, a plurality of bit plugs 107, and a plurality of first horizontal wirings B1.

Each of the plurality of isolation patterns 89 may extend in the third direction D3, and may be aligned in the second direction D2. Each of the plurality of isolation patterns 89 may pass through the first upper insulating layer 103, the stack structure 85, the support portion 75, and the connection electrode layer 73, and may extend to the inside of the lower horizontal wiring 71. For example, as shown in the exemplary embodiment of fig. 10, the lower surfaces of the plurality of isolation patterns 89 may be at a height lower than the upper surface of the lower horizontal wiring 71 (e.g., in the third direction D3). In an exemplary embodiment, the plurality of isolation patterns 89 may include silicon oxide, silicon nitride, silicon oxynitride, SiBN, SiCN, a low-k dielectric, a high-k dielectric, or a combination thereof.

Referring to the exemplary embodiment of fig. 11, a plurality of channel structures 99 may pass through the stack structure 85. The first upper insulating layer 103 may cover the stack structure 85 and the plurality of channel structures 99. The second upper insulating layer 105 may be disposed on the first upper insulating layer 103. The first line recognition part 255 may be disposed on the second upper insulation layer 105. The first line recognition part 255 may not be electrically connected to the plurality of channel structures 99. The first line recognition part 255 may be insulated from the plurality of channel structures 99. The first upper insulating layer 103 and the second upper insulating layer 105 may be disposed between the first line recognition part 255 and the plurality of channel structures 99.

Referring to the exemplary embodiment of fig. 12, a first upper insulating layer 103 may be disposed on the stack structure 85. The second upper insulating layer 105 may be disposed on the first upper insulating layer 103. The first line recognition part 255 may be disposed on the second upper insulation layer 105. As shown in the exemplary embodiment of fig. 12, in contrast to the exemplary embodiment of fig. 1, which includes a plurality of channel structures 99, in the illustrated partial region, the semiconductor device may not include a plurality of channel structures 99 (e.g., in the third direction D3) between the substrate 51 and the first line recognition portion 255. The first line recognition part 255 may not be electrically connected to the plurality of electrode layers 81 of the stack structure 85. The first line recognition part 255 may be insulated from the plurality of electrode layers 81.

Referring to the exemplary embodiment of fig. 13, the semiconductor device includes the first dummy contact plug 287, and the first dummy contact plug 287 passes through the first upper insulating layer 103, the stack structure 85, the support portion 75, and the connection electrode layer 73 and extends to the inside of the lower horizontal wiring 71. For example, as shown in the exemplary embodiment of fig. 13, the lower surface of the first dummy contact plug 287 may be at a lower height than the upper surface of the lower horizontal wiring 71. The first dummy contact plug 287 may directly contact the lower horizontal wiring 71. The contact spacer 286 may surround a side surface of the first dummy contact plug 287. The contact spacer 286 may be disposed between the first dummy contact plug 287 and the plurality of electrode layers 81 and the plurality of insulating layers 83 of the stack structure 85. The contact spacers 286 may provide an insulating structure between the plurality of electrode layers 81 and the first dummy contact plugs 287.

The second dummy contact plug 288 passes through the second upper insulating layer 105 and contacts the first dummy contact plug 287. For example, the lower surface of the second dummy contact plug 288 may directly contact the upper surface of the first dummy contact plug 287. The first line recognition part 255 contacting the second dummy contact plug 288 may be disposed on the second upper insulating layer 105. For example, as shown in the exemplary embodiment of fig. 13, the lower surface of the first line recognition part 255 may directly contact the upper surface of the second dummy contact plug 288. The first line recognition portion 255 may be electrically connected to the lower horizontal wiring 71 via the second dummy contact plug 288 and the first dummy contact plug 287. However, the number of dummy contact plugs may vary in other exemplary embodiments, and at least one dummy contact plug may be configured to connect the first line recognition part 255 to the lower horizontal wiring 71.

In an exemplary embodiment, the contact spacer 286 may include silicon oxide, silicon nitride, silicon oxynitride, SiBN, SiCN, a low-k dielectric, a high-k dielectric, or a combination thereof. In example embodiments, each of the first and second dummy contact plugs 287 and 288 may include a metal, a metal nitride, a metal silicide, a metal oxide, conductive carbon, polysilicon, or a combination thereof.

Referring to the example embodiment of fig. 14, the channel structure 99 may include a core pattern 97, a channel layer 96 surrounding the outside of the core pattern 97, an information storage pattern 95 surrounding the outside of the channel layer 96, and a bit pad (bit pad)98 disposed on the channel layer 96. As shown in the exemplary embodiment of fig. 14, the information storage pattern 95 may include a tunnel insulation layer 91 surrounding and directly contacting the outside of the channel layer 96, a charge storage layer 92 surrounding and directly contacting the outside of the tunnel insulation layer 91, and a blocking layer 93 surrounding and directly contacting the outside of the charge storage layer 92. In the portion 36, a channel structure 99 may pass through the electrode layer 81 and the plurality of insulating layers 83. The bit plug 107 may pass through the first upper insulating layer 103 and may contact the bit pad 98 of the channel structure 99. For example, as shown in the exemplary embodiment of fig. 14, the lower surface of bit plug 107 may directly contact the upper surface of bit pad 98.

In an exemplary embodiment, the tunnel insulating layer 91 may include an insulating layer such as silicon oxide. The charge storage layer 92 may include an insulating layer such as silicon nitride. Barrier layer 93 may comprise silicon oxide, silicon nitride, silicon oxynitride, SiBN, SiCN, low-k dielectric, high-k dielectric, or combinations thereof. The channel layer 96 may include a semiconductor layer of polysilicon, amorphous silicon, single crystal silicon, or combinations thereof. The core pattern 97 may include silicon oxide, silicon nitride, silicon oxynitride, SiBN, SiCN, low-k dielectric, high-k dielectric, or a combination thereof. The bit pad 98 may comprise a conductive layer of metal, metal nitride, metal oxide, metal silicide, conductive carbon, polysilicon, or combinations thereof.

Referring to the exemplary embodiment of fig. 15, a plurality of electrode layers 81 and a plurality of insulating layers 83 may be repeatedly and alternately stacked. The channel structure 99 may pass through the plurality of electrode layers 81 and the plurality of insulating layers 83. The channel structure 99 may include a core pattern 97, a channel layer 96, and an information storage pattern 95. The information storage pattern 95 may include a tunnel insulating layer 91, a charge storage layer 92, and a blocking layer 93.

Referring to the exemplary embodiment of fig. 16, the connection electrode layer 73 may be disposed between the lower horizontal wiring 71 and the support portion 75. For example, as shown in the exemplary embodiment of fig. 16, the lower surface of the connection electrode layer 73 may directly contact the upper surface of the lower horizontal wiring 71, and the upper surface of the connection electrode layer 73 may directly contact the lower surface of the support portion 75. The insulating layer 83 may be disposed on the support portion 75. The channel structure 99 may pass through the insulating layer 83 and the support portion 75, and may extend to the inside of the lower horizontal wiring 71. For example, as shown in the exemplary embodiment of fig. 16, the lower surface of the channel structure 99 may be at a lower height than the upper surface of the lower horizontal wiring 71. The connection electrode layer 73 may pass through a side surface of the information storage pattern 95, and may directly contact a side surface of the channel layer 96. The lowermost end of the channel structure 99 may be disposed at a height higher than the bottom surface of the lower horizontal wiring 71. The channel layer 96 may be electrically connected to the lower horizontal wiring 71 via the connection electrode layer 73.

Referring to fig. 17, the semiconductor device according to an exemplary embodiment of the inventive concept may include a substrate 51, a lower horizontal wiring 71, a connection electrode layer 73, a connection molding layer 73M, a support portion 75, a first lower insulating layer 76, a second lower insulating layer 77, a buried insulating pattern 78, a stack structure 85, at least one interlayer insulating layer 86, a plurality of channel structures 99, a first upper insulating layer 103, a second upper insulating layer 105, a third upper insulating layer 106, a plurality of bit plugs 107, a first contact plug 307, a second contact plug 308, a third contact plug 309, a plurality of first horizontal wirings B1, a plurality of second horizontal wirings B2, and a third horizontal wiring X3. The connection electrode layer 73 and the connection molding layer 73M may form a connection wiring layer.

The lower horizontal wiring 71 and the first lower insulating layer 76 may be disposed on the substrate 51. For example, as shown in the exemplary embodiment of fig. 17, the lower surfaces of the lower horizontal wiring 71 and the first lower insulating layer 76 may directly contact the upper surface of the substrate 51 and may be aligned in the first direction D1 with respect to each other. The top surfaces of the lower horizontal wiring 71 and the first lower insulating layer 76 may be substantially coplanar with each other (e.g., in the third direction D3). The connection molding layer 73M, the connection electrode layer 73, the support portion 75, the second lower insulation layer 77, and the buried insulation pattern 78 may be disposed on the lower horizontal wiring 71 and the first lower insulation layer 76.

In an exemplary embodiment, the connection molding layer 73M may include a material having an etching selectivity with respect to the lower horizontal wiring 71 and the support portion 75. Connection molding layer 73M may include a lower molding layer 73L, an upper molding layer 73U disposed on lower molding layer 73L, and an intermediate molding layer 73C disposed between lower molding layer 73L and upper molding layer 73U (e.g., in third direction D3). The middle molding layer 73C may include a material having an etching selectivity with respect to the lower molding layer 73L and the upper molding layer 73U. For example, in an exemplary embodiment, each of the lower and upper molding layers 73L and 73U may include silicon oxide. The intermediate molding layer 73C may include silicon nitride.

The support portion 75 may cover the connection molding layer 73M and the connection electrode layer 73. The support portion 75 may include a portion passing through the connection molding layer 73M and the connection electrode layer 73, and may directly contact the top surface of the lower horizontal wiring 71. As shown in the exemplary embodiment of fig. 17, the support portion 75 may directly contact the top and side surfaces of the connection molding layer 73M and the top and side ends of the connection electrode layer 73. A side end of the second lower insulating layer 77 may contact a side end of the support portion 75 and a side end of the connection molding layer 73M. The buried insulation pattern 78 may be disposed on the support portion 75.

Top surfaces of the support portion 75, the second lower insulating layer 77, and the buried insulating pattern 78 may be substantially coplanar with each other (e.g., in the third direction D3). In an exemplary embodiment, each of the first lower insulating layer 76, the second lower insulating layer 77, and the buried insulating pattern 78 may include silicon oxide, silicon nitride, silicon oxynitride, SiBN, SiCN, a low-k dielectric, a high-k dielectric, or a combination thereof. In an exemplary embodiment, the support portion 75 may include a polysilicon layer. The connection electrode layer 73 may include a metal, a metal nitride, a metal oxide, a metal silicide, conductive carbon, polysilicon, or a conductive layer such as a combination thereof.

The stack structure 85 and the interlayer insulating layer 86 may be disposed (e.g., in the third direction D3) on the support portion 75, the second lower insulating layer 77, and the buried insulating pattern 78. An interlayer insulating layer 86 may be disposed on a side surface of the stack structure 85. In an exemplary embodiment, the interlayer insulating layer 86 may include silicon oxide, silicon nitride, silicon oxynitride, SiBN, SiCN, a low-k dielectric, a high-k dielectric, or a combination thereof.

The first upper insulating layer 103, the second upper insulating layer 105, and the third upper insulating layer 106 may be sequentially stacked (e.g., in the third direction D3) on the stack structure 85 and the interlayer insulating layer 86. The first contact plug 307 may extend substantially in the third direction D3 and pass through the first upper insulating layer 103 and the interlayer insulating layer 86, and may contact a corresponding electrode layer of the plurality of electrode layers 81. The second contact plug 308 may extend substantially in the third direction D3 and pass through the second upper insulating layer 105, and may contact the first contact plug 307. For example, as shown in the exemplary embodiment of fig. 17, the lower surface of the second contact plug 308 may directly contact the upper surface of the first contact plug 307. The third contact plug 309 may substantially extend in the third direction D3 and pass through the third upper insulating layer 106, and may contact the second contact plug 308. For example, as shown in the exemplary embodiment of fig. 17, the lower surface of the third contact plug 309 may directly contact the upper surface of the second contact plug 308. The third horizontal wiring X3 may be disposed on the third upper insulating layer 106, and may contact the third contact plug 309. For example, as shown in the exemplary embodiment of fig. 17, the lower surface of the third horizontal wiring X3 may directly contact the upper surface of the third contact plug 309. However, the exemplary embodiments of the inventive concept are not limited thereto. The third horizontal wiring X3 may be connected to a corresponding electrode layer of the plurality of electrode layers 81 via the third contact plug 309, the second contact plug 308, and the first contact plug 307. In an exemplary embodiment, each of the first contact plug 307, the second contact plug 308, the third contact plug 309, and the third horizontal wiring X3 may include a metal, a metal nitride, a metal oxide, a metal silicide, conductive carbon, polysilicon, or a conductive layer such as a combination thereof.

The third horizontal wiring X3 may be disposed at a different height from the plurality of first horizontal wirings B1 and the plurality of second horizontal wirings B2. For example, as shown in the exemplary embodiment of fig. 17, the third horizontal wiring X3 may be formed at a height higher than the plurality of first horizontal wirings B1 and the plurality of second horizontal wirings B2. In an exemplary embodiment, the third horizontal wiring X3 may be disposed on the third upper insulating layer 106. For example, as shown in the exemplary embodiment of fig. 17, the lower surface of the third horizontal wiring X3 may directly contact the upper surface of the third upper insulating layer 106. A plurality of first horizontal wirings B1 and a plurality of second horizontal wirings B2 may be formed in the third upper insulating layer 106. For example, the third upper insulating layer 106 may directly contact upper surfaces and side surfaces of the plurality of first horizontal wirings B1 and the plurality of second horizontal wirings B2.

Referring to fig. 18, the semiconductor device according to an exemplary embodiment of the inventive concept may include a substrate 51, a first lower insulating layer 76, a second lower insulating layer 77, at least one interlayer insulating layer 86, a first upper insulating layer 103, a second upper insulating layer 105, a third upper insulating layer 106, a third wiring group 313 including a plurality of third horizontal wirings X3, a fourth wiring group 314 including a plurality of fourth horizontal wirings X4, and a plurality of second line recognition portions 356.

The plurality of third horizontal wiring lines X3, the plurality of fourth horizontal wiring lines X4, and the plurality of second line recognition parts 356 may be disposed on the third upper insulating layer 106. For example, as shown in the exemplary embodiment of fig. 18, the lower surfaces of the plurality of third horizontal wiring lines X3, the plurality of fourth horizontal wiring lines X4, and the plurality of second line recognition parts 356 may directly contact the upper surface of the third upper insulating layer 106. Each of the plurality of third horizontal wirings X3 may have substantially the same horizontal width (e.g., length in the second direction D2). Each of the plurality of third horizontal wirings X3 may have substantially the same interval between the corresponding third horizontal wiring X3 and the adjacent third horizontal wiring X3 (e.g., a length in the second direction D2 by which each third horizontal wiring X3 is spaced apart from the adjacent third horizontal wiring X3). Each of the plurality of fourth horizontal wirings X4 may have substantially the same horizontal width (e.g., length in the second direction D2). Each of the plurality of fourth horizontal wirings X4 may have substantially the same interval between the corresponding fourth horizontal wiring X4 and the adjacent fourth horizontal wiring X4 (e.g., a length in the second direction D2 by which each fourth horizontal wiring X4 is spaced apart from the adjacent fourth horizontal wiring X4). In an exemplary embodiment, the plurality of third horizontal wirings X3 may have substantially the same pitch as the plurality of fourth horizontal wirings X4.

The plurality of second line recognition parts 356 may be disposed at substantially the same height as the plurality of third horizontal wiring lines X3 and the plurality of fourth horizontal wiring lines X4. In an exemplary embodiment, the plurality of second line recognition parts 356, the plurality of third horizontal wiring lines X3, and the plurality of fourth horizontal wiring lines X4 may include the same material formed substantially simultaneously. Each of the plurality of second line recognition parts 356, the plurality of third horizontal wirings X3, and the plurality of fourth horizontal wirings X4 may have substantially the same thickness (e.g., length in the third direction D3). In an exemplary embodiment, the plurality of second line recognition parts 356, the plurality of third horizontal wirings X3, and the plurality of fourth horizontal wirings X4 may include a metal, a metal nitride, a metal oxide, a metal silicide, conductive carbon, polysilicon, or a conductive layer such as a combination thereof. The top surfaces of the plurality of second line recognition parts 356, the plurality of third horizontal wirings X3, and the plurality of fourth horizontal wirings X4 may be substantially coplanar with each other (e.g., in the third direction D3). Bottom surfaces of the plurality of second line recognition parts 356, the plurality of third horizontal wirings X3, and the plurality of fourth horizontal wirings X4 may be substantially coplanar with each other (e.g., in the third direction D3).

In an exemplary embodiment, the plurality of second line recognition parts 356 may include a material different from that of the plurality of third horizontal wiring lines X3 and the plurality of fourth horizontal wiring lines X4. In an exemplary embodiment, the plurality of second line recognition parts 356 may include empty spaces. The plurality of second line recognition parts 356 may include an insulating layer.

Each of the plurality of second line recognition parts 356 may have a horizontal width (e.g., a length in the second direction D2) larger than a horizontal width (e.g., a length in the second direction D2) of each of the plurality of third horizontal wirings X3 and the plurality of fourth horizontal wirings X4. In an exemplary embodiment, the horizontal width of each of the plurality of second line recognition parts 356 may be in a range of about 2 to about 20 times the horizontal width of each of the plurality of third horizontal wirings X3 and the plurality of fourth horizontal wirings X4. For example, the horizontal width of each of the plurality of second line identification parts 356 may be about 300 nm. In an exemplary embodiment, a horizontal width of each of the plurality of third horizontal wirings X3 and the plurality of fourth horizontal wirings X4 may be in a range of about 15nm to about 150 nm. An interval between one second line recognition part 356 selected from among the plurality of second line recognition parts 356 and one third horizontal wiring X3 immediately adjacent to the one second line recognition part 356 among the plurality of third horizontal wirings X3 (e.g., in the second direction D2) may be substantially the same as an interval between mutually adjacent third horizontal wirings X3 among the plurality of third horizontal wirings X3. An interval between one second line recognition part 356 selected from among the plurality of second line recognition parts 356 and one fourth horizontal wiring X4, which is immediately adjacent to the one second line recognition part 356, among the plurality of fourth horizontal wirings X4 (e.g., in the second direction D2) may be substantially the same as an interval between the fourth horizontal wirings X4, which are adjacent to each other, among the plurality of fourth horizontal wirings X4.

Referring again to fig. 1 and 17 in conjunction with fig. 18, each of the plurality of third horizontal wirings X3 and the plurality of fourth horizontal wirings X4 may be connected to a corresponding one of the plurality of electrode layers 81 via the third contact plug 309, the second contact plug 308, and the first contact plug 307. The plurality of second line recognition parts 356 may not be electrically connected to the plurality of electrode layers 81. The plurality of third horizontal wirings X3, the plurality of fourth horizontal wirings X4, and the plurality of second line recognition parts 356 may be formed at a different height from the plurality of first horizontal wirings B1, the plurality of second horizontal wirings B2, and the plurality of first line recognition parts 255. In an exemplary embodiment, a plurality of third horizontal wiring lines X3, a plurality of fourth horizontal wiring lines X4, and a plurality of second line recognition parts 356 may be disposed on the third upper insulating layer 106. For example, as shown in the exemplary embodiment of fig. 18, the lower surfaces of the plurality of third horizontal wiring lines X3, the plurality of fourth horizontal wiring lines X4, and the plurality of second line recognition parts 356 may directly contact the upper surface of the third upper insulating layer 106. The plurality of first horizontal wirings B1, the plurality of second horizontal wirings B2, and the plurality of first line recognition parts 255 may be formed in the third upper insulating layer 106 and disposed below the upper surface of the third upper insulating layer 106.

Fig. 19 and 20 are schematic views for describing a semiconductor device according to an exemplary embodiment of the inventive concept.

Referring to fig. 19, the semiconductor device according to an exemplary embodiment of the inventive concept may include a page buffer 202, a column decoder 204, a row decoder 304, a first wiring group 211 including a plurality of first horizontal wirings B1, a second wiring group 212 including a plurality of second horizontal wirings B2, a plurality of first line recognition parts 255, a third wiring group 313 including a plurality of third horizontal wirings X3, and a fourth wiring group 314 including a plurality of fourth horizontal wirings X4.

The plurality of first horizontal wirings B1 and the plurality of second horizontal wirings B2 may be arranged in the first direction D1. Each of the plurality of first horizontal wirings B1 and the plurality of second horizontal wirings B2 may extend in the second direction D2. One first line recognition part 255 selected from among the plurality of first line recognition parts 255 may be disposed (e.g., in the first direction D1) between the first wiring group 211 and the second wiring group 212.

The first and second wiring groups 211 and 212 may be disposed adjacent to the third and fourth wiring groups 313 and 314 in the first direction D1. The plurality of third horizontal wirings X3 and the plurality of fourth horizontal wirings X4 may be arranged in the second direction D2. Each of the plurality of third horizontal wirings X3 and the plurality of fourth horizontal wirings X4 may extend in the first direction D1. In an exemplary embodiment, each of the plurality of third horizontal wirings X3 and the plurality of fourth horizontal wirings X4 may have substantially the same width (e.g., length in the second direction D2).

The third wiring group 313 and the fourth wiring group 314 may be disposed adjacent to the row decoder 304 in the first direction D1. Each of the plurality of third horizontal wirings X3 and the plurality of fourth horizontal wirings X4 may be connected to the row decoder 304.

Referring to fig. 20, the semiconductor device according to an exemplary embodiment of the inventive concept may include a page buffer 202, a column decoder 204, a first wiring group 211 including a plurality of first horizontal wirings B1, a second wiring group 212 including a plurality of second horizontal wirings B2, and a plurality of first line recognition parts 255.

The plurality of first horizontal wirings B1 and the plurality of second horizontal wirings B2 may be arranged in the first direction D1. Each of the plurality of first horizontal wirings B1 and the plurality of second horizontal wirings B2 may extend in the second direction D2. One first line recognition part 255 selected from among the plurality of first line recognition parts 255 may be disposed (e.g., in the first direction D1) between the first wiring group 211 and the second wiring group 212.

According to an exemplary embodiment of the inventive concept, the line recognition part may be provided between a plurality of horizontal wirings. A semiconductor device for enabling the position of each of a plurality of wirings parallel to each other to be easily recognized can be realized.

In the foregoing, exemplary embodiments of the inventive concept have been described with reference to the accompanying drawings, but it is understood that those skilled in the art can implement the exemplary embodiments in additional detail without changing the inventive concept or essential features. It should be understood that the above-described exemplary embodiments are only examples in all aspects and the inventive concept is not limited thereto.

This application claims priority to korean patent application No. 10-2020-0062192, filed on the korean intellectual property office on 25/5/2020, the disclosure of which is incorporated herein by reference in its entirety.