阅读说明：本技术 并行路径延迟线 (Parallel path delay line ) 是由 扬·保罗·安东尼·范德瓦特 丹尼斯·泽列宁 于 2020-04-23 设计创作，主要内容包括：电路及其操作方法以将信号延迟精确且可变的量。一个实施方案涉及一种在自动化测试设备中使用的高速延迟线。本发明人已经认识到并理解,具有高数据速率的输入信号可被分离成具有较低数据速率的并行分离信号,该并行分离信号在被组合以生成延迟信号之前在相应的并行延迟路径中被延迟。以这种方式延迟信号的一个优点是在高数据速度下提供高延迟线时序精度,同时使用紧凑电路设计,该设计使用较低带宽的电路部件并降低功耗,例如通过使用互补金属氧化物半导体(CMOS)。另一优点是高速延迟线可由模块化的多个较低数据速率的并行延迟线构造,从而简化电路设计。(Circuits and methods of operating the same to delay a signal by a precise and variable amount. One embodiment relates to a high speed delay line for use in automated test equipment. The present inventors have recognized and appreciated that an input signal having a high data rate may be split into parallel split signals having lower data rates, which are delayed in respective parallel delay paths before being combined to generate a delayed signal. One advantage of delaying signals in this manner is to provide high delay line timing accuracy at high data speeds while using a compact circuit design that uses lower bandwidth circuit components and reduces power consumption, for example, by using Complementary Metal Oxide Semiconductor (CMOS). Another advantage is that a high speed delay line can be constructed from a modular plurality of lower data rate parallel delay lines, simplifying circuit design.)

1. An apparatus for delaying a signal, the apparatus comprising:

a splitter circuit comprising an input and N outputs, wherein:

n is at least two, and

the splitter circuit is configured to receive an input signal having a first data rate at the input and generate N split signals at respective outputs, each of the N split signals having a data rate less than the first data rate; and

a delay circuit configured to generate a delayed signal based on the N split signals, wherein the delayed signal is the input signal with a delay.

2. The apparatus of claim 1, wherein:

the delay circuit includes N delay paths and a combiner circuit, each delay path configured to receive a respective split signal and generate a delayed split signal, and

the combiner circuit is configured to generate the delayed signal based on the delayed N split signals.

3. The apparatus of claim 2, wherein the combiner circuit comprises an exclusive or gate.

4. The apparatus of claim 1, wherein N is two, and wherein each of the split signals has a data rate that is one-half of the first data rate.

5. The apparatus of claim 1, wherein:

n is two, and N is a hydrogen atom,

the N outputs comprise a first output and a second output,

the splitter circuit is configured to generate a first split signal at the first output and a second split signal at the second output,

each of the input signal and the first and second split signals has a plurality of rising and falling edges,

the splitter circuit is configured to generate a first edge at the first output but not in the second output in response to a rising edge of the input signal, and

the splitter circuit is configured to generate a second edge at the second output but not in the first output in response to a falling edge of the input signal.

6. The apparatus of claim 1, wherein:

n is two such that the splitter circuit comprises two outputs, an

The splitter circuit is configured such that a logic high at the input corresponds to one logic high and one logic low at the two outputs, and a logic low at the input corresponds to two outputs having the same polarity.

7. The apparatus of claim 1, wherein N is two, and the splitter circuit comprises:

a first D-latch having a first clock input, a first latch input, and a first latch output, wherein the input to the splitter circuit is connected to the first clock input of the first D-latch.

8. The apparatus of claim 7, wherein:

the splitter circuit further comprises a second D-latch having a second clock input, a second latch input, and a second latch output,

the second D-latch is configured to receive an inverted input signal at the second clock input,

the second latch input is connected to the first latch output,

an inverted second latch output is connected to the first latch input,

the first output is connected to the second latch output, and

the second output is connected to the first latch output.

9. A method for delaying a signal, the method comprising:

receiving, with a splitter circuit, an input signal having a plurality of rising edges and falling edges at a first data rate;

generating, with the splitter circuit, a first split signal having a plurality of rising and falling edges at a second data rate, and a second split signal having a plurality of rising and falling edges at a third data rate, wherein the second and third data rates are less than the first data rate;

generating, at a delay circuit, a delayed signal based on the first split signal and the second split signal, wherein the delayed signal is the input signal with a delay.

10. The method of claim 9, wherein the second data rate and the third data rate are each half of the first data rate.

11. The method of claim 9, wherein generating the first and second split signals comprises:

generating the first split signal and the second split signal such that a logic high at the input signal corresponds to a logic high and a logic low at the first split signal and the second split signal, and a logic low at the input signal corresponds to both the first split signal and the second split signal being at the same polarity.

12. The method of claim 9, wherein generating the first and second split signals comprises:

generating a first edge in the first split signal but not in the second split signal in response to a rising edge of the input signal, an

Generating a second edge in the second output signal stream in response to a falling edge of the input signal, but not in the first split signal.

13. The method of claim 9, wherein the splitter circuit comprises a first D-latch having a first clock input, a first latch input, and a first latch output, and generating the first split signal and the second split signal comprises:

receiving the input signal at an input of the splitter circuit;

connecting the input to a first clock input of the first D-latch.

14. The method of claim 13, wherein the splitter circuit further comprises a second D latch having a second clock input, a second latch input, and a second latch output, and generating the first split signal and the second split signal further comprises:

connecting the second latch output to the first latch input of the first D latch;

connecting the second latch input to the first latch output of the first D latch;

receiving an inverted input signal at the second clock input;

generating the first split signal at the second latch output; and

generating the second split signal at the first latch output.

15. The method of claim 9, wherein generating the delayed signal comprises:

delaying the first split signal and the second split signal by a programmable amount; and

combining the first delayed split signal and the second delayed split signal.

16. The method of claim 15, further comprising:

delaying the first split signal by a first amount;

delaying the second split signal by a second amount; and wherein combining the first split signal and the second split signal comprises:

the delayed first split signal and the delayed second split signal are combined.

17. The method of claim 16, wherein the delay circuit comprises an exclusive or gate, and wherein combining the delayed first split signal and the delayed second split signal comprises:

connecting the delayed first split signal and the delayed second split signal to inputs of the exclusive or gate, an

The delayed signal is generated at an output of the exclusive or gate.

18. A method for calibrating test equipment, the test equipment comprising a splitter circuit configured to receive an input signal having a first data rate and generate a first split signal and a second split signal, the first split signal and the second split signal each having a data rate less than the first data rate; a first delay path configured to delay the first split signal by a first amount; a second delay path configured to delay the second split signal by a second amount; and a combiner circuit configured to receive the delayed first split signal and the delayed second split signal at a first input and a second input, respectively, and to generate a delayed signal at an output based on the delayed first split signal and the delayed second split signal, the method comprising:

measuring the delayed signal at an output of the combiner circuit;

calibrating the first and second quantities based on the measured delay signal.

19. The method of claim 18, wherein calibrating the first quantity comprises:

setting a high signal level or a low signal level at the first input of the combiner circuit;

adjusting parameters of the second delay path such that data edges in the delayed signal have a predetermined timing.

20. The method of claim 18, wherein calibrating the first amount and the second amount comprises:

the output of the combiner circuit is connected to the first delay path and the second delay path via a feedback path.

Background

Electronic components such as semiconductor devices, circuits, and Printed Circuit Board (PCB) assemblies are frequently tested during and after their manufacture using test systems such as Automated Test Equipment (ATE). To perform these tests, ATE may include instruments that generate or measure test signals so that a range of operating conditions may be tested on a particular Device Under Test (DUT). For example, an instrument may generate or measure a pattern of digital signals to enable testing of digital logic within a semiconductor device. The digital signal has a timing represented by the position of a data edge (such as a rising edge or a falling edge) in the time domain within the digital signal.

ATE is typically used to apply test signals with a particular timing, or in some cases, multiple test signals with coordinated timing, to one or more sites of a DUT. To coordinate timing, ATE may be designed to synchronize the generation of multiple test signals within different channels. However, merely synchronizing the time at which test signals are generated may not be sufficient to coordinate the time at which the signals arrive at the DUT test points. Differences in propagation delays through instruments within the ATE may change the relative timing of the test signals, thereby affecting the accuracy of the test results. To improve test accuracy, one or more delay lines may be employed in the ATE to provide adjustable propagation delays. The ATE may be calibrated by adjusting the relative propagation delay through the delay line. Such calibration may be performed at different times, including when the ATE is manufactured, when the ATE is installed, on a periodic schedule, or sometimes according to usage.

Disclosure of Invention

Aspects of the present application relate to an apparatus and a method of operating the same to delay timing of a signal.

According to some embodiments, an apparatus for delaying a signal is provided. The apparatus includes a splitter circuit having an input and N outputs (N being at least two). The splitter circuit is configured to receive an input signal having a first data rate at an input and generate N split signals at respective outputs, each of the N split signals having a data rate less than the first data rate. The apparatus also includes a delay circuit configured to generate a delayed signal based on the N split signals. The delayed signal is an input signal having a delay.

According to some embodiments, a method for delaying a signal is provided. The method includes receiving, with a splitter circuit, an input signal having a plurality of rising edges and falling edges at a first data rate; generating, with a splitter circuit, a first split signal having a plurality of rising and falling edges at a second data rate, and a second split signal having a plurality of rising and falling edges at a third data rate, wherein the second and third data rates are less than the first data rate; a delay signal is generated at a delay circuit based on the first split signal and the second split signal. The delayed signal is an input signal having a delay.

According to some embodiments, a method for calibrating a test device is provided. The test equipment includes a splitter circuit configured to receive an input signal having a first data rate and generate a first split signal and a second split signal, each having a data rate less than the first data rate; a first delay path configured to delay a first split signal by a first amount; a second delay path configured to delay a second split signal by a second amount; and a combiner circuit configured to receive the delayed first split signal and the delayed second split signal at the first input and the second input, respectively, and to generate a delayed signal at the output based on the delayed first split signal and the delayed second split signal. The method comprises measuring a delayed signal at an output of a combiner circuit; and calibrating the first and second quantities based on the measured delay signal.

Drawings

Various aspects and embodiments will be described in conjunction with the following figures. It should be understood that the drawings are not necessarily drawn to scale. In the drawings, each identical or nearly identical component that is illustrated in various figures is represented by a like numeral. For purposes of clarity, not every component may be labeled in every drawing.

FIG. 1 is a schematic diagram of an exemplary embodiment of an automated test system in which a delay line architecture according to aspects of the present application may be applied, according to some embodiments;

FIG. 2 is a schematic diagram illustrating a delay line circuit for delaying a signal in accordance with aspects of the present application;

FIG. 3 is a schematic diagram illustrating an exemplary implementation of the delay line circuit shown in FIG. 2 having two split signals and two delay paths, according to some embodiments;

FIG. 4 is a schematic diagram illustrating an exemplary implementation of a splitter circuit employing two D-latches, according to some embodiments;

fig. 5 illustrates a series of signal waveforms representing different operating states of the splitter circuit 420 shown in fig. 3 and 4, in accordance with some embodiments;

FIG. 6 illustrates a series of signal waveforms representing different operating states during a calibration method according to some embodiments; and

fig. 7 is a schematic diagram of a delay line 700 with a feedback path for calibration according to some embodiments.

Detailed Description

The present inventors have recognized and appreciated techniques and circuit designs for efficiently generating high-speed signals with high timing accuracy but low power consumption. Such techniques may require splitting an input signal having a high data rate into parallel split signals having lower data rates. The separate signals may be delayed in respective parallel delay paths before being combined to generate a delayed signal as the input signal with the delay.

The techniques described herein may be used to generate timing signals in ATE. Each of the plurality of signal paths may include a delay circuit, and the amount of delay introduced by each such delay circuit may be variable. The amount of delay for each delay circuit may be determined based on the intended use of the delayed signal and may be programmed as part of the programming of the test system and then offset by a determined calibration value during a calibration process so that the amount of delay may correct for delay variations between signal paths.

Delaying the signals in this manner can provide high timing accuracy at high data speeds using a compact and modular circuit design. In some embodiments, the high speed delay line may be constructed from a plurality of lower data rate parallel delay lines, each being modular, thereby simplifying the circuit design of the high speed circuit. In one embodiment, a delay line according to aspects of the present application may operate on signals having a data speed of at least 10 Gbps. Such high speed delay lines may be implemented with components having bandwidths less than 10Gbps, for example, with half rate (5Gbps) bandwidth components. In one example, a half-rate component may be constructed in a compact design using tens of Complementary Metal Oxide Semiconductor (CMOS) transistors.

This type of variable delay line may be used, for example, in Pin Electronics (PE) of ATE. Within ATE, a digital test instrument may be implemented with Pin Electronics (PE), a Timing Generator (TG), which contains multiple variable delay lines to delay digital data in small time increments. The TG acquires vector data and period information from a Pattern Generator (PG), and generates a tick signal that controls the PE by generating a reception gate pulse and a driving path edge time. The PEs, PGs and TGs may be separate components or may be implemented as one or more Integrated Circuits (ICs) comprising a large number of transistors. The variable delay of each delay line may be based on using the signal output from the delay line. For example, if the delay line output is connected to the control input of the driver such that the delay line output sets the time to drive the path edge, the variable delay may be set to produce a signal that controls the driver to output the edge at the desired time. The amount of delay to produce such signals may be based on the programmed value of the edge offset plus a calibration value that may be determined for the signal path, including delay circuits and drivers and other components that may affect the time at which such edges are generated.

The present inventors have recognized and appreciated that when the test signals in the PE have high data rates, such as up to 10Gbps, on the order of multiple Gbps, low cost and low power technologies, such as CMOS, may be used to implement delay lines that may provide accurate data edge placement with resolution in the single picosecond range.

Various aspects of the present application relate to a delay line architecture in which an input signal having a high data rate may be split in a splitter circuit into parallel split signals having lower data rates that are delayed in respective parallel delay paths. Because each of the split signals has a lower data (rising/falling) edge rate than the input signal and, in general, a larger timing separation between adjacent data edges, the parallel delay paths may be implemented using circuit components having a bandwidth that is lower than the data rate of the input signal, for example using CMOS transistors based on 65nm or 40nm node technology. The present inventors have recognized and appreciated that using lower bandwidth CMOS components operating at lower data rates reduces the overall electrical power consumption of the delay line compared to using a single high data rate delay line, among other benefits. Even though the number of components may be larger. The lower bandwidth component may be part of a delay circuit of a parallel delay line architecture.

The delay circuit is configured to apply a selective amount of delay to each of the split signals using a plurality of parallel delay paths, and combine the delayed split signals in a combiner to delay generating substantially the same delayed signal as the input signal based on the parallel split signals. The amount of delay can be programmed by using variable delay components in each parallel delay path.

In some embodiments, an input signal having a high data rate is split into two signals, each of the two signals having a data rate of substantially half of the input signal. For such signals, and assuming that the input signal edges may only be present at locations defined by the periodic clock, the minimum data edge spacing is twice the minimum data edge spacing of the input signal. For a sufficiently long random input signal, the average data rate of such a signal will converge to half the data rate of the input signal. However, the splitter circuit may be implemented using simple circuit components, and the instantaneous data rate of each split signal may vary over time based on the pattern of rising and falling edges in the input signal.

A delay circuit with low bandwidth components may be used to delay two separate signals that, when recombined into a full rate signal, produce a delayed version of the input signal. Such a delay signal may be generated with reduced electrical power consumption of the delay line relative to delay lines implemented in semiconductor technology, which delay lines delay full rate signals while providing an accurate amount of delay.

For the purpose of illustrating the circuit design of the delay line, a circuit is described herein that splits an input signal into two substantially half-rate signals. However, it should be understood that the delay line may be implemented with a circuit that splits the input signal into N parallel paths, each of which is delayed before being recombined into a delayed version of the input. For example, the double separation and combination may be repeated twice in a layered fashion, resulting in four parallel paths. As another example, compact, non-hierarchical circuits for separating and combining more than two signals may be used, and these are a natural generalization of the exemplary designs described below that will be recognized by those skilled in the art.

Any suitable method may be used to split the input signal into two low rate split signals. According to an aspect, a split circuit may be used to receive an input signal at an input and generate a first split signal and a second split signal at two outputs. In some embodiments, each of the first split signal and the second split signal comprises, on average, half of the amount of data edges in a given time period as compared to the input signal, and thus has a data rate of substantially half of the input signal.

Because the input signal typically includes a series of consecutive and alternating rising and falling edges, the present inventors have recognized and appreciated that one way to split the input signal into two half-rate split signals is to alternately generate rising/falling edges in the two split signals for each rising/falling edge received from the input signal. In one exemplary embodiment, the splitter circuit is configured to generate a first edge in the first split signal but not in the second split signal in response to receiving a rising edge in the input signal, and to generate a second edge in the second split signal but not in the first split signal in response to receiving a falling edge following the rising edge in the input signal. In practice, each of the data edges in the first split signal corresponds to a rising edge of the input signal, and each of the data edges in the second split signal corresponds to a falling edge of the input signal. Without wishing to be bound by a particular theory, the inventors have realized that the splitter circuit in the above exemplary embodiment effectively operates as an "inverted exclusive or gate" such that a logic high at the input corresponds to a logic high and a logic low at both outputs, and a logic low at the input corresponds to both outputs having the same polarity. It will be appreciated that in such an "inverted xor gate", the real table of inputs and two outputs of the splitter circuit is the same as the real table of xor gates, with the inputs of the splitter circuit corresponding to the xor gate outputs in the real table and the two outputs of the splitter circuit corresponding to the xor gate inputs in the real table. The present inventors have recognized and appreciated simple circuit designs that implement such an "inverted exclusive or gate". In some embodiments, the inverted exclusive-or gate design may be implemented with a small number of CMOS transistors. CMOS based delay line circuit designs can provide devices with compact footprint and small electrical power consumption.

The lower rate signals may be processed separately and then combined back to the full rate of the input signal in an exclusive or gate. In the example of a delay line, the processing of the low rate split signals may require delaying each signal by a variable amount.

According to an aspect of the application, the individually adjustable delays may be applied to the two split signals, for example by using two parallel delay paths connected to respective outputs of the splitter circuit. The two delay paths generate two respective delayed split signals that can be combined in a combiner circuit. The combiner circuit is configured to combine information carried within data edges in each of the delayed two lower data rate split signals to generate a delayed input signal having the same amount and relative timing of data edges as the input signal, but with a variable delay. In some embodiments, an exclusive or gate may be used within the combiner circuit, with both inputs configured to receive the delayed split signals and the output of the exclusive or gate configured to generate the delayed input signal.

According to another aspect of the present application, the amount of delay within each parallel delay path of the delay circuit may be offset by a calibration value to produce the amount of delay required to delay the input signal at the output of the combiner circuit relative to the original input signal.

Referring to the drawings, FIG. 1 is a schematic diagram of an exemplary embodiment of an automated test system to which a delay line architecture according to aspects of the present application may be applied. FIG. 1 shows a test system 10 containing a test computer 12 that controls a tester 16 to perform tests on a Device Under Test (DUT)20 in accordance with the methods disclosed herein. In some cases, tester 16 may be Automated Test Equipment (ATE) constructed using techniques known in the art. The DUT 20 may be any suitable device for testing. For example, the DUT 20 may be a semiconductor device. ATE 16 may include circuitry for generating and/or measuring a plurality of test signals 14 for DUT 20. ATE 16 may include multiple instruments configured to generate or measure different types of analog or digital signals. ATE 16 may include one or more timing generators configured to synchronize the generation of multiple test signals within different channels. In some implementations, ATE 16 may include a programmable delay line for delaying a signal that controls each of a plurality of timing signals for each of a plurality of test signals, as described in detail below.

It should be understood that FIG. 1 is a greatly simplified illustration of an automated test system. For example, although not shown, test system 10 may include control circuitry that controls the operation of instruments within ATE 16. Additionally, the test system 10 may include processing circuitry to process the measurements and determine whether the DUT 20 is operating properly. Furthermore, although FIG. 1 shows a scenario in which a single DUT 20 is being tested, test system 10 may be configured to test multiple devices. Regardless of the number of instruments or other components that generate or measure test signals and the number of devices under test, test system 10 may include signal-passing components that route signals between DUT 20 and instruments within ATE 16.

Further, it should be understood that the other components shown are exemplary and not limiting. For example, although test computer 12 is shown in FIG. 1 as a Personal Computer (PC), it should be understood that the test computer may be implemented using any suitable computing device, such as a mobile device or a computer workstation. The test computer 12 may be connected to a network and may be capable of accessing resources and/or communicating with one or more other computers connected to the network via the network.

Fig. 2 is a schematic diagram illustrating a delay line circuit for delaying a signal according to some aspects of the present disclosure. As shown in fig. 2, a delay line circuit 200 is provided to receive an input signal 102 having a plurality of rising/falling edges and to generate a delayed signal 106 substantially identical to the input signal 102 with a programmable delay based on parallel split signals. The delay line circuit 200 may be used at any desired location within a test system, including within pin electronics. The input signal 102 may be a high frequency edge signal generated within a timing generator. Since there may be multiple edges for each channel and for multiple channels in a pin electronics chip, there may be multiple copies of the delay line circuit 200 in a pin electronics chip. Thus, implementing a delay line with compact, low cost, and low power circuitry (e.g., CMOS) that can operate in the Gbps range may provide desirable characteristics for a test system. The design as described herein enables these characteristics of the test system.

In the schematic shown in fig. 2, splitter circuit 120 receives input signal 102 at input 122 and at corresponding output 124₁-124_NTo generate N split signals 104₁-104_NWherein N is an integer. According to some embodiments, the separation signal 104₁-104_NHas a lower data rate than the data rate in the input signal 102. Delay circuit 230 receives split signal 104₁-104_NAnd generates a delayed signal 106, which is the input signal 102 with the delay. The delayed signals 106 have substantially identical data edges, where the relative timing between the data edges is substantially the same as the input signal 102, but the timing of each data edge is offset by a predetermined delay.

According to an aspect of the present application, input signal 102 may be a digital data stream having a data rate of 5Gbps, 20Gbps, 1Gbps to 100Gbps, or 5Gbps to 50Gbps, although it should be understood that aspects of the techniques disclosed herein may be used with digital data streams having any bandwidth. The delay line circuit 200 is configured as a high speed delay line circuit. As a specific example, the data rate may be 10 Gbps. N split signals 104₁-104_NHas a corresponding data rate that is lower than the data rate of the input signal 102.

In some embodiments, delay circuit 230 includes N delay paths 230₁-230_NAnd a combiner circuit 240. Delay path 230₁-230_NEach of which receives a respective split signal 104₁-104_NApplying an adjustable amount of delay and generating a corresponding delayed separation signal 204₁-204_N. As described above, the adjustable delay may comprise a programmable delay, such as may be applied by a timing generator based on programming in a pattern generator. The programmed delay may be offset by a calibration value that is determined as part of a calibration routine to compensate for variations in propagation delay of different signal paths within the test system. In some embodiments, delay path 230₁-230_NEach delay path in (a) may be individually delayedRising and falling edges of signals passing late through it. Such a configuration can provide accurate delay for circuits with asymmetric rise and fall times. Delay path 230₁-230_NEach delay path in (a) may be implemented by suitable techniques known in the art to apply an adjustable amount of delay to a signal propagating therein.

The combiner 240 receives the N delayed split signals 204₁-204_NAnd separates the signals 204 based on the N delays₁-204_NA delayed signal 106 is generated.

According to an aspect, because the signal 104 is split₁-104_NHas a lower data rate than the input signal 102, so low bandwidth components may be used in the delay circuit 230 and calibrated at a lower data rate than the input signal 102. Accordingly, embodiments of the present application may provide high accuracy in delaying high speed signals. In one non-limiting example, for 10Gbps of input data, each of the delay paths may see a data rate of 5Gbps, and the Trailing Edge Error (TEE) of the delay line may be less than 10 ps. Another advantage is reduced electrical power consumption using components that operate at a lower bandwidth than the data rate of the input signal.

Another advantage is modularity. Because the delay line includes lower bandwidth components, in some embodiments, a delay line operating on a high data rate input signal may include parallel modules that are themselves delay lines, but are configured to operate on a lower data rate input signal. For example, a 10Gbps delay line may split an input signal into two half-rate split signals having a 5Gbps data rate, and include two parallel 5Gbps sub-delay lines of any suitable design to delay the respective half-rate split signals before combining the results into a delayed version of the 10Gbps input signal. Such modularity may simplify the circuit design of the high-speed delay line.

Fig. 3 is a schematic diagram illustrating an exemplary implementation of the delay line circuit shown in fig. 2 with two separate signals and two delay paths according to some embodiments. As shown in FIG. 3, the delay line circuit 300 isIs arranged to receive the input signal d _1 and to generate a delayed signal d _2 which is substantially identical to the input signal d _1 with the delay. Divider circuit 320 receives input signal d _1 at input 322 and at corresponding output 324₁And 324₂Two separate signals xr and xf are generated. Delay circuit 330 includes two delay paths 330₁And 330₂And an exclusive or gate 340. Delay path 330₁And 330₂Each delay path in (a) receives a respective split signal xr and xf, applies an adjustable amount of delay and generates a respective delayed split signal xr 'and xf'. The xor gate 340 receives the two delayed separation signals xr 'and xf' and generates a delayed signal d _2 at the xor gate output based on the delayed separation signals xr 'and xf'.

According to an aspect of the present application, input signal d _1 may be a digital data stream having a data rate of 5Gbps, 10Gbps, 20Gbps, 1Gbps to 100Gbps, or 5Gbps to 50Gbps, although it should be understood that aspects of the techniques disclosed herein may be used with digital data streams having any bandwidth. Each of the two split signals xr and xf has a respective data rate that is lower than the data rate of the input signal d _ 1. In some embodiments, xr and xf are half rate signals having a data rate that is substantially half the data rate in d _ 1. In one non-limiting example, d _1 has a data rate of 10Gbps, while xr and xf have a data rate of 5 Gbps.

In some embodiments, splitter circuit 320 is configured to operate as an "inverted exclusive or gate" such that a logic high at input 322 corresponds to two outputs 324₁And 324₂One logic high and one logic low at, and the logic low at input 322 corresponds to two outputs 324 having the same polarity₁And 324₂And both. It should be appreciated that in such a configuration, the splitter circuit 320 is at two outputs 324₁、324₂And the real table between the single input 322 would map (00,01,10,11) to (0,1,1, 0). When the input switches between 0 and 1, both outputs change state, 1 bit at a time. For example, for each edge transition, the splitter circuit 320 may be weighted by (0,0), (0,1), (1,0)The complex sequence goes through the output state (xr, xf), returns to (0,0) and repeats the pattern.

Exemplary embodiments of the splitter circuit 320 and the relationship between signal waveforms at the input and output of the splitter circuit 320 will be discussed in detail below with respect to fig. 4 and 5.

Fig. 4 is a schematic diagram illustrating an exemplary implementation of a splitter circuit employing two D latches, according to some embodiments. As shown in fig. 4, splitter circuit 420 has an input 422 and two outputs 424₁And 424₂. The divider circuit 420 includes two D latches 430 and 450. The first D-latch 430 has a first clock input 431, a first latch D-input 432, and a first latch Q-output 433. The second D-latch 450 has a second clock input 451, a second latch D-input 452, and a second latch Q-output 453. The two D-latches 430 and 450 are connected in series with the second latch D-input 452 connected to the first latch Q-output 433. The second latch Q output 453 is inverted and then connected to the first latch D input 432. The clocks of the two D-latches 430 and 450 are out of phase, with a first clock input 431 connected to the input 422 and a second clock input 451 configured to receive the inverted signal from the input 422. Output 424₁Is connected to the second latch Q output 453, and 424₂Connected to the first latch Q output 433.

The divider circuit 420 shown in fig. 4 is a modified D flip-flop (DFF), referred to as D2 FF. Input 422 is the clock of D2FF, output 424 is the Q output of D2FF, and has a D input of D2FF at 423. DFFs are flip-flops consisting of D-latches triggered by two edges of an out-of-phase clock. At the rising edge of the clock, the input data is latched in the first latch, while the second latch provides the same data to the output, i.e. starts tracking its input data. On the falling edge of the clock, the latched data from the first latch is latched into the second latch, and the first latch begins to track the input data. When the above sequence repeats in the DFF, output 424₁(Q) remains constant until the next clock rising edge. Divider circuit 420 is D2FF, with output 424₁(Q) is inverted and connected to the first432(D) is input and acts as a toggle flip-flop (TFF). When TFF is clocked, the output Q is the divided by 2 version of the clock. For a given clock mode, two output Q modes are possible, depending on the initial state of the TFF node, where the two possible Q modes are inverted from each other.

Transistor level circuits for D-latches and inverters are known in the art. Such components may be relatively simple to implement, including using CMOS transistors. The transistor level schematic of the D-latch may comprise, for example, about 10 transistors. The inverter can be implemented with as few as two transistors. Optionally and for example in a differential circuit, the inverter may be implemented by swapping the positive and negative leads without using any transistors. The divider circuit 420 may thus be implemented with a total of 20-25 transistors, and may be easy to implement and consume low power.

Referring back to FIG. 3, when splitter circuit 320 is implemented as D2FF 420 clocked at 422 by input signal D _1, its output 424₁(Q) will contain half of the edge of the input signal d _ 1. According to some aspects, because splitter circuit 420 is a positive edge triggered DFF, output 324 is₁Any data edge (falling or rising) in the signal xr at (Q) corresponds to a rising d _1 edge. At the same time, the output 324₂(D') is output 324₁A falling clock (d _1) edge preview of a rising clock (d _1) edge in (Q). It should be appreciated that the output 324₂The signal xf at (D') has an edge (rising or falling) for any falling D _1 edge. Thus, d _1 is split into two half-rate signals xr and xf, each having half the amount of data edges during the same time period as compared to d _ 1.

Still referring to FIG. 3, because the data edges in signal xr correspond only to rising d _1 edges, and the data edges in signal xf correspond only to falling d _1 edges, it should be understood that rising (falling) xr edges occur only when xf is low (high). Thus, when the split signals xr and xf are at delay paths 330, respectively₁And 330₂Where intermediate delays are made to delay the split signals xr 'and xf', the split signals xr and xf may be combined in exclusive-or gate 340 to generateIs a delayed signal d _2, which is a delayed version of the original input signal d _ 1. Thus, in delay path 330₁After a first amount of time has been spent, each input signal d _1 rising edge causes an edge in xr, which in turn causes an edge in xr ', and in response, xor gate 340 will generate a rising output edge for the xr' edge that corresponds to the original rising edge in d _ 1. Similarly, in delay path 330₂After a second amount of time, each input signal d _1 falling edge causes a falling output edge. In practice, edges in the delayed signal d _1 correspond to corresponding edges in the input signal d _ 1. According to another aspect, the first and second delay amounts applied to xr and xf may be calibrated to adjust the relative timing of the data edges in d _2 to match the data edges in the input signal d _1, as discussed in more detail below with respect to fig. 6 and 7.

Fig. 5 illustrates a series of signal waveforms representing different operating states of the splitter circuit 420 shown in fig. 3 and 4, according to some embodiments. Waveform 500 represents a time line of the input signal d _1 received at input 422 to splitter circuit 420. Waveforms 510a-510c represent the response of the input signal d _1 at the output 424 of the splitter circuit 420₁And 424₂The two resulting split signals xr and xf and the time line of the delayed signal d _2 at the output of the xor gate 340. Waveforms 520a-520c represent alternative timelines of separating signals xr, xf, and d _2 in response to input signal d _ 1. Although the data edges in waveforms 500, 510a-510c, and 520a-520c are aligned in time as shown in FIG. 5, it should be understood that such alignment is simplified for illustration purposes only, and that the data edges in separate signals xr, xf, and d _2 will be affected by transmission delays, and in the case of d _2, delay path 330₁And 330₂Adding additional delay time.

From the initial states at xr and xf, D2FF 420 has two alternative startup modes in response to the data edge received from D _1 at input 422. As shown in FIG. 5, waveforms 510a-510c represent a first pattern in which a rising edge 501 in d _1 causes xr to flip from logic low to logic high with rising edge 511, while rising edge 503 in d _1 causes a falling edge 513 in xr. In an alternative pattern shown by waveforms 520a-520c, rising edge 501 in d _1 causes xr to flip from logic high to logic low with falling edge 521, while rising edge 503 in d _1 causes rising edge 523 in xr. It should be understood that the two alternative waveforms of xr are inverted from each other, and that the falling/rising edge in xr always corresponds to the rising edge in d _ 1. It should also be appreciated from waveforms 510a-510c and 520a-520c that xf remains at a constant logic level in response to a rising edge in d _1, without any data edges.

The other split signal xf is inverted in response to a falling edge in the input signal d _ 1. As shown by waveforms 510a-510c in FIG. 5, falling edge 502 in d _1 causes xf to flip from logic low to logic high with rising edge 512, while falling edge 504 in d _1 causes falling edge 514 in xf. In an alternative pattern shown by waveforms 520a-520c, falling edge 502 in d _1 causes xf to flip from logic high to logic low with falling edge 522, while rising edge 504 in d _1 causes rising edge 524 in xf. It should be understood that the two alternative waveforms of xf are inverted with respect to each other, and that the falling/rising edge in xf always corresponds to the falling edge in d _ 1. It should also be appreciated from waveforms 510a-510c and 520a-520c that xr remains at a constant logic level in response to a falling edge in d _1, without any data edges.

It should be understood that as shown in FIG. 5, when only one of xr and xf is at logic high, d _1 is at logic high, and when both of the two outputs have the same polarity, d _1 is at logic low. It should be understood that the real tables of xr, xf and d _1 map (00,01,10,11) in xr, xf to (0,1,1,0) in d _1, which is the real table of the exclusive or gate. Thus, splitter circuit 420 may be considered an "inverted exclusive or gate".

It should also be appreciated that as shown in FIG. 5, each of xr and xf includes half the number of data edges in a given time period as compared to input signal d _1, and thus the separation signals xr and xf may be considered half-rate separation signals. The interval between adjacent data edges is also longer in xr, xf than in d _ 1. In some embodiments, the data edges in the input signal d _1 may be separated by a Unit Interval (UI) that is the duration of a data period. For example, in fig. 5, edges 501 and 502 in d _1 are separated by one UI, while in each of the half-rate separation signals xr and xf, the separation between data edges is never closer than the two original UIs.

Referring back to FIG. 3, the split signals xr and xf are combined in XOR gate 340 before being combined to generate the delayed signal d _2 at the output, the split signals xr and xf being in respective delay paths 330₁、330₂Of the individual delays. As shown in FIG. 5, in waveforms 510a-510c, output signal d _2 has rising edges 531 and 533 corresponding to the original rising edges 501 and 503. Specifically, rising edge 531 is based on rising edge 511 in xr and may be referred to as xr _ r, while rising edge 533 in d _2 is based on falling edge 513 in xr and may be referred to as xr _ f. The falling edge 532 in d _2 corresponds to the falling edge 502 in d _1 and is referred to as xf _ r because it is an xf-based rising edge 512. The falling edge 534 in d _2 corresponds to the falling edge 504 in d _1 and is referred to as xf _ f because it is xf-based falling edge 514. The waveforms 520a-520c generally illustrate the correspondence between the data edges of d _2 and d _1, xr, and xf in an alternative mode and are not discussed in detail.

According to an aspect of the present application, an advantage of delaying a signal using the techniques described herein is an improved rise/fall deviation (RFS) range. RFS is the difference between the rising edge propagation delay and the falling edge propagation delay. In an operation known as rise/fall deskew (RFD), a circuit may be used to adjust the relative delay between a rising edge and a falling edge in a signal. RFD may be used, for example, to alter the width of a single pulse within a signal stream. According to one aspect, the delay path 330 in the delay line architecture 300 shown in FIG. 3₁、330₂Each delay path in (a) may be used to perform RFD within itself. For example and referring to waveforms 510a-510c in FIG. 5, first delay path 330₁Can be used to perform RFD on xr by adjusting rising/falling edges 511 and 513 within xr, while the second delay path 330₁RFD may be performed on xf to adjust rising/falling edges 512 and 514. Thus, as shown in FIG. 5, because the splitter circuit 320 splits the dataThe number of paths doubles from one full rate data path to two half rate data paths, so two delay paths 330₁、330₂Adjustment of the relative delay timing of the four rising/falling edges xr _ r, xr _ f, xf _ r and xf _ f may be provided. Therefore, the range of RFS control in a circuit such as the splitter circuit 320 is increased. For example, the circuit may perform rise/rise deskew (RRD) to determine the path length by using the first delay path 330 on xr₁RFD in (1) adjusts the delay timing of xr _ r and xr _ f to adjust the relative delay between the even and odd rising edges of d _ 2. Similarly, a second delay path 330 on xf may be used₂RFD in (1) performs fall/fall deskew (FFD) on d _ 2.

According to one embodiment, the input signal d _1 is a 10Gbps signal and the two split signals are half-rate 5Gbps signals. A delay line according to aspects of the present application may have an RFD (e.g., xr _ r or xr _ f vs. xf _ r or xf _ f edge deskew) range between-500 ps and 500 ps. The delay line may have an RRD (e.g., xr _ r vs. xr _ f edge deskew) range between-200 ps and 200 ps. The delay line may have an FFD (e.g., xf _ r vs. xf _ f edge deskew) range between-200 ps and 200 ps. The RFD range is particularly large since the xr line processes all rising edges of the input signal and xf processes all falling edges of the input signal, essentially ranging from minus the xr delay line range to plus the xf delay line range when pulse broadening is counted as positive RFD.

An aspect of the present application relates to a method of calibrating parallel delay paths within a delay line, such as delay line 300 shown in fig. 3. It should be understood from fig. 5 that there may be two boot modes depending on the initial state of xr and xf at initial power-up or boot. It should be understood from FIG. 5 that based on the initial startup mode of xr or xf, no special measurement or "startup" is required, as any first d _1 edge received in splitter circuit 420 will result in an edge on xr or xf according to one of waveforms 510a-510c or 520a-520c, and the delay line will generate a delayed signal d _2 with the same edge as d _1, regardless of the startup mode. Even the first edge after start-up is properly processed.

According to an aspect, the delay line 300 may be calibrated while considering its two start-up modes. As shown by waveforms 510a-510c and 520a-520c in FIG. 5, the two start modes exchange the history of successive rising output edges and similarly the history of output falling edges. For example, in the first start-up mode shown by waveforms 510a-510c, two consecutive rising edges 531, 533 in the output signal d _2 correspond to xr _ r, followed by xr _ f. In contrast, in the second start-up mode shown by waveforms 520a-520c, the successive rising edges 541, 543 in the output signal d _2 correspond first to xr _ f, followed by xr _ r. Edges xr _ r and xr _ f both contribute to rising edges in output signal d _2, but act as xr delay path 330₁An ascending edge or a descending edge. Therefore, it is necessary to adjust the delay path 330₁And 330₂All four edges xr _ r, xr _ f, xf _ r and xf _ f are calibrated so that the splitter circuit start-up mode does not affect the timing calibration of the resulting output signal d _ 2.

An exemplary method for calibrating each of the four edges xr _ r, xr _ f, xf _ r and xf _ f will now be discussed with reference to fig. 6. Fig. 6 illustrates a series of signal waveforms representing different operating states during a calibration method according to some embodiments. Fig. 6 shows a waveform 600 of an input signal d _1 with rising/falling edges switched at line data intervals.

To calibrate xr _ r and xr _ f, tuning involves a first delay path 330₁While monitoring the output delay signal d _2, the adjustable delay of the propagation of the rising and falling edges in (1). In some embodiments, the delayed separation signal xf' may be set at a constant level to allow for calibration xr. Waveforms 610a-610c show that when xf 'is forced to logic low, combiner exclusive-or gate 340 combines rising edge xr _ r with xf' to generate rising edge 611 in d _ 2. Thus, the rising edge 611 measured in d _2 represents the rising edge xr _ r through the first delay path 330 based on xr₁Is delayed. To calibrate the rising edge xr _ r, the delay path 330 may be adjusted₁Until the rising edge 611 monitored in d _2 is at the desired predetermined timing. According to delay path 330₁Any suitable method may be used to adjust the amount of propagation delay at its rising edge. In one example, the control signal may be sent to the delay path 330₁To indicate a change in the amount of rising edge delay. The desired predetermined timing of the rising edge 611 in d _2 can be a set amount of delay time compared to a known reference (e.g., the initial rising edge 601), but it should be understood that any reference timing can be used to calibrate the desired timing of the rising edge 611. In one example, the calibration may be relative, i.e., for each edge type (such as xr _ r), the delay setting in the delay path may be adjusted so that the monitored d _2 edge is at a value set relative to the reference delay line. The reference delay line settings may be individually calibrated by one or more external connections to the delay line circuit (e.g., by connecting to an external signal generator and oscilloscope).

Other unique edge types in the delay line may be similarly calibrated using the methods described above with respect to the calibration of the rising edge xr _ r in xr. By setting xf' to a constant logic high, as shown by waveforms 620a-620c in FIG. 6, splitter circuit 420 is forced to operate in a manner similar to the alternative startup mode shown by waveforms 520a-520c of FIG. 5. The measured rising edge 613 in d _2 represents the falling edge xr _ f passing through the first delay path 330 based on the falling edge of xr₁Is delayed. To calibrate the falling edge xr _ f, the delay path 330 may be adjusted₁Until the rising edge 613 monitored in d _2 is at the desired predetermined timing.

Similarly, for calibration purposes, for the second delay path 330₂The delayed separation signal xr' may be set to a constant logic high (for calibrating xf _ r, see waveforms 630a-630c) or a constant logic low (for calibrating xf _ r, see waveforms 640a-640c) for the falling edge delay and rising edge delay of the propagation of xf in (e). To calibrate xf _ r, delay path 330 may be adjusted₂Until the monitored falling edge 632 in d _2 is at the desired predetermined timing. To calibrate xf _ f, the delay path 330 may be adjusted₂Until the rising edge detected in d _2 is reachedThe edge 644 is at the desired predetermined timing.

According to an aspect of the present application, the full-rate delay line may be calibrated by separately calibrating the two half-rate delay lines. Fig. 7 is a schematic diagram of a delay line 700 with a feedback path for calibration. In delay line 700, a splitter circuit 720 receives a full-rate input signal d _1 and generates two corresponding parallel delay paths 730₁And 730₂The two half-rate split signals xr and xf of medium delay. The delayed separation signals xr 'and xf' at the outputs of the delay paths are combined in combiner exclusive-or gate 740 to generate the delayed signal d _ 2. Feedback path 750 connects the output of exclusive or gate 740 to two delay paths 730₁And 730₂To monitor the output signal during calibration of the delay path using, for example, the calibration method described above in connection with fig. 6.

In some embodiments, feedback path 750 includes a loop frequency (RLF) box. The RLF block includes a ring oscillator circuit formed by closing an inversion loop around a plurality of delay elements. Variations in the delay of the loop element will result in variations in frequency, allowing accurate measurement of the timing delay. An exemplary RLF implementation is described in detail in U.S. patent No. 9147620, which is incorporated herein by reference in its entirety. FIG. 7 shows a half-rate delay path 730₁、730₂Is connected to the feedback path 750 to allow the RLF signal to be inserted to calibrate the half rate delay path. A control unit 752 is provided for inserting the RLF signal into the respective delay path 730₁、730₂Into the two drv _ dd x { r, f } sub-line inputs.

Having thus described aspects of at least one embodiment of this invention, it is to be appreciated various alterations, modifications, and improvements will readily occur to those skilled in the art.

For example, the separator is shown as a bi-directional separator. For an N-way splitter, the splitter may function similarly, distributing each rising edge and falling edge to N parallel paths, with each application of a rising edge or falling edge to a path resulting in a state change within that path. N-phase dividers, where N may be greater than two, are known in the art and will be an exemplary generalization of the two-phase divider we focus on in this specification. It will be used as an N-way "inverse xor" and at the line exit the signal may be combined with an N-way xor circuit, as is also known in the art.

Such alterations, modifications, and improvements are intended to be part of this disclosure, and are intended to be within the spirit and scope of the invention. Moreover, while advantages of the invention are indicated, it should be understood that not every embodiment of the technology described herein will include every described advantage. Some embodiments may be unable to implement any of the features described as advantageous herein, and in some cases, one or more of the features may be implemented to implement additional embodiments. Accordingly, the foregoing description and drawings are by way of example only.

The various aspects of the present invention may be used alone, in combination, or in a variety of configurations not specifically discussed in the embodiments described in the foregoing and is therefore not limited in its application to the details and arrangement of components set forth in the foregoing description or illustrated in the drawings. For example, aspects described in one embodiment may be combined in any manner with aspects described in other embodiments.

Additionally, the invention may be embodied as a method, and examples thereof have been provided. The operations performed as part of the method may be ordered by any suitable means. Thus, embodiments may be constructed in which operations are performed in an order different than illustrated, which may include performing certain operations concurrently, even though the operations are illustrated as sequential operations in various exemplary embodiments.

Such alterations, modifications, and improvements are intended to be part of this disclosure, and are intended to be within the spirit and scope of the invention. Moreover, while advantages of the invention are indicated, it is to be understood that not every embodiment of the invention will include every described advantage. Some embodiments may not implement any of the features described as being advantageous herein and in some cases. Accordingly, the foregoing description and drawings are by way of example only.

Use of ordinal terms such as "first," "second," "third," etc., in the claims to modify a claim element does not by itself connote any priority, precedence, or order of one claim element over another or the temporal order in which acts of a method are performed, but are used merely as labels to distinguish one claim element having a certain name from another element having a same name (but for use of the ordinal term) to distinguish the claim elements.

Also, the phraseology and terminology used herein is for the purpose of description and should not be regarded as limiting. The use of "including," "comprising," or "having," "containing," "involving," and variations thereof herein, is meant to encompass the items listed thereafter and equivalents thereof as well as additional items.