阅读说明：本技术 一种时序单元建立时间的测量方法和测量电路 (Method and circuit for measuring time sequence unit establishing time ) 是由 彭敏强 于 2020-05-29 设计创作，主要内容包括：本申请提出一种时序单元建立时间的测量方法和测量电路。该测量方法适用于时序单元建立时间的测量电路,该测量方法包括：分别确定时钟信号的第一周期值、第二周期值和第三周期值,其中,第一周期值为在第一测试路径下待测时序单元正确接收时钟信号的临界周期,第二周期值为在第二测试路径下延迟检测模块正确接收时钟信号的临界周期,第三周期值为在第三测试路径下延迟检测模块正确接收时钟信号的临界周期；根据第一周期值、第二周期值和第三周期值确定时序单元的建立时间。(The application provides a measuring method and a measuring circuit for time sequence unit establishing time. The measuring method is suitable for a measuring circuit of time sequence unit establishing time, and comprises the following steps: respectively determining a first period value, a second period value and a third period value of the clock signal, wherein the first period value is a critical period for the timing sequence unit to be tested to correctly receive the clock signal under the first test path, the second period value is a critical period for the delay detection module to correctly receive the clock signal under the second test path, and the third period value is a critical period for the delay detection module to correctly receive the clock signal under the third test path; and determining the setup time of the timing unit according to the first period value, the second period value and the third period value.)

1. A measuring method of time sequence unit establishing time is characterized in that the measuring method is suitable for a measuring circuit of the time sequence unit establishing time, the measuring circuit comprises a clock signal generating module, a first selecting module, a second selecting module, a delay detecting module, a data signal transmission module, a clock signal transmission module, a time sequence unit to be tested and a control module, the control module controls the first selecting module and the second selecting module to form a first testing path, a second testing path and a third testing path, the first testing path consists of the clock signal generating module, the data signal transmission module, the clock signal transmission module, the time sequence unit to be tested and the control module, the second testing path consists of the clock signal generating module, the delay detecting module, the data signal transmission module and the control module, the third test path is composed of the clock signal generation module, the delay detection module, the clock signal transmission module and the control module;

the method comprises the following steps:

respectively determining a first period value, a second period value and a third period value of a clock signal, wherein the first period value is a critical period for the timing unit under test to correctly receive the clock signal under the first test path, the second period value is a critical period for the delay detection module to correctly receive the clock signal under the second test path, and the third period value is a critical period for the delay detection module to correctly receive the clock signal under the third test path;

and determining the setup time of the timing unit according to the first period value, the second period value and the third period value.

2. The method of claim 1, wherein the setup time of the sequential cell is equal to the sum of the first period value and the third period minus the second period value.

3. The method of claim 1, wherein the determining a period value of the clock signal, the period value being any one of the first period value, the second period value, and the third period value, comprises:

determining N critical period test values;

and determining the period value of the clock signal according to the N critical period test values.

4. The method of claim 3, wherein the determining N critical cycle test values comprises:

s1, determining the critical period estimation range of the clock signal;

s2, determining the first step length;

s3, testing the right interval value of the critical period estimation range and the left interval value of the critical period estimation range according to the first step length in sequence until the time sequence unit to be tested or the delay detection module correctly receives the clock signal, and recording the period of the clock signal at the current moment as a first critical period test value;

repeating the steps S1-S3 for N-1 times to respectively obtain a second critical period test value, a third critical period test value, … and an Nth critical period test value.

5. The method of claim 4, wherein determining the predicted range of critical periods of the clock signal comprises:

acquiring an expected value of a critical period of the clock signal;

determining a period step, wherein the period step comprises a plurality of preset time windows;

and sequentially testing from small to large according to the period step length, taking the difference between the test value when the test value of the critical period of the clock signal is inconsistent with the expected value of the critical period for the first time and the period step length as the left interval value of the critical period estimated range, and taking the sum of the test value when the test value of the critical period of the clock signal is inconsistent with the expected value of the critical period for the first time and the period step length as the right interval value of the critical period estimated range.

6. The method of claim 4, wherein the first step size is determined according to a length of time that the clock signal is jittered.

7. A measuring circuit for time sequence unit establishing time is characterized by comprising a clock signal generating module, a first selecting module, a second selecting module, a delay detecting module, a data signal transmission module, a clock signal transmission module, a time sequence unit to be detected and a control module;

the clock signal generation module is electrically connected with the first selection module, the delay detection module and the control module respectively; the delay detection module is electrically connected with the first selection module, the second selection module and the control module respectively; the first selection module is electrically connected with the control module, the data signal transmission module and the clock signal transmission module respectively; the second selection module is electrically connected with the control module, the data signal transmission module and the clock signal transmission module respectively; the data signal transmission module is respectively and electrically connected with the time sequence unit to be tested and the control module, the clock signal transmission module is respectively and electrically connected with the time sequence unit to be tested and the control module, and the time sequence unit to be tested is electrically connected with the control module;

the control module is used for controlling the first selection module and the second selection module to form a first test path, a second test path and a third test path so as to determine the establishment time of the time sequence unit based on the first test path, the second test path and the third test path, wherein the first test path is composed of the clock signal generation module, the data signal transmission module, the clock signal transmission module, the time sequence unit to be tested and the control module, the second test path is composed of the clock signal generation module, the delay detection module, the data signal transmission module and the control module, and the third test path is composed of the clock signal generation module, the delay detection module, the clock signal transmission module and the control module.

8. The circuit for measuring the setup time of a timing unit according to claim 7, wherein the clock signal generating module comprises a clock frequency modulation unit and a clock pulse control unit, the clock frequency modulation unit is electrically connected to the clock pulse control unit, the clock pulse control unit is electrically connected to the delay detection module and the first input terminal of the first selection module, respectively, and the control module is electrically connected to the clock frequency modulation unit and the clock pulse control unit, respectively.

9. The circuit for measuring the setup time of a timing unit according to claim 7, wherein the delay detection module comprises a first transmission register and a receiving register, wherein a first input terminal of the first transmission register is electrically connected to the clock signal generation module, a second input terminal of the first transmission register is input with an external data signal, and an output terminal of the first transmission register is electrically connected to a second input terminal of the first selection module;

the first input end of the receiving register is electrically connected with the clock signal generating module, the second input end of the receiving register is electrically connected with the output end of the second selecting module, and the output end of the receiving register is electrically connected with the control module.

10. The circuit for measuring the setup time of a timing unit according to claim 9, wherein the data signal transmission module comprises a second sending register, a first input terminal of the second sending register is electrically connected to the output terminal of the first selection module, a second input terminal of the second sending register is used for inputting an external data signal, and an output terminal of the second sending register is electrically connected to the second input terminal of the second selection module and the second input terminal of the timing unit to be measured, respectively.

11. The circuit for measuring the setup time of a sequential cell according to claim 10, wherein the data signal transmission module further comprises a first buffer module, an input terminal of the first buffer module is electrically connected to an output terminal of the second sending register, and an output terminal of the first buffer module is electrically connected to the second input terminal of the second selection module and the second input terminal of the sequential cell to be tested, respectively;

the clock signal transmission module comprises a second buffer module, the input end of the second buffer module is electrically connected with the output end of the first selection module, and the output end of the second buffer module is respectively electrically connected with the first input end of the second selection module and the first input end of the time sequence unit to be detected.

12. The sequential cell setup time measurement circuit of claim 11,

when the control module controls the first input end of the first selection module to be closed and the second input end of the first selection module to be opened, and the first input end and the second input end of the second selection module are both opened, the first test path is formed;

when the control module controls the first input end of the first selection module to be opened and the second input end of the first selection module to be closed and controls the first input end of the second selection module to be opened and the second input end of the second selection module to be closed, the second test path is formed;

and when the control module controls the first input end of the first selection module to be opened and the second input end to be closed and controls the first input end of the second selection module to be closed and the second input end to be opened, the third test path is formed.

Technical Field

The present application relates to the field of measurement technology for digital integrated circuits, and for example, to a method and a circuit for measuring a setup time of a sequential cell.

Background

The time for establishing the time sequence unit is one of the important factors influencing the stable transmission of signal data, and when the time sequence unit library is designed, the accurate measurement of the time for establishing the time sequence unit directly influences the performance, the production and the manufacture of the chip. In the prior art, the establishment time is usually measured equivalently by a clock phase fine adjustment method or a plurality of buffers as a minimum measurement scale. However, these methods have many disadvantages, such as limited by the small adjustable range of clock phase and the delay of buffer, the difference between the measured clock path and data path, and the performance of the difference is more obvious under different test voltages, thereby causing the measurement error of the timing unit setup time to be very large.

Disclosure of Invention

In view of this, embodiments of the present application provide a method and a circuit for measuring a setup time of a timing unit, so as to improve measurement accuracy of the setup time of the timing unit and meet performance requirements of a chip.

The embodiment of the application provides a measuring circuit for establishing time of a time sequence unit, which comprises a clock signal generating module, a first selecting module, a second selecting module, a delay detecting module, a data signal transmission module, a clock signal transmission module, a time sequence unit to be measured and a control module;

the clock signal generation module is electrically connected with the first selection module, the delay detection module and the control module respectively; the delay detection module is electrically connected with the first selection module, the second selection module and the control module respectively; the first selection module is electrically connected with the control module, the data signal transmission module and the clock signal transmission module respectively; the second selection module is electrically connected with the control module, the data signal transmission module and the clock signal transmission module respectively; the data signal transmission module is respectively and electrically connected with the time sequence unit to be tested and the control module, the clock signal transmission module is respectively and electrically connected with the time sequence unit to be tested and the control module, and the time sequence unit to be tested is electrically connected with the control module;

the control module is used for controlling the first selection module and the second selection module to form a first test path, a second test path and a third test path so as to determine the establishment time of the time sequence unit based on the first test path, the second test path and the third test path, wherein the first test path is composed of the clock signal generation module, the data signal transmission module, the clock signal transmission module, the time sequence unit to be tested and the control module, the second test path is composed of the clock signal generation module, the delay detection module, the data signal transmission module and the control module, and the third test path is composed of the clock signal generation module, the delay detection module, the clock signal transmission module and the control module.

The embodiment of the application also provides a method for measuring the time for establishing the time sequence unit, which is suitable for a circuit for measuring the time for establishing the time sequence unit, wherein the circuit comprises a clock signal generation module, a first selection module, a second selection module, a delay detection module, a data signal transmission module, a clock signal transmission module, a time sequence unit to be tested and a control module, the control module controls the first selection module and the second selection module to form a first test path, a second test path and a third test path, the first test path consists of the clock signal generation module, the data signal transmission module, the clock signal transmission module, the time sequence unit to be tested and the control module, and the second test path consists of the clock signal generation module, the delay detection module, the clock signal transmission module, the time sequence unit to be tested and the control module, The third test path consists of the clock signal generation module, the delay detection module, the clock signal transmission module and the control module;

the method comprises the following steps:

respectively determining a first period value, a second period value and a third period value of a clock signal, wherein the first period value is a critical period for the timing unit under test to correctly receive the clock signal under the first test path, the second period value is a critical period for the delay detection module to correctly receive the clock signal under the second test path, and the third period value is a critical period for the delay detection module to correctly receive the clock signal under the third test path;

and determining the setup time of the timing unit according to the first period value, the second period value and the third period value.

With regard to the above embodiments and other aspects of the present application and implementations thereof, further description is provided in the accompanying drawings description, detailed description and claims.

Drawings

FIG. 1 is a diagram illustrating a timing unit setup time in the prior art;

FIG. 2 is a schematic diagram of a circuit for measuring a setup time of a sequential cell according to an embodiment of the present disclosure;

FIG. 3 is a schematic diagram of another circuit for measuring the setup time of a sequential cell according to an embodiment of the present disclosure;

fig. 4 is a flowchart of a method for measuring a time sequence unit setup time according to an embodiment of the present application;

FIG. 5 is a flowchart of a method for determining a period value of a clock signal according to an embodiment of the present disclosure;

FIG. 6 is a flowchart of a method for determining test values of N critical periods according to an embodiment of the present disclosure;

fig. 7 is a flowchart of a method for determining an estimated critical period range of a clock signal according to an embodiment of the present disclosure.

Detailed Description

Hereinafter, embodiments of the present application will be described with reference to the drawings. In the present application, the embodiments and features of the embodiments may be arbitrarily combined with each other without conflict.

FIG. 1 is a diagram illustrating a timing unit setup time in the prior art. Referring to fig. 1, the setup time (tsu: setup time) of a timing unit (e.g., a flip-flop) refers to the time that a data signal needs to be stable before the rising edge of a clock signal of the timing unit arrives. If the settling time tsu, which is the minimum settling time, is not sufficient, data will not be able to be stably driven into the flip-flop on this clock rising edge.

In the prior art, the setup time of the timing unit can be obtained by simulation by a spice tool when the unit library is designed, but the setup time is only a theoretical calculation value, if the theoretical calculation value is larger than an actual value in a chip, unnecessary difficulty is aggravated for rear-end timing convergence, and if the theoretical calculation value is smaller, a timing problem may occur after the chip is produced, and the chip cannot reach an actual working frequency, so that the value between the theory and the actual value of the setup time is very important to keep consistency after the design of the timing unit library is completed. To ensure that the actual value of the setup time is consistent with the theoretical value, a measurement verification of the setup time is usually required.

In a conventional technical solution, a method for measuring setup time based on fine adjustment of clock phase is proposed, for example, two clocks with phase deviation after fine adjustment are respectively used as clock and data to be sent to a time sequence unit to be measured for setup time violation identification through fine adjustment of clock phase, so as to determine setup time of the time sequence unit, but the measurement accuracy itself is limited by the minimum step with adjustable clock phase, and the clocks have differences on different transmission paths, and the differences are different in performance under different voltages, and the setup time error is very large.

In another conventional technical solution, it is proposed to use a buffer (buffer) with a smaller delay as the minimum measurement scale, and construct different number of buffers for the clock and data paths of the timing unit, so as to determine how many minimum measurement scale buffers the setup time is equivalent to, where the accuracy of the method is also limited by the delay of the buffer as the minimum measurement scale, and there is also a difference between the measured clock and data paths, and the difference is significantly increased under different voltages, resulting in a very large measurement result error.

In view of this, the present application provides a measurement circuit and a measurement method for a setup time of a timing unit, which first control a first selection module and a second selection module through a control module to form a first test path, a second test path and a third test path, then respectively determine a critical period (denoted as a first period value) for a clock signal to be correctly received by the timing unit under test in the first test path, a critical period (denoted as a second period value) for a delay detection module to correctly receive the clock signal in the second test path, a critical period (denoted as a third period value) for a delay detection module to correctly receive the clock signal in the third test path, and finally determine the setup time of the timing unit according to the first period value, the second period value and the third period value. Therefore, the timing unit setup time is determined only by the first period value, the second period value and the third period value, and is not limited by the clock phase adjustment range and the buffer delay, and the problem of large measurement error caused by large difference of different test voltages is solved, so that the measurement accuracy is improved.

In an implementation manner, fig. 2 is a schematic structural diagram of a measurement circuit for establishing time of a timing unit according to an embodiment of the present application, and referring to fig. 2, the measurement circuit includes a clock signal generation module 110, a first selection module 120, a second selection module 130, a delay detection module 140, a data signal transmission module 150, a clock signal transmission module 160, a timing unit 170 to be tested, and a control module 180;

the clock signal generating module 110 is electrically connected to the first selecting module 120, the delay detecting module 140 and the control module 180, respectively; the delay detection module 140 is electrically connected to the first selection module 120, the second selection module 130 and the control module 180, respectively; the first selection module 120 is electrically connected with the control module 180, the data signal transmission module 150 and the clock signal transmission module 160 respectively; the second selection module 130 is electrically connected with the control module 180, the data signal transmission module 150 and the clock signal transmission module 160 respectively; the data signal transmission module 150 is respectively and electrically connected with the time sequence unit 170 to be tested and the control module 180, the clock signal transmission module 160 is respectively and electrically connected with the time sequence unit 170 to be tested and the control module 180, and the time sequence unit 170 to be tested is electrically connected with the control module 180;

the control module 180 is configured to control the first selection module 120 and the second selection module 130 to form a first test path, a second test path, and a third test path, so as to determine the setup time of the timing unit based on the first test path, the second test path, and the third test path, where the first test path is composed of the clock signal generation module 110, the data signal transmission module 150, the clock signal transmission module 160, the timing unit 170 to be tested, and the control module 180, the second test path is composed of the clock signal generation module 110, the delay detection module 140, the data signal transmission module 150, and the control module 180, and the third test path is composed of the clock signal generation module 110, the delay detection module 140, the clock signal transmission module 160, and the control module 180.

In one embodiment, the first selection module 120 is configured to control one of the clock signal generation module 110 and the delay detection module 140 to be connected to the data signal transmission module 150 and the clock signal transmission module 160, respectively. The second selection module 130 is used for controlling one of the data signal transmission module 150 and the clock signal transmission module 160 to be connected with the delay detection module 140. For example, when the control module 180 controls the first selection module 120 to control the signal generation module 110 to be connected to the data signal transmission module 150 and the clock signal transmission module 160, respectively, the test circuit enters a critical point test mode of the time setup time of the timing unit to be tested, i.e., a first test path is formed by the clock signal generation module 110, the data signal transmission module 150, the clock signal transmission module 160, the timing unit to be tested 170, and the control module 180.

When the control module 180 controls the first selection module 120 to control the delay detection module 140 to be connected to the data signal transmission module 150 and the clock signal transmission module 160, and controls the second selection module 130 to control one of the data signal transmission module 150 and the clock signal transmission module 160 to be connected to the delay detection module 140, the test circuit enters a delay comparison mode between a clock signal transmission path and a data signal transmission path, wherein the data signal transmission path is a second test path composed of the clock signal generation module 110, the delay detection module 140, the data signal transmission module 150 and the control module 180, and the clock signal transmission path is a third test path composed of the clock signal generation module 110, the delay detection module 140, the clock signal transmission module 160 and the control module 180.

In an embodiment, fig. 3 is a schematic structural diagram of another timing unit setup time measurement circuit provided in this embodiment of the present application, and referring to fig. 3, the clock signal generation module 110 includes a clock frequency modulation unit 111 and a clock pulse control unit 112, the clock frequency modulation unit 111 is electrically connected to the clock pulse control unit 112, the clock pulse control unit 112 is electrically connected to the delay detection module 140 and the first input end a1 of the first selection module 120, respectively, and the control module 180 is electrically connected to the clock frequency modulation unit 111 and the clock pulse control unit 112, respectively.

In an embodiment, the clock frequency modulation unit 111 may be a PLL (Phase Locked Loop) used as a clock source, and has high clock frequency precision and stability, small jitter, and fine frequency adjustment. The clock control unit 112 may be an OCC circuit (on-chip-clock) for outputting a clock signal.

In an embodiment, referring to fig. 3, the delay detection module 140 includes a first transmission register 141 and a receiving register 142, wherein a first input terminal of the first transmission register 141 is electrically connected to the clock signal generation module 110, a second input terminal of the first transmission register 141 inputs the external data signal data1, and an output terminal of the first transmission register 141 is electrically connected to the second input terminal a2 of the first selection module 120; a first input terminal of the receiving register 142 is electrically connected to the clock signal generating module 110, a second input terminal of the receiving register 142 is electrically connected to an output terminal of the second selecting module 130, and an output terminal of the receiving register 142 is electrically connected to the control module 180.

In an embodiment, the first sending register 141 is used for testing the start point of data signal transmission of the circuit under the second test path and the third test path, and the receiving register 142 is used for testing the end point of data signal transmission of the circuit under the second test path and the third test path. For example, in the second test path, the control module 180 controls the second input terminal a2 of the first selection module 120 to be connected, that is, the output terminal of the first transmission register 141 of the delay detection module is connected to the data signal transmission module 150 and the clock signal transmission module 160, respectively, and the control module 180 also controls the second input terminal B2 of the second selection module 130 to be connected to the receiving register 142 of the delay detection module 140, that is, the second test path composed of the clock signal generation module 110, the first transmission register 141, the data signal transmission module 150, the receiving register 142 and the control module 180 is formed. During testing in the second testing path, the clock signal output by the clock signal generating module 110 is input to the first input terminal of the first transmitting register 141, the external data signal data1 is input to the second input terminal of the first transmitting register 141, and the external data signal data1 is output from the first transmitting register 141, passes through the data signal transmission module 150, and is finally transmitted to the receiving register 142. In the third test path, the control module 180 controls the second input terminal a2 of the first selection module 120 to be connected, that is, the output terminal of the first transmission register 141 of the delay detection module is respectively connected to the data signal transmission module 150 and the clock signal transmission module 160, and the control module 180 also controls the first input terminal B1 of the second selection module 130 to be connected to the receiving register 142 of the delay detection module 140, that is, a third test path composed of the clock signal generation module 110, the first transmission register 141, the clock signal transmission module 160, the receiving register 142, and the control module 180 is formed. During testing in the third testing path, the clock signal output by the clock signal generating module 110 is input to the first input terminal of the first transmitting register 141, the external data signal data1 is input to the second input terminal of the first transmitting register 141, and the external data signal data1 is output from the first transmitting register 141, and is finally transmitted to the receiving register 142 through the clock signal transmitting module 160.

In an embodiment, referring to fig. 3, the data signal transmission module 150 includes a second sending register 151, a first input terminal of the second sending register 151 is electrically connected to the output terminal of the first selection module, a second input terminal of the second sending register 151 inputs the external data signal data1, and output terminals of the second sending register 151 are electrically connected to a second input terminal of the second selection module 130 and a second input terminal of the timing unit 170 to be tested, respectively.

In an embodiment, the external data signal data1 is input to the second input terminal of the second sending register 151 for providing a data signal for the first test path test. For example, in the first test path, the control module 180 controls the first input terminal a1 of the first selection module 120 to be turned on, that is, the output terminal of the signal generation module 110 is respectively connected to the data signal transmission module 150 and the clock signal transmission module 160, so as to form a first test path composed of the clock signal generation module 110, the data signal transmission module 150, the clock signal transmission module 160, the timing unit 170 to be tested, and the control module 180. During testing in the first testing path, the clock signal output by the clock signal generating module 110 is input to the first input terminal of the second transmitting register 151, the external data signal data1 is input to the second input terminal of the second transmitting register 151, and the external data signal data1 is output from the second transmitting register 151 and then is transmitted to the timing unit 170 to be tested.

In an embodiment, referring to fig. 3, the reset terminal of the second sending register 151, the reset terminal of the first sending register 141, the reset terminal of the receiving register 142, and the reset terminal of the timing unit 170 to be tested are all electrically connected to the control module 180, and the control module 180 can control the reset and clear functions of the second sending register 151, the first sending register 141, the receiving register 142, and the timing unit 170 to be tested.

In an embodiment, referring to fig. 3, the data signal transmission module 150 further includes a first buffer module b1, an input terminal of the first buffer module b1 is electrically connected to an output terminal of the second sending register 151, and an output terminal of the first buffer module b1 is electrically connected to a second input terminal of the second selection module 130 and a second input terminal of the timing unit 170 to be tested, respectively; the clock signal transmission module 160 includes a second buffer module B2, an input terminal of the second buffer module B2 is electrically connected to an output terminal of the first selection module 120, and an output terminal of the second buffer module B2 is electrically connected to a first input terminal B1 of the second selection module 130 and a first input terminal of the timing unit 170 to be tested, respectively.

In an embodiment, the second transmission register 151 and the first buffer module b1 constitute a data signal transmission path, and the first buffer module b1 is used to adjust a delay time of the data transmission module 150. The second buffer module b2 forms a clock signal transmission path, and the second buffer module b2 is used to adjust the delay time of the clock signal transmission module 160. It should be noted that the number of the first buffer modules b1 of the data signal transmission path may include a plurality, and the number of the second buffer modules b2 of the clock signal transmission path may also include a plurality, and the specific number thereof may be set according to an actual test requirement, and the specific number is not specifically limited herein.

In one embodiment, a first test path is formed when the control module 180 controls the first input A1 of the first selection module 120 to be closed and the second input A2 to be open, and the first input B1 and the second input B2 of the second selection module 130 to be both open; a second test path is formed when the control module 180 controls the first input A1 of the first selection module 120 to be open and the second input A2 to be closed, and the first input B1 of the second selection module 130 to be open and the second input B2 to be closed; a third test path is formed when the control module 180 controls the first input A1 of the first selection module 120 to be open and the second input A2 to be closed, and the first input B1 of the second selection module 130 to be closed and the second input B2 to be open.

In an embodiment, when the control module 180 controls the first input terminal a1 of the first selection module 120 to be closed and the second input terminal a2 to be open, and the first input terminal B1 and the second input terminal B2 of the second selection module 130 to be open, that is, the delay detection module is disconnected from the data signal transmission module 150 and the clock signal transmission module 160, and the output terminal of the signal generation module 110 is respectively connected to the data signal transmission module 150 and the clock signal transmission module 160, a first test path is formed by the clock signal generation module 110, the data signal transmission module 150 (including the data signal transmission path formed by the second sending register 151 and the first buffer module B1), the clock signal transmission module 160 (including the clock signal transmission path formed by the second buffer module B2), the timing unit under test 170, and the control module 180. In the first test path, the data signal transmission path has a fixed delay, and the delay value is denoted as T _ data, and the clock signal transmission path also has a fixed delay, and the delay value is denoted as T _ clk. During testing in the first test path, the clock signal output by the clock signal generation module 110 is input to the first input terminal of the second transmission register 151, the external data signal data1 is input to the second input terminal of the second transmission register 151, and the clock signal frequency can be adjusted by the clock signal generation module 110, generally, when the clock signal frequency is relatively slow, the external data signal data1 can be captured by the timing sequence unit 170 to be tested after being output by the second transmission register 151, but when the clock signal frequency reaches a certain threshold, a setup violation occurs, the timing sequence unit 170 to be tested cannot capture the data signal sent by the second transmission register 151, at this time, a critical Period of the clock signal where the setup violation occurs is recorded as Period _ su, and the critical Period satisfies the following conditions:

T_data-T_clk＝Period_su-Tsu

wherein Tsu is the setup time of the timing sequence unit to be tested.

When the control module 180 controls the first input terminal a1 of the first selection module 120 to be open and the second input terminal a2 to be closed, the first input terminal B1 of the second selection module 130 to be open and the second input terminal B2 to be closed, that is, the first transmission register 141 and the data signal transmission module 150 (including the data signal transmission path composed of the second transmission register 151 and the first buffer module B1) are made to be on, and the data signal transmission module 150 and the reception register 142 are made to be on, a second test path composed of the clock signal generation module 110, the first transmission register 141, the second transmission register 151, the first buffer module B1, the reception register 142 and the control module 180 is formed. During testing under the second test path, the clock signal output by the clock signal generation module 110 is input to the first input terminal of the first transmission register 141, the external data signal data1 is input to the second input terminal of the first transmission register 141, and the frequency of the clock signal can be adjusted by the clock signal generation module 110, generally, when the frequency of the clock signal is relatively slow, the external data signal data1 is output by the first transmission register 141 and can be captured by the receiving register 142 after being output by the second transmission register 151 and the first buffer module b1, and when the frequency of the clock signal is relatively fast, the transmission rate of the data signal can be increased, but when the frequency of the clock signal is too fast, the receiving register 142 cannot normally receive the data signal output by the first transmission register 141. The Period of the clock signal when the receiving register 142 can just receive the data signal when the frequency of the clock signal reaches a certain threshold value is a critical Period, and the critical Period is denoted as Period _ data.

When the control module 180 controls the first input terminal a1 of the first selection module 120 to be open and the second input terminal a2 to be closed, the first input terminal B1 of the second selection module 130 to be closed and the second input terminal B2 to be open, that is, the first transmission register 141 and the clock signal transmission module 160 (including the data signal transmission path formed by the second buffer module B2) are made to be on, and the clock signal transmission module 160 and the reception register 142 are made to be on, a third test path is formed by the clock signal generation module 110, the first transmission register 141, the second buffer module B2, the reception register 142 and the control module 180. During testing under the third test path, the clock signal output by the clock signal generation module 110 is input to the first input terminal of the first transmission register 141, the external data signal data1 is input to the second input terminal of the first transmission register 141, and the frequency of the clock signal can be adjusted by the clock signal generation module 110, generally, when the frequency of the clock signal is relatively slow, the external data signal data1 output by the first transmission register 141 and output by the second buffer module b2 can be captured by the receiving register 142, and when the frequency of the clock signal is relatively fast, the transmission rate of the data signal can be increased, but when the frequency of the clock signal is too fast, the receiving register 142 cannot normally receive the data signal output by the first transmission register 141. The Period of the clock signal at which the receiving register 142 can just receive the data signal when the frequency of the clock signal reaches a certain threshold is the critical Period, which is denoted as Period _ clk. Then, the critical Period _ data under the second test path and the Period _ clk under the third test path satisfy the following condition:

T_data-T_clk＝Period_data-Period_clk

then, combining the condition that the critical Period of the clock signal in which the setup violation occurs in the first test path is recorded as Period _ su, we can obtain:

T_su＝Period_su-(Period_data-Period-clk)

from this, the time sequence unit establishes the time T_suThe critical Period of the clock signal is recorded as Period _ su only when the timing sequence unit to be tested in the first test path is violated, the critical Period _ data of the clock signal when the delay detection module under the second test path can just normally receive the data signal is related to the critical Period _ clk of the clock signal when the delay detection module under the third test path can just normally receive the data signal, and the critical Period _ clk of the clock signal is related to the difference between the data signal transmission path and the clock signal transmission pathThe method has the advantages that the method is independent of the delay of the buffer and the test voltage, and can avoid the problem of larger measurement result error caused by the problems of difference of a data signal transmission path and a clock signal transmission path, delay of the buffer, large difference of different test voltages and the like in the prior art, so that the measurement precision of the set-up time of the time sequence unit to be measured can be improved.

In an implementation manner, fig. 4 is a flowchart of a method for measuring a time period of a time sequence unit, where the method for measuring a time period of a time sequence unit is applicable to a circuit for measuring a time period of a time sequence unit according to any embodiment of the present disclosure, and the circuit includes a clock signal generation module, a first selection module, a second selection module, a delay detection module, a data signal transmission module, a clock signal transmission module, a time sequence unit to be tested, and a control module, where the control module controls the first selection module and the second selection module to form a first test path, a second test path, and a third test path, where the first test path is composed of the clock signal generation module, the data signal transmission module, the clock signal transmission module, the time sequence unit to be tested, and the control module, and the second test path is composed of the clock signal generation module, the data signal transmission module, the clock signal transmission module, the time sequence unit to be tested, and the control module, The third test path consists of a clock signal generation module, a delay detection module, a clock signal transmission module and a control module;

referring to fig. 4, the measuring method includes the steps of:

s210, respectively determining a first period value, a second period value and a third period value of the clock signal, wherein the first period value is a critical period for the timing sequence unit to be tested to correctly receive the clock signal under the first test path, the second period value is a critical period for the delay detection module to correctly receive the clock signal under the second test path, and the third period value is a critical period for the delay detection module to correctly receive the clock signal under the third test path;

s220, determining the setup time of the timing unit according to the first period value, the second period value and the third period value.

In one embodiment, the setup time of the timing unit is equal to the first period value- (the second period value — the third period value).

In an embodiment, the period or frequency of the clock signal output by the clock signal generation module 110 may be controlled by the control module 180 to enable adjustment of the frequency of the clock signal in the first test path, the second test path, and the third test path.

In an example, with reference to fig. 4, it was determined that: in the first test path, when the timing unit to be tested is violated, the timing unit to be tested can capture the data signal sent by the second sending register 151 of the data signal transmission module 150, and the Period value of the clock signal, i.e. the first Period value Period _ su; in the second test path, the receiving register 142 can capture the Period value of the clock signal, i.e. the second Period value Period _ data, when the data signal outputted from the first sending register 141 of the delay detection module 140 via the data signal transmission module 150 is captured; in the third test path, the receiving register 142 can capture the Period value of the clock signal, i.e., the third Period value Period _ clk, when the data signal outputted from the clock signal transmission module 160 is transmitted from the first transmitting register 141 of the delay detection module 140. The first period value, the second period value, the third period value and the establishing time of the time sequence unit to be tested satisfy the following relations:

T_su＝Period_su-(Period_data-Period_clk)

therefore, the establishing time T of the time sequence unit to be tested can be determined_su。

In an implementation manner, fig. 5 is a flowchart of a method for determining a period value of a clock signal according to an embodiment of the present application, and the method may determine the period value of the clock signal according to the method described in fig. 5, where the period value is any one of a first period value, a second period value, and a third period value. The method for determining the period value of the clock signal comprises the following steps:

s310, determining N critical period test values;

s320, determining the period value of the clock signal according to the N critical period test values.

In an embodiment, the process of determining the first period value comprises: when the timing sequence unit to be tested is tested to be illegal in the first test path, the timing sequence unit to be tested can just capture the data signal sent by the second sending register 151 of the data signal transmission module 150, and the Period value of the clock signal obtains a critical Period test value Period _ su _ trigger _ 1. Repeating the above test N-1 times to obtain the critical period test values of N first period values. And averaging the critical period test values of the N first period values to obtain a first period value. The expression is as follows:

the Period _ su _ trigger _ i is a critical Period test value of the first Period value measured in the ith test experiment, and the Period _ su _ avg is an average value of the critical Period test values of the first Period values in the N test experiments.

In an embodiment, the process of determining the second period value comprises: the test receiving register 142 in the second test path can capture the Period value of the clock signal when the data signal transmitted from the first transmitting register 141 of the delay detection module 140 and outputted via the data signal transmission module 150 is captured, so as to obtain a critical Period test value Period _ data _ trigger _ 1. Repeating the above test N-1 times to obtain the critical period test values of N second period values. And averaging the critical period test values of the N second period values to obtain a second period value. The expression is as follows:

the Period _ data _ trigger _ i is a critical Period test value of the second Period value measured in the ith test experiment, and the Period _ data _ avg is an average value of the critical Period test values of the second Period values in the N test experiments.

In an embodiment, the process of determining the third cycle value comprises: in the third test path, when the test receiving register 142 just captures the data signal output by the clock signal transmission module 160 from the first sending register 141 of the delay detection module 140, the Period value of the clock signal obtains a critical Period test value Period _ clk _ trigger _ 1. Repeating the above test N-1 times to obtain the critical period test values of N third period values. And averaging the critical period test values of the N third period values to obtain a third period value. The expression is as follows:

the Period _ clk _ trigger _ i is a critical cycle test value of a third cycle value measured in the ith test experiment, and the Period _ clk _ avg is an average value of the critical cycle test values of the third cycle values in the N test experiments.

In an implementation manner, fig. 6 is a flowchart of a method for determining N critical cycle test values provided in an embodiment of the present application, and referring to fig. 6, the method for determining N critical cycle test values includes the following steps:

s410 and S1, determining the critical period estimation range of the clock signal;

s420, S2, determining a first step length;

s430 and S3, testing the right interval value of the critical period prediction range and the left interval value of the first step length direction critical period prediction range in sequence until the time sequence unit or the delay detection module to be tested correctly receives the clock signal, and recording the period of the clock signal at the current moment as a first critical period test value;

s440, repeating the steps S1-S3 for N-1 times, and respectively obtaining a second critical period test value, a third critical period test value, … and an Nth critical period test value.

In an embodiment, taking the determination of the N critical period test values of the first period value as an example, the process of determining the N critical period test values of the first period value includes: in the first test path, the clock signal generation module sends out a clock signal at a certain clock frequency, adjusts the frequency of the clock signal, tests the condition of violation of the time sequence unit to be tested at different clock frequencies, records the frequency or the Period of the clock signal when the time sequence unit to be tested violates, and finds out the approximate range of the critical Period of the time sequence unit to be tested, namely the critical Period estimation range F, which is marked as < Period _ gross-step _ p, Period _ gross + step _ p >. Then, a first step1 is determined, and the control module 180 changes the period of the clock signal outputted from the clock signal generating module 110 to test the violation of the sequential unit under test at each different clock cycle. Wherein, the period of the clock signal may be changed by: starting from the right interval value Period _ gross + step _ p of the critical Period estimation range F, testing the left interval value Period _ gross-step _ p of the critical Period estimation range F according to the first step1 in sequence until the time sequence unit to be tested correctly receives the clock signal, and recording the Period of the clock signal at the current moment as the first critical Period test value. And repeating the above process for N-1 times to obtain the second critical period test value, the third critical period test value, … and the Nth critical period test value. Similarly, N critical period test values for the second period value and N critical period test values for the third period value may be determined according to the method described above.

In an implementation manner, fig. 7 is a flowchart of a method for determining a predicted critical period range of a clock signal according to an embodiment of the present application, and referring to fig. 7, the method for determining the predicted critical period range of the clock signal includes the following steps:

s510, acquiring an expected value of a critical period of a clock signal;

s520, determining a period step, wherein the period step comprises a plurality of preset time windows;

s530, testing is sequentially carried out from small to large according to the period step size until the test value of the critical period of the clock signal is inconsistent with the expected value of the critical period for the first time, the difference between the test value and the period step size when the test value of the critical period of the clock signal is inconsistent with the expected value of the critical period for the first time is used as the left interval value of the critical period estimation range, and the sum of the test value and the period step size when the test value of the critical period of the clock signal is inconsistent with the expected value of the critical period for the first time is used as the right interval value of the critical period estimation range.

In an embodiment, taking the process of determining the predicted critical period range of the clock signal with the first period value as an example, the process of determining the predicted critical period range of the clock signal is as follows: first, the expected value of the critical period of the clock signal is obtained by theoretical calculation, for example, it can be obtained by simulation from a spice tool. Then, a period step2 is determined, where the period step2 is variable and includes a plurality of preset time windows of different periods, for example, the period step2 includes a plurality of unequal-sized durations, such as T1, T2, T3 … Tn, etc. Finally, the control module 180 changes the period of the clock signal output by the clock signal generation module 110, and tests the critical period of the clock signal when the timing unit under test in the corresponding clock signal period under the first test path is violated. Wherein, the period of the clock signal may be changed by: and sequentially changing the period of the clock signal according to the sequence of the preset time windows of the period step2 from small to large, and respectively testing until the test value of the critical period of the clock signal is inconsistent with the expected value of the critical period for the first time, taking the difference between the test value and the period step when the test value of the critical period of the clock signal is inconsistent with the expected value of the critical period for the first time as the left interval value of the critical period estimation range, and taking the sum of the test value and the period step when the test value of the critical period of the clock signal is inconsistent with the expected value of the critical period for the first time as the right interval value of the critical period estimation range. Similarly, the estimated critical period range of the clock signal with the second period value and the estimated critical period range of the clock signal with the third period value can be determined according to the method.

In one embodiment, the first step size is determined based on a length of time that the clock signal is jittered.

Generally, clock signals generated by clock sources generally have jitter phenomena, the jitter occurrence magnitude can have great difference due to different clock source qualities, and the jitter can affect the determination of the first period value, the second period value and the third period value of the clock signals. In order to eliminate or reduce the influence of clock jitter on the accuracy of the measurement result as much as possible, the first step length is determined according to the jitter generation time length of the clock signal. Assuming that the first step size is step1 and the time duration of the clock signal jittering is T _ jitter, the first step size can be determined according to the following formula,

step1＝T_jitter/M

wherein, M is an integer, the larger the value of M, the smaller the step length, the higher the fine tuning precision, and the better the effect of reducing the jitter influence.

The above description is only exemplary embodiments of the present application, and is not intended to limit the scope of the present application. In general, the various embodiments of the application may be implemented in hardware or special purpose circuits, software, logic or any combination thereof. For example, some aspects may be implemented in hardware, while other aspects may be implemented in firmware or software which may be executed by a controller, microprocessor or other computing device, although the application is not limited thereto.

The foregoing has provided by way of exemplary and non-limiting examples a detailed description of exemplary embodiments of the present application. Various modifications and adaptations to the foregoing embodiments may become apparent to those skilled in the relevant arts in view of the following drawings and the appended claims without departing from the scope of the invention. Therefore, the proper scope of the invention is to be determined according to the claims.