阅读说明：本技术 一种分时复用单ddr的sar成像数据处理系统 (SAR imaging data processing system of time-sharing multiplexing single DDR ) 是由 闵锐 李晋 黄太 徐浩典 余雷 曹宗杰 崔宗勇 于 2021-09-07 设计创作，主要内容包括：本发明属于雷达成像信号处理领域,具体的说是涉及一种分时复用单DDR的SAR成像数据处理系统。本发明包括数据采集前端、第一数据处理模块、第二数据处理模块、第一异步FIFO,第二异步FIFO、第三异步FIFO、数据通道选择器、DDR总线仲裁单元、DDR驱动单元以及一片DDR3SDRAM。本发明采用单片DDR3的时分复用方式,减少了存储器的个数,节省了FPGA的IO资源,降低了开发成本。(The invention belongs to the field of radar imaging signal processing, and particularly relates to an SAR imaging data processing system of time division multiplexing single DDR. The DDR SDRAM bus interface circuit comprises a data acquisition front end, a first data processing module, a second data processing module, a first asynchronous FIFO, a second asynchronous FIFO, a third asynchronous FIFO, a data channel selector, a DDR bus arbitration unit, a DDR drive unit and a piece of DDR3 SDRAM. The invention adopts the time division multiplexing mode of the single DDR3, reduces the number of the memories, saves the IO resources of the FPGA and reduces the development cost.)

1. A SAR imaging data processing system of time-sharing multiplexing single DDR comprises a data acquisition front end, a first data processing module, a second data processing module, a first asynchronous FIFO, a second asynchronous FIFO, a third asynchronous FIFO, a data channel selector, a DDR bus arbitration unit, a DDR drive unit and a piece of DDR3 SDRAM;

the DDR3 address space is divided into two contiguous storage areas: the DDR is a first storage area and a DDR second storage area, the DDR is subjected to time division multiplexing, under the control of a DDR bus arbitration unit, a data acquisition front end, a first data processing module and a second data processing module access the DDR3 in a time division mode according to a set time segment distribution mode, so that data transposition operation in echo data storage and processing processes is completed;

the DDR bus arbitration unit enables a corresponding FIFO enabling control end to gate one path of data through a data channel selector, and controls the DDR drive unit to access the DDR3 through a read-write control line and an address line; the DDR bus arbitration unit can be divided into four states in total: 1) the first state is that when the data acquisition front end and the first data processing module multiplex DDR3 in a time-sharing manner, the DDR3 interface is controlled to write data output by the data acquisition front end into a DDR3 first storage area; 2) the second state is that when the data acquisition front end and the first data processing module multiplex DDR3 in a time-sharing manner, the DDR3 interface is controlled to write data output by the first data processing module into a DDR3 second storage area; 3) the third state is that when the data acquisition front end and the second data processing module multiplex DDR3 in a time-sharing manner, the DDR3 interface is controlled to write data output by the data acquisition front end into the DDR3 first storage area; 4) the fourth state is that when the data acquisition front end and the second data processing module multiplex DDR3 in a time-sharing manner, the DDR3 interface is controlled to read data required by the second data processing module from the DDR3 second storage area;

the data acquisition front end writes data into a first DDR3 storage area according to a set address hopping sequence, the first data processing module writes the data into a second DDR3 storage area according to the set address hopping sequence, and the second data processing module reads radar echo data out of the second DDR3 storage area according to the set address hopping sequence; the initial address interval between the DDR3 first storage area and the DDR3 second storage area is the address length occupied by one frame data;

the data acquisition front end outputs data according to rows, and the time division multiplexing control unit writes the data into a DDR3 first storage area according to rows; when the DDR bus arbitration unit is in the first state and the third state, the DDR bus arbitration unit controls the DDR drive unit to write data output by the data acquisition front end into a DDR3 first storage area; the data written in the first storage area of the DDR3 is not read and used in the current operation period;

the first data processing module outputs data according to rows, and the time division multiplexing control unit generates write jump addresses to write the data into a DDR3 second storage area according to rows; when the DDR bus arbitration unit is in a second state, the DDR bus arbitration unit controls the DDR drive unit to write the data output by the first data processing module into a DDR3 second storage area;

the second data processing module time-sharing multiplexing control unit generates a read jump address to read data out of the DDR3 second storage area in columns; when the DDR bus arbitration unit is in the fourth state, the DDR bus arbitration unit controls the DDR drive unit to read out the data required by the second data processing module from the DDR3 second storage area, and the data are sent to the second data processing module through the third asynchronous FIFO.

2. The SAR imaging data processing system of claim 1, wherein the depth of the first asynchronous FIFO is greater than or equal to the number of data output by the data acquisition front-end module in a period of time when the first data processing module or the second data processing module accesses DDR 3; the depth of the second asynchronous FIFO is greater than or equal to the size of data output by the first data processing module in a period of time when the data acquisition front end accesses the DDR 3; the depth of the third asynchronous FIFO is larger than or equal to the difference value between the data volume written into the third asynchronous FIFO by the DDR bus arbitration unit in the fourth state and the data volume read out from the third asynchronous FIFO by the second data processing module.

Technical Field

The invention belongs to the field of radar imaging signal processing, and particularly relates to an SAR imaging data processing system of time division multiplexing single DDR.

Background

Synthetic Aperture Radars (SAR) have all-weather working characteristics and high-resolution imaging accuracy all day long, and play a great role in remote sensing mapping in cloudy and foggy areas, military reconnaissance, national economic construction and the like. In recent years, with the rapid development of the hardware manufacturing level, the design of the SAR real-time imaging system based on the FPGA is receiving more and more researches. In the SAR imaging signal processing process, the DDR is used for storing a large amount of data, so that the data reading and writing system of the time division multiplexing DDR is designed, the number of the used DDR3 can be reduced, occupation of an FPGA port is further reduced, and the radar miniaturization design is facilitated.

In the time-sharing multiplexing single DDR SAR imaging data processing system based on the FPGA, the access authority of three different data modules, namely a data acquisition front end, a first data processing module and a second data processing module, to DDR3 is controlled through a DDR bus arbitration unit. When the data module obtains the DDR3 access right, the DDR bus arbitration unit reads data from the corresponding FIFO and writes the data into the DDR3 or reads data from the DDR3 and writes the data into the FIFO. When the data module does not obtain the access right of the DDR3, the data acquisition front end and the first data processing module write data into the FIFO buffer, and the second data processing module reads the data which is written into the FIFO buffer by the DDR3 before from the FIFO.

When the data acquisition front end or the first data processing module does not have DDR3 access right, the data output by the data acquisition front end or the first data processing module is guaranteed to be cached in a limited FIFO depth; when the second data processing module has no DDR3 access right, data written into the FIFO is guaranteed to be buffered by a limited FIFO depth DDR 3.

To meet the above requirements when reading and writing data to DDR3, the data block outputs a data rate f_dDDR Access Peak data Rate f_pThe number x of consecutive write or read addresses needs to satisfy the following relationship:

at f_pAt 1600MHz, t_ckCorresponding to a clock period of 800M clocks. t is t_busyThe time that data cannot be written into the DDR3 or read out of the DDR3 in one state operation period of the DDR bus arbitration unit is represented, and the DDR3 line activation and page change time and the state switching occupation time are included. DDR3 row activation and page break time depends on the DDR3 chip model and the frequency of operation, and the state switch occupation time represents the time it takes for the DDR bus arbitration unit to switch from the current state to another state and then to the current state.

To utilize the burst (burst) transmission technique of DDR3, x needs to be a multiple of 8; to ensure that no DDR3 line boundaries are crossed when writing data to DDR3 a single time, x needs to be an integer power of 2.

Disclosure of Invention

The technical scheme of the invention is as follows:

the invention discloses a time-sharing multiplexing single DDR SAR imaging data processing system which comprises a data acquisition front end, a first data processing module, a second data processing module, a first asynchronous FIFO, a second asynchronous FIFO, a third asynchronous FIFO, a data channel selector, a DDR bus arbitration unit, a DDR drive unit and a piece of DDR3 SDRAM.

The DDR3 address space is divided into two contiguous storage areas: the invention adopts a group of DDR time-sharing multiplexing design, and under the control of a DDR bus arbitration unit, a data acquisition front end, a first data processing module and a second data processing module access a DDR3 in a time-sharing mode to complete the transposition operation of data in the echo data storage and processing process according to a certain time segment distribution mode.

The DDR bus arbitration unit enables a corresponding FIFO enabling control end to gate one path of data through a data channel selector, and controls the DDR drive unit to access the DDR3 through a read-write control line and an address line; the DDR bus arbitration unit can be divided into four states in total: 1) the first state is that when the data acquisition front end and the first data processing module multiplex DDR3 in a time-sharing manner, the DDR3 interface is controlled to write data output by the data acquisition front end into a DDR3 first storage area; 2) the second state is that when the data acquisition front end and the first data processing module multiplex DDR3 in a time-sharing manner, the DDR3 interface is controlled to write data output by the first data processing module into a DDR3 second storage area; 3) the third state is that when the data acquisition front end and the second data processing module multiplex DDR3 in a time-sharing manner, the DDR3 interface is controlled to write data output by the data acquisition front end into the DDR3 first storage area; 4) the fourth state is that when the data acquisition front end and the second data processing module multiplex DDR3 in a time-sharing mode, the DDR3 interface is controlled to read out data required by the second data processing module from the DDR3 second storage area.

The data acquisition front end writes data into a first DDR3 storage area according to a set address hopping sequence, the first data processing module writes the data into a second DDR3 storage area according to the set address hopping sequence, and the second data processing module reads radar echo data out of the second DDR3 storage area according to the set address hopping sequence; the initial address interval between the DDR3 first storage area and the DDR3 second storage area is the address length occupied by one frame data.

The data acquisition front end outputs data according to rows, and the time division multiplexing control unit writes the data into a DDR3 first storage area according to rows; when the DDR bus arbitration unit is in the first state and the third state, the DDR bus arbitration unit controls the DDR drive unit to write data output by the data acquisition front end into a DDR3 first storage area; in the invention, the data written in the first storage area of the DDR3 is not read and used in the current operation period.

The first data processing module outputs data according to rows, and the time division multiplexing control unit generates write jump addresses to write the data into a DDR3 second storage area according to rows. When the DDR bus arbitration unit is in the second state, the DDR bus arbitration unit controls the DDR drive unit to write the data output by the first data processing module into the DDR3 second storage area.

The second data processing module time-sharing multiplexing control unit generates a read jump address to read data out of the DDR3 second storage area in columns; when the DDR bus arbitration unit is in the fourth state, the DDR bus arbitration unit controls the DDR drive unit to read out the data required by the second data processing module from the DDR3 second storage area, and the data are sent to the second data processing module through the third asynchronous FIFO.

The SAR imaging data processing system with the time-division multiplexing single DDR is characterized in that the depth of the first asynchronous FIFO is more than or equal to the large number of data output by a data acquisition front-end module in a first data processing module or a time period of accessing DDR3 by 2; the depth of the second asynchronous FIFO is greater than or equal to the size of data output by the first data processing module in a period of time when the data acquisition front end accesses the DDR 3; the depth of the third asynchronous FIFO is larger than or equal to the difference value between the data volume written into the third asynchronous FIFO by the DDR bus arbitration unit in the fourth state and the data volume read out from the third asynchronous FIFO by the second data processing module.

The invention has the advantages that the invention adopts the time division multiplexing mode of the single DDR3, reduces the number of the memories, saves the IO (input/output) resource of the FPGA and reduces the development cost.

Drawings

FIG. 1 is a block diagram of an SAR imaging data processing system according to the present invention with a single DDR for time division multiplexing;

FIG. 2 is a data acquisition front end, first data processing module output data sequence in accordance with the present invention;

FIG. 3 shows an arrangement of data acquisition front-end data written into a DDR first storage area in the invention;

FIG. 4 shows an arrangement of writing data output by the first data processing module into the DDR second storage area in the present invention;

fig. 5 is a sequence of reading out data from the DDR second storage area by the second data processing module in the present invention.

Detailed Description

The technical scheme of the invention is explained in detail in the following with the accompanying drawings.

As shown in fig. 1, the SAR imaging data processing system with time division multiplexing and single DDR provided by the present invention includes a data acquisition front end, a first data processing module, a second data processing module, a first asynchronous FIFO, a second asynchronous FIFO, a third asynchronous FIFO, a data channel selector, a DDR bus arbitration unit, a DDR drive unit, and a piece of DDR3 SDRAM.

Examples

In this example, the FPGA selects an xc7v690tffg1761-3 chip from XILINX, and the model of the DDR3SDRAM chip is MT8KTF51264HZ-1G9 from Micron, and the burst transfer length (BL) is set to 8. The development environment is Vivado 2018.3 of XILINX, the DDR drive unit uses the MIG core provided by Vivado, the working clock is 800MHz, and the user clock is 200 MHz.

In the specific embodiment, the size of the radar echo data matrix is 8192 multiplied by 8192, the bit width of a single data is 64bits, and when the burst transmission length is set to 8, the bit width of the asynchronous FIFO data port needs to be set to 512bits, so that serial-to-parallel conversion is needed when the data acquisition front end and the first data processing module output data, and parallel-to-serial conversion is needed when the second data processing module reads data.

The front-end working clock of data acquisition is 100MHz, the module outputs data in sequence as shown in FIG. 2, and the module outputs 8192 data at each distance upward line by line, and writes the data into the first asynchronous FIFO after serial-parallel conversion.

The DDR bus arbitration unit reads data from the first asynchronous FIFO and writes the data into the DDR first storage area when the DDR bus arbitration unit is in a first state of writing the data output by the data acquisition front end into the DDR 3.

In this state, the arrangement of the DDR bus arbitration unit reading data from the first asynchronous FIFO and writing data into the DDR first storage area is shown in fig. 3:

the DDR bus arbitration unit generates the first write address variable with the initial value of 0, and each write of data with the length of 1 burst (a in FIG. 3)_1,1…a_1,8) Thereafter, i.e., 512bits wide data, the first write address variable is incremented by 8 (i.e., from a)_1,1Jump to a_1,9)；

Every 4 burst length data written (i.e. a)_1,1…a_1,32) Then, the DDR bus arbitration unit switches to the second state, and writes the data buffered in the second asynchronous FIFO by the first data processing module into the DDR3 second storage area. At the moment, the data output by the data acquisition front end is cached in the first asynchronous FIFO and waits for the next minuteTime multiplexed time periods are read.

The working clock of the first data processing module is 400MHz, the output data sequence of the module is shown in figure 2, and the module outputs 8192 data at each distance upwards row by row, and writes the data into the first asynchronous FIFO after serial-parallel conversion.

And the DDR bus arbitration unit reads data from the second asynchronous FIFO and writes the data into a DDR second storage area when the DDR bus arbitration unit is in a second state of writing the data output by the first data processing module into the DDR 3.

In this state, the arrangement of writing the output data of the first data processing module into the second storage area of the DDR3 is as shown in fig. 4:

the DDR bus arbitration unit generates a second write address variable start value equal to the echo data size of one frame, which is 67108964. Each time data of 1 burst length is written (a in fig. 4)_1,1…a_1,8) Thereafter, i.e., 512bits wide data, the second write address variable is incremented by 8 (i.e., from a)_1,1Jump to a_1,9)；

Each write of 16 burst length data (i.e. a)_1,1…a_1,128) Then, the DDR bus arbitration unit switches to the first state, and the data cached in the first asynchronous FIFO from the data acquisition front end is written into the DDR 3. At this time, the data output by the first data processing module is buffered in the second asynchronous FIFO, and the next time division multiplexing time period is waited for reading.

The double write DDR process described above is a loop, and the loop is repeated. The address jump law of the next cycle relative to the current cycle is as follows:

when the system is in the first state, the data addresses are kept continuous; when the system is in the second state, 16 burst length data are written (i.e. a)_1,1…a_1,128) Then, 1048576 is added to the second write address variable on the original basis, and the second write address variable corresponds to the first address of the next row of the DDR second storage area (a in FIG. 4)_1,129) (ii) a After each 1024 burst data writes (i.e. a)_1,1…a_1,8192) The second write address variable is subtracted 66060160 from the original to correspond to the first burst data (i.e., a) in the next range direction_2,1…a_2,8)。

According to this rule, when the first data processing module first writes all the frame data into the second storage area of the DDR3, the operating cycle in which the DDR bus arbitration unit switches between the first state and the second state ends, and the operating cycle in which the DDR bus arbitration unit switches between the third state and the fourth state is entered.

The DDR bus arbitration unit is in a third state of writing data output by the data acquisition front end into the DDR3, and reads the data out of the first asynchronous FIFO and writes the data into the DDR first storage area.

In this state, the data output by the front end of the DDR bus arbitration unit is continuously written into the DDR first storage area by the data of the DDR bus arbitration unit, and the change rule of the first write address variable is as follows:

adding 8 to the first write address variable on the original basis, namely adding 8 to the last burst data address of the write data in the first state; adding 8 to the first write address variable every time one burst length data, namely 512bits of bit width data, is written;

after 8 burst-length data are written, the DDR bus arbitration unit switches to the fourth state, and reads out the data in the DDR3 second storage area to the third asynchronous FIFO. At this time, the data output by the data acquisition front end is cached in the first asynchronous FIFO, and the next time division multiplexing time period is waited for reading.

And when the DDR bus arbitration unit is in a fourth state that the second data processing module reads the DDR3, the data is read from the DDR second storage area and written into the third asynchronous FIFO.

The second data processing module works at 400MHz, and since 8 data are read from the DDR3 second storage area at a time, and the data module 2 can only process one azimuth data at a time, the remaining 7 data which are not used currently need to be cached by using a cache in the second data processing module.

In this state, the arrangement of reading data from the DDR second storage area and writing data into the third asynchronous FIFO by the DDR bus arbitration unit is shown in fig. 5:

the DDR bus arbitration unit generates a read address variable with a starting value equal to the size of one frame of echo data, which is 67108964. Each readingOne burst length data (a in fig. 5)_1,1…a_1.8) Thereafter, i.e., 512bits wide data, the read address variable is incremented by 128 (i.e., from a)_1,1Jump to a_2,1)；

32 burst length data (i.e. a) per read_1,1…a_1,8、a_2,1…a_2,8、…、a_32,1…a_32,8) Then, the DDR bus arbitration unit switches to the second state, and the data cached in the first asynchronous FIFO from the data acquisition front end is written into the DDR 3. At this time, the data output by the second data processing module is buffered in the third asynchronous FIFO, and the next time division multiplexing time interval is waited for reading.

The read-write DDR process is a loop, and the loop is repeated. The address jump law of the next cycle to the current cycle is as follows:

when the system is in the third state, the data addresses are kept continuous; when the system is in the fourth state, every 32 burst length data (namely a) are read out_1,1…a_1,8、a_2,1…a_2,8、…、a_32,1…a_32,8) Then, adding 128 to the read address variable on the original basis; after each read of 8192 burst data (i.e. a)_1,1…a_1,8、a_2,1…a_2,8、…、a_8192,1…a_8192,8) Thereafter, the read address variable is decremented 1048440 (i.e., jumps to a)_1,9) (ii) a 131072 burst data (i.e. a) per read_1,1…a_1,128、a_2,1…a_2,128、…、a_8192,1…a_8192,128) Then, the read address variable is added with 8 (a in FIG. 5)_1,129)。

According to the rule, after the second data processing module reads all the frame data from the DDR3 second storage area, the switching operation cycle of the DDR bus arbitration unit between the third state and the fourth state is finished, and the state that the DDR is continuously accessed by the data acquisition front end is entered; and marking the end of the whole time division multiplexing period after the data acquisition front end writes all the data of one frame into the DDR first storage area.