阅读说明：本技术 集成式组合件和形成集成式组合件的方法 (Integrated assembly and method of forming an integrated assembly ) 是由 S·索尔斯 R·J·希尔 于 2021-04-26 设计创作，主要内容包括：本申请案涉及集成式组合件和形成集成式组合件的方法。一些实施例包含一种具有交替的绝缘层级与导电层级的竖直堆叠的集成式组合件。所述导电层级包含导电结构。沟道材料竖直地延伸通过所述堆叠。所述导电结构具有接近所述沟道材料的近侧区,且具有相比于所述近侧区更远离所述沟道材料的远侧区。所述绝缘层级在相邻导电结构的所述近侧区之间竖直地具有第一区,且在所述相邻导电结构的所述远侧区之间竖直地具有第二区。空隙是所述在绝缘层级内且横跨所述第一区和所述第二区的部分延伸。一些实施例包含形成集成式组合件的方法。(The present application relates to an integrated assembly and a method of forming an integrated assembly. Some embodiments include an integrated assembly having a vertical stack of alternating insulating levels and conductive levels. The conductive levels include conductive structures. Channel material extends vertically through the stack. The conductive structure has a proximal region proximate to the channel material and has a distal region further from the channel material than the proximal region. The insulating level has a first region vertically between the proximal regions of adjacent conductive structures and a second region vertically between the distal regions of the adjacent conductive structures. A void is the portion within the insulating level layer and extending across the first and second regions. Some embodiments include methods of forming an integrated assembly.)

1. An integrated assembly, comprising:

a vertical stack of alternating insulating levels and conductive levels; the conductive level comprises a conductive structure;

a channel material extending vertically through the stack; the conductive structure has a proximal region proximate to the channel material and has a distal region further from the channel material than the proximal region;

the insulating level having a first region vertically between the proximal regions of adjacent conductive structures and a second region vertically between the distal regions of the adjacent conductive structures;

a void within the insulating level layer and extending across portions of the first and second regions;

the insulating level includes an insulating liner along the proximal region of the conductive structure and not along the distal region of the conductive structure; the insulating liner has an outer surface on a side of the insulating liner opposite the conductive structure; the outer surface faces the void; and

an insulating material extending through the stack and directly along the distal region of the conductive structure; the insulating material covers ends of the voids and is not substantially along the outer surface of the insulating liner.

2. The integrated assembly of claim 1, further comprising:

a tunneling material adjacent to the channel material;

a charge storage material adjacent to the tunneling material; and

a high-k dielectric material between the charge storage material and the proximal region of the conductive structure.

3. The integrated assembly of claim 1, wherein the insulating material is not directly against the outer surface of the insulating liner.

4. The integrated assembly of claim 1, wherein the insulating liner comprises SiO, wherein the chemical formula indicates a majority component rather than a specific stoichiometry.

5. The integrated assembly of claim 1, wherein the insulating liner comprises silicon dioxide poisoned with one or more of: n, N dimethylaminotrimethylsilane, bis (N, N-dimethylamino) dimethylsilane, ethylenediamine, 1-trimethylsilylpyrrolidine, 1-trimethylsilylpyrrole, 3, 5-dimethyl-1-trimethylsilyl, and R1- (C-OH) -R2; wherein R1 and R2 are organic moieties.

6. The integrated assembly of claim 1, wherein the insulating liner comprises SiN, wherein the chemical formula indicates a majority component rather than a specific stoichiometry.

7. The integrated assembly of claim 1, wherein the insulating liner comprises SiON, wherein the chemical formula indicates a majority component rather than a particular stoichiometry.

8. The integrated assembly of claim 1, wherein the insulating material comprises one or more of SiO, SiN, and SiON; where the chemical formula indicates the major constituent rather than a specific stoichiometry.

9. The integrated assembly of claim 1, wherein each of the conductive structures includes a tungsten-containing core and a metal-nitride-containing liner along a periphery of the tungsten-containing core.

10. The integrated assembly of claim 9, wherein each of the metal nitride liners surrounds a proximal end of an associated one of the tungsten-containing cores and is such that a distal end of the associated one of the tungsten-containing cores is exposed; wherein each of the metal nitride liners includes, along a cross-section, a first surface directly against the associated one of the tungsten-containing cores and a second surface in opposing relation to the first surface; wherein the distal region of each of the conductive structures comprises:

a pair of exposed sections of the second surface of one of the metal-nitride-containing liners, one of the exposed sections of the pair of exposed sections being above the associated one of the tungsten-containing cores and the other one of the exposed sections of the pair of exposed sections being below the associated one of the tungsten-containing cores; and

an exposed distal end of the associated one of the tungsten-containing cores.

11. The integrated assembly of claim 10, wherein the insulating material is directly against the exposed section of the second surface of the metal-nitride-containing liner and directly against the exposed distal end of the tungsten-containing core.

12. The integrated assembly of claim 11, wherein the insulating liner is directly against a region of the second surface.

13. The integrated assembly of claim 12, wherein the void is within a four-sided area along the cross-section; wherein the insulating liner is along three of four sides of the four-sided area, and wherein the insulating material is along a fourth side of the four-sided area.

14. The integrated assembly of claim 9, wherein the metal-nitride-containing liner comprises titanium nitride.

15. The integrated assembly of claim 9, wherein the metal-nitride-containing liner comprises titanium nitride, and wherein the insulating liner comprises silicon dioxide.

16. The integrated assembly of claim 9, wherein the metal-nitride-containing liner comprises titanium nitride, and wherein the insulating liner comprises silicon dioxide poisoned with one or more of: n, N-dimethylaminotrimethylsilane, bis (N, N-dimethylamino) dimethylsilane, ethylenediamine, 1-trimethylsilylpyrrolidine, 1-trimethylsilylpyrrole, 3, 5-dimethyl-1-trimethylsilyl, and R1- (C-OH) -R2; wherein R1 and R2 are organic moieties.

17. A method of forming an integrated assembly, comprising:

forming a vertical stack of alternating first levels and second levels; the first level comprises a first material and the second level comprises a second material;

forming an opening to extend through the stack;

forming a charge storage material, a tunneling material and a channel material in the opening;

forming a slit to extend through the stack;

flowing an etchant into the slots to remove the second material and leave first voids between the first levels;

forming a conductive structure within the first void; the conductive structure has a proximal end adjacent the channel material and has a distal end adjacent the slit;

removing the first material to leave second voids between the conductive structures;

forming an insulating liner within the second void to line the second void, a region of the insulating liner being along the distal end of the conductive structure;

forming a sacrificial material within a lined second void and over the region of the insulating liner along the distal end of the conductive structure;

recessing the sacrificial material to expose the region of the insulating liner along the distal end of the conductive structure;

removing exposed regions of the insulating liner to expose the distal ends of the conductive structures;

removing the sacrificial material to reopen the second void; the reopened second void has an end region along the slit; and

forming an insulating material in the slit; the insulative material is selectively formed along the conductive material relative to the insulative liner and extends across the end regions of the reopened second voids.

18. The method of claim 17, further comprising forming a dielectric barrier material and a charge blocking material within the opening.

19. The method of claim 17, wherein the first material comprises silicon dioxide, and wherein the second material comprises silicon nitride.

20. The method of claim 17, wherein the sacrificial material comprises silicon.

21. The method of claim 20, wherein removing the sacrificial material utilizes tetramethyl ammonium hydroxide.

22. The method of claim 17, wherein the insulating liner comprises silicon dioxide.

23. The method of claim 17, wherein the insulating liner comprises silicon dioxide; wherein the insulating material comprises one or more of silicon dioxide, silicon oxynitride, and silicon nitride; and the method further comprises treating the insulating liner prior to forming the insulating material, the treating comprising exposing the insulating liner to one or more of: n, N-dimethylaminotrimethylsilane, bis (N, N-dimethylamino) dimethylsilane, ethylenediamine, 1-trimethylsilylpyrrolidine, 1-trimethylsilylpyrrole, 3, 5-dimethyl-1-trimethylsilyl, and R1- (C-OH) -R2; wherein R1 and R2 are organic moieties.

24. The method of claim 17, wherein each of the conductive structures comprises a metal-containing core and a metal-containing nitride liner along a periphery of the metal-containing core; and wherein the exposed distal end of the conductive structure comprises an exposed region of the metal-containing core and an exposed region of the metal-nitride-containing liner.

25. A method of forming an integrated assembly, comprising:

forming a vertical stack of alternating first levels and second levels; the first level comprises a first material and the second level comprises a second material;

forming an opening to extend through the stack;

forming a first liner within the opening to line the opening; the first liner has a first region along the first level and a second region along the second level;

forming a dielectric blocking material, a charge storage material, a tunneling material, and a channel material within the lined opening;

removing the second material to leave first voids between the first levels and expose the second region of the first liner;

removing the second region of the first liner;

forming a conductive structure within the first void after removing the second region of the first liner; the conductive structure has a proximal end adjacent the channel material and has a distal end in opposing relation to the proximal end;

removing the first material to leave second voids between the conductive structures;

lining the second void with an insulating liner having a region extending around the distal end of the conductive structure;

forming a sacrificial material within the lined second void and over the distal end of the conductive structure;

recessing the sacrificial material to expose the region of the insulating liner along the distal end of the conductive structure;

removing exposed regions of the insulating liner to expose the distal ends of the conductive structures;

removing the sacrificial material to open the second voids; and

after removing the sacrificial material, an insulating material is formed along the exposed distal end of the conductive structure and across an end of the second void to cover the end of the second void.

26. The method of claim 25, further comprising removing the first region of the first liner prior to forming the insulating liner within the second void.

27. The method of claim 25, wherein the insulating material is formed selectively along the conductive structure relative to the insulating liner.

28. The method of claim 25, wherein the insulating liner comprises one or more of SiO, SiN, and SiNO, wherein a chemical formula indicates a major component rather than a specific stoichiometry.

29. The method of claim 25, wherein the insulating liner comprises silicon dioxide.

30. The method of claim 29, wherein the insulating liner comprises silicon dioxide; wherein the insulating material comprises one or more of silicon dioxide, silicon oxynitride, and silicon nitride; and the method further comprises treating the insulating liner prior to forming the insulating material, the treating comprising exposing the insulating liner to one or more of: n, N-dimethylaminotrimethylsilane, bis (N, N-dimethylamino) dimethylsilane, ethylenediamine, 1-trimethylsilylpyrrolidine, 1-trimethylsilylpyrrole, 3, 5-dimethyl-1-trimethylsilyl, and R1- (C-OH) -R2; wherein R1 and R2 are organic moieties.

31. The method of claim 30, wherein the insulating material comprises silicon dioxide.

32. The method of claim 25, wherein the first liner is a carbonaceous material.

Technical Field

An integrated assembly (e.g., an integrated NAND memory). A method of forming an integrated assembly.

Background

The memory provides data storage for the electronic system. Flash memory is one type of memory and is used in large numbers in modern computers and devices. For example, modern personal computers may have the BIOS stored on a flash memory chip. As another example, it is increasingly common for computers and other devices to utilize flash memory in the form of a solid state drive in place of a traditional hard disk drive. As yet another example, flash memory is popular in wireless electronic devices because flash memory enables manufacturers to support new communication protocols as they become standardized and to provide manufacturers with the ability to remotely upgrade devices for enhanced features.

NAND may be the basic architecture of flash memory and may be configured to include vertically stacked memory cells.

Before describing NAND in detail, it may be helpful to describe the relationship of the memory arrays within an integrated arrangement more generally. FIG. 1 shows a block diagram of a prior art device 1000 including: a memory array 1002 having a plurality of memory cells 1003 arranged in rows and columns; and access lines 1004 (e.g., word lines to conduct signals WL0 through WLm); and a first data line 1006 (e.g., a bit line to conduct signals BL 0-BLn). Access line 1004 and first data line 1006 may be used to transfer information to memory cell 1003 and to transfer information from the memory cell 1003. Row decoder 1007 and column decoder 1008 decode address signals a0 through AX on address lines 1009 to determine which of memory cells 1003 to access. Sense amplifier circuit 1015 operates to determine the value of the information read from memory cell 1003. I/O circuitry 1017 transfers values of information between memory array 1002 and input/output (I/O) lines 1005. Signals DQ0 through DQN on I/O line 1005 may represent values of information read from memory cells 1003 or to be written into memory cells 1003. Other devices may communicate with device 1000 through I/O lines 1005, address lines 1009, or control lines 1020. Memory control unit 1018 is to control memory operations to be performed on memory cells 1003 and utilizes signals on control lines 1020. Device 1000 may receive supply voltage signals Vcc and Vss on first supply line 1030 and second supply line 1032, respectively. The device 1000 includes a selection circuit 1040 and an input/output (I/O) circuit 1017. Selection circuit 1040 may be responsive to signals CSEL 1-CSELn via I/O circuit 1017 to select signals on first data line 1006 and second data line 1013 that may represent values of information to be read from memory cell 1003 or programmed into memory cell 1003. Column decoder 1008 may selectively activate the CSEL 1-CSELn signals based on the A0-AX address signals on address lines 1009. Select circuit 1040 may select signals on first data line 1006 and second data line 1013 to enable communication between memory array 1002 and I/O circuit 1017 during read and program operations.

The memory array 1002 of FIG. 1 can be a NAND memory array, and FIG. 2 shows a schematic of a three-dimensional NAND memory device 200 that can be used with the memory array 1002 of FIG. 1. The device 200 includes multiple strings of charge storage devices. In the first direction (Z-Z'), each string of charge storage devices may include, for example, thirty-two charge storage devices stacked on top of each other, where each charge storage device corresponds to, for example, one row of thirty-two layers (e.g., layer 0 through layer 31). The charge storage devices of the respective strings may share a common channel region, such as a common channel region formed in a respective pillar of semiconductor material (e.g., polysilicon) around which the strings of charge storage devices are formed. In the second direction (X-X'), each first group, e.g., sixteen first groups, of the multiple strings may include, for example, eight strings sharing multiple (e.g., thirty-two) access lines (i.e., "global Control Gate (CG) lines," also referred to as word lines WL). Each of the access lines may couple a charge storage device within the layer. When each charge storage device includes a cell capable of storing two bits of information, the charge storage devices coupled by the same access line (and thus corresponding to the same layer) may be logically grouped into, for example, two pages, e.g., P0/P32, P1/P33, P2/P34, and so on. In a third direction (Y-Y'), each second group of the multiple strings, e.g., eight second groups, may comprise sixteen strings coupled by corresponding ones of the eight data lines. The size of a memory block may include 1,024 pages, and a total of about 16MB (e.g., 16WL × 32 layers × 2 bits 1,024 pages/block, block size 1,024 pages × 16 KB/page 16 MB). The number of strings, layers, access lines, data lines, first groups, second groups, and/or pages may be greater or less than those shown in FIG. 2.

FIG. 3 shows a cross-section of a memory block 300 of the 3D NAND memory device 200 of FIG. 2 in the X-X' directionA view of the memory block including fifteen strings of charge storage devices in one of the sixteen first groups of strings described with respect to fig. 2. The multi-string memory block 300 may be grouped into a plurality of subsets 310, 320, 330 (e.g., tile columns), such as tile columns_IAnd the piece column_jAnd a jigsaw puzzle column_KWhere each subset (e.g., tile column) comprises a "partial block" of memory block 300. A global drain side Select Gate (SGD) line 340 may be coupled to the SGDs of the multiple strings. For example, the global SGD line 340 may be coupled to a plurality (e.g., three) of sub-SGD lines 342, 344, 346 via a corresponding sub-SGD driver of the plurality (e.g., three) of sub-SGD drivers 332, 334, 336, where each sub-SGD line corresponds to a respective subset (e.g., a tile column). Each of the sub-SGD drivers 332, 334, 336 may simultaneously couple or disconnect SGDs of strings of a corresponding partial block (e.g., a tile column) independently of SGDs of strings of other partial blocks. A global source side Select Gate (SGS) line 360 may be coupled to the SGS of the multiple strings. For example, global SGS line 360 may be coupled to a plurality of sub-SGS lines 362, 364, 366 via a corresponding sub-SGS driver of the plurality of sub-SGS drivers 322, 324, 326, with each sub-SGS line corresponding to a respective subset (e.g., a tile column). Each of the sub-SGS drivers 322, 324, 326 may simultaneously couple or decouple SGSs of strings of corresponding partial blocks (e.g., tile columns) independently of SGSs of strings of other partial blocks. A global access line (e.g., a global CG line) 350 may couple charge storage devices of respective layers corresponding to each of the multiple strings. Each global CG line (e.g., global CG line 350) may be coupled to a plurality of sub-access lines (e.g., sub-CG lines) 352, 354, 356 via a corresponding sub-string driver of the plurality of sub-string drivers 312, 314, and 316. Each of the sub-string drivers may simultaneously couple or decouple the charge storage devices corresponding to the respective partial block and/or layer independently of the charge storage devices of the other partial blocks and/or other layers. The charge storage devices corresponding to the respective subsets (e.g., partial blocks) and respective layers may comprise "partial-layer" (e.g., single "tiles") charge storage devices. Strings corresponding to respective subsets (e.g., partial blocks) may be coupled to ones of sub-sources 372, 374, and 376 (e.g., "tile sources")Corresponding sub-sources, wherein each sub-source is coupled to a respective power supply.

Alternatively, the NAND memory device 200 is described with reference to the schematic illustration of FIG. 4.

The memory array 200 includes word lines 202₁To 202_NAnd bit line 228₁To 228_M。

The memory array 200 also includes NAND strings 206₁To 206_M. Each NAND string includes a charge storage transistor 208₁To 208_N. The charge storage transistor may store charge using a floating gate material (e.g., polysilicon), or may store charge using a charge trapping material (e.g., silicon nitride, metal nanodots, etc.).

A charge storage transistor 208 is located at the intersection of the word line 202 and the string 206. The charge storage transistor 208 represents a non-volatile memory cell for storing data. The charge storage transistors 208 of each NAND string 206 are connected in series, source to drain, between a source select device (e.g., source side select gate SGS)210 and a drain select device (e.g., drain side select gate SGD) 212. Each source select device 210 is located at the intersection of a string 206 and a source select line 214, while each drain select device 212 is located at the intersection of a string 206 and a drain select line 215. The selection devices 210 and 212 may be any suitable access devices and are generally illustrated by the blocks in FIG. 4.

The source of each source select device 210 is connected to a common source line 216. The drain of each source select device 210 is connected to the source of the first charge storage transistor 208 of the corresponding NAND string 206. For example, the source selection device 210₁Is connected to the corresponding NAND string 206₁Charge storage transistor 208₁Of the substrate. The source select device 210 is connected to a source select line 214.

The drain of each drain select device 212 is connected to a bit line (i.e., digit line) 228 at a drain contact. For example, the drain select device 212₁Is connected to a bit line 228₁. The source of each drain select device 212 is connected to the drain of the last charge storage transistor 208 of the corresponding NAND string 206. By way of example toIn other words, the drain select device 212₁Is connected to the corresponding NAND string 206₁Charge storage transistor 208_NOf the substrate.

Charge storage transistor 208 includes a source 230, a drain 232, a charge storage region 234, and a control gate 236. The control gate 236 of the charge storage transistor 208 is coupled to the word line 202. The columns of charge storage transistors 208 are those transistors within a NAND string 206 coupled to a given bit line 228. A row of charge storage transistors 208 are those transistors commonly coupled to a given word line 202.

It is desirable to develop improved NAND architectures and improved methods for fabricating NAND architectures.

Disclosure of Invention

An aspect of the present disclosure provides an integrated assembly, wherein the integrated assembly includes: a vertical stack of alternating insulating levels and conductive levels; the conductive level comprises a conductive structure; a channel material extending vertically through the stack; the conductive structure has a proximal region proximate to the channel material and has a distal region further from the channel material than the proximal region; the insulating level having a first region vertically between proximal regions of adjacent conductive structures and a second region vertically between distal regions of adjacent conductive structures; a void within the insulating level layer and extending across portions of the first and second regions; the insulating layer comprises an insulating liner along a proximal region of the conductive structure and not along a distal region of the conductive structure; the insulating liner has an outer surface on a side of the insulating liner opposite the conductive structure; the outer surface faces the void; and an insulating material extending through the stack and directly along the distal region of the conductive structure; the insulating material covers the ends of the voids and is not substantially along the outer surface of the insulating liner.

Another aspect of the present disclosure provides a method of forming an integrated assembly, wherein the method comprises: forming a vertical stack of alternating first and second levels; the first level comprises a first material and the second level comprises a second material; forming an opening to extend through the stack; forming a charge storage material, a tunneling material and a channel material in the opening; forming a slit to extend through the stack; flowing an etchant into the slit to remove the second material and leave first voids between the first levels; forming a conductive structure in the first void; the conductive structure has a proximal end adjacent to the channel material and has a distal end adjacent to the slit; removing the first material to leave second voids between the conductive structures; forming an insulating liner within the second void to line the second void, a region of the insulating liner along the distal end of the conductive structure; forming a sacrificial material within the lined second void and over the region of the insulating liner along the distal end of the conductive structure; recessing the sacrificial material to expose a region of the insulating liner along a distal end of the conductive structure; removing the exposed region of the insulating liner to expose a distal end of the conductive structure; removing the sacrificial material to reopen the second void; the reopened second void has an end region along the slit; and forming an insulating material in the slit; an insulating material is selectively formed along the conductive material relative to the insulating liner and extends across the end regions of the reopened second voids.

Another aspect of the present disclosure provides a method of forming an integrated assembly, wherein the method comprises: forming a vertical stack of alternating first and second levels; the first level comprises a first material and the second level comprises a second material; forming an opening to extend through the stack; forming a first liner within the opening to line the opening; the first liner has a first region along a first level and a second region along a second level; forming a dielectric blocking material, a charge storage material, a tunneling material, and a channel material within the lined opening; removing the second material to leave first voids between the first levels and expose a second region of the first liner; removing the second region of the first liner; forming a conductive structure within the first void after removing the second region of the first liner; the conductive structure has a proximal end adjacent the channel material and has a distal end in opposing relation to the proximal end; removing the first material to leave second voids between the conductive structures; lining the second gap with an insulating liner having a region extending around the distal end of the conductive structure; forming a sacrificial material within the lined second void and over the distal end of the conductive structure; recessing the sacrificial material to expose a region of the insulating liner along a distal end of the conductive structure; removing the exposed region of the insulating liner to expose a distal end of the conductive structure; removing the sacrificial material to open the second voids; and after removing the sacrificial material, forming an insulating material along the exposed distal ends of the conductive structures and across the ends of the second voids to cover the ends of the second voids.

Drawings

FIG. 1 shows a block diagram of a prior art memory device having a memory array with memory cells.

FIG. 2 shows a schematic diagram of the prior art memory array of FIG. 1 in the form of a 3D NAND memory device.

FIG. 3 shows a cross-sectional view of the prior art 3D NAND memory device of FIG. 2 in the X-X' direction.

FIG. 4 is a schematic of a prior art NAND memory array.

Fig. 5 and 6 are schematic cross-sectional side views of regions of an integrated assembly shown at example sequential process stages of an example method for forming an example NAND memory array.

FIG. 6A is a top down diagrammatic view of a portion of the integrated assembly of FIG. 6.

Figure 7 is a schematic cross-sectional side view of a region of the integrated assembly of figure 5 shown at an example process stage of an example method for forming an example NAND memory array. The process stage of fig. 7 may follow the process stage of fig. 6.

FIG. 7A is a top down diagrammatic view of a portion of the integrated assembly of FIG. 7.

Figure 8 is a schematic cross-sectional side view of a region of the integrated assembly of figure 5 shown at an example process stage of an example method for forming an example NAND memory array. The process stage of fig. 8 may follow the process stage of fig. 7.

FIG. 8A is a top down diagrammatic view of a portion of the integrated assembly of FIG. 8.

Figures 9-19 are schematic cross-sectional side views of regions of the integrated assembly of figure 5 shown at example sequential process stages of an example method for forming an example NAND memory array. The process stage of fig. 9 may follow the process stage of fig. 8.

Fig. 20 is a schematic cross-sectional side view of a region of an example integrated assembly. The assembly of fig. 20 may be the same as the assembly of fig. 19, and the regions of fig. 20 may correspond to larger regions of the assembly than shown in fig. 19.

Detailed Description

It may be desirable to have voids between the conductive structures to reduce or even remove capacitive coupling and/or other crosstalk mechanisms between the conductive structures. Some embodiments include an integrated assembly having voids between conductive structures. Some embodiments include methods of forming an integrated assembly. Example embodiments are described with reference to fig. 5-20.

Referring to fig. 5, a construction (integrated assembly, integrated structure) 10 includes a vertical stack 12 of alternating first and second levels 14, 16. The first level 14 includes a first material 60 and the second level 16 includes a second material 62. The first and second materials may comprise any suitable composition and have different compositions relative to each other. In some embodiments, first material 60 may comprise, consist essentially of, or consist of silicon dioxide; and second material 62 may comprise, consist essentially of, or consist of silicon nitride. The levels 14 and 16 may have any suitable thickness; and may have the same thickness as each other or have different thicknesses with respect to each other. In some embodiments, levels 14 and 16 may have vertical thicknesses ranging from about 10 nanometers (nm) to about 400 nm. In some embodiments, levels 14 and 16 may have a vertical thickness ranging from about 10nm to about 50 nm. In some embodiments, the first and second levels 14 and 16 may have vertical thicknesses ranging from about 15nm to about 40nm, ranging from about 15nm to about 20nm, and so forth. Any suitable number of levels 14 and 16 may be present within the stack 12. In some embodiments, there may be more than 10 levels within the stack, more than 50 levels within the stack, more than 100 levels within the stack, and so on.

The stack 12 is shown supported by (formed over) a source structure 17, which in turn is supported by (formed over) a base 18.

The source structures 17 may correspond to the source structures 214 and/or 360 described with reference to fig. 1-4, and may be lines, expanses, or any other suitable configuration. The source structure 17 may comprise any suitable material, and in some applications may comprise a conductively-doped semiconductor material (e.g., conductively-doped silicon) over a metal-containing material (e.g., tungsten silicide).

Substrate 18 may comprise a semiconductor material; and may, for example, comprise, consist essentially of, or consist of monocrystalline silicon. The base 18 may be referred to as a semiconductor substrate. The term "semiconductor substrate" means any construction comprising semiconductor material, including, but not limited to, bulk semiconductor materials such as semiconductor wafers (alone or in assemblies comprising other materials), and layers of semiconductor material (alone or in assemblies comprising other materials). The term "substrate" refers to any supporting structure, including but not limited to the semiconductor substrate described above. In some applications, base 18 may correspond to a semiconductor substrate containing one or more materials associated with integrated circuit fabrication. Such materials may include, for example, one or more of refractory metal materials, barrier materials, diffusion materials, insulator materials, and the like.

A gap is provided between the stack 12 and the source structure 17. Gaps are utilized to indicate that other components and materials may be disposed between the stack 12 and the source structure 17. Such other components and materials may include additional stack levels, source side Select Gates (SGS), and the like. Similarly, a gap is disposed between the source structure 17 and the substrate 18 to indicate that other components and materials may be disposed between the source structure 17 and the substrate 18.

Referring to fig. 6, an opening 64 is formed to extend through the stack 12. Opening 64 has sidewalls 65 that extend along first and second materials 60 and 62. The base 18 (fig. 5) is not shown in fig. 6 or in any of the figures subsequent to fig. 6 in order to reduce the size of the figures. It will be understood that the substrate will remain in the assembly 10 of figure 6 and in the assembly shown in the figures following figure 6.

Fig. 6A is a top view of one of the levels 14 through the regions of the assembly 10 at the process stage of fig. 6, and shows that the opening 64 may have a closed shape (circular, oval, square or other polygonal, etc.) when viewed from above. In the illustrated embodiment, the opening 64 is circular when viewed from above. The sidewall 65 along the cross-section of fig. 6 is part of a continuous sidewall 65, as shown by the top view of fig. 6A. The sidewall 65 may be referred to as a peripheral sidewall of the opening, or a peripheral sidewall surface of the opening. The terms "peripheral sidewall" and "peripheral sidewall surface" may be used interchangeably. The use of one term or another may provide a language change within the disclosure to simplify the antecedent basis within the claims that follow.

Opening 64 may represent a number of substantially identical openings formed at the process stage of fig. 6 and 6A. The term "substantially the same" means the same within reasonable manufacturing and measurement tolerances.

Referring to fig. 7 and 7A (where fig. 7A is a top view through one of levels 14 of fig. 7), a liner 20 is formed along peripheral sidewalls 65 to line opening 64. The liner includes a liner material. The liner material may serve as an etch stop layer in subsequent processing and may comprise any suitable composition. In some embodiments, the liner material may be a carbonaceous material. For example, the liner material may comprise, consist essentially of, or consist of carbon and one or more of silicon, oxygen, and nitrogen. In some embodiments, the liner material may include, consist essentially of, or consist of SiOC, where the formula indicates the major constituent rather than a particular stoichiometry; and wherein the carbon is present at a concentration in a range from about 1 atomic percent (at%) to about 50 at%. In some embodiments, carbon may be present in the SiOC at a concentration in a range from about 4 at% to about 20 at%. In some embodiments, the liner material can include, consist essentially of, or consist of SiC, where the chemical formula indicates the major constituent rather than a particular stoichiometry; and wherein the carbon is present at a concentration in a range from about 1 at% to about 50 at%. In some embodiments, carbon may be present in the SiC at a concentration in a range from about 4 at% to about 20 at%. In some embodiments, the liner material may comprise, consist essentially of, or consist of SiNC, where the chemical formula indicates the major constituent rather than a particular stoichiometry; and wherein the carbon is present at a concentration in a range from about one part per million (1ppm) to about 5 at%. In some embodiments, the liner material can include, consist essentially of, or consist of one or more metals (e.g., one or both of tungsten and ruthenium).

The liner 20 may comprise any suitable thickness. In some embodiments, such thicknesses may range from about 1nm to about 12 nm; in the range from about 2nm to about 4 nm; and so on.

Although the liner 20 is shown as having a single homogeneous composition, in other embodiments (not shown), the liner 20 may comprise a laminate having two or more different compositions.

The liner 20 may be considered to have a first region 24 along the first level 14 and a second region 26 along the second level 16.

Liner 20 may be referred to as a first liner.

A high-k dielectric material (dielectric barrier material) 28 is formed along the liner 20 (adjacent the liner 20). The dielectric barrier material 28 may be considered to be the sidewalls 65 adjacent the opening 64 even though it is spaced from the sidewalls by the liner 20 in the embodiment shown. The term "high-k" means a dielectric constant that is greater than the dielectric constant of silicon dioxide. In some embodiments, the high-k dielectric material 28 may comprise, consist essentially of, or consist of one or more of the following: aluminum oxide (AlO), hafnium oxide (HfO), hafnium silicate (HfSiO), zirconium oxide (ZrO), and zirconium silicate (ZrSiO); where the chemical formula indicates the major constituent rather than a specific stoichiometry.

The high-k dielectric material 28 has a substantially uniform thickness, wherein the term "substantially uniform" means uniform within reasonable tolerances in fabrication and measurement. The high-k dielectric material 28 may be formed to any suitable thickness; and in some embodiments may be formed to a thickness in a range from about 1nm to about 5 nm.

A charge blocking material 34 is formed along the dielectric blocking material 28. The charge blocking material 34 may comprise any suitable composition; and is arranged atIn some embodiments, silicon oxynitride (SiON) and silicon dioxide (SiO)₂) Consists essentially of, or consists of one or both of silicon oxynitride and silicon dioxide.

A charge storage material 38 is formed adjacent to the charge blocking material 34. The charge storage material 38 may comprise any suitable composition. In some embodiments, the charge storage material 38 may include one or more charge trapping materials; such as one or more of silicon nitride, silicon oxynitride, conductive nanodots, and the like. For example, in some embodiments, the charge storage material 38 may comprise, consist essentially of, or consist of silicon nitride.

The charge storage material 38 has a planar configuration in the illustrated embodiment of fig. 7. The term "flat configuration" means that the material 38 has a substantially continuous thickness and extends substantially vertically straight as opposed to wavy.

A gate dielectric material (i.e., tunneling material, charge transport material) 42 is formed adjacent to the charge storage material 38. The gate dielectric material 42 may comprise any suitable composition. In some embodiments, the gate dielectric material 42 may comprise, for example, one or more of silicon dioxide, silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, zirconium oxide, and the like. The gate dielectric material 42 may be band gap engineered to achieve desired electrical properties; and thus may comprise a combination of two or more different materials.

Channel material 44 is formed adjacent to gate dielectric material 42 and extends vertically along (through) stack 12. Channel material 44 comprises a semiconductor material; and may comprise any suitable composition or combination of compositions. For example, the channel material 44 may include one or more of silicon, germanium, III/V semiconductor material (e.g., gallium phosphide), semiconductor oxide, and the like; wherein the term III/V semiconductor material refers to a semiconductor material comprising an element selected from groups III and V of the periodic table (wherein groups III and V are old terms and are currently referred to as groups 13 and 15). In some embodiments, the channel material 44 may comprise, consist essentially of, or consist of silicon.

Insulative material 36 is formed adjacent channel material 44 and fills the remaining portions of openings 64 (fig. 6). Insulating material 36 may include any suitable composition; and in some embodiments may comprise, consist essentially of, or consist of silicon dioxide.

In the illustrated embodiment of fig. 7 and 7A, channel material 44 is configured as a loop around insulative material 36. Such configurations of channel material may be considered to include hollow channel configurations, wherein insulative material 36 is disposed within a "hollow" of the annular ring-shaped channel configuration. In other embodiments (not shown), the channel material may be configured in a solid pillar configuration.

In the cross-sectional view of fig. 7, the channel material 44 is shown electrically coupled with the source structure 17. Any suitable configuration may be employed to accomplish such electrical coupling. For example, in some embodiments, the channel material 44 may directly contact the source structure 17.

Referring to fig. 8 and 8A (with fig. 8A being a top view through one of the levels 14 of fig. 8), a slit 66 is formed to extend through the stack 12. In some embodiments, slots 66 may be used to separate memory block regions from one another.

Referring to fig. 9, the second material 62 (fig. 8) is removed to leave voids 30 along the second levels 16 (i.e., between the first levels 14). The void 30 may be referred to as a first void.

Voids 30 may be formed using any suitable process that selectively removes material 62 (fig. 8) relative to materials 60 and 20. In some embodiments, such processes may utilize an etchant (e.g., hot phosphoric acid) that flows into the slots 66.

The second region 26 of the liner 20 is exposed through the void 30.

Referring to fig. 10, the exposed second region 26 of the liner 20 is removed (fig. 9). Such removal may include any suitable treatment. In some embodiments, the removing may comprise oxidizing exposed regions of the liner (e.g., exposing such regions to O)₂、H₂O₂、O₃Etc.), followed by the removal of the oxidized region using an appropriate chemistry/conditions (e.g., an appropriate etchant). In some embodiments, the removal of the liner 20 comprisesAn etchant of HF, the insulating material 60 of level 14 comprising silicon dioxide, and which thins the insulating material 60 of level 14 (i.e., vertically expands voids 30).

Removal of the second region 26 of the liner 20 exposes the dielectric barrier material 28 along the level 16.

Referring to fig. 11, a conductive material 54 is formed within the voids 30 to line the voids, and in the embodiment shown, is formed directly against the high-k dielectric material 28. Conductive material 54 may include any suitable conductive composition; such as one or more of various metals (e.g., titanium, tungsten, cobalt, nickel, platinum, ruthenium, etc.), metal-containing compositions (e.g., metal silicides, metal nitrides, metal carbides, etc.), and/or conductively-doped semiconductor materials (e.g., conductively-doped silicon, conductively-doped germanium, etc.). In some embodiments, the conductive material 54 may comprise one or more metal nitrides (e.g., may comprise titanium nitride, tungsten nitride, etc.).

Referring to fig. 12, a conductive material 52 is formed within the lined void 30. Conductive material 52 may include any suitable conductive composition; such as one or more of various metals (e.g., titanium, tungsten, cobalt, nickel, platinum, ruthenium, etc.), metal-containing compositions (e.g., metal silicides, metal nitrides, metal carbides, etc.), and/or conductively-doped semiconductor materials (e.g., conductively-doped silicon, conductively-doped germanium, etc.). In some embodiments, the conductive material 52 may comprise one or more metals (e.g., may comprise tungsten).

The conductive material 52 is different in composition from the conductive material 54. In some embodiments, material 52 may be referred to as a conductive core material (or metal-containing core material), and material 54 may be referred to as a conductive liner material (or metal-nitride-containing liner material). A conductive liner material 54 is along the periphery of the conductive core material 52.

Referring to fig. 13, materials 52 and 54 are removed from within slot 66 using a suitable etch (e.g., an anisotropic etch). The remaining regions of materials 52 and 54 are configured as conductive structures 32, with such conductive structures being within voids 30 (fig. 9) and along levels 16. Level 16 may be considered a conductive level at the process stage of fig. 13, where such conductive level includes conductive structure 32. At the process stage of fig. 13, in the vertical stack 12, the conductive levels 16 alternate with the insulating levels 14.

The conductive structure 32 has a proximal region 56 adjacent the dielectric barrier material 28 and has a distal region 58 in opposing relation to the proximal region 56. In some embodiments, the proximal region 56 of the conductive structure 32 may be considered to have a proximal end 57 adjacent to the channel material 44 (and in the embodiment shown, directly against the dielectric barrier material 28), and the distal region 58 of the conductive structure 32 may be considered to have a distal end 59 adjacent to the slit 66.

The conductive levels 16 may be considered a level of memory cells (also referred to herein as a level of word lines) of a NAND configuration. The NAND configuration includes strings of memory cells (i.e., NAND strings), where the number of memory cells in a string is determined by the number of vertically stacked levels 16. A NAND string can include any suitable number of levels of memory cells. For example, a NAND string may have 8 levels of memory cells, 16 levels of memory cells, 32 levels of memory cells, 64 levels of memory cells, 512 levels of memory cells, 1024 levels of memory cells, etc. The stack 12 is indicated to extend vertically beyond the illustrated region to show that there may be more levels of vertical stacking than specifically illustrated in the diagram of fig. 13.

The NAND memory cell 40 includes dielectric barrier material 28, charge blocking material 34, charge storage material 38, gate dielectric material 42, and channel material 44. The illustrated NAND memory cell 40 forms part of a vertically extending string of memory cells. Such strings may represent a large number of substantially identical NAND strings formed during the fabrication of a NAND memory array (the term "substantially identical" means identical within reasonable tolerances of fabrication and measurement).

Each of the NAND memory cells 40 includes a control gate region 72 within the conductive structure 32 along the conductive level 16. The control gate region 72 includes a control gate similar to the control gates described above with reference to fig. 1-4. The conductive structure 32 also includes a region 74 adjacent (near) the control gate region 72. The region 74 may be referred to as a wiring region (word line region). The control gate region 72 includes the proximal region 56 of the conductive structure 32 and the wiring region 74 includes the distal region 58 of the conductive structure 32.

Referring to fig. 14, first material 60 (fig. 13) is removed to form second voids 76 along levels 14 (i.e., leaving second voids 76), and in the embodiment shown, first regions 24 (fig. 9) of liner 20 (fig. 9) are removed during formation of second voids 76. The second gap 76 is vertically between the conductive structures 32.

Referring to fig. 15, an insulating liner 78 is formed within the void 76 to line the void 76. The liner 76 includes a region 80 extending along the distal end 59 of the conductive structure 32.

The insulating liner 78 may comprise any suitable composition; and in some embodiments may comprise, consist essentially of, or consist of one or more of silicon dioxide, silicon oxynitride, and silicon nitride. In some embodiments, the liner 78 may be referred to as comprising, consisting essentially of, or consisting of one or more of SiO, SiN, and SiON, where the formula indicates the predominant composition and not the particular stoichiometry.

The insulating liner 78 may be formed to any suitable thickness, and in some embodiments, may be formed to a thickness in a range from about 1nm to about 10nm, a thickness in a range from about 2nm to about 4nm, and so forth.

Sacrificial material 82 is formed within lined void 76 and over distal end 59 of conductive structure 32. Sacrificial material 82 may comprise any suitable composition, and in some embodiments may comprise, consist essentially of, or consist of silicon. The silicon may be in any suitable crystalline form (e.g., one or more of single crystal, polycrystalline, amorphous, etc.) and may or may not have dopants therein (e.g., phosphorus, arsenic, boron, etc.).

Referring to fig. 16, the sacrificial material 82 is recessed to expose a region 80 of the insulating liner 78 along the distal end 59 of the conductive structure 32.

Referring to fig. 17, exposed regions 80 (fig. 16) of liner 78 are removed to expose distal ends 59 of conductive structures 32. In the embodiment shown, the exposed distal end 59 comprises an exposed region of the metal-containing core material 52 and an exposed region of the metal-containing liner material 54. In some embodiments, the core material 52 may be considered to be configured as a core 83, and the liner material 54 may be considered to be configured as a liner 85, and the distal end 59 may be considered to be an exposed region including the core 83 and the liner 85.

In some embodiments, each of the liners 85 can be considered to surround the proximal end 87 of the associated core 83 and so that the distal end 89 of the associated core is exposed. The cross-sectional view of fig. 17 shows the illustrated liners 85 each having a first surface 91 directly against an associated one of the cores 83 and having a second surface 93 in opposing relation to the first surface 91. The distal region 58 of the conductive structure 32 includes a pair of exposed sections 84 and 86 of a liner 85. Section 84 is above an associated one of the cores 83 and section 86 is below an associated one of the cores 83. The distal region 58 of the conductive structure 32 also includes an exposed distal end 89 of an associated one of the cores 83.

Referring to fig. 18, the remaining portion of sacrificial material 82 (fig. 17) is removed to open (reopen) void 76. The reopened void 76 may be considered as having an end region 88 along the slit 66. In some embodiments, the sacrificial material 82 may comprise silicon, and may be removed using tetramethylammonium hydroxide.

The insulating lining 78 is directly against a region of the second surface 93 of the conductive lining 85. In some embodiments, the conductive liner 85 may comprise a metal nitride, and the insulating liner 78 may be referred to as directly against the metal nitride-containing second surface 93 of such conductive liner.

Referring to fig. 19, an insulating material 90 is formed within the slot 66. The insulating material 90 may be formed by any suitable deposition process (e.g., atomic layer deposition, chemical vapor deposition, etc.). Insulating material 90 may include any suitable composition; and in some embodiments may comprise one or more of SiO, SiON, and SiN, where the formula indicates the major constituent rather than a particular stoichiometry. Accordingly, in some embodiments, the insulating material 90 may comprise, consist essentially of, or consist of more of silicon dioxide, silicon oxynitride, and silicon nitride.

Insulative material 90 is formed selectively with respect to insulative liner 78 along conductive materials 52 and 54 of structure 32. For purposes of understanding the present disclosure and appended claims, a first material is considered to be selectively formed on a second material relative to a third material if the first material is formed on the second material faster than the third material; this may include, but is not limited to, a process that has 100% selectivity to a third material to form a first material over a second material.

The insulating liner 78 may be considered to have an outer surface 95 facing the void 76. In the illustrated embodiment, the insulating material 90 is not substantially along the outer surface 95 of the insulating liner 78. In some embodiments, there may be no insulating material 90 against the outer surface 95 of the insulating liner 78. In other embodiments, some insulating material 90 may be present along the outer surface 95 of the insulating liner 78 and not completely close the voids 76 between the conductive structures 32.

In some embodiments, the insulating liner 78 comprises silicon dioxide, and a barrier material (also referred to herein as a poisoning material) is formed along the silicon dioxide of the insulating liner 78 to preclude subsequent formation of an insulating material 90 on the surface of the insulating liner 78. The barrier material (poisoning material) may be formed by treating the insulating liner 78 with any suitable substance; and in some embodiments, the treating may include exposing the insulating liner to one or more of: n, N-dimethylaminotrimethylsilane, bis (N, N-dimethylamino) dimethylsilane, ethylenediamine, 1-trimethylsilylpyrrolidine, 1-trimethylsilylpyrrole, 3, 5-dimethyl-1-trimethylsilyl, and R1- (C-OH) -R2; wherein R1 and R2 are organic moieties.

The insulating material 90 extends across the end regions 88 of the voids 76 and may be considered to cover the end regions 88 of the voids. The remainder of void 76 remains within insulating level 14.

The level 16 of fig. 19 can be considered a conductive level (memory cell level), where such a conductive level includes a conductive structure 32. At the process stage of fig. 19, in the vertical stack 12, the conductive levels 16 alternate with the insulating levels 14.

The conductive structure 32 has a proximal region 56 proximate the channel material 44 and has a distal region 58 that is further from the channel material 44 than the proximal region 56.

Insulating level 14 may be considered to have a first region 68 vertically between the proximal regions 56 of vertically adjacent conductive structures 32 and a second region 70 vertically between the distal regions 58 of vertically adjacent conductive structures. Void 76 extends across first and second regions 68 and 70. In some embodiments, the insulating liner 78 may be considered to be along the proximal region 56 and not along the distal region 58 of the conductive structure 32; and thus may be considered to be along the first region 68 and not along the second region 70 of the insulating level 14.

In some embodiments, each of the voids 76 of fig. 19 may be considered to be within a four-sided region 92 along the cross-section of fig. 19. The insulating liner 78 is along three of the four sides of the four-sided area, and the insulating material 90 is along the fourth side of the four-sided area.

The configuration of FIG. 19 includes the NAND memory cell 40 described above with reference to FIG. 13. Each of the NAND memory cells 40 includes a control gate region 72 within the conductive level 16 (i.e., associated with the conductive structure 32). The control gate region 72 includes a control gate similar to the control gates described above with reference to fig. 1-4. The conductive structure 32 includes a routing (word line) region 74 adjacent (near) the control gate region 72.

The process described herein may advantageously form insulating material 90 within slots 66 of high stacks 12 of alternating insulating and conductive levels (14 and 16) without pinching voids 76 between conductive structures 32 within conductive levels 16. For example, fig. 20 shows a region of the tall stack 12, and shows that the insulating material 90 can fill the stack from bottom to top without pinching the voids 76. The high stack may include any suitable number of conductive levels 16; and in some embodiments may include 16 conductive levels 16, 32 conductive levels 16, 64 conductive levels 16, 128 conductive levels 16, etc.

A source side Select Gate (SGS) device is illustrated diagrammatically as along a conductive contact extending from the channel material 44 to the source structure 17. The SGS device may have any suitable configuration.

The configuration of fig. 19 and 20 may be the final structure of the memory arrangement (e.g., an assembly configured to include NAND memory).

In operation, the charge storage material 38 (fig. 19) may be configured to store information in the memory cells 40 of the various embodiments described herein. The value of the information stored in an individual memory cell (where the term "value" denotes a bit or bits) may be based on the amount of charge (e.g., the number of electrons) stored in the charge storage region of the memory cell. The amount of charge within the individual charge storage regions may be controlled (e.g., increased or decreased) based at least in part on the value of the voltage applied to the associated gate 72 (fig. 19) and/or based on the value of the voltage applied to the channel material 44.

The tunneling material 42 (fig. 19) forms the tunneling region of the memory cell 40. Such tunneling regions may be configured to achieve a desired migration (e.g., transport) of charges (e.g., electrons) between the charge storage material 38 (fig. 19) and the channel material 44. The tunneling region may be configured (i.e., designed) to achieve a selected criterion, such as, but not limited to, an Equivalent Oxide Thickness (EOT). The EOT quantifies the electrical properties (e.g., capacitance) of the tunneling region from a representative physical thickness. For example, EOT may be defined as the thickness of a theoretical silicon dioxide layer that would be required to have the same capacitance density as a given dielectric, ignoring leakage current and reliability issues.

The charge blocking material 34 (fig. 19) may provide a mechanism for preventing charge from flowing from the charge storage material 38 to the associated gate 72.

The dielectric barrier material (high-k material) 28 (fig. 19) may be used to prevent reverse tunneling of charge carriers from the gate 72 toward the charge storage material 38. In some embodiments, the dielectric barrier material 28 may be considered to form a dielectric barrier region within the memory cell 40.

The assemblies and structures discussed above may be utilized within an integrated circuit (where the term "integrated circuit" refers to an electronic circuit supported by a semiconductor substrate); and may be incorporated into an electronic system. Such electronic systems may be used in, for example, memory modules, device drivers, power modules, communication modems, processor modules, and application-specific modules, and may include multilayer, multichip modules. The electronic system may be any of a wide range of systems: such as cameras, wireless devices, displays, chipsets, set-top boxes, games, lighting systems, vehicles, clocks, televisions, cellular telephones, personal computers, automobiles, industrial control systems, aircraft, and so forth.

Unless otherwise specified, the various materials, substances, compositions, etc. described herein can be formed by any suitable method now known or to be developed, including, for example, Atomic Layer Deposition (ALD), Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), etc.

The terms "dielectric" and "insulating" may be used to describe a material having insulating electrical properties. The terms are considered synonymous in this disclosure. The use of the term "dielectric" in some instances and the term "insulating" (or "electrically insulating") in other instances may provide language changes within the present disclosure to simplify the antecedent basis within the appended claims rather than to indicate any significant chemical or electrical difference.

The terms "electrically connected" and "electrically coupled" may both be used in this disclosure. The terms are considered synonymous. The use of one term in some instances and another term in other instances may be intended to provide a linguistic variation within the disclosure to simplify the antecedent basis within the appended claims.

The particular orientation of the various embodiments in the drawings is for illustrative purposes only, and in some applications, the embodiments may be rotated relative to the orientation shown. The description provided herein and the appended claims refer to any structure having a described relationship between various features, regardless of whether the structure is in a particular orientation of the drawings or rotated relative to such orientation.

Unless otherwise specified, the cross-sectional views illustrated by the figures only show features within the plane of the cross-section, and do not show material behind the plane of the cross-section, in order to simplify the drawings.

When a structure is referred to as being "on," "adjacent to," or "against" another structure, the structure may be directly on the other structure or intervening structures may also be present. In contrast, when a structure is referred to as being "directly on," "directly adjacent to," or "directly against" another structure, there are no intervening structures present. The terms "directly under", "directly over", and the like do not indicate direct physical contact (unless explicitly stated otherwise), but instead indicate upright alignment.

Structures (e.g., layers, materials, etc.) may be referred to as "vertically extending," to indicate that the structures generally extend upward from an underlying base (e.g., substrate). The vertically extending structures may or may not extend substantially orthogonally relative to the upper surface of the base.

Some embodiments include an integrated assembly having a vertical stack of alternating insulating levels and conductive levels. The conductive levels comprise conductive structures. Channel material extends vertically through the stack. The conductive structure has a proximal region proximate to the channel material and has a distal region further from the channel material than the proximal region. The insulating level has a first region vertically between proximal regions of adjacent conductive structures and a second region vertically between distal regions of adjacent conductive structures. The void is within the insulating level layer and extends across portions of the first region and the second region. The insulating level includes an insulating liner along a proximal region of the conductive structure and not along a distal region of the conductive structure. The insulating liner has an outer surface on a side of the insulating liner opposite the conductive structure. The outer surface faces the void. An insulating material extends through the stack and directly along a distal region of the conductive structure. The insulating material covers the ends of the voids and is not substantially along the outer surface of the insulating liner.

Some embodiments include a method of forming an integrated assembly. The stack is formed with alternating first and second levels along a vertical direction. The first level includes a first material and the second level includes a second material. An opening is formed to extend through the stack. A charge storage material, a tunneling material, and a channel material are formed within the opening. The slit is formed to extend through the stack. The etchant flows into the slots to remove the second material and leave first voids between the first levels. The conductive structure is formed in the first gap. The conductive structure has a proximal end adjacent the channel material and has a distal end adjacent the slit. The first material is removed to leave second voids between the conductive structures. An insulating liner is formed within the second void to line the second void. The region of the insulating liner is along the distal end of the conductive structure. A sacrificial material is formed within the lined second void along the distal end of the conductive structure and over the region of the insulating liner. The sacrificial material is recessed to expose a region of the insulating liner along a distal end of the conductive structure. The exposed region of the insulating liner is removed to expose a distal end of the conductive structure. The sacrificial material is removed to reopen the second void. The reopened second void has an end region along the slit. An insulating material is formed within the slot. An insulating material is selectively formed along the conductive material relative to the insulating liner and extends across the end regions of the reopened second voids.

Some embodiments include a method of forming an integrated assembly. Forming a vertical stack of alternating first levels and second levels. The first level includes a first material and the second level includes a second material. An opening is formed to extend through the stack. A first liner is formed within the opening to line the opening. The first liner has a first region along a first level and a second region along a second level. A dielectric blocking material, a charge storage material, a tunneling material, and a channel material are formed within the lined opening. The second material is removed to leave first voids between the first levels and expose a second region of the first liner. The second region of the first liner is removed and then a conductive structure is formed within the first void. The conductive structure has a proximal end adjacent the channel material and has a distal end in opposing relation to the proximal end. The first material is removed to leave second voids between the conductive structures. The second gap is lined with an insulating liner. The insulating liner has a region extending around the distal end of the conductive structure. A sacrificial material is formed within the lined second void and over the distal end of the conductive structure. The sacrificial material is recessed to expose a region of the insulating liner along a distal end of the conductive structure. The exposed region of the insulating liner is removed to expose a distal end of the conductive structure. The sacrificial material is removed to open the second void, and then an insulating material is formed along the exposed distal end of the conductive structure and across the end of the second void. An insulating material covers the ends of the second void.

In accordance with the provisions, the subject matter disclosed herein has been described in language more or less specific as to structural and methodical features. It is to be understood, however, that the claims are not limited to the specific features shown and described, since the means herein disclosed comprise example embodiments. The claims are, therefore, to be accorded the full scope as literally set forth and appropriately interpreted in accordance with the doctrine of equivalents.