阅读说明：本技术 调节在刷新操作中供应的激活电压的电平的设备 (Apparatus for adjusting level of activation voltage supplied in refresh operation ) 是由 金敬默 金雄来 朴相一 李承燻 于 2020-09-25 设计创作，主要内容包括：本申请公开了调节在刷新操作中供应的激活电压的电平的设备。一种设备包括操作控制电路和驱动控制信号发生电路。操作控制电路基于被激活以执行刷新操作的刷新信号来产生被激活以对单元阵列执行激活操作的内部刷新信号,所述单元阵列被耦接至由行地址选择的字线。另外,操作控制电路基于刷新信号来产生预刷新脉冲,并且基于内部刷新信号来产生刷新结束脉冲。驱动控制信号发生电路基于内部刷新信号、预刷新脉冲和刷新结束脉冲来产生驱动控制信号,以控制供应给由行地址选择的字线的激活电压的驱动。(An apparatus for adjusting a level of an activation voltage supplied in a refresh operation is disclosed. An apparatus includes an operation control circuit and a drive control signal generation circuit. The operation control circuit generates an internal refresh signal activated to perform an active operation on a cell array coupled to a word line selected by a row address based on a refresh signal activated to perform the refresh operation. In addition, the operation control circuit generates a pre-refresh pulse based on the refresh signal, and generates a refresh end pulse based on the internal refresh signal. The drive control signal generation circuit generates a drive control signal to control driving of an activation voltage supplied to a word line selected by a row address based on the internal refresh signal, the pre-refresh pulse, and the refresh end pulse.)

1. An apparatus, comprising:

an operation control circuit configured to: generating an internal refresh signal activated to perform an activation operation on a cell array coupled to a word line selected by a row address, configured to generate a pre-refresh pulse based on the refresh signal, and configured to generate a refresh end pulse based on the internal refresh signal, based on a refresh signal activated to perform the refresh operation; and

a drive control signal generation circuit configured to generate a drive control signal to control driving of an activation voltage supplied to the word line selected by the row address based on the internal refresh signal, the pre-refresh pulse, and the refresh end pulse.

2. The device of claim 1, wherein the operation control circuit comprises a start pulse generation circuit configured to generate a start pulse when the refresh signal is activated.

3. The device of claim 2, wherein the operation control circuit further comprises a refresh pulse generation circuit configured to: generating a refresh pulse during each internal refresh period, the each internal refresh period being set based on a refresh clock signal generated when the refresh signal is activated, and configured to: generating the pre-refresh pulse prior to generating the refresh pulse.

4. The apparatus of claim 3, wherein a period of the refresh clock signal is set to be constant.

5. The device of claim 3, wherein a period of the refresh clock signal is adjusted based on an internal temperature of the device.

6. The apparatus of claim 3, wherein the operation control circuit further comprises an internal refresh signal generation circuit configured to generate the internal refresh signal, the internal refresh signal being activated when the start pulse or the refresh pulse is generated.

7. The apparatus of claim 6, wherein the operation control circuit further comprises a refresh end pulse generation circuit configured to generate the refresh end pulse in synchronization with a point in time at which the internal refresh signal is deactivated.

8. The apparatus of claim 1, wherein the drive control signal generation circuit is configured to: generating the driving control signal to raise the level of the activation voltage when the refresh signal is deactivated or both the refresh signal and the internal refresh signal are activated.

9. The apparatus of claim 1, wherein the drive control signal generation circuit is configured to: generating the driving control signal to raise the level of the activation voltage during a period from a time point of generating the pre-refresh pulse until a time point of generating the refresh end pulse in a case where the refresh signal is activated.

10. The device of claim 1, further comprising an activation voltage generation circuit configured to: driving the activation voltage to a first internal voltage when the driving control signal has a first logic level, and configured to: driving the activation voltage to a second internal voltage when the driving control signal has a second logic level.

11. The apparatus of claim 10, wherein the first internal voltage is set higher than the second internal voltage.

12. The apparatus of claim 10, wherein the drive control signal generation circuit is configured to: generating the driving control signal having the first logic level when the refresh signal is deactivated; is configured to: generating the driving control signal having the first logic level when both the refresh signal and the internal refresh signal are activated; and is configured to: generating the driving control signal having the first logic level during a period from a time point of generating the pre-refresh pulse until a time point of generating the refresh end pulse in a case where the refresh signal is activated.

13. The apparatus of claim 1, further comprising:

a row address generation circuit configured to generate the row address based on the internal refresh signal; and

a word line driver circuit configured to supply the activation voltage to the word line selected by the row address.

14. An apparatus, comprising:

a refresh pulse generation circuit configured to generate a refresh pulse during each internal refresh period that is set based on a refresh clock signal generated when a refresh signal is activated, and configured to generate a pre-refresh pulse before generating the refresh pulse;

an internal refresh signal generation circuit configured to generate an internal refresh signal based on a start pulse generated when the refresh signal is activated and the refresh pulse;

a refresh end pulse generation circuit configured to generate a refresh end pulse based on the internal refresh signal; and

a drive control signal generation circuit configured to generate a drive control signal to control driving of an activation voltage supplied to a word line selected by a row address based on the internal refresh signal, the pre-refresh pulse, and the refresh end pulse.

15. The device of claim 14, wherein a period of the refresh clock signal is adjusted based on an internal temperature of the device.

16. The apparatus of claim 14, wherein the refresh end pulse is generated in synchronization with a point in time at which the internal refresh signal is deactivated.

17. The device of claim 14, further comprising an activation voltage generation circuit configured to: driving the activation voltage to a first internal voltage when the drive control signal has a first logic level, and configured to: driving the activation voltage to a second internal voltage when the driving control signal has a second logic level.

18. The apparatus of claim 17, wherein the first internal voltage is set higher than the second internal voltage.

19. The apparatus of claim 17, wherein the drive control signal generation circuit is configured to: generating the driving control signal having the first logic level when the refresh signal is deactivated; is configured to: generating the driving control signal having the first logic level when both the refresh signal and the internal refresh signal are activated; and is configured to: generating the driving control signal having the first logic level during a period from a time point of generating the pre-refresh pulse until a time point of generating the refresh end pulse in a case where the refresh signal is activated.

20. An apparatus, comprising:

a refresh clock generation circuit configured to: generating a refresh clock signal when a refresh signal is activated, a period of the refresh clock signal being adjusted based on a temperature code;

a refresh pulse generation circuit configured to: generating a refresh pulse during each internal refresh period set based on the refresh clock signal, and configured to: generating a pre-refresh pulse prior to generating the refresh pulse;

an internal refresh signal generation circuit configured to generate an internal refresh signal based on a start pulse generated when the refresh signal is activated and the refresh pulse;

a refresh end pulse generation circuit configured to generate a refresh end pulse based on the internal refresh signal; and

a drive control signal generation circuit configured to generate a drive control signal to control driving of an activation voltage supplied to a word line selected by a row address based on the internal refresh signal, the pre-refresh pulse, and the refresh end pulse.

Technical Field

Embodiments of the present disclosure relate to a device that performs a refresh operation, and more particularly, to a device that adjusts a level of an activation voltage supplied in a refresh operation.

Background

Unlike static random access random (SRAM) devices and flash memory devices, dynamic random access random (DRAM) devices of semiconductor devices may lose information (i.e., data) stored in their cell arrays over time even when power is supplied. Accordingly, the DRAM device may periodically perform an activation operation to sense and amplify the level of data stored in the cell array in order to prevent the data in the cell array from being lost, and the activation operation for sensing and amplifying the level of data stored in the cell array may be referred to as a refresh operation. The refresh operation may be performed by activating a word line in a cell array at least once within a data retention time of a memory cell in the cell array disposed in a bank to sense and amplify a level of data. The data retention time may correspond to the longest time that the memory cell can retain the minimum charge required to present the original data without any refresh operation.

Disclosure of Invention

According to one embodiment, an apparatus includes an operation control circuit and a drive control signal generation circuit. The operation control circuit is configured to generate an internal refresh signal activated to perform an activation operation on a cell array coupled to a word line selected by a row address based on a refresh signal activated to perform the refresh operation. In addition, the operation control circuit is configured to generate a pre-refresh pulse based on the refresh signal, and is configured to generate a refresh end pulse based on the internal refresh signal. The drive control signal generation circuit is configured to generate a drive control signal to control driving of an activation voltage supplied to a word line selected by a row address based on the internal refresh signal, the pre-refresh pulse, and the refresh end pulse.

According to another embodiment, an apparatus includes a refresh pulse generating circuit, an internal refresh signal generating circuit, a refresh end pulse generating circuit, and a drive control signal generating circuit. The refresh pulse generation circuit is configured to generate a refresh pulse during each internal refresh period that is set based on a refresh clock signal generated when the refresh signal is activated, and is configured to generate a pre-refresh pulse before generating the refresh pulse. The internal refresh signal generation circuit is configured to generate the internal refresh signal based on a start pulse and a refresh pulse generated when the refresh signal is activated. The refresh end pulse generation circuit is configured to generate a refresh end pulse based on the internal refresh signal. The drive control signal generation circuit is configured to generate a drive control signal to control driving of an activation voltage supplied to a word line selected by a row address based on the internal refresh signal, the pre-refresh pulse, and the refresh end pulse.

According to still another embodiment, an apparatus includes a refresh clock generation circuit, a refresh pulse generation circuit, an internal refresh signal generation circuit, a refresh end pulse generation circuit, and a drive control signal generation circuit. The refresh clock generation circuit is configured to: a refresh clock signal is generated when the refresh signal is activated, a period of the refresh clock signal being adjusted based on the temperature code. The refresh pulse generation circuit is configured to generate a refresh pulse during each internal refresh period set based on the refresh clock signal, and is configured to generate a pre-refresh pulse before generating the refresh pulse. The internal refresh signal generation circuit is configured to generate the internal refresh signal based on a start pulse and a refresh pulse generated when the refresh signal is activated. The refresh end pulse generation circuit is configured to generate a refresh end pulse based on the internal refresh signal. The drive control signal generation circuit is configured to generate a drive control signal to control driving of an activation voltage supplied to a word line selected by a row address based on the internal refresh signal, the pre-refresh pulse, and the refresh end pulse.

Drawings

Fig. 1 is a block diagram illustrating a configuration of a system according to an embodiment of the present disclosure.

Fig. 2 is a block diagram showing a configuration of an example of devices included in the system shown in fig. 1.

Fig. 3 illustrates an example of an internal refresh signal generation circuit included in the apparatus shown in fig. 2.

Fig. 4 is a circuit diagram showing an example of a refresh end pulse generating circuit included in the apparatus shown in fig. 2.

Fig. 5 is a circuit diagram showing an example of a drive control signal generation circuit included in the apparatus shown in fig. 2.

Fig. 6 is a circuit diagram showing an example of an activation voltage generation circuit included in the apparatus shown in fig. 2.

Fig. 7 to 14 illustrate the operation of the apparatus shown in fig. 2.

Fig. 15 is a block diagram showing a configuration of another example of the devices included in the system shown in fig. 1.

Fig. 16 is a block diagram illustrating an example of a refresh clock generation circuit included in the apparatus shown in fig. 15.

Detailed Description

In the following description of the embodiments, when a parameter is referred to as "predetermined," it may be intended to mean that the value of the parameter is determined in advance when the parameter is used in a process or algorithm. The value of the parameter may be set at the beginning of the process or algorithm, or may be set during the period in which the process or algorithm is executed.

It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Thus, a first element in some embodiments may be termed a second element in other embodiments, and vice versa, without departing from the teachings of the present disclosure.

Further, it will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.

Logic "high" levels and logic "low" levels may be used to describe the logic levels of an electrical signal. A signal having a logic "high" level may be distinguished from a signal having a logic "low" level. For example, when a signal having a first voltage corresponds to a signal having a logic "high" level, a signal having a second voltage corresponds to a signal having a logic "low" level. In one embodiment, the voltage level of the logic "high" level may be set to a voltage level higher than the logic "low" level. In addition, the logic levels of the signals may be set differently or otherwise depending on the embodiment. For example, a certain signal having a logic "high" level in one embodiment may be set to a logic "low" level in another embodiment.

Various embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. However, the embodiments described herein are for illustrative purposes only and are not intended to limit the scope of the present disclosure.

Fig. 1 is a block diagram illustrating a configuration of a system 10 according to an embodiment of the present disclosure. As shown in fig. 1, the system 10 may include a controller 101 and a device 103. The controller 101 may include a first control pin 101_1 and a second control pin 101_ 3. The device 103 may include a first device pin 103_1 and a second device pin 103_ 3. The controller 101 may transmit a command CMD to the device 103 through a first transmission line 105_1 connecting the first control pin 101_1 to the first device pin 103_ 1. The controller 101 may supply the supply voltage VDD to the device 103 through a second transmission line 105_3 connecting the second control pin 101_3 to the second device pin 103_ 3. In this embodiment, the command CMD may include a plurality of bits. In some embodiments, the command CMD may be transmitted with the address through the same transmission line.

The device 103 may be implemented by using a semiconductor device. The device 103 may include a command decoder (CMD _ DEC)111 that receives the command CMD from the controller 101 and decodes the command CMD to generate a refresh signal (SREF of fig. 2) for performing a refresh operation. The refresh operation may be performed by sequentially accessing a cell array included in the device 103, by performing an activation operation for sensing, and by amplifying a level of data stored in the accessed cell array. The accessed cell array refers to a cell array coupled to a word line selected by a row address (RADD of fig. 2) to be driven by an activation voltage (SVPP of fig. 2). The device 103 may include an operation control circuit (OP _ CNT)113, and when a refresh operation is performed, the operation control circuit (OP _ CNT)113 controls an activation operation of the cell arrays sequentially accessed based on a refresh clock signal (TOSC of fig. 2). The refresh clock signal TOSC may be generated to have a period that is adjusted based on the internal temperature of the device 103. For example, the period of the refresh clock signal TOSC may increase as the internal temperature of the device 103 decreases. The device 103 may include an activation voltage generation circuit (SVPP _ GEN)119 that adjusts a level of an activation voltage (SVPP of fig. 2) supplied to a wordline when a refresh operation is performed. For example, the activation voltage generation circuit 119 may generate the activation voltage SVPP having a high level only when an activation operation for a memory cell accessed during a refresh operation is performed, thereby reducing power consumption of the device 103. That is, it is possible to reduce the amount of current leakage such as junction current leakage due to a Gate Induced Drain Leakage (GIDL) phenomenon of cell transistors included in cells that are not accessed.

Fig. 2 is a block diagram showing a configuration of a device 103A corresponding to an example of the device 103 included in the system 10 shown in fig. 1. As shown in fig. 2, the device 103A may include a command decoder 111, an operation control circuit 113, a drive control signal generation circuit (PCTR _ GEN)115, an internal voltage generation circuit (VPP _ GEN)117, an activation voltage generation circuit (SVPP _ GEN)119, a row address generation circuit (RADD _ GEN)121, and a word line drive circuit (WL _ DRV) 123.

The command decoder 111 may receive a command CMD from the controller 101. The command decoder 111 may decode the command CMD to generate the refresh signal SREF to perform the refresh operation. In the case where the refresh operation is performed, the command decoder 111 may generate the refresh signal SREF that is activated based on a logic level combination of bits included in the command CMD. In the present embodiment, although the refresh signal SREF is generated to maintain the active state having the logic "high" level from the time point when the refresh operation starts up to the time point when the active operations for all the cell arrays included in the device 103A are terminated, the present disclosure is not limited thereto.

The operation control circuit 113 may receive the refresh signal SREF from the command decoder 111. The operation control circuit 113 may generate an internal refresh signal IREF, a refresh pulse RSP, a PRE-refresh pulse RSP _ PRE, and a refresh end pulse RFINP based on the refresh signal SREF. When the refresh signal SREF is activated, the operation control circuit 113 may generate an internal refresh signal IREF that is activated to perform an activation operation for a cell array accessed based on the row address RADD. The operation control circuit 113 may generate the refresh clock signal TOSC when the refresh signal SREF is activated, and may generate the refresh pulse RSP during each internal refresh period set by the refresh clock signal TOSC. The operation control circuit 113 may generate an internal refresh signal IREF activated to perform an activation operation for a cell array accessed based on a row address RADD whenever a refresh pulse RSP is generated. The operation control circuit 113 may generate the PRE-refresh pulse RSP _ PRE before generating the refresh pulse RSP during each internal refresh period set by the refresh clock signal TOSC. In one embodiment, the PRE-refresh pulse RSP _ PRE may be generated before performing an activation operation for a cell array accessed by the row address RADD. When the active operation for the cell array is terminated based on the internal refresh signal IREF, the operation control circuit 113 may generate a refresh end pulse RFINF. The operation control circuit 113 may generate the refresh end pulse RFINP in synchronization with a point of time at which the internal refresh signal IREF is deactivated by terminating the activation operation for the cell array.

The operation control circuit 113 may include a start pulse generation circuit (STRP _ GEN)131, a refresh clock generation circuit (TOSC _ GEN)133, a refresh pulse generation circuit (RSP _ GEN)135, an internal refresh signal generation circuit (IREF _ GEN)137, and a refresh end pulse generation circuit (RFINP _ GEN) 139.

The start pulse generating circuit 131 may receive the refresh signal SREF from the command decoder 111. When the refresh signal SREF is activated, the start pulse generating circuit 131 may generate the start pulse STRP. In the present embodiment, the start pulse STRP may be generated to have a logic "high" level. However, in some other embodiments, the logic level of the start pulse STRP is not limited to the logic "high" level.

The refresh clock generation circuit 133 may receive the refresh signal SREF from the command decoder 111. The refresh clock generation circuit 133 may generate the refresh clock signal TOSC when the refresh signal SREF is activated. Although the period of the refresh clock signal TOSC is set to be constant in the present embodiment, the present disclosure is not limited thereto.

The refresh pulse generation circuit 135 may receive the refresh clock signal TOSC from the refresh clock generation circuit 133. The refresh pulse generation circuit 135 may generate the refresh pulse RSP during each internal refresh period set by the refresh clock signal TOSC. The refresh pulse RSP may be created to generate an internal refresh signal IREF activated to perform an activation operation for a cell array accessed based on a row address RADD. The refresh pulse generation circuit 135 may generate the PRE-refresh pulse RSP _ PRE before generating the refresh pulse RSP. The PRE-refresh pulse RSP _ PRE may be generated before performing an activation operation for a cell array accessed by the row address RADD.

The internal refresh signal generation circuit 137 may receive the start pulse STRP from the start pulse generation circuit 131 and may receive the refresh pulse RSP from the refresh pulse generation circuit 135. The internal refresh signal generation circuit 137 may generate an internal refresh signal IREF that is activated when the start pulse STRP or the refresh pulse RSP is generated. The internal refresh signal generation circuit 137 may generate an internal refresh signal IREF that is activated when the refresh signal SREF is activated to create the start pulse STRP. The internal refresh signal generation circuit 137 may generate an internal refresh signal IREF that is activated when the refresh pulse RSP is generated during each internal refresh period set by the refresh clock signal TOSC. Although the internal refresh signal IREF is set to be activated during an activation operation for the cell array accessed by the row address RADD in the present embodiment, the present disclosure is not limited thereto.

The refresh end pulse generation circuit 139 may receive the internal refresh signal IREF from the internal refresh signal generation circuit 137. The refresh end pulse generation circuit 139 may generate the refresh end pulse RFINF when the active operation for the cell array is terminated based on the internal refresh signal IREF. Although the refresh end pulse RFINP is generated when a level transition of the internal refresh signal IREF from an active state having a logic "high" level to a deactivated state having a logic "low" level occurs (i.e., in synchronization with a falling edge of the internal refresh signal IREF) in the present embodiment, the present disclosure is not limited thereto. For example, in some other embodiments, the refresh end pulse RFINF may be generated in synchronization with the rising edge of the internal refresh signal IREF.

The drive control signal generation circuit 115 may receive the refresh signal SREF from the command decoder 111. The drive control signal generation circuit 115 may receive the PRE-refresh pulse RSP _ PRE, the internal refresh signal IREF, and the refresh end pulse RFINP from the operation control circuit 113. More specifically, the drive control signal generation circuit 115 may receive the PRE-refresh pulse RSP _ PRE from the refresh pulse generation circuit 135, may receive the internal refresh signal IREF from the internal refresh signal generation circuit 137, and may receive the refresh end pulse RFINP from the refresh end pulse generation circuit 139. The drive control signal generation circuit 115 may generate the drive control signal PCTR set to the first logic level based on the refresh signal SREF deactivated before the refresh operation is performed. When the refresh signal SREF is activated to perform the refresh operation and the internal refresh signal IREF is activated by the start pulse STRP, the driving control signal generation circuit 115 may generate the driving control signal PCTR set to the first logic level. In the case where the refresh operation is performed, the drive control signal generation circuit 115 may generate the drive control signal PCTR having the first logic level during a period from a time point of generating the PRE-refresh pulse RSP _ PRE until a time point of generating the refresh end pulse RFINP. In the case where an activation operation for a cell array accessed by the row address RADD is performed, the driving control signal generation circuit 115 may generate the driving control signal PCTR having a first logic level. In the case where the refresh operation is performed, the driving control signal generation circuit 115 may generate the driving control signal PCTR having the second logic level when the internal refresh signal IREF is deactivated and the PRE-refresh pulse RSP _ PRE is not generated. In the case where the activation operation for the cell array accessed by the row address RADD is not performed, the driving control signal generation circuit 115 may generate the driving control signal PCTR having the second logic level. In this embodiment, the first logic level may be set to a logic "low" level, and the second logic level may be set to a logic "high" level. However, the present disclosure is not limited to examples in which the first logic level is a logic "low" level and the second logic level is a logic "high" level.

The internal voltage generation circuit 117 may receive the power supply voltage VDD from the controller 101. The internal voltage generation circuit 117 may generate the first internal voltage VPPH and the second internal voltage VPPL based on the power supply voltage VDD. The internal voltage generation circuit 117 may be implemented by using a charge pumping circuit such that the levels of the first and second internal voltages VPPH and VPPL are higher than the level of the power supply voltage VDD. In the present embodiment, the level of the first internal voltage VPPH may be set to be higher than the level of the second internal voltage VPPL.

The activation voltage generation circuit 119 may receive the drive control signal PCTR from the drive control signal generation circuit 115. The activation voltage generation circuit 119 may generate an activation voltage SVPP that is driven to the first internal voltage VPPH or the second internal voltage VPPL based on the driving control signal PCTR. The activation voltage generation circuit 119 may drive the activation voltage SVPP to the first internal voltage VPPH when the driving control signal PCTR has the first logic level based on the refresh signal SREF, which is deactivated before the refresh operation is performed. The activation voltage generation circuit 119 may drive the activation voltage SVPP to the first internal voltage VPPH when the driving control signal PCTR has the first logic level based on the activated refresh signal SREF and the internal refresh signal IREF activated by the start pulse STRP. When the driving control signal PCTR has the first logic level during a period from a time point of generating the PRE-refresh pulse RSP _ PRE until a time point of generating the refresh end pulse RFINP, the activation voltage generation circuit 119 may drive the activation voltage SVPP to the first internal voltage VPPH. When the driving control signal PCTR is set to the first logic level by the active operation with respect to the cell array accessed by the row address RADD, the active voltage generation circuit 119 may drive the active voltage SVPP to the first internal voltage VPPH. In the case where the refresh operation is performed, the activation voltage generation circuit 119 may drive the activation voltage SVPP to the second internal voltage VPPL when the driving control signal PCTR is set to the second logic level by the deactivated internal refresh signal IREF and the non-generated PRE-refresh pulse RSP _ PRE. When the driving control signal PCTR is set to the second logic level by not performing the activation operation for the cell array, the activation voltage generation circuit 119 may drive the activation voltage SVPP to the second internal voltage VPPL. In the case where the activation operation is not performed, the activation voltage generation circuit 119 may drive the activation voltage SVPP to the second internal voltage VPPL lower than the first internal voltage VPPH, thereby reducing power consumption of the device 103A. That is, the amount of current leakage such as junction current leakage due to a Gate Induced Drain Leakage (GIDL) phenomenon of the cell transistor included in the device 103A can be reduced.

The row address generation circuit 121 may receive the internal refresh signal IREF from the internal refresh signal generation circuit 137. The row address generation circuit 121 may generate a row address RADD based on the internal refresh signal IREF. The row address generation circuit 121 may generate a row address RADD that is sequentially counted whenever the internal refresh signal IREF is activated. More specifically, the row address generation circuit 121 may generate a row address RADD having a first combination R1 to supply the activation voltage SVPP to a first wordline included in the device 103A when the internal refresh signal IREF is activated for a first time, and may generate a row address RADD having a second combination R2 to supply the activation voltage SVPP to a second wordline included in the device 103A when the internal refresh signal IREF is activated for a second time. When the number of word lines included in the device 103A is "N", the row address generating circuit 121 may generate a row address RADD having an nth combination RAN to supply an activation voltage SVPP to the nth word line included in the device 103A when the internal refresh signal IREF is activated for an nth time (where the number "N" may be set to a natural number). The row address generation circuit 121 may count the row address RADD based on the internal refresh signal IREF until the activation operation for all the cell arrays included in the device 103A is performed.

The word line driving circuit 123 may receive the activation voltage SVPP from the activation voltage generation circuit 119, and may receive the row address RADD from the row address generation circuit 121. The word line driving circuit 123 may supply an activation voltage SVPP to a specific word line to perform an activation operation on a cell array coupled to the specific word line selected by the row address RADD. For example, when a first wordline is selected by a row address RADD having a first combination R1, the wordline driver circuit 123 may supply an activation voltage SVPP to the first wordline to perform an activation operation on a cell array coupled to the first wordline. In one embodiment, when an activation operation for a cell array coupled to a first word line is performed, the activation voltage SVPP supplied to the first word line may be driven to a first internal voltage VPPH higher than a second internal voltage VPPL. In the case of performing the refresh operation, the activation voltage SVPP supplied to the word line may be driven to the first internal voltage VPPH only when an activation operation is performed for the cell array coupled to the word line, and may be driven to the second internal voltage VPPL lower than the first internal voltage VPPH when the activation operation is not performed. As a result, it is possible to reduce the power consumption of the device 103A.

Fig. 3 shows the configuration of the internal refresh signal generation circuit 137. As shown in fig. 3, the internal refresh signal generation circuit 137 may include an or gate 141, a pulse delay circuit (PUL _ DLY)143, and an internal refresh signal LATCH circuit (IREF _ LATCH) 145. The or gate 141 may perform a logical or operation of the start pulse STRP and the refresh pulse RSP to generate the synthetic pulse SUMP. When the start pulse STRP or the refresh pulse RSP has a logic "high" level, the or gate 141 may generate the resultant pulse SUMP having a logic "high" level. The pulse delay circuit 143 may delay the synthesized pulse SUMP to generate a delayed synthesized pulse SUMPd. In the present embodiment, the delay time of the synthesized pulse SUMP delayed by the pulse delay circuit 143 may be set equal to a period in which the activation operation for the cell array is performed. However, the delay time of the synthesized pulse SUMP delayed by the pulse delay circuit 143 is not limited to the present embodiment. The internal refresh signal latch circuit 145 may generate an internal refresh signal IREF that is activated during a period from a time point of generating the synthesis pulse SUMP until a time point of generating the delayed synthesis pulse SUMPd. When the start pulse STRP is generated by the activated refresh signal SREF, the internal refresh signal IREF may be generated. The internal refresh signal IREF may be activated whenever the refresh pulse RSP is generated during each internal refresh period set by the refresh clock signal TOSC. The internal refresh signal IREF may be activated during an activation operation for a cell array accessed by the row address RADD.

Fig. 4 is a circuit diagram showing the configuration of the refresh end pulse generating circuit 139. As shown in fig. 4, the refresh end pulse generating circuit 139 may include an inverter 151, an inversion/delay circuit 153, and a pulse output circuit 155. The inverter 151 may invert the buffered internal refresh signal IREF to output an inverted buffered signal of the internal refresh signal IREF. The inverting/delaying circuit 153 may include an odd number of inverters coupled in series, and may delay and invert an output signal of the inverter 151 to output a delayed and inverted signal of the output signal of the inverter 151. The pulse output circuit 155 may perform a logical and operation on the output signal of the inverter 151 and the output signal of the inverting/delaying circuit 153 to generate the refresh end pulse RFINP. The refresh end pulse RFINP may be generated in synchronization with a point of time when the level of the internal refresh signal IREF changes from a logic "high" level to a logic "low" level (i.e., in synchronization with a falling edge of the internal refresh signal IREF). The refresh end pulse RFINP may be generated in synchronization with a point of time when an activation operation for a cell array accessed by the row address RADD is terminated.

Fig. 5 is a circuit diagram showing the configuration of the drive control signal generation circuit 115. As shown in fig. 5, the driving control signal generation circuit 115 may include inverters 161_1 and 161_3, a nand gate 163, and nor gates 165_1, 165_3, and 165_ 5. The inverter 161_1 may invert the buffered internal refresh signal IREF to output an inverted buffered signal of the internal refresh signal IREF. The nand gate 163 may perform a logical nand operation on the refresh signal SREF and the output signal of the inverter 161_1 to generate the first state signal NA. Before performing the refresh operation, the first state signal NA may be activated to a logic "high" level, and the refresh signal SREF is deactivated to a logic "low" level. The first state signal NA may be set to a logic "high" level when the internal refresh signal IREF is activated to a logic "high" level and the refresh signal SREF is activated to a logic "high" level to perform a refresh operation. The first state signal NA may be set to a logic "low" level when the internal refresh signal IREF is deactivated to a logic "low" and the refresh signal SREF is activated to a logic "high". The nor gate 165_1 may perform a logical nor operation of the output signal of the PRE-refresh pulse RSP _ PRE and the nor gate 165_ 3. The nor gate 165_3 may perform a logical nor operation of the refresh end pulse RFINP, the reset signal RST, and the output signal of the nor gate 165_ 1. The inverter 161_3 may inversely buffer the output signal of the nor gate 165_1 to output an inversely buffered signal of the output signal of the nor gate 165_1 as the second state signal NB. During an initialization operation of the device 103A, the reset signal RST may be generated to have a logic "high" level. The second state signal NB may be set to a logic "high" level during a period from a time point at which the PRE-refresh pulse RSP _ PRE is generated to have a logic "high" level until a time point at which the refresh end pulse RFINP is generated to have a logic "high" level. When the reset signal RST is generated to have a logic "high" level for an initialization operation, the second state signal NB may be set to a logic "low" level. The nor gate 165_5 may perform a logical nor operation on the first and second state signals NA and NB to generate the driving control signal PCTR. Before performing the refresh operation, the driving control signal PCTR may be set to a logic "low" level based on the refresh signal SREF that is disabled to the logic "low" level. The drive control signal PCTR may be set to a logic "low" level when the refresh signal SREF is activated to a logic "high" level for the refresh operation and the internal refresh signal IREF is activated to a logic "high" level by the start pulse STRP. The drive control signal PCTR may be set to a logic "low" level during a period from a time point of generating the PRE-refresh pulse RSP _ PRE until a time point of generating the refresh end pulse RFINP. In the case where the refresh operation is performed, the driving control signal PCTR may be set to a logic "high" level when the internal refresh signal IREF is deactivated to a logic "low" level and the PRE-refresh pulse RSP _ PRE is not generated.

Fig. 6 is a circuit diagram showing the configuration of the activation voltage generating circuit 119. As shown in fig. 6, the activation voltage generation circuit 119 may include PMOS transistors 171_1 and 171_3 and an inverter 173. The PMOS transistor 171_1 may be coupled between a supply terminal of the first internal voltage VPPH and a node nd171 through which the activation voltage SVPP is output, and may be turned on based on the driving control signal PCTR. When the driving control signal PCTR has a logic "low" level, the PMOS transistor 171_1 may be turned on to drive the activation voltage SVPP to the first internal voltage VPPH. The inverter 173 may invert the buffered drive control signal PCTR to output an inverted buffered signal of the drive control signal PCTR. The PMOS transistor 171_3 may be coupled between a supply terminal of the second internal voltage VPPL and a node nd171 through which the activation voltage SVPP is output, and may be turned on based on an output signal of the inverter 173. When the driving control signal PCTR has a logic "high" level, the PMOS transistor 171_3 may be turned on to drive the activation voltage SVPP to the second internal voltage VPPL. The active voltage generation circuit 119 may drive the active voltage SVPP to the first internal voltage VPPH when the driving control signal PCTR is set to a logic "low" level by performing an active operation for the cell array accessed by the row address RADD. The activation voltage generation circuit 119 may drive the activation voltage SVPP to the second internal voltage VPPL when the driving control signal PCTR is set to a logic "high" level by not performing an activation operation for the cell array. In the case where the activation operation for the cell array is not performed, the activation voltage generation circuit 119 may drive the activation voltage SVPP to the second internal voltage VPPL lower than the first internal voltage VPPH to reduce the current leakage of the device 103A. As a result, the power consumption of the device 103A can be reduced.

Fig. 7 to 14 illustrate the operation of the device 103A.

Hereinafter, the operation of device 103A will be described in detail with reference to FIGS. 7 and 8 in connection with an embodiment in which refresh signal SREF is deactivated to a logic "low" level prior to performing a refresh operation. As shown in fig. 7 and 8, when the refresh signal SREF is deactivated to the logic "low" level, the first state signal NA may be set to the logic "high (H)" level, and the driving control signal PCTR may be set to the logic "low (L)" level (see path "S11" of fig. 7). When the driving control signal PCTR has a logic "low (L)" level, the activation voltage SVPP may be driven to have the first internal voltage VPPH (see path "S13" of fig. 7).

Hereinafter, the operation of device 103A will be described in detail with reference to FIGS. 9 and 10 in connection with an embodiment in which refresh signal SREF is activated to a logic "high" level to perform a refresh operation. As shown in fig. 9 and 10, when the refresh signal SREF is activated to a logic "high" level in synchronization with the command CMD having the predetermined combination C1 (see path "S21" of fig. 9), the start pulse STRP may be generated (see path "S23" of fig. 9). When the start pulse STRP is generated, the internal refresh signal IREF may be activated to a logic "high" level (see path "S25" of fig. 9). When the internal refresh signal IREF is activated to a logic "high" level, the first state signal NA may be set to a logic "high (H)" level, and the driving control signal PCTR may be set to a logic "low (L)" (see path "S27" of fig. 9). When the internal refresh signal IREF is activated to a logic "high" level, the row address RADD may be counted as having the first combination R1 (see path "S28" of fig. 9). When the driving control signal PCTR has a logic "low (L)" level, the activation voltage SVPP may be driven to have the first internal voltage VPPH (see path "S29" of fig. 9), and an activation operation may be performed for a cell array coupled to the first word line selected by the row address RADD having the first combination R1.

Hereinafter, the operation performed by the device 103A during each internal refresh period after the refresh signal SREF is activated to the logic "high" level will be described in detail with reference to fig. 11 to 14. As shown in fig. 11 and 12, when the refresh signal SREF is activated to a logic "high" level in synchronization with the command CMD having the predetermined combination C1, the refresh clock signal TOSC may be generated (see path "S31" of fig. 11). The refresh pulse RSP may be generated at a time point when the internal refresh period tREFI elapses from a time point when the refresh clock signal TOSC is generated. Although fig. 1 shows an example in which the internal refresh period tREFI is greater than 3 periods of the refresh clock signal TOSC, the present disclosure is not limited thereto. The refresh pulse RSP may be repeatedly generated at a time point when the internal refresh period tREFI elapses from a time point when the refresh clock signal TOSC is generated. The PRE-refresh pulse RSP _ PRE may be generated before the refresh pulse RSP is generated, and a point of time at which the PRE-refresh pulse RSP _ PRE is generated may be set to be different according to embodiments. As shown in fig. 11 and 12, when the PRE-refresh pulse RSP _ PRE is generated to have a logic "high (H)" level, the driving control signal PCTR may be set to a logic "low (L)" level (see path "S33" of fig. 11), and the activation voltage SVPP may be driven to have the first internal voltage VPPH (see path "S34" of fig. 11). Before the PRE-refresh pulse RSP _ PRE is generated to have a logic "high (H)" level, the driving control signal PCTR may be set to a logic "high (H)" level, and the activation voltage SVPP may be driven to have the second internal voltage VPPL. Therefore, the current leakage of the device 103A can be reduced, and the power consumption of the device 103A can also be reduced. As shown in fig. 11 and 13, when the refresh pulse RSP is generated to have a logic "high" level, the internal refresh signal IREF may be activated to a logic "high" level (see path "S35" of fig. 11). When the internal refresh signal IREF is activated to a logic "high" level, the first state signal NA may be set to a logic "high (H)" level, and the driving control signal PCTR may maintain a logic "low" level (see path "S36" of fig. 11). When the internal refresh signal IREF is activated to a logic "high" level, the row address RADD may be counted as having the second combination R2 (see path "S37" of fig. 11). When the driving control signal PCTR has a logic "low" (L) level, the activation voltage SVPP may be driven to have the first internal voltage VPPH and may perform an activation operation for a cell array coupled to the second word line selected by the row address RADD having the second combination R2. As shown in fig. 11 and 14, the refresh end pulse RFINP may be generated to have a logic "high" level in synchronization with a point of time when the level of the internal refresh signal IREF changes from a logic "high" level to a logic "low" (see path "S38" of fig. 11). Since the internal refresh signal IREF is deactivated to a logic "low" level and the refresh end pulse RFINP is generated to have a logic "high" level, both the first state signal NA and the second state signal NB may be set to a logic "low (L)" level and the drive control signal PCTR may be set to a logic "high (H)" level (see path "S39" of fig. 11). When the driving control signal PCTR is set to a logic "high (H)" level, the activation voltage SVPP may be driven to have the second internal voltage VPPL to reduce current leakage of the device 103A. Thus, the power consumption of the device 103A can be reduced.

Fig. 15 is a block diagram showing a configuration of a device 103B included in the system 10 shown in fig. 1 corresponding to another example of the device 103. As shown in fig. 15, the device 103B may include a command decoder (CMD _ DEC)211, an operation control circuit 213, a drive control signal generation circuit (PCTR _ GEN)215, an internal voltage generation circuit (VPP _ GEN)217, an activation voltage generation circuit (SVPP _ GEN)219, a row address generation circuit (RADD _ GEN)221, and a word line drive circuit (WL _ DRV) 223.

The command decoder 211 may decode the command CMD to generate the refresh signal SREF to perform the refresh operation. The command decoder 211 may generate a refresh signal SREF, which may be activated based on a logic level combination of bits included in the command CMD in a case where a refresh operation is performed. The command decoder 211 may be implemented by using the same circuit as the command decoder 111 included in the device 103A shown in fig. 2.

The operation control circuit 213 may receive the refresh signal SREF from the command decoder 211. The operation control circuit 213 may generate the internal refresh signal IREF, the refresh pulse RSP, the PRE-refresh pulse RSP _ PRE, and the refresh end pulse RFINP based on the refresh signal SREF. When the refresh signal SREF is activated, the operation control circuit 213 may generate an internal refresh signal IREF that is activated to perform an activation operation for a cell array accessed based on the row address RADD. When the refresh signal SREF is activated, the operation control circuit 213 may generate the refresh clock signal TOSC whose period is adjusted based on the temperature, and may generate the refresh pulse RSP during each internal refresh period set by the refresh clock signal TOSC. The operation control circuit 213 may generate an internal refresh signal IREF activated to perform an activation operation for a cell array accessed based on a row address RADD whenever generating a refresh pulse RSP. During each internal refresh period set by the refresh clock signal TOSC, the operation control circuit 213 may generate the PRE-refresh pulse RSP _ PRE before the refresh pulse RSP is generated. In one embodiment, the PRE-refresh pulse RSP _ PRE may be generated before an activation operation is performed for a cell array accessed by the row address RADD. The operation control circuit 213 may generate a refresh end pulse RFINF when an active operation for the cell array is terminated based on the internal refresh signal IREF.

The operation control circuit 213 may include a start pulse generation circuit (STRP _ GEN)231, a temperature sensor (TEMP _ SEN)232, a refresh clock generation circuit (TOSC _ GEN)233, a refresh pulse generation circuit (RSP _ GEN)235, an internal refresh signal generation circuit (IREF _ GEN)237, and a refresh end pulse generation circuit (RFINP _ GEN) 239.

When the refresh signal SREF is activated, the start pulse generating circuit 231 may generate the start pulse STRP. The start pulse generating circuit 231 can be implemented by using the same circuit as the start pulse generating circuit 131 included in the device 103A shown in fig. 2.

The temperature sensor 232 may sense the internal temperature of the device 103B to generate a temperature code TC. The temperature code TC may include a plurality of bits, and each logic level combination of the bits included in the temperature code TC may correspond to an internal temperature of the device 103B. For example, a first logic level combination of temperature codes TC may correspond to a first internal temperature T1 of device 103B, and a second logic level combination of temperature codes TC may correspond to a second internal temperature T2 of device 103B.

The refresh clock generation circuit 233 may receive the refresh signal SREF from the command decoder 211 and may receive the temperature code TC from the temperature sensor 232. When the refresh signal SREF is activated, the refresh clock generation circuit 233 may generate the refresh clock signal TOSC whose period is adjusted based on the temperature code TC. The period of the refresh clock signal TOSC may be adjusted based on a logic level combination of bits included in the temperature code TC. For example, when the internal temperature T2 of the device 103B changes from the first internal temperature T1 to a second internal temperature T2 that is higher than the first internal temperature T1, the period of the refresh clock signal TOSC generated based on the second combination of the temperature codes TC corresponding to the second internal temperature T2 may be shorter than the period of the refresh clock signal TOSC generated based on the first combination of the temperature codes TC corresponding to the first internal temperature T1.

The refresh pulse generation circuit 235 may receive the refresh clock signal TOSC from the refresh clock generation circuit 233. The refresh pulse generation circuit 235 may generate the refresh pulse RSP during each internal refresh period set by the refresh clock signal TOSC. The refresh pulse generation circuit 235 may generate the PRE-refresh pulse RSP _ PRE before generating the refresh pulse RSP. The refresh pulse generation circuit 235 can be implemented by using the same circuit as the refresh pulse generation circuit 135 included in the device 103A shown in fig. 2.

The internal refresh signal generation circuit 237 may receive the start pulse STRP from the start pulse generation circuit 231 and may receive the refresh pulse RSP from the refresh pulse generation circuit 235. The internal refresh signal generation circuit 237 may generate an internal refresh signal IREF that is activated when the start pulse STRP or the refresh pulse RSP is generated. The internal refresh signal generation circuit 237 may be implemented by using the same circuit as the internal refresh signal generation circuit 137 included in the device 103A shown in fig. 2.

The refresh end pulse generation circuit 239 may receive the internal refresh signal IREF from the internal refresh signal generation circuit 237. The refresh end pulse generation circuit 239 may generate the refresh end pulse RFINP when an active operation for the cell array is terminated based on the internal refresh signal IREF. The refresh end pulse generating circuit 239 can be implemented by using the same circuit as the refresh end pulse generating circuit 139 included in the device 103A shown in fig. 2.

The driving control signal generation circuit 215 may receive the refresh signal SREF from the command decoder 211. The drive control signal generation circuit 215 may receive the PRE-refresh pulse RSP _ PRE from the refresh pulse generation circuit 235, may receive the internal refresh signal IREF from the internal refresh signal generation circuit 237, and may receive the refresh end pulse RFINP from the refresh end pulse generation circuit 239. The drive control signal generation circuit 215 may generate the drive control signal PCTR based on the refresh signal SREF, the PRE-refresh pulse RSP _ PRE, the internal refresh signal IREF, and the refresh end pulse RFINP. The drive control signal generation circuit 215 can be realized by using the same circuit as the drive control signal generation circuit 115 included in the device 103A shown in fig. 2.

The internal voltage generation circuit 217 may generate the first internal voltage VPPH and the second internal voltage VPPL based on the power supply voltage VDD. The internal voltage generation circuit 217 can be realized by using the same circuit as the internal voltage generation circuit 117 included in the device 103A shown in fig. 2.

The activation voltage generation circuit 219 may receive the drive control signal PCTR from the drive control signal generation circuit 215. The activation voltage generation circuit 219 may generate an activation voltage SVPP that is driven to the first internal voltage VPPH or the second internal voltage based on the driving control signal PCTR. The activation voltage generation circuit 219 may drive the activation voltage SVPP to the second internal voltage VPPL lower than the first internal voltage VPPH without performing an activation operation, thereby reducing power consumption of the device 103B. That is, it is possible to reduce the amount of current leakage such as junction current leakage due to a Gate Induced Drain Leakage (GIDL) phenomenon of the cell transistor included in the device 103B. The activation voltage generation circuit 219 can be implemented by using the same circuit as the activation voltage generation circuit 119 included in the device 103A shown in fig. 2.

The row address generation circuit 221 may receive an internal refresh signal IREF from the internal refresh signal generation circuit 237. The row address generation circuit 221 may generate a row address RADD based on the internal refresh signal IREF. The row address generation circuit 221 may generate a row address RADD that is sequentially counted whenever the internal refresh signal IREF is activated. The row address generating circuit 221 can be implemented by using the same circuit as the row address generating circuit 121 included in the device 103A shown in fig. 2.

The word line driver circuit 223 may receive the activation voltage SVPP from the activation voltage generation circuit 219 and may receive the row address RADD from the row address generation circuit 221. The word line driving circuit 223 may supply an activation voltage SVPP to a specific word line to perform an activation operation on the cell array coupled to the specific word line selected by the row address RADD. The word line driver circuit 223 can be implemented by using the same circuit as the word line driver circuit 123 included in the device 103A shown in fig. 2.

Fig. 16 is a block diagram showing the configuration of the refresh clock generation circuit 233. As shown in fig. 16, the refresh clock generation circuit 233 may include a unit clock generation circuit (UCLK _ GEN)241, a frequency-divided clock generation circuit (DCLK _ GEN)243, a CODE decoder (CODE _ DEC)245, and a refresh clock selection circuit (TOSC _ SEL) 247.

The unit clock generation circuit 241 may receive the refresh signal SREF from the command decoder 211. The unit clock generating circuit 241 may generate the unit clock signal UCLK when the refresh signal SREF is activated to perform a refresh operation. The period of the unit clock signal UCLK may be set equal to a predetermined unit period, and the predetermined unit period may be set different according to embodiments.

The divided clock generating circuit 243 may receive the unit clock signal UCLK from the unit clock generating circuit 241. The divided clock generating circuit 243 may divide the frequency of the unit clock signal UCLK to generate the divided clock signal DCLK. In the present embodiment, the divided clock signal DCLK may include an "M" divided clock signal of the unit clock signal UCLK. In the "M" divided clock signal, the number "M" may be set to a natural number equal to or greater than 2. For example, the divided clock signal DCLK may include a divided-by-2 clock signal of the unit clock signal UCLK, a divided-by-4 clock signal of the unit clock signal UCLK, and a divided-by-8 clock signal of the unit clock signal UCLK.

The code decoder 245 may receive the temperature code TC from the temperature sensor 232. The code decoder 245 may decode the temperature code TC to generate a decoded signal DEC. The number of bits included in the decoded signal DEC may be set to be greater than the number of bits included in the temperature code TC. The logic level combination of the bits included in the decoded signal DEC may correspond to one of various internal temperatures of the device 103B.

The refresh clock selection circuit 247 may receive the frequency-divided clock signal DCLK from the frequency-divided clock generation circuit 243 and may receive the decoding signal DEC from the code decoder 245. The refresh clock selection circuit 247 may select one of the "M" divided clock signals of the unit clock signal UCLK included in the divided clock signal DCLK based on a logic level combination of the decoding signal DEC to output the selected divided clock signal as the refresh clock signal TOSC. When the internal temperature of the device 103B decreases, the period of the refresh clock signal TOSC may be adjusted to be increased by "M" times the period of the unit clock signal UCLK.

According to an embodiment, an activation voltage supplied to a word line coupled to an accessed cell may be raised only when an activation operation is performed for the cell accessed during a refresh operation to reduce power consumption required to drive the activation voltage during the refresh operation.

In addition, when the activation operation for the accessed cell is not performed during the refresh operation, the activation voltage may be lowered to reduce the amount of current leakage of the accessed cell.

These concepts have been disclosed in connection with some embodiments as described above. Those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the disclosure. Therefore, the embodiments disclosed in the present specification should not be considered from a limiting point of view but from an illustrative point of view. The scope of the concept is not limited by the above description but is defined by the appended claims, and all unique features within the equivalent scope should be construed as being included in the concept.