阅读说明：本技术 半导体装置 (Semiconductor device with a plurality of semiconductor chips ) 是由 杨智铨 于 2021-04-08 设计创作，主要内容包括：本公开提供半导体装置。半导体装置包括位于一存储器区的多个存储器单元以及位于一虚拟区的一第一截止晶体管,而虚拟区相邻于存储器区。每一存储器单元包括一静态随机存取存储器单元,而静态随机存取存储器单元包括一第一下拉晶体管和一第二下拉晶体管。存储器单元包括一第一存储器单元。在第一存储器单元中的第一下拉晶体管的一第一源极/漏极区是电性耦接到第一截止晶体管的一第一源极/漏极区,以及第一截止晶体管的一第二源极/漏极区是电性耦接至一电源电压。(The present disclosure provides a semiconductor device. The semiconductor device comprises a plurality of memory cells located in a memory area and a first cut-off transistor located in a dummy area, wherein the dummy area is adjacent to the memory area. Each memory cell includes a sram cell, which includes a first pull-down transistor and a second pull-down transistor. The memory cell includes a first memory cell. A first source/drain region of the first pull-down transistor in the first memory cell is electrically coupled to a first source/drain region of the first off transistor, and a second source/drain region of the first off transistor is electrically coupled to a power supply voltage.)

1. A semiconductor device, comprising:

a plurality of memory cells in a memory region, wherein each of the memory cells comprises a static random access memory cell comprising a first pull-down transistor and a second pull-down transistor, wherein the memory cell comprises a first memory cell; and

a first cut-off transistor located in a dummy region adjacent to the memory region,

wherein a first source/drain region of the first pull-down transistor in the first memory cell is electrically coupled to a first source/drain region of the first turn-off transistor, and a second source/drain region of the first turn-off transistor is electrically coupled to a power supply voltage.

Technical Field

Embodiments of the present disclosure relate to semiconductor devices, and more particularly, to semiconductor devices having memory cells.

Background

Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic devices. Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor material layers on a semiconductor substrate, and lithographically patterning the material layers to form circuit features and devices on the semiconductor substrate.

The semiconductor industry has continued to reduce the minimum feature size to enable more components to be integrated in a given area to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). However, as the minimum feature size shrinks, additional problems that should be solved also arise.

Static Random Access Memory (SRAM) is commonly used in integrated circuits. SRAM cells have the advantage of saving data without a refresh (refresh). As the speed requirements of integrated circuits continue to increase, the read and write speeds of SRAM cells also become increasingly important.

Disclosure of Invention

The disclosed embodiments provide a semiconductor device. The semiconductor device includes a plurality of memory cells in a memory region and a first off transistor in a dummy region adjacent to the memory region. Each memory cell includes a sram cell, which includes a first pull-down transistor and a second pull-down transistor. The memory cell includes a first memory cell. A first source/drain region of a first pull-down transistor in the first memory cell is electrically coupled to a first source/drain region of the first off transistor, and a second source/drain region of the first off transistor is electrically coupled to a power supply voltage.

Furthermore, the disclosed embodiments provide a semiconductor device. The semiconductor device includes a semiconductor device, a dummy region, a first cut-off transistor and a well pickup region. The first memory cell is located in a memory array and includes a static random access memory cell, wherein the static random access memory cell includes a first pull-down transistor and a second pull-down transistor. The dummy area is along the boundary of the memory array. The first off transistor is located in the dummy region, and has a first source/drain region electrically coupled to a first source/drain region of the first pull-down transistor and a second source/drain region electrically coupled to a ground terminal. The well pick-up zone is adjacent to a dummy zone, wherein the dummy zone is between the well pick-up zone and the memory array.

Furthermore, the disclosed embodiments provide a method of forming a semiconductor device. A memory cell is formed in a memory array. A first pull-down transistor and a second pull-down transistor are formed in a memory region of the memory array. A first cut-off transistor is formed in a dummy area of the memory array. A first source/drain region of the first off transistor is electrically connected to a source/drain region of the first pull-down transistor. A second source/drain region of the first turn-off transistor is electrically connected to a power voltage.

Drawings

FIG. 1 shows a semiconductor wafer including an array of SRAM cells according to some embodiments.

FIG. 2A shows an SRAM array according to some embodiments.

FIGS. 2B and 2C are circuit diagrams illustrating the SRAM cell of FIG. 2A according to some embodiments.

FIG. 3A shows an SRAM array according to some embodiments.

FIG. 3B is a circuit diagram showing the SRAM cell of FIG. 3A in accordance with some embodiments.

FIG. 4A shows an SRAM array according to some embodiments.

FIG. 4B is a circuit diagram showing the SRAM cell of FIG. 4A in accordance with some embodiments.

FIG. 5A shows an SRAM array according to some embodiments.

FIG. 5B is a circuit diagram showing the SRAM cell of FIG. 5A in accordance with some embodiments.

FIG. 6 is a cross-sectional view showing the layers involved in an SRAM cell as described in some embodiments.

7A-7F are block diagrams showing SRAM cell layouts according to some embodiments.

FIGS. 8A-8F are block diagrams showing SRAM cell layouts according to some embodiments.

Wherein the reference numerals are as follows:

10, 20, 20',30, 30': SRAM cell

40: driver

52, 54, 56a-56d, 58a-58 d: grid electrode

62a-62c, 64, 66a-66 b: active region

70A-70I: contact point

74: gate contact

76A-76G, 86, 88, 94: conducting hole

80, 82, 90: conducting wire

100: memory area

110: zone(s)

150: virtual zone

200: PW/NW pickup area

302, 304: CVdd node

306, 308: CVss node

310, 312: SD node

314, BL: bit line

316, BLB: bit line of the reverse

318: BL node

320: BLB node

322, 324: node point

1000: SRAM array

CL: control wire

CVdd: positive supply voltage

contact, Gate _ CO: contact layer

M1-M4: metal layer

STI: OD layer

T1, T2: pull-down transistor

T3, T4: pull-up transistor

T5, T6: transmission gate transistor

T7, T8: cut-off transistor

VDD: positive power supply node

Via _0, Via _1, Via _2, Via _ 3: conductive via layer

Vss: ground connection

WL: word line

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the subject matter provided herein. Specific examples of components and arrangements are described below to simplify the embodiments of the present disclosure. However, these are merely examples and are not intended to limit the scope of the present disclosure. For example, in the following description, forming a first feature over or on a second feature may encompass embodiments in which the first and second features are formed in direct contact, and may also encompass embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact. Moreover, embodiments of the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

In addition, spatially related terms such as "below … (beneath)", "below (below)", "below (lower)", "above … (above)", "above (upper)" and the like are used to explain the relationship between a certain feature and another feature shown in the drawings. These relative terms include a different orientation of the elements being used or operated upon, in addition to the orientation depicted in the figures. Other orientations of the components (rotated 90 degrees or at other orientations) are possible, and the relative spatial relationships provided herein may be similarly explained based on the above principles.

A Static Random Access Memory (SRAM) cell is provided according to various embodiments. This disclosure discusses some variations of some embodiments. Throughout the various views and illustrative embodiments, like reference numerals are used to indicate like elements formed using like processes. Furthermore, although various embodiments are described in the specific context of an SRAM layout, other embodiments may also be applied to other memory cell configurations, such as Read Only Memory (ROM) cells, Dynamic Random Access Memory (DRAM) cells, Magnetic Random Access Memory (MRAM) cells, phase change random access memory (PRAM) cells, and Resistive Random Access Memory (RRAM) cells.

The embodiments disclosed below may reduce standby leakage from the SRAM circuit. Generally, as SRAM circuit design dimensions continue to shrink, the severity of standby leakage problems in SRAM circuits may increase. Most standby leakage in SRAM circuits comes from sub-threshold channel currents. For SRAM circuit designs with smaller transistor sizes and lower threshold voltages, it may be difficult to reduce the standby leakage of the sub-critical channel current. To reduce standby leakage, embodiments may include a switchable high-impedance path between the SRAM cell and the supply voltage Vss. The high impedance path may be one or more transistors formed in a dummy (dummy) region on the edge of the SRAM array electrically interposed between the SRAM cell and a supply voltage Vss, which may be electrical ground. In the standby mode, the transistors in the dummy region may act as resistors, thereby limiting or reducing leakage current, and in the active mode, the transistors in the dummy region are in a low impedance state conducting current. In some embodiments, standby current may be reduced by, for example, approximately 70% compared to designs where no transistors are connected to Vss in the dummy region. Embodiments of SRAM array designs with transistors in the dummy regions can achieve better results without affecting read/write capability due to shorter bit line loading by achieving smaller array sizes with the dummy regions.

Fig. 1 shows an SRAM array 1000 comprising a memory region 100, a P-type well/N-type well (PW/NW) pickup (pickup) region 200 on an opposite side of the memory region 100, and a dummy region 150 disposed between the memory region 100 and the PW/NW pickup region 200. Dummy region 150 may provide space to connect the SRAM cells in memory region 100 with PW/NW pickup region 150 and provide a buffer space between the SRAM cells and the edges of SRAM array 1000. In some embodiments, the dummy region 150 includes three dummy gates and/or is equal to the width of one or more dummy gates (e.g., equal to the width of three dummy gate pitches) between the dummy region 150 and the boundary of the memory region 100 and between the dummy region 150 and the opposite boundary of the PW/NW pickup region 200. In some embodiments, dummy region 150 includes less than three dummy gates, such as two dummy gates, or more than three dummy gates, such as four or five dummy gates. Region 110 is a region representing a reference layout that will be described in more detail, such as the description with reference to the following, e.g., fig. 7A-7F and 8A-8F.

The SRAM array 1000 is formed on a substrate, which may be doped (e.g., with p-type doping or n-type doping), and the substrate may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like. The substrate may be a wafer, such as a silicon wafer or a single die (e.g., a process performed in a wafer and then removed from other elements of the wafer using a singulation process).

Figures 2A-2C show a first memory array layout according to some embodiments. As will be discussed in more detail below, the embodiment shown, for example, in fig. 2A to 2C provides a memory array in which memory cells adjacent to the dummy area 150 are connected to the power supply voltage Vss via off transistors. Other transistors within the memory array may be connected to the power supply voltage Vss without passing through the off transistor. In this manner, the memory cells along the boundary with the dummy region 150 have a high impedance path to the supply voltage Vss, which can reduce leakage along the boundary of the memory array while avoiding the high impedance problem of the supply voltage Vss. In some embodiments, the SRAM array 1000 comprises a total storage capacity of 8Kb for a word line load of 128 bits through the word line WL and a bit line load of 64 bits through the bit line BL. Using 128 SRAM cells 20 under the word line WL along the boundary of each dummy region 150 can reduce the standby leakage current of 8Kb of the SRAM array 1000 by 2 bits (256 bits), for example, by about 3%.

Referring now to FIG. 2A, there is shown an SRAM array comprising SRAM cells 10 and 20, respectively. SRAM cell 10 is disposed along an interior region of the memory array, while SRAM cell 20 is disposed along an interface between the memory array and boundary region 150. The driver 40 is connected to a vertical Bit Line (BL)314 and a bit Bar Line (BLB) 316. The SRAM cells 10 and SRAM cells 20 in each column of the SRAM array are electrically connected to a bit line 314 and a bit bar line 316. Each SRAM cell 10 and each SRAM cell 20 in each column (row) of the SRAM array is connected to a horizontal word line WL.

FIG. 2B is a circuit diagram showing an SRAM cell 10 according to some embodiments. As shown in fig. 1 and 2A, SRAM cell 10 is a memory cell in memory array 100 (see fig. 1) that is separate from the interface between memory array 100 and boundary region 150 (see fig. 1). The SRAM cell 10 includes pull-down (PD) transistors T1 and T2, which may be N-type metal oxide semiconductor (NMOS) transistors; pull-up (PU) transistors T3 and T4, which may be P-type metal oxide semiconductor (PMOS) transistors, and Pass Gate (PG) transistors T5 and T6, which may be NMOS transistors. The gates of PG transistors T5 and T6 are controlled by a Word Line (WL) that determines whether SRAM cell 10 is selected. The latch formed by PU transistors T3 and T4 and PD transistors T1 and T2 stores a bit, the complement of which is stored in the Store Data (SD) node 310 and the SD node 312. The stored bit may be written to or read from the SRAM cell 10 through a complementary bit line including a Bit Line (BL)314 and a bit Bar Line (BLB) 316. The SRAM cell 10 is powered by a positive power supply node VDD having a positive power supply voltage (also denoted CVdd). The SRAM cell 10 is also connected to a supply voltage Vss (also denoted CVss). In some embodiments, Vss or CVss is electrical ground. The transistors T3 and T1 form a first inverter, while the transistors T4 and T2 form a second inverter. The input of the first inverter would be connected to transistor T6 and the output of the second inverter at node 324. The output of the first inverter will be connected to transistor T5 and the input of the second inverter at node 322.

The sources of PU transistors T3 and T4 are connected to CVdd node 302 and CVdd node 304, respectively, which are further connected to the supply voltage (and line) VDD. The sources of PD transistors T1 and T2 are connected to CVss node 306 and CVss node 308, respectively, which are further connected to a supply voltage/line Vss. The gates of transistors T3 and T1 are connected to the drains of transistors T4 and T2, which form a connection node and are referred to as SD node 310. The gates of the transistors T4 and T2 are connected to the drains of the transistors T3 and T1, and the connection node thereof is referred to as the SD node 312. The source/drain region of PG transistor T5 is connected to inversion bit line 316 at BLB node 320. The source/drain regions of PG transistor T6 are connected to bit line 314 at BL node 318.

FIG. 2C is a circuit diagram illustrating the SRAM cell 20 of FIG. 2A according to some embodiments of the present disclosure. As shown in fig. 1 and 2A, SRAM cell 20 is a memory cell in memory array 100 (refer to fig. 1) along the interface between memory array 100 and border region 150 (refer to fig. 1). The circuit diagram of SRAM cell 20 is similar to the layout of SRAM cell 10 in that the source/drains of PD transistors T1 and T2 are connected to the first source/drain of additional cutoff transistor T7 instead of CVss node 306 and CVss node 308, as in SRAM cell 10 of fig. 2B. The off transistor T7 may be an NMOS transistor. The second source/drain region of the off transistor T7 is connected to the power supply voltage Vss. The gate of the off transistor T7 is controlled by the word line WL of the row of memory cells adjacent to the boundary region 150. When the SRAM cell 20 is in the standby mode and the word line WL is not asserted, the turn-off transistor T7 will be turned off and act as a high impedance. The transistor T1 or T2 may split the voltage and reduce the standby leakage of the SRAM cell 20 by turning off the leakage path of the transistor T7 to Vss. The additional off transistor T7 may be located in a dummy region of the SRAM array containing the SRAM cell 20, and thus the off transistor T7 may not require additional process steps to build up or occupy area compared to a design that does not include the off transistor T7.

Fig. 3A-3B are diagrams illustrating layouts of a second memory array according to some embodiments of the present disclosure. As will be discussed in more detail below, embodiments such as those shown in fig. 3A-3B provide a memory array in which memory cells are connected to a supply voltage Vss by an off transistor located in dummy region 150. For example, a plurality of memory cells along the bit line may be connected to a power supply voltage through a single off transistor in the dummy region 150, thereby allowing a high impedance path to be established between each memory cell and the power supply voltage Vss, thereby reducing leakage of individual memory cells in the standby mode. Using SRAM cell 20' (see fig. 3B) instead of SRAM cell 10 may reduce the standby leakage of the SRAM. Standby current may be reduced by approximately 70% compared to a design consisting of only SRAM cells 10 having six transistors, etc., because using SRAM cells 20' may reduce standby current by reducing or limiting leakage through off transistors T7 and/or T8.

Referring now to FIG. 3A, an SRAM array is shown that includes an SRAM cell 20' (see FIG. 3B). The source of the PD transistors T1 and T2 of each SRAM cell 20' is connected to a first source/drain region of one or more off transistors T7 located outside the SRAM array in the dummy region 150. The second source/drain of the cut-off transistor T7 is connected to the power supply voltage Vss. The gates of the off transistors T7 are controlled by respective control lines CL. In some embodiments, the SRAM cells 20' of each row coupled to a single bit line are connected to the turn-off transistor T7, and there is one turn-off transistor T7 for each row of the memory array or memory sub-array. In some embodiments, the control line CL that controls the gate of the off transistor T7 in a row is connected to the bit line and the bit bar line of the respective row, and may be configured to turn on the off transistor T7 when the SRAM cell 20' in the same row and connected to the same respective bit line and bit bar line is selected for reading and/or writing.

FIG. 3B is a circuit diagram showing the SRAM cell 20' of FIG. 3A, in accordance with some embodiments. The circuit diagram of the SRAM cell 20' is similar to the layout of the SRAM cell 20 (refer to fig. 2C), but the turn-off transistor T7 is connected to a separate control line CL instead of the word line WL. The off transistor T7 may be located in the dummy region 150 of the SRAM array including the SRAM cell 20', and thus the off transistor T7 may not require additional process steps to create or occupy area compared to a design that does not include the off transistor T7.

Fig. 4A-4B are diagrams showing a third memory array layout according to some embodiments. As will be discussed in more detail below, embodiments such as that shown in fig. 4A-4B provide a memory array in which memory cells adjacent to dummy region 150 are connected to a power supply voltage Vss via a plurality of off transistors. For example, as discussed in more detail below, the pull-down transistor T1 is electrically coupled to the power supply voltage Vss via a first off transistor, and the pull-down transistor T2 is electrically coupled to the power supply voltage Vss via a second off transistor. Other memory cells in the memory array may be connected to the supply voltage Vss without any of the off transistors. In this manner, the memory cells along the boundary with the dummy region 150 have a high impedance path to the supply voltage Vss, thereby reducing leakage along the memory array boundary. In some embodiments, the SRAM array 1000 includes a total storage capacity of 8Kb for a word line load of 128 bits through the word line WL and a bit line load of 64 bits through the bit line BL. Using 128 SRAM cells 20 under the word line WL along the boundary of each dummy region 150 can reduce the standby leakage current of 8Kb of the SRAM array 1000 by 2 bits (256 bits), for example, by about 3%.

Referring now to FIG. 4A, there is shown an SRAM array comprising SRAM cells 10 and 30, respectively. SRAM cell 10 is disposed along an interior region of the memory array, and SRAM cell 30 is disposed along an interface between the memory array and boundary region 150. Driver 40 is connected to vertical bitline 314 and bitline bar 316. Each SRAM cell 10 and each SRAM cell 30 in each column of the SRAM array is electrically connected to a bit line 314 and a bit bar line 316. The SRAM cells 10 and 30 in each column of the SRAM array are connected to a horizontal word line WL.

FIG. 4B is a circuit diagram showing an SRAM cell 30 according to some embodiments. The circuit diagram of SRAM cell 30 is similar to the layout of SRAM cell 20, where like reference numerals are used to denote like components. In addition, the source of the PD transistor T1 is connected to the first source/drain region of the first off transistor T7, and the source of the PD transistor T2 is connected to the first source/drain region of the second off transistor T8. The first and second off transistors T7 and T8 may be NMOS transistors. The second source/drain regions of the first turn-off transistor T7 and the second source/drain region of the second turn-off transistor T8 are connected to the power supply voltage Vss. The gate of the second off transistor T8 is controlled by the word line WL of the memory cell adjacent to the boundary region 150. When the SRAM cell 20 is in the standby mode and WL is not established, the first off transistor T7 and the second off transistor T8 will be turned off and act as a high impedance. The leakage path of the transistor T1 or T2 to the power supply voltage Vss through the first cut-off transistor T7 and the second cut-off transistor T8, respectively, can separate the voltages and reduce standby leakage of the SRAM cell 20. The off transistors T7 and T8 may be located in the dummy region 150 of the SRAM array including the SRAM cell 30, and thus the off transistors T7 and T8 may not require additional process steps to create or occupy area compared to designs that do not include the off transistors T7 and T8.

FIGS. 5A-5B are diagrams showing a fourth memory array layout according to some embodiments. As will be discussed in more detail below, embodiments such as those shown in fig. 5A-5B provide a memory array in which memory cells are connected to a supply voltage Vss by a plurality of off transistors located in dummy region 150. For example, a plurality of memory cells along a bit line may be connected to a power supply voltage through a first off transistor and a second off transistor, and each memory cell may be located in the dummy region 150 and connected to an individual memory cell through a metal layer as described below, thereby allowing a high impedance path to be created between each memory cell and the power supply voltage Vss, thus reducing leakage of the respective memory cell in the standby mode. Using SRAM cell 30' (see fig. 5B) instead of SRAM cell 10 may reduce the standby leakage of the SRAM. The standby current may be reduced by about 70% compared to a design consisting of only SRAM cells 10 with six transistors, etc., because using SRAM cells 30' may reduce the standby current by turning off the leakage of transistors T7 and/or T8.

Referring now to FIG. 5A, an SRAM array is shown that includes an SRAM cell 30' (see FIG. 5B). The sources of the PD transistors T1 and T2 of each SRAM cell 30' are connected to first source/drain regions of off transistors T7 and T8, respectively, located outside the SRAM array in the dummy region 150. Second source/drains of the cut-off transistors T7 and T8 are connected to the power supply voltage Vss. The gates of the off transistors T7 and T8 are controlled by respective control lines CL. In some embodiments, each pull-down transistor T1 of each SRAM cell 30' in each row of SRAM cells 30' coupled to a single bit line is connected to a first cutoff transistor T7, and the pull-down transistor T2 of each SRAM cell 30' in each row coupled to a single bit line is coupled to a second cutoff transistor T8. Thus, there are two off transistors T7 and T8 per row. In some embodiments, a control line CL controlling the gates of the turn-off transistors T7 and T8 in a row is connected to the bit line and the bit bar line of the respective row, and the control line CL may be configured to turn on the turn-off transistors T7 and T8 when the SRAM cell 30' in the same row and connected to the same respective bit line and bit bar line is selected for reading and/or writing.

FIG. 5B is a circuit diagram showing an SRAM cell 30' according to some embodiments. The circuit diagram of the SRAM cell 30' is similar to the layout of the SRAM cell 30 (refer to fig. 4A-4B), but the turn-off transistors T7 and T8 are connected to separate control lines CL instead of word lines WL. The off transistors T7 and T8 may be located in the dummy region 150 of the SRAM array including the SRAM cell 30', and thus the off transistors T7 and T8 may not require additional process steps to build or occupy area compared to designs that do not include the off transistors T7 and T8.

Fig. 6 is a schematic cross-sectional view showing the layers involved in SRAM cells 10, 20', 30, and 30', which are formed on a semiconductor die or wafer. It is noted that fig. 6 schematically shows various levels of interconnect structures and transistors to provide reference for the layout description provided below, and may not reflect the actual cross-sectional view of the SRAM cell 10, 20', 30, or 30'. The interconnect structure includes a contact layer, an OD (oxide definition or active region) layer, Via layers Via _0, Via _1, Via _2, and Via _3, and metal layers M1, M2, M3, and M4. Each of the layers illustrated includes one or more dielectric layers and conductive features formed therein. The conductive features at the same level may have top surfaces that are substantially horizontal to each other, bottom surfaces that are substantially horizontal to each other, and may be formed simultaneously. The contact layers may include gate contacts (also referred to as contacts) for connecting gates of transistors (such as the exemplary transistors T3 and T4 shown) to upper layers, such as the Via layer Via _0, and source/drain contacts (labeled as "contacts") for connecting source/drains of transistors to upper layers.

Fig. 7A-7F are detailed diagrams illustrating section 110 of fig. 1 showing a layout of features of a memory cell, such as SRAM cell 20 shown in fig. 2C, according to some embodiments. Region 110 includes a portion of memory region 100, a portion of dummy region 150, and a portion of PW/NW pickup region 200. Features are described in different levels of the SRAM cell 20 (e.g., OD layer, contact layer, via layer via _0, metal layer M1, via layer via _1, metal layer M2, refer to fig. 6), described sequentially for clarity.

Referring first to fig. 7A, features are shown in the OD layer (fig. 6) and on the gate electrodes of the various transistors in the SRAM cell 20. The active regions 62a, 62b, and 62c extend from the memory region 100 to the dummy region 150. The active regions 62a, 62b, and 62c may be a plurality of fins, such as two fins. In some embodiments, the active regions 62a, 62b, and 62c extend across the dummy region 150 to the boundary of the PW/NW pick-up region 200. The active region 64 also extends across the boundary of the memory region 100 and the dummy region 150. The active region 64 may be a single fin. The active region 66a may be a single fin in the memory region 100. The active region 66b may be a single fin in the dummy region 150 longitudinally across the active region 66a along a line. The active regions 62a, 62b, 62c, 64, 66a, and 66b may be along the vertical direction Y.

Still referring to fig. 7A, the gate electrodes 52, 54, 56a, 56b, 56c, 56d, 58a, 58b, 58c, and 58d may be along a horizontal direction X perpendicular to the vertical direction Y. Gate electrodes 52 and 54 may be located in memory region 100 along horizontal lines. Gate electrodes 56a and 58a may be in memory region 100 along another horizontal line. In some embodiments, the first gap between gate electrodes 52 and 54 does not align with the second gap between gate electrodes 56a and 58 a. Gate electrodes 56b-56d and 58b-58d may be in dummy region 150 and separated from each other by a gap substantially similar to width W2. In some embodiments, the gate electrodes 56b-56d and 58b-58d that are not part of a transistor may be dummy gates, such as inactive gates. The gaps between gate electrodes 56a-56d and 58a-58d may be aligned along the vertical direction, respectively.

Referring still to fig. 7A, in memory region 100, gate electrode 56 forms PD transistor T1 with underlying active region 62b, and active region 62b may be two or more fins, such as fin 62b, disposed below gate electrode 56a (e.g., gate electrode 56a may be disposed on and extend along a sidewall of active region 62 b). Gate electrode 56a and underlying active region 64 further form PU transistor T3. In some embodiments, the active region T3 is a single fin 64 disposed below the gate electrode 56a (e.g., the gate electrode 56a may be disposed above the active region 64 and extend along sidewalls of the active region 64). Gate electrode 52 and active region 62b form PG transistor T5, and active region 62b may be two or more fins, such as fin 62 b.

As further shown in fig. 7A, the gate electrode 54 and the underlying active region 66a form a PU transistor T4. In some embodiments, the active region 66a is a single fin, such as the fin 66a disposed below the gate electrode 54 (e.g., the gate electrode 54 may be disposed above the active region 66a and extend along sidewalls of the active region 66 a). Gate electrode 54 and the underlying active region 62c further form PD transistor T2. In some embodiments, the active region 62c includes two or more fins, such as fins 62c, disposed below the gate electrode 54 (e.g., the gate electrode 54 may be disposed above the active region 62c and extend along the sidewalls of the active region 62 c). Gate electrode 58a and underlying active region 62c form PG transistor T6. In some embodiments, the gate electrode 58a is disposed over and extends along sidewalls of the active region 62 c.

In the dummy region 150, the gate electrode 56b and the active region 62b form a turn-off transistor T7, and the active region 62b may be two or more fins, such as the fin 62 b. Because the off transistor T7 is located in the dummy region 150 of the SRAM array 1000, the off transistor T7 may not require additional process steps to create or occupy area compared to a design that does not include an off transistor.

According to some embodiments of the present disclosure, the PD transistors T1 and T2, the PU transistors T3 and T4, the PG transistors T5 and T6, and the off transistor T7 are fin field effect transistors (finfets). As previously described, the active regions 64 and 66a are single fins, and the active regions 62b and 62c include multiple fins. Active regions 62b, 62c, 64 and 66a provide the source/drain of the various transistors on opposite sides of the respective gate electrodes.

Fig. 7B shows the features of the SRAM cell 20 at the contact level (see fig. 6) and lower. As shown in fig. 7B, SD node 310 (also see fig. 2A-2C) includes source/drain contacts 70A and gate contacts 72A, which are features in the contact layer of SRAM cell 20 (see fig. 6). In some embodiments where the SRAM cell 20 is fabricated on a physical semiconductor wafer, the contacts 70A and 72A may be formed as a single continuous butt contact, such as an L-shaped butt contact. The source/drain contacts 70A may be elongated and have a longitudinal direction in the X direction, which is parallel to the direction of extension of the gate electrodes 56a and 54. A portion of gate contact 72A is on gate electrode 56a and is electrically connected to gate electrode 56 a. According to some embodiments of the present disclosure, the gate contact 72A has a longitudinal direction in the Y-direction, which is perpendicular to the X-direction.

The SD node 312 includes source/drain contacts 70B and gate contacts 72B. The gate contact 72B has a portion that overlaps the source/drain contact 70B. Since SD node 310 may be symmetrical to SD node 312, the details of gate contact 72B and source/drain contact 70B may be similar to gate contact 72A and source/drain contact 70A, respectively, and are not repeated here for simplicity.

Fig. 7B also shows a gate contact 74 connected to gate electrodes 52, 56B, and 58a, which may be used to electrically couple gate electrodes 52, 56B, and 58a to one or more word lines WL, as will be described in more detail below.

Further, the elongated contact 70C is used to connect the source regions of the PD transistors T1 and T2 to the CVss line (e.g., electrical ground line) through the off transistor T7. The elongated contact 70C has a length direction parallel to the X direction, and may be formed to overlap an edge of the SRAM cell 20. Furthermore, the elongated contact 70C may extend further into adjacent SRAM cells of a different row (column) adjacent to the SRAM cell 20. The elongated contact 70C may be more shared between two adjacent SRAM cells in different columns (rows) adjacent to each other. In addition, the junction 70D is for connecting the source regions of the PU transistors T3 and T4 to a CVdd line (e.g., a power supply voltage line). Contact 70D is part of CVdd nodes 302 and 304 (see also fig. 2A-2C).

As further shown in fig. 7B, contacts 70E and 70F are used to connect the source/drain regions of PG transistors T5 and T6 to bit line BL and bit bar BLB, respectively. Contacts 70E and 70F are part of the bit line bar node 320 and bit line node 316, respectively (see also FIGS. 2A-2C). Contacts 70E and 70F may further be shared between two adjacent SRAM cells in different columns that are adjacent to each other. Elongated contact 70G is used to connect the source/drain region of off transistor T7 to the CVss line (e.g., electrical ground). Additional contacts 70H and 70I are formed over the source/drain regions of the active region 62a of the transistor in another SRAM cell adjacent to SRAM cell 20.

Fig. 7C shows features of the SRAM cell 20 of the via layer via _0 (refer to fig. 6) and lower layers. For example, vias 76 (labeled 76A through 76F) located in via layer via _0 (see fig. 6).

As shown in fig. 7C, the via 76A is connected to a gate contact 74 (e.g., a gate contact for a transistor T5, T6, T7, or T8). The via 76A is then connected to a conductive line 80 (see fig. 7D below), and the conductive line 80 may be used to electrically couple the gate electrodes of the transistors T5, T6, and T7 to one or more word lines WL, as described in more detail below with respect to fig. 7E. Further, the via 76B is connected to the elongated contact 70C (e.g., the source contacts of the PD transistors T1 and T2). The via 76B is further connected to a conductive line 82 (see fig. 7D), and the conductive line 82 may be used to electrically couple the source regions of the PD transistors T1 and T2 to each other and to the source/drain region of the off transistor T7, which is connected to the CVss line (e.g., an electrical ground line), as described in more detail below with respect to fig. 7D. Further, via 76B may extend further into an adjacent SRAM cell in a different row adjacent to SRAM cell 20. Vias 76B may further be shared between two adjacent SRAM cells in different columns adjacent to each other.

In addition, the via 76C is connected to the contact 70D (e.g., the source contacts of the PU transistors T3 and T4). The via 76C would then be connected to the CVdd line, which electrically connects the sources of PU transistors T3 and T4 to CVdd, as shown in fig. 7D below. Thus, via 76C is part of CVdd nodes 302 and 304 (see also fig. 2A-2C). The via 76C may further be shared between two adjacent SRAM cells in different columns that are adjacent to each other.

As further shown in fig. 7C, vias 76D and 76E are connected to contacts 70E and 70F (e.g., source/drain contacts of PG transistors T5 and T6), respectively. Vias 76D and 76E will then connect to bit line bar 316 and bit line 314, respectively. Thus, vias 76D and 76E are part of bit line node 320 and bit line bar node 318, respectively (see also fig. 2A-2C). Vias 76D and 76E may be shared between two adjacent SRAM cells in different columns that abut each other.

Still referring to fig. 7C, the via 76F is connected to the elongated contact 70G. Via 76F will then be connected to a Vss or CVss line (e.g., an electrical ground line), as described in more detail below in fig. 7D.

FIG. 7D shows the features of the SRAM cell 20 at the metal layer M1 and lower (see FIG. 6). For example, various conductive lines, such as conductive line 80, conductive line 82, bit line 314, CVdd line, bit bar line 316, and Vss or CVss line are disposed in metal layer M1 and over various vias in via layer via _ 0.

As shown in fig. 7D, a wire 80 is connected to the via 76A. The conductive line 80 may be used to electrically couple the gate electrodes of the PG transistors T5 and T6 and the off transistor T7 to one or more word lines WL, as described in more detail below with reference to fig. 7E. In addition, a conductive line 82 is connected to the via 76B, and the conductive line 82 may be used to subsequently electrically couple the source regions of the PD transistors T1 and T2 to the CVss line (e.g., an electrical ground line) via the off transistor T7. Furthermore, conductive line 82 may extend further into adjacent SRAM cells in a different row adjacent to SRAM cell 20. Conductive line 82 may further be shared between two adjacent SRAM cells in different columns adjacent to each other. A Vss or CVss line (e.g., an electrical ground line) may be connected to the source/drain region of off transistor T7 through via 76F.

Fig. 7E shows the features of SRAM cell 20 at metal layer M2 and via layer via _1 and lower (see fig. 6). A via 86 is disposed in via layer via _1 and is connected to a conductive line 80, which is electrically connected to via 76A and gate contact 74 (e.g., a gate contact for transistor T5, T6, or T7). The via hole 86 is further connected to the word line WL of the metal layer M2. The word line WL is electrically coupled to the gate electrodes 52, 56A and 56b of the transistors T5, T6 and T7, respectively, via the vias 76A and 86, the conductive line 80 and the gate contact 74 word line. In some embodiments, the off transistor T7 may be coupled to the control line CL instead of the word line WL of the transistors T5 and T6. Thus, the SRAM cell 20 includes a wordline node electrically connected to the gates of PG transistors T5 and T6 and the additional turn-off transistor T7.

As further shown in fig. 7E, via 88 is disposed in via layer via _1, which is connected to wire 82, while wire 82 is connected to via 76B. The via 88 may electrically couple the source regions of the PD transistors T1 and T2 to the CVss line (e.g., an electrical ground line) by turning off transistor T7. The via 88 is further connected to the conductive line 90 of the metal layer M2.

Fig. 7F shows the features of SRAM cell 20 of metal layer M3 and via layer via _2 (see fig. 6) and lower. In fig. 7F, a via hole 94 is provided in a via hole layer via _2 (refer to fig. 6), and a wire 98 is provided in a metal layer M3 (refer to fig. 6). As shown in fig. 7F, conductive line 98 and via 94 electrically connect the source regions of PD transistors T1 and T2 to Vss or CVss lines (e.g., electrical ground lines) via off transistor T7. Accordingly, the conductive line 98 electrically connects the source regions of the PD transistors T1 and T2 to the CVss line (e.g., an electrical ground line) via the source/drain regions of the off transistor T7.

In some embodiments, via 94 is connected to a plurality of wires 98, and wires 98 are connected to each other via higher vias and wires, such as in via layer via _3 and metal layer M4 (see fig. 6). For example, in some embodiments, the conductive line 98 of each memory cell may be more connected to the other source regions of PD transistors T1 and T2 in the adjacent SRAM cell 20, and the source regions of PD transistors T1 and T2 in the adjacent SRAM cell 20 may be coupled to the Vss line via the off transistor T7. When the turning off transistor T7 is in standby mode and acts as a resistor, the source region of the transistor T1 or T2 may reduce standby leakage of the SRAM cell 20 by turning off the leakage path of the transistor T7 to the Vss line.

Fig. 7A to 7F are circuit diagrams showing the SRAM cell 20 shown in fig. 2C according to the embodiment shown in fig. 2A to 2C. In some embodiments of fig. 3A and 3B, the SRAM cell 20' (see fig. 3B) has a similar layout to the SRAM cell 20 shown in fig. 7A-7F, but the off transistors T7 and T8 are connected to one or more separate control lines CL instead of the word lines WL.

Fig. 8A-8F illustrate the region 110 of fig. 1 showing a layout of features of a memory cell, such as the SRAM cell 30 shown in fig. 4B, according to some embodiments. The area 110 includes a portion of the memory area 100, a portion of the dummy area 150, and a portion of the PW/NW pickup area 200. Features are described in different levels of the SRAM cell 30 (e.g., OD layer, contact layer, via layer via _0, metal layer M1, via layer via _1, metal layer M2, refer to fig. 6), described sequentially for clarity.

Referring first to fig. 8A, features are shown in the OD layer (fig. 6) and on the gate electrodes of the various transistors in the SRAM cell 30. The active region and gate electrode may have a substantially similar layout as the SRAM cell 20 shown above with respect to fig. 7A.

In the dummy region 150, the gate electrode 56b forms an additional off transistor T7 with the active region 62b, which may be two or more fins, such as fin 62 b. The gate electrode 58c forms an additional off transistor T8 with the active region 62c, which may be two or more fins, such as fin 62 c. Since the additional turn-off transistors T7 and T8 are located in the dummy region 150 of the SRAM array 1000, the additional turn-off transistors T7 and T8 do not require additional process steps to build up or occupy area compared to designs that do not include the additional turn-off transistors T7 and T8.

According to some embodiments of the present disclosure, the PD transistors T1 and T2, the PU transistors T3 and T4, the PG transistors T5 and T6, and the additional transistors T7 and T8 are fin field effect transistors (finfets). As previously described, the active regions 64 and 66a are single fins, while the active regions 62b and 62c include multiple fins. Active regions 62b, 62c, 64 and 66a provide the source/drain of the various transistors on opposite sides of the respective gate electrodes.

Fig. 8B shows the features of the SRAM cell 30 at the contact level (see fig. 6) and lower. As shown in fig. 8B, SD node 310 (also see fig. 3A-3B) includes source/drain contacts 70A and gate contacts 72A, which are features of the contact layer of SRAM cell 30 (see fig. 6). In some embodiments where the SRAM cell 30 is fabricated on a physical semiconductor wafer, the contacts 70A and 72A may be formed as a single continuous butt contact, such as an L-shaped butt contact. The source/drain contacts 70A may be elongated and have a longitudinal direction in the X direction, which is parallel to the direction of extension of the gate electrodes 56a and 54. A portion of gate contact 72A is on gate electrode 56a and is electrically connected to gate electrode 56 a. According to some embodiments of the present disclosure, the gate contact 72A has a longitudinal direction in the Y-direction, which is perpendicular to the X-direction.

The SD node 312 includes source/drain contacts 70B and gate contacts 72B. The gate contact 72B has a portion that overlaps the source/drain contact 70B. Since SD node 310 may be symmetrical to SD node 312, the details of gate contact 72B and source/drain contact 70B may be similar to gate contact 72A and source/drain contact 70A, respectively, and are not repeated here for simplicity.

Fig. 8B also shows a gate contact 74 connected to gate electrodes 52, 56B, and 58a, which may be used to electrically couple gate electrodes 52, 56B, and 58a to one or more word lines WL, as will be described in more detail below.

Further, elongated contact 70C is used to connect the source region of PD transistor T1 to a CVss line (e.g., an electrical ground line) through off transistor T7. When the transistor T1 is in standby mode and acts as a resistor, the source region of the transistor T1 or T2 may reduce the standby leakage of the SRAM cell 30 through the leakage path of the transistor T1 to the Vss line. The elongated contacts 70C have a length direction parallel to the X direction and may be formed to overlap the edges of the SRAM cell 30. Furthermore, the elongated contacts 70C may extend further into adjacent SRAM cells of a different row adjacent to the SRAM cell 30. The elongated contact 70C may be more shared between two adjacent SRAM cells in different columns adjacent to each other. In addition, the junction 70D is for connecting the source regions of the PU transistors T3 and T4 to a CVdd line (e.g., a power supply voltage line). Contact 70D is part of CVdd nodes 302 and 304 (see also fig. 3A-3B).

As further shown in fig. 8B, contacts 70E and 70F are used to connect the source/drain regions of PG transistors T5 and T6 to bit line BL and bit bar BLB, respectively. Contacts 70E and 70F are part of the bit line bar node 320 and bit line node 316, respectively (see also FIGS. 3A-3B). Contacts 70E and 70F may further be shared between two adjacent SRAM cells in different columns that are adjacent to each other. Elongated contact 70G is used to connect the source/drain region of additional transistor T7 to the CVss line (e.g., an electrical ground line). Additional contacts 70H and 70I are formed over the source/drain regions of the active region 62a of the transistor in another SRAM cell adjacent to SRAM cell 30.

Still referring to fig. 8B, elongated contacts 70J and 70L are used to connect the source region of PD transistor T2 to the source/drain region of off transistor T8, which is connected to a CVss line (e.g., an electrical ground line). Elongated contact 70K is used to connect the source/drain region of off transistor T8 to the CVss line (e.g., an electrical ground line).

Fig. 8C shows features of the SRAM cell 30 of the via layer via _0 (refer to fig. 6) and lower layers. For example, vias 76 (labeled 76A through 76G) located in via layer via _0 (see fig. 6).

As shown in fig. 8C, the via 76A is connected to a gate contact 74 (e.g., a gate contact for a transistor T5, T6, T7, or T8). The via 76A is then connected to a conductive line 80 (see fig. 8D below), the conductive line 80 being operable to electrically couple the gate electrodes of the transistors T5, T6, T7, and T8 to one or more word lines WL, as described in more detail below with respect to fig. 8E. Further, vias 76B and 76G are connected to elongated contacts 70L and 70J (e.g., source or source/drain contacts for transistors T2 and T8, respectively). The vias 76B and 76G are further connected to a conductive line 82 (see fig. 8D), and the conductive line 82 may be used to electrically couple the source region of the PD transistor T2 to the source/drain region of the off transistor T8, which is connected to a CVss line (e.g., an electrical ground line), as described in more detail below with respect to fig. 8D. Further, via 76B may extend further into an adjacent SRAM cell in a different row adjacent to SRAM cell 30. Via 76B may further be shared between two adjacent SRAM cells in different columns adjacent to each other.

In addition, the via 76C is connected to the contact 70D (e.g., the source contacts of the PU transistors T3 and T4). The via 76C would then be connected to the CVdd line, which electrically connects the sources of PU transistors T3 and T4 to CVdd, as shown in fig. 8D below. Thus, via 76C is part of CVdd nodes 302 and 304 (see also fig. 3A-3B). The via 76C may further be shared between two adjacent SRAM cells in different columns that are adjacent to each other.

As further shown in fig. 8C, vias 76D and 76E are connected to contacts 70E and 70F (e.g., source/drain contacts of PG transistors T5 and T6), respectively. Vias 76D and 76E will then connect to bit line bar 316 and bit line 314, respectively. Thus, vias 76D and 76E are part of bit line node 320 and bit line bar node 318, respectively (see also fig. 2A-2C). Vias 76D and 76E may be shared between two adjacent SRAM cells in different columns that abut each other.

Still referring to fig. 8C, vias 76F connect to elongated contacts 70G and 70K. Via 76F will be more connected to a Vss or CVss line (e.g., an electrical ground line), as described in more detail below with respect to fig. 8D.

FIG. 8D shows the features of the SRAM cell 30 at the metal layer M1 and lower (see FIG. 6). For example, various conductive lines, such as conductive line 80, conductive line 82, bit line 314, CVdd line, bit bar line 316, and Vss or CVss line are disposed in metal layer M1 and over various vias in via layer via _ 0.

As shown in fig. 8D, a wire 80 is connected to the via 76A. The conductive line 80 may be used to electrically couple the gate electrodes of the PG transistors T5 and T6 and the additional off transistors T7 and T8 to one or more word lines WL, as described in more detail below with respect to fig. 8F. In addition, a conductive line 82 is connected to via 76B, and conductive line 82 may be used to subsequently electrically couple the source region of PD transistor T2 to a CVss line (e.g., an electrical ground line) via transistor T8. Furthermore, conductive line 82 may extend further into adjacent SRAM cells in a different row adjacent to SRAM cell 30. Conductive line 82 may further be shared between two adjacent SRAM cells in different columns adjacent to each other. A Vss or CVss line (e.g., an electrical ground line) may be connected to the source/drain regions of off transistors T7 and T8 through via 76F.

Fig. 8E shows the features of the SRAM cell 30 at metal layer M2 and via layer via _1 and lower (see fig. 6). A via 86 is disposed in via layer via _1 and is connected to a conductive line 80, which is electrically connected to via 76A and gate contact 74 (e.g., a gate contact for transistor T5, T6, T7, or T8). The via hole 86 is further connected to the word line WL of the metal layer M2. The word line WL is electrically coupled to the gate electrodes 52, 56A, 56b and 58c of the transistors T5, T6, T7 and T8, respectively, via the vias 76A and 86, the conductive line 80 and the gate contact 74 word line. In some embodiments, the turning-off transistors T7 and T8 may be coupled to the control line CL instead of the word line WL of the transistors T5 and T6. Thus, the SRAM cell 30 includes a wordline node electrically connected to the gates of PG transistors T5 and T6 and additional turn-off transistors T7 and T8.

As further shown in fig. 8E, via 88 is disposed in via layer via _1 which is connected to wire 82, and wire 82 is connected to via 76B. The via 88 may then electrically couple the source region of the PD transistor T2 to the CVss line (e.g., an electrical ground line) via the pass transistor T8. The via 88 is further connected to the conductive line 90 of the metal layer M2.

Fig. 8F shows the features of SRAM cell 30 for metal layer M3 and via layer via _2 (see fig. 6) and lower. In fig. 8F, a via hole 94 is provided in a via hole layer via _2 (refer to fig. 6), and a wire 98 is provided in a metal layer M3 (refer to fig. 6). As shown in fig. 8F, a conductive line 98 is connected to via 94, which further electrically connects the source region of PD transistor T2 to a Vss or CVss line (e.g., an electrical ground line) via off transistor T8. Accordingly, conductive line 98 electrically connects the source region of PD transistor T2 to the CVss line (e.g., electrical ground) via the source/drain regions of off transistor T8.

In some embodiments, via 94 is connected to a plurality of wires 98, and wires 98 are connected to each other via higher vias and wires, such as in via layer via _3 and metal layer M4 (see fig. 6). When the turning off transistor T8 is in standby mode and acts as a resistor, the source region of transistor T2 may reduce the standby leakage of the SRAM cell 30 by cutting off the leakage path of transistor T8 to the Vss line. In some embodiments, the conductive line 98 may be more connected to other source regions of the PD transistor T2 in the adjacent SRAM cell 30, and may couple the source region of the PD transistor T2 in the adjacent SRAM cell 20 to the Vss line via the off transistor T8. Other conductive lines and vias (not shown) may couple the source region of PD transistor T1 in the adjacent SRAM cell 30 to Vss through turn-off transistor T7.

Fig. 8A to 8F are circuit diagrams showing the embodiment shown in fig. 4A and 4B, and the circuit diagrams include the SRAM cell 30 shown in fig. 4B. In some embodiments of fig. 5A and 5B, the SRAM cell 30' (see fig. 5B) has a similar layout to the SRAM cell 30 shown in fig. 8A-8F, but the off transistors T7 and T8 are connected to one or more separate control lines CL instead of the word lines WL.

Advantages may be realized by the memory circuit of embodiments of the present disclosure, including reduced standby leakage from the SRAM circuit. Transistors may be formed in dummy regions on the edges of the SRAM array and used in the SRAM cells to provide the power supply voltage Vss (which may be electrically grounded), which may effectively reduce standby leakage without requiring additional wafer area or processing steps. When the control word line is turned off, the transistor in the dummy region can be regarded as a resistance. The standby leakage of SRAM circuitry inside the SRAM array to Vss through the transistors in the dummy region may be reduced by about 70% compared to a design in which no transistors in the dummy region are connected to Vss. Embodiments of SRAM array designs with transistors in the dummy regions can achieve better results without affecting read/write capability due to shorter bit line loading.

The present disclosure provides a semiconductor device. The semiconductor device includes a plurality of memory cells in a memory region and a first off transistor in a dummy region. Each memory cell includes an SRAM cell, and the SRAM cell includes a first pull-down transistor and a second pull-down transistor. The memory cell includes a first memory cell. The virtual area is adjacent to the memory area. A first source/drain region of the first pull-down transistor in the first memory cell is electrically coupled to a first source/drain region of the first off transistor, and a second source/drain region of the first off transistor is electrically coupled to a power supply voltage.

In some embodiments, the supply voltage is ground.

In some embodiments, a first source/drain region of the second pull-down transistor is electrically coupled to the first source/drain region of the first turn-off transistor.

In some embodiments, a gate electrode of the first disable transistor is electrically coupled to a word line.

In some embodiments, the semiconductor device further comprises a second off transistor located in the dummy region. A first source/drain region of the second pull-down transistor in the first memory cell is electrically coupled to a first source/drain region of the second off transistor. A second source/drain region of the second off transistor is electrically coupled to the power voltage.

In some embodiments, a gate electrode of the first off transistor and a gate electrode of the second off transistor are electrically coupled to a word line.

In some embodiments, the memory includes a second memory cell, and the first memory cell and the second memory cell are electrically coupled to the same bit line, wherein the first pull-down transistor of the second memory cell is electrically coupled to the first source/drain region of the first turn-off transistor.

In some embodiments, the memory includes a second memory cell, and the first memory cell and the second memory cell are electrically coupled to the same bit line. The semiconductor device further includes a second off transistor in the dummy region. A first source/drain region of the second pull-down transistor in the second memory cell is electrically coupled to a first source/drain region of the second off transistor. A second source/drain region of the second off transistor is electrically coupled to the power voltage.

In some embodiments, the gate electrodes of the first and second turning-off transistors are coupled to the same control line.

The present disclosure provides a semiconductor device. The semiconductor device includes a first memory cell, a dummy region, a first cut-off transistor, and a well pickup region. The first memory cell is located in a memory array and includes a static random access memory cell, wherein the static random access memory cell includes a first pull-down transistor and a second pull-down transistor. The dummy area is along the boundary of the memory array. The first off transistor is located in the dummy region, and has a first source/drain region electrically coupled to a first source/drain region of the first pull-down transistor and a second source/drain region electrically coupled to a ground terminal. The well pickup region is adjacent to a dummy region, wherein the dummy region is between the well pickup region and the memory array.

In some embodiments, the first memory cell is a memory cell closest to the virtual region among memory cells connected to the same bit line.

In some embodiments, the semiconductor device further includes a second memory cell in the memory array. The first memory array and the second memory cell are electrically coupled to the same bit line, wherein the first blocking transistor is not electrically interposed between the second memory cell and ground.

In some embodiments, the semiconductor device further includes a second memory cell in the memory array. The first memory array and the second memory cell are electrically coupled to the same bit line, wherein a first source/drain region of the first pull-down transistor of the second memory cell is electrically coupled to the first off transistor.

In some embodiments, a gate electrode of the first off transistor and a gate electrode of the second off transistor are electrically coupled to a control line different from a word line.

In some embodiments, the semiconductor device further comprises a second off transistor. The second cut-off transistor has a first source/drain region electrically coupled to a first source/drain region of the second pull-down transistor and a second source/drain region electrically coupled to the ground terminal.

In some embodiments, a gate electrode of the first off transistor and a gate electrode of the second off transistor are electrically coupled to a word line.

In some embodiments, the semiconductor device further includes a second memory cell and a second off transistor in the memory array. The first memory array and the second memory cell are electrically coupled to the same bit line, wherein a first source/drain region of the first pull-down transistor of the second memory cell is electrically coupled to a first source/drain region of the first turn-off transistor. The second off transistor has a first source/drain region electrically coupled to a first source/drain region of the second pull-down transistor of the first memory cell and electrically coupled to a first source/drain region of the second pull-down transistor of the second memory cell, and the second off transistor has a second source/drain region coupled to ground.

In some embodiments, a gate electrode of the first off transistor and a gate electrode of the second off transistor are electrically coupled to a control line different from a word line.

The present disclosure provides a method of forming a semiconductor device. A memory cell is formed within a memory array. A first pull-down transistor and a second pull-down transistor are formed within a memory region of the memory array. A first cut-off transistor is formed in a dummy region of the memory array. A first source/drain region of the first turn-off transistor is electrically connected to a source/drain region of the first pull-down transistor. A second source/drain region of the first turn-off transistor is electrically connected to a power voltage.

In some embodiments, a second off transistor is formed in the dummy region of the memory array. A first source/drain region of the second off transistor is electrically connected to a source/drain region of the second pull-down transistor. A second source/drain region of the second off transistor is electrically connected to the power voltage.

Although the present disclosure has been described with reference to preferred embodiments, it is not intended to be limited thereto, and it is to be understood that changes and modifications can be made by those skilled in the art without departing from the spirit and scope of the present disclosure, and therefore the scope of the present disclosure is to be determined by that defined in the appended claims.