阅读说明：本技术 半导体非易失性存储器器件 (Semiconductor nonvolatile memory device ) 是由 孙永顺 卓荣发 陈学深 蔡新树 王蓝翔 于 2021-05-25 设计创作，主要内容包括：本公开涉及半导体非易失性存储器器件。提供一种存储器器件。该存储器器件包括在衬底中的有源区域、电隔离电极和电介质层。电隔离电极被设置在有源区域之上。电介质层被设置在电隔离电极与有源区域之间,并包括具有第一厚度的第一电介质部分和具有第二厚度的第二电介质部分。(The present disclosure relates to semiconductor non-volatile memory devices. A memory device is provided. The memory device includes an active region, an electrically isolated electrode, and a dielectric layer in a substrate. An electrically isolated electrode is disposed over the active region. A dielectric layer is disposed between the electrically isolated electrode and the active region and includes a first dielectric portion having a first thickness and a second dielectric portion having a second thickness.)

1. A memory device, comprising:

a substrate having an active region;

an electrically isolated electrode over the active region; and

a dielectric layer between the electrically isolated electrode and the active region, wherein the dielectric layer comprises a first dielectric portion having a first thickness and a second dielectric portion having a second thickness.

2. The memory device of claim 1, wherein the electrically isolated electrode is capacitively coupled to a control gate.

3. The memory device of claim 1, wherein the first thickness of the dielectric layer is greater than the second thickness.

4. The memory device of claim 3, wherein the first dielectric portion has a thickness no more than three times a thickness of the second dielectric portion.

5. The memory device of claim 1, wherein the dielectric layer further comprises a third dielectric portion having a third thickness.

6. The memory device of claim 5, wherein the second dielectric portion is disposed between the first dielectric portion and the third dielectric portion of the dielectric layer.

7. The memory device of claim 5, wherein the third thickness is substantially equal to the first thickness.

8. The memory device of claim 5, wherein the first dielectric portion, the second dielectric portion, and the third dielectric portion have different thicknesses.

9. A memory device, comprising:

a substrate having a first active region and a second active region;

an isolation region between the first active region and the second active region;

a first electrically isolated electrode over the first active region;

a second electrically isolated electrode over the second active region; and

a dielectric layer between the first electrically isolated electrode and the first active region, wherein the dielectric layer comprises a first dielectric portion having a first thickness and a second dielectric portion having a second thickness.

10. The memory device of claim 9, wherein the second electrically isolated electrode is spaced apart from the second active region by the second dielectric portion of the dielectric layer.

11. The memory device of claim 10, wherein the second active region, the second dielectric portion of the dielectric layer, and the second electrically isolated electrode form a capacitor for the memory device.

12. The memory device of claim 9, further comprising:

a plurality of doped regions including a first doped region and a second doped region in the first active region, the first doped region and the second doped region located on opposite sides of the first electrically isolated electrode to form a field effect transistor for the memory device.

13. The memory device of claim 12, wherein the plurality of doped regions further comprises a third doped region in the second active region adjacent to the second electrode, wherein the third doped region capacitively biases the second electrically isolated electrode.

14. The memory device of claim 13, wherein the second electrically isolated electrode is at the same potential as the first electrically isolated electrode.

15. The memory device of claim 9, wherein the second electrically isolated electrode is electrically coupled to the first electrically isolated electrode to define a floating gate for the memory device.

16. The memory device of claim 9, wherein the second active region capacitively couples the second electrically isolated electrode.

17. The memory device of claim 9, wherein the second active region has N-type conductivity.

18. The memory device of claim 9, wherein the memory device is a non-volatile memory device.

19. A method of manufacturing a memory device, comprising:

providing a substrate;

forming a first active region;

forming a second active region;

forming a dielectric layer over the first active region and the second active region, wherein the dielectric layer comprises a first dielectric portion having a first thickness and a second dielectric portion having a second thickness; and

forming first and second electrically isolated electrodes over the first and second active regions, respectively, wherein the first and second electrically isolated electrodes are electrically coupled to define a floating gate for the memory device.

20. The method of claim 18, wherein forming the dielectric layer further comprises:

depositing the first dielectric portion over the first active region; and

depositing the second dielectric portion over the first active area adjacent to the first dielectric portion and over the second active area.

Technical Field

The disclosed subject matter relates generally to semiconductor devices and, more particularly, to semiconductor non-volatile memory devices and methods of forming the same.

Background

Memory devices are widely used in semiconductor devices, and may be generally divided into volatile memory devices and non-volatile memory (NVM) devices. Volatile memory devices require a power supply to retain stored information, but lose information when the power supply is interrupted. On the other hand, NVM devices retain stored information even in the absence of power supply.

NVM devices may operate by employing a charge retention mechanism for storing information, such as, but not limited to, a charge storage mechanism or a charge trapping mechanism. For example, charge may be stored in the floating gate structure during a program operation, and charge may be expelled from the floating gate structure during an erase operation of the NVM device (expel).

As the semiconductor industry continues to evolve, it is desirable to provide NVM devices having optimized performance and methods of forming the same.

Disclosure of Invention

To achieve the foregoing and other aspects of the present disclosure, a non-volatile memory (NVM) device and a method of forming the same are presented.

According to an aspect of the present disclosure, a memory device is provided. The memory device includes: a substrate having an active region; an electrically isolated electrode over the active region; and a dielectric layer between the electrically isolated electrode and the active region, wherein the dielectric layer comprises a first dielectric portion having a first thickness and a second dielectric portion having a second thickness.

According to another aspect of the present disclosure, a memory device is provided. The memory device includes: a substrate having a first active region and a second active region; an isolation region between the first active region and the second active region; a first electrically isolated electrode over the first active region; a second electrically isolated electrode over the second active region; and a dielectric layer between the first electrically isolated electrode and the first active region, wherein the dielectric layer comprises a first dielectric portion having a first thickness and a second dielectric portion having a second thickness.

According to yet another aspect of the present disclosure, a method of manufacturing a memory device is provided. The method comprises the following steps: providing a substrate; forming a first active region; forming a second active region; forming a dielectric layer over the first active region and the second active region, wherein the dielectric layer comprises a first dielectric portion having a first thickness and a second dielectric portion having a second thickness; and forming first and second electrically isolated electrodes over the first and second active regions, respectively, wherein the first and second electrically isolated electrodes are electrically coupled to define a floating gate for the memory device.

Drawings

Embodiments of the present disclosure will be better understood by reading the following detailed description in conjunction with the drawings:

fig. 1 is a cross-sectional view of a non-volatile memory (NVM) device according to an embodiment of the present disclosure.

Fig. 2 is a cross-sectional view of a non-volatile memory (NVM) device according to another embodiment of the present disclosure.

Fig. 3A-3D are cross-sectional views of a non-volatile memory (NVM) device showing various stages in forming the NVM device according to embodiments of the present disclosure.

For simplicity and clarity of illustration, the drawings show a general manner of construction, and certain descriptions and details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the discussion of the described embodiments of the present devices. Additionally, elements in the drawings figures are not necessarily drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help to improve understanding of embodiments of the present device. Like reference symbols in the various drawings indicate like elements, and similar reference symbols may, but do not necessarily, indicate similar elements.

Detailed Description

The present disclosure relates to semiconductor non-volatile memory (NVM) devices having optimized performance and methods of forming the same. Various embodiments of the present disclosure will now be described in detail with the aid of the accompanying drawings. It should be noted that similar and corresponding elements are referred to by using the same reference numerals. The embodiments disclosed herein are exemplary and are not intended to be exhaustive or limiting of the disclosure.

Fig. 1 is a cross-sectional view of an NVM device 100 according to an embodiment of the present disclosure. The NVM device 100 can be disposed in a memory cell region of a semiconductor device, and the NVM device 100 can be part of a plurality of NVM devices disposed in an array configuration of rows and columns in the memory cell region. For clarity, only one NVM device is shown. In embodiments of the present disclosure, NVM device 100 may be a Multiple Time Programmable (MTP) NVM device with a floating gate or a flash memory cell.

NVM device 100 may include multiple active regions in a substrate (not shown). The multiple active regions may have different dopant conductivity types, such as P-type or N-type conductivity, as well as different dopant depths and different dopant concentrations. The P-type conductivity dopant may include, but is not limited to, boron, aluminum, or gallium. The N-type conductivity dopant may include, but is not limited to, arsenic, phosphorus, or antimony. For example, the dopant concentration and/or dopant depth in the substrate may vary depending on the technology node and design requirements of the NVM device 100.

The plurality of active regions may include a first active region 102a having a first conductive type and a second active region 102b having a second conductive type in a substrate (not shown). The first active region 102a may be disposed laterally adjacent to the second active region 102 b. In an embodiment of the present disclosure, the first active region 102a may have P-type conductivity and the second active region 102b may have N-type conductivity.

The NVM device 100 can include a Field Effect Transistor (FET)104 formed in the first active region 102 a. The FET 104 may also include a first doped region 106a, a second doped region 106b, a first electrode 108, a dielectric layer 112. The first doped region 106a and the second doped region 106b may be disposed in the first active region 102a at opposite sides of the first electrode 108 such that the first doped region 106a and the second doped region 106b define a channel 110 therebetween. In embodiments of the present disclosure, the first and second doped regions (106 a and 106b, respectively) may have N-type conductivity. In another embodiment of the present disclosure, the first doped region 106a may serve as a drain region of the FET 104 and the second doped region 106b may serve as a source region of the FET 104.

The NVM device 100 can also include a capacitor 114 formed in the second active region 102 b. The capacitor 114 may also include a second electrode 116 and at least one doped region 106 c. The at least one doped region 106c may be disposed in the second active region 102b adjacent to the second electrode 116. In an embodiment of the present disclosure, the at least one third doped region 106c may have an N-type conductivity.

A dielectric layer 112 may be disposed over the first and second active regions (102 a and 102b, respectively). A dielectric layer 112 over the first active area 102a separates the first electrode 108 from the first active area 102a, and a dielectric layer over the second active area 102b separates the second electrode 116 from the second active area 102 b. In an embodiment of the present disclosure, the dielectric layer 112 is formed of silicon dioxide. As will be appreciated by those skilled in the art, other suitable dielectric materials known in the art may also be suitable for use with the embodiments disclosed herein.

The first electrode 108 of the FET 104 and the second electrode 116 of the capacitor 114 may be electrically isolated electrodes, and they may be electrically coupled together to define a floating gate 118; the electrical coupling is generally indicated by a line. The floating gate is an electrically isolated gate structure that serves as charge storage for the NVM device. The electrical coupling between the first electrode 108 and the second electrode 116 may be used to balance the two electrodes at the same potential, while the voltage level of each of them is varied. In an embodiment of the present disclosure, the first electrode 108 and the second electrode 116 may be formed of polysilicon.

Although not shown in the figures, isolation regions may be provided for isolating or separating FET 104 from capacitor 114 and NVM device 100 from adjacent conductive features. For example, the isolation regions may include Shallow Trench Isolation (STI) regions, Deep Trench Isolation (DTI) regions, and the like. In addition, it is understood that other features such as sidewall spacers, Lightly Doped Diffusion (LDD) regions, and silicidation (silicidation) may be further applied to the NVM device 100.

The NVM device can be programmed by utilizing a Hot Carrier Injection (HCI) mechanism and erased by utilizing a Fowler-Nordheim (FN) tunneling mechanism. To increase the performance of NVM devices during a programming operation, it is desirable to increase the coupling ratio of the NVM devices.

The coupling ratio is one of the factors that affect the programming performance of NVM devices. The term "coupling ratio" as used herein refers to the capacitance C of the control gate_CGTotal capacitance C with NVM device_{General assembly}The ratio of (a) to (b). C of NVM device_{General assembly}Is the sum of the capacitances between all terminals of the NVM device and the floating gate, including the capacitance C between the control gate and the floating gate_CGA capacitor C between the source terminal and the floating gate_sA capacitance C between the drain terminal and the floating gate_dAnd a capacitance C between the substrate and the floating gate_b. The coupling ratio of NVM devices affects the operating voltage and device operating speed. In general, a high coupling ratio advantageously enables the use of lower operating voltages while maintaining comparable device operating speeds, thereby achieving optimized programming performance and improving device margin (margin) of the NVM device. By reducing the capacitive coupling between the floating gate and the first active region, the coupling ratio of the NVM device can be increased; this may also be achieved by increasing the thickness of the dielectric layer therebetween.

However, a thicker dielectric layer potentially renders the erase operation ineffective. The electric field necessary for an effective FN tunneling mechanism may not be sufficient to repel charge from the floating gate to the active region through the thicker dielectric layer.

Thus, to balance the programming and erase performance using a thicker dielectric layer, dielectric layer 112 may have different thicknesses. As shown in fig. 1, the dielectric layer 112 includes a first dielectric portion 112a having a first dielectric thickness and a second dielectric portion 112b having a second dielectric thickness. In an embodiment of the present disclosure, the second portion 112b of the dielectric layer is thinner than the first portion 112a of the dielectric layer. In another embodiment of the present disclosure, the dielectric layer 112 of the FET 104 has a second portion 112b of the dielectric layer that may be disposed adjacent to the second doped region 106 b. In yet another embodiment of the present disclosure, the dielectric layer 112 of the capacitor 114 has a second portion 112b of the dielectric layer disposed between the second electrode 116 and the second active region 102 b.

Dielectric layers 112 having different dielectric thicknesses advantageously optimize programming and erasing performance of NVM device 100. The first portion 112a of the dielectric layer is relatively thick, which reduces the capacitive coupling of the first electrode 108 to the first active region 102a, thereby increasing the coupling ratio of the FET 104 and achieving optimized programming operation performance. In addition, the second portion 112b of the dielectric layer is relatively thin, which maintains the effectiveness of the erase operation.

Although the first and second portions of the dielectric layer (112 a and 112b, respectively) are shown in fig. 1 as having substantially similar lengths at the first active region 102a, it is to be understood that the lengths of the first and second portions of the dielectric layer (112 a and 112b, respectively) may not be the same at the first active region 102 a. In the embodiment of the present disclosure, it is preferable that the length of the first portion 112a of the dielectric layer is longer than the length of the second dielectric portion 112b at the first active region 102 a. Having a larger proportion of thicker dielectric layer advantageously reduces the capacitive coupling of the NVM device 100 even further to the substrate and drain, thereby further improving the coupling ratio of the NVM device 100.

In an embodiment of the present disclosure, the first portion 112a of the dielectric layer has a thickness of aboutThe dielectric thickness of (a). In another embodiment of the present disclosure, the second portion 112b of the dielectric layer has at leastThe dielectric thickness of (a). In yet another embodiment, the first portion 112a of the dielectric layer may have a dielectric thickness of no more than three times the thickness of the second dielectric portion 112 b.

As shown in FIG. 1, multiple terminals can be connected to an NVM device100. In an embodiment of the present disclosure, the first operating voltage V₁May be supplied to the first terminal to bias the first doped region 106a, the second operating voltage V₂May be supplied to the second terminal to bias the second doped region 106b, and a third operating voltage V₃May be supplied to the third terminal to bias the third doped region 106 c. The third terminal may be electrically coupled to the second active region 102b to capacitively bias the second electrode 116. In an embodiment of the present disclosure, the third operating voltage V₃May be supplied by the control gate of NVM device 100.

As will be appreciated by those skilled in the art, the first, second and third operating voltages may be provided by on-chip or external circuitry, or a combination thereof.

Fig. 2 is a cross-sectional view of an NVM device 200 according to another embodiment of the present disclosure. The NVM device 200 can be disposed in a memory cell region of a semiconductor device, and the NVM device 200 can be part of a plurality of NVM devices disposed in an array configuration of rows and columns in the memory cell region. For clarity, only one NVM device is shown. In embodiments of the present disclosure, NVM device 200 may be a multi-time programmable (MTP) NVM device with a floating gate or a flash memory cell.

Similar to the embodiment of NVM device 100 in fig. 1, NVM device 200 may include FET 204 and capacitor 214 disposed over first and second active regions 202a and 202b, respectively.

The FET 204 may include a first electrode 208, a first doped region 206a, a second doped region 206b, and a dielectric layer 212; a dielectric layer 212 separates the first electrode 208 from the first active region 202 a. The first doped region 206a and the second doped region 206b are spaced apart to define a channel 210 therebetween and are disposed on opposite sides of the first electrode 208.

The capacitor 214 may include a second electrode 216, at least one third doped region 206c, and a dielectric layer 212 separating the second electrode 216 from the second active region 202 b. The first electrode 208 of the FET 204 may be electrically coupled to the second electrode 216 of the capacitor 214 to define a floating gate 218; the electrical coupling is generally indicated by a line.

The dielectric layer 212 of the FET 204 may also have a different thickness, similar to the dielectric layer 112 in the embodiment of the NVM 100 in fig. 1. The dielectric layer 212 may include a first dielectric portion 212a having a first thickness, a second dielectric portion 212b having a second thickness, and a third dielectric portion 212c having a third thickness, such that the second dielectric portion 212b may be disposed between the first and third portions of the dielectric layer (212 a and 212c, respectively). In an embodiment of the present disclosure, the third thickness may be substantially equal to the first thickness. In other embodiments of the present disclosure, the third thickness may be a different thickness than the first thickness and the second thickness.

In this embodiment of the present disclosure, the first and third portions of the dielectric layer (212 a and 212c, respectively) reduce capacitive coupling of the first electrode 208 to the first active region 202a for optimized programming operations of the NVM device 200 using the HCI mechanism. The second portion 212b of the dielectric layer is relatively thin, advantageously providing for an efficient erase operation of the NVM device using an FN tunneling mechanism.

Fig. 3A-3C are cross-sectional views of an NVM device 100 illustrating a method of forming the NVM device 100 according to embodiments of the present disclosure. For example, certain structures may be conventionally fabricated using known processes and techniques, and the various aspects of the disclosure may also be implemented using specifically disclosed processes and methods.

As shown in fig. 3A, a first active region 102a and a second active region 102b may be disposed in a substrate (not shown). The first and second active regions (102 a and 102b, respectively) may be regions defined to form a FET 104 and a capacitor 114, respectively, for the NVM device 100. The first active region 102a and the second active region 102b may be formed by introducing dopants into the substrate.

A dielectric layer 112 may be deposited over the first and second active regions (102 a and 102b, respectively). The dielectric layer 112 may be deposited using various deposition techniques, such as, but not limited to, Chemical Vapor Deposition (CVD) or plasma-enhanced CVD. In an embodiment of the present disclosure, the dielectric layer 112 may be deposited to have a thickness of aboutIs measured.

Fig. 3B shows NVM device 100 after patterning dielectric layer 112 according to an embodiment of the present disclosure. The dielectric layer 112 may be patterned using various patterning techniques such that portions of the dielectric layer 112 may be removed, leaving a first portion 112a of the dielectric layer over the first active region 102 a.

As used herein, "patterning techniques" include depositing patterned materials or photoresists, patterning, exposing, developing, etching, cleaning and/or removing patterned materials or photoresists as needed in forming the described patterns, structures or openings. Illustrative examples of techniques for patterning include, but are not limited to, wet etch photolithography processes, dry etch photolithography processes, or direct patterning processes. Such techniques may use mask sets and/or mask layers.

As described above in fig. 3A and 3B, the deposition of the dielectric layer and the patterning of the first portion 112a of the dielectric layer may be performed simultaneously with other active devices having similar dielectric thicknesses, such as transistors in other regions of the semiconductor device. No additional patterning mask or layer is required to specifically pattern the first portion 112a of the dielectric layer.

Fig. 3C shows the NVM device 100 after forming the second portion of the dielectric layer 112b according to an embodiment of the present disclosure. A layer of dielectric material may be deposited to form the second portion 112b of the dielectric layer. The second portion of the dielectric layer 112b may be deposited over the first active region 102a and over the second active region 102b adjacent to the first portion of the dielectric layer 112 a. The second portion 112b of the dielectric layer may share a patterned mask or layer with other active devices (such as transistors) having similar dielectric thicknesses in other regions of the semiconductor device, and may be fabricated simultaneously with those active devices.

In embodiments of the present disclosure, the first portion 112a of the dielectric layer, as well as other areas, may be protected with a layer of material, such as a patterned layer or a photoresist layer, such that a second layer of dielectric material may not be deposited over the first portion 112a of the dielectric layer. The first and second portions of the dielectric layer (112 a and 112b, respectively) form the dielectric layer 112 of the NVM device 100.

The second portion 112b of the dielectric layer may be deposited to a thinner thickness than the first dielectric portion 112 a. In embodiments of the present disclosure, the second portion 112b of the dielectric layer may be deposited to aboutIs measured. In another embodiment, the second portion 112b of the dielectric layer may be deposited to a thickness of no less than one third of the thickness of the first portion 112 a. In an embodiment of the present disclosure, the dielectric layer 112 comprises silicon dioxide.

Fig. 3D shows NVM device 100 after forming first electrode 108 and second electrode 116 according to an embodiment of the present disclosure. A layer of conductive material may be deposited over the first and second active regions 102a, 102b, covering the dielectric layer 112. The layer of conductive material may be patterned using various patterning techniques to form the first electrode 108 over the first active region 102a and the second electrode 116 over the second active region 102 b. The first electrode 108 in the first active region 102a and the second electrode 116 in the second active region 102b may be coupled together to define a floating gate 118; the electrical coupling is generally indicated by a line. In an embodiment of the present disclosure, the conductive material layer may include polysilicon.

NVM device 100 may undergo further fabrication steps to form FET 104 and capacitor 114. Multiple doped regions can be fabricated similar to the embodiment of NVM device 100 shown in fig. 1. The first doped region 106a and the second doped region 106b may be disposed on opposite sides of the first electrode 108, thereby forming a channel 110 between the first doped region and the second doped region (106 a and 106b, respectively). At least one third doped region 106c may be disposed adjacent to the second electrode 116.

It is understood that other fabrication steps, such as, but not limited to, forming contact structures, depositing interlayer dielectric layers, and forming interconnect structures, may further be performed to NVM device 100.

As described above, various embodiments of NVM devices having dielectric layers of different thicknesses have been described. The NVM device can be disposed in a memory cell region of the semiconductor device, and the NVM device can be part of a plurality of NVM devices disposed in an array configuration of rows and columns in the memory cell region.

Dielectric layers with different dielectric thicknesses advantageously optimize the performance of NVM device 100. The thicker portion of the dielectric layer improves the coupling ratio of the NVM device for optimized programming operations using the HCI mechanism, while the thinner portion of the dielectric layer enables efficient erase operations using the FN tunneling mechanism. The dielectric thickness can be adjusted accordingly to achieve the desired performance of the NVM device.

NVM devices can be operated by applying appropriate operating voltages. The memory access operation may include a program operation, an erase operation, or a read operation. When the floating gate is inherently an electrically isolated gate structure, a voltage may be supplied to the floating gate through the capacitively coupled control gate.

Table 1 below shows an exemplary set of voltages that may be supplied to an NVM device for different memory access operations. It should be understood that other suitable types of voltage values may be provided depending on the design and technology node of the NVM device. Programming and erasing NVM devices has techniques known in the art.

In the description and claims, the terms "top," "bottom," "over," "under," and the like, if any, are used for descriptive purposes and not necessarily for describing permanent relative positions. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the device described herein are, for example, capable of operation in other orientations than those illustrated or otherwise described herein.

In addition, in the following description, forming a first feature over or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature interposed between the first and second features may be formed such that the first and second features may not be in direct contact.

Similarly, if a method is described herein as involving a series of steps, the order of such steps as presented herein is not necessarily the only order in which such steps may be performed, and some of the recited steps may be omitted and/or some other steps not described herein may be added to the method. Furthermore, the terms "comprises," "comprising," "includes," "including," "has," "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements is not necessarily limited to those elements, but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. The appearances of the phrase "in an embodiment" in this document are not necessarily all referring to the same embodiment.

Moreover, unless otherwise indicated, all numbers expressing quantities, ratios, and numerical characteristics of materials, reaction conditions, and so forth used in the specification and claims are to be understood as being modified in all instances by the term "about.

While several exemplary embodiments have been presented in the foregoing detailed description of the devices, it should be appreciated that a vast number of variations exist. It should also be appreciated that the embodiments are merely examples, and are not intended to limit the scope, applicability, size, or configuration of the device in any way. Rather, the foregoing detailed description will provide those skilled in the art with a convenient road map for implementing an exemplary embodiment of the device, it being understood that various changes may be made in the function and arrangement of elements and method of manufacture described in an exemplary embodiment without departing from the scope of the disclosure as set forth in the appended claims.