阅读说明：本技术 数据访问方法、控制器、存储器和存储介质 (Data access method, controller, memory and storage medium ) 是由 吴边 于 2020-06-10 设计创作，主要内容包括：本申请提供数据访问方法、控制器、存储器和存储介质,包括：接收应用端发送的访问请求,其中,所述访问请求中携带访问地址；若所述访问地址中包含的任一地址是错误节点地址,基于错误节点地址与映射节点地址的映射关系确定映射节点地址；基于所述访问请求和所述映射节点地址对数据进行读写访问。(The application provides a data access method, a controller, a memory and a storage medium, comprising: receiving an access request sent by an application terminal, wherein the access request carries an access address; if any address contained in the access address is an error node address, determining a mapping node address based on a mapping relation between the error node address and the mapping node address; and performing read-write access on data based on the access request and the mapping node address.)

1. A method of data access, comprising:

receiving an access request sent by an application terminal, wherein the access request carries an access address;

if any address contained in the access address is an error node address, determining a mapping node address based on a mapping relation between the error node address and the mapping node address;

and accessing data based on the access request and the mapping node address.

2. The method according to claim 1, wherein before receiving the access request sent by the application, the method further comprises:

and establishing a mapping relation between the error node address and the mapping node address.

3. The method of claim 2, wherein determining the mapping relationship between the error node address and the mapping node address comprises:

performing read-write test on the storage space by taking the node as a unit;

determining the node address failed in the test as the error node address;

selecting any node from the node addresses which are tested successfully as the mapping node address;

and establishing a mapping relation between the error node address and the mapping node address.

4. The method of claim 3, wherein before performing the read/write test on the storage space in units of nodes, the method further comprises:

the storage space is divided in units of nodes.

5. The method according to claim 3, wherein before performing read-write test on the storage space of the dynamic memory in units of nodes, the method further comprises:

setting a preset number of recording bits; the recording bit is used for recording the mapping relation between the error node address and the mapping node address.

6. The method of claim 5, wherein a valid flag is further recorded in the recording bit, wherein the valid flag is used to indicate whether the record is valid.

7. The method of claim 5, wherein the establishing a mapping relationship between the faulty node address and the mapping node address comprises:

and under the condition that the number of the error node addresses is smaller than the number of the recording bits, sequentially recording the mapping relation between the error node addresses and the mapping node addresses in each recording bit.

8. The method of claim 5, wherein the number of recording bits is determined by the application.

9. The method of claim 3, wherein after establishing the mapping relationship between the faulty node address and the mapping node address, further comprising:

and sending the number of the error node addresses to the application end.

10. A controller, comprising: the unit of access is recorded, wherein,

the record access unit is configured to receive an access request sent by an application terminal, wherein the access request carries an access address; if any address contained in the access address is an error node address, determining a mapping node address based on a mapping relation between the error node address and the mapping node address; and accessing data based on the access request and the mapping node address.

11. The controller of claim 10, further comprising: a test unit, wherein,

the test unit is configured to perform read-write test on the storage space of the memory by taking the node as a unit, and transmit the node address failed in the test to the record access unit;

and the record access unit is configured to determine the node address failed in the test as the error node address, determine the node address successful in the tail test of the storage space as the mapping node address, and establish a mapping relation between the error node address and the mapping node address.

12. A memory comprising a controller according to any of claims 10-11.

13. A storage medium, characterized in that the storage medium stores a computer program which, when executed by a processor, implements the method of any one of claims 1-9.

Technical Field

The present application relates to the field of storage technologies, and in particular, to a data access method, a controller, a memory, and a storage medium.

Background

Fig. 1 is a schematic structural diagram of a Dynamic Random Access Memory (DRAM) controller, as shown in fig. 1, the DRAM controller includes two interfaces: the application end is connected with the DRAM controller through the application end interface, the DRAM controller uses the DRAM as a storage space with continuous addresses through the DRAM chip interface, and the DRAM chip meets the access time sequence required by the DRAM for accessing.

In practical application, due to the DRAM itself, part of the storage in the DRAM may be damaged and cannot be used, and if the damaged area is not accessed in an identified way, an error in accessing data is caused, so that the application side is affected.

In general application, after a chip is powered on, a controller performs read-write test on a DRAM chip, if a test failure occurs in part of addresses during reading and writing and because a part of a storage area in the DRAM chip is damaged, at this time, if the controller and the DRAM chip are mutually independent, the DRAM chip needs to be replaced, and if the controller and the DRAM chip are sealed together, such as an HBM chip, the whole sealed chip needs to be replaced.

Disclosure of Invention

The data access method, the controller, the memory and the storage medium are used for improving the utilization rate of the dynamic memory and saving the product cost.

In a first aspect, an embodiment of the present application provides a data access method, including:

receiving an access request sent by an application terminal, wherein the access request carries an access address;

if any address contained in the access address is an error node address, determining a mapping node address based on a mapping relation between the error node address and the mapping node address;

and performing read-write access on data based on the access request and the mapping node address.

In a second aspect, an embodiment of the present application provides a controller, including: the unit of access is recorded, wherein,

the record access unit is configured to receive an access request sent by an application terminal, wherein the access request carries an access address; if any address contained in the access address is an error node address, determining a mapping node address based on a mapping relation between the error node address and the mapping node address; and performing read-write access on data based on the access request and the mapping node address.

In a third aspect, an embodiment of the present application provides a memory including the controller according to any one of the embodiments of the present application.

In a fourth aspect, embodiments of the present application provide a storage medium storing a computer program, which when executed by a processor implements the method according to any one of the embodiments of the present application.

According to the data access method, the controller, the memory and the storage medium provided by the embodiment of the application, if any address contained in the access address is an error node address, a mapping node address is determined based on a mapping relation between the error node address and the mapping node address; and performing read-write access on data based on the access request and the mapping node address. The problem that a part of storage areas in the DRAM chip are damaged and the DRAM chip needs to be replaced is solved, the effect of improving the utilization rate of the DRAM chip is achieved, the product cost is saved, and the product availability is improved.

With regard to the above embodiments and other aspects of the present application and implementations thereof, further description is provided in the accompanying drawings description, detailed description and claims.

Drawings

FIG. 1 is a schematic diagram of a DRAM controller;

FIG. 2 is a flow chart of a data access method provided by an embodiment of the present application;

fig. 3 is a schematic diagram of a recording manner of a mapping relationship provided in an embodiment of the present application;

FIG. 4 is a schematic diagram of testing and recording mapping relationships according to an embodiment of the present disclosure;

FIG. 5 is a schematic structural diagram of a controller provided in an embodiment of the present application;

Detailed Description

To make the objects, technical solutions and advantages of the present application more apparent, embodiments of the present application will be described in detail below with reference to the accompanying drawings. It should be noted that the embodiments and features of the embodiments in the present application may be arbitrarily combined with each other without conflict.

The steps illustrated in the flow charts of the figures may be performed in a computer system such as a set of computer-executable instructions. Also, while a logical order is shown in the flow diagrams, in some cases, the steps shown or described may be performed in an order different than here.

In one embodiment, a memory access method is provided, and fig. 2 is a flowchart of a memory access method provided by an embodiment of the present application. The memory access method is performed by a controller of a memory.

As shown in fig. 2, the memory access method provided in the embodiment of the present application mainly includes steps S11, S12, and S13.

S11, receiving an access request sent by an application terminal, wherein the access request carries an access address.

S12, if any address contained in the access address is the wrong node address, determining the mapping node address based on the mapping relation between the wrong node address and the mapping node address.

And S13, accessing data based on the access request and the mapping node address.

In this embodiment, the node address can be understood as the number of each segment of the storage space that is transmitted consecutively.

In this embodiment, the wrong node address may be understood as an address where the memory is damaged and unusable when the memory performs a read/write test, resulting in a test failure. The mapping node address can be understood as an address of a memory, which can be normally used and successfully tested when the memory is subjected to read-write test.

In the embodiment, after the access address is determined, whether the access address exists in a mapping table for recording the mapping relationship between the wrong node address and the mapping node address is judged, and if the access address exists in the mapping table, the access address is determined to be the wrong node address. If the address does not exist in the mapping table, the access address is determined to be the correct node address, and the DRAM can be accessed by directly using the original address.

In an exemplary embodiment, before receiving the access request sent by the application, the method further includes: and establishing a mapping relation between the error node address and the mapping node address.

It should be noted that the mapping relationship between the error node address and the mapping node address may be determined by using any storage method. In this embodiment, the above-mentioned mapping relationship is recorded by using a mapping relationship table, specifically, as shown in fig. 3, a "valid flag" indicates whether the record is valid, an "error node address" indicates a node address failing the test, and a "mapping node address" indicates a node address succeeding the test for replacing the node address.

In an exemplary embodiment, the determining a mapping relationship between the error node address and the mapping node address includes: performing read-write test on the storage space by taking the node as a unit; determining the node address failed in the test as the error node address; selecting any node from the node addresses which are tested successfully as the mapping node address; and establishing a mapping relation between the error node address and the mapping node address.

In this example, read-write testing is performed on the storage space in units of nodes, and the node address failing the testing and the node address succeeding the testing are sequentially recorded. And determining the node address failed in the test as an error node address, and determining the node address successful in the test as a correct node address. And counting the number of the wrong node addresses, and selecting a specified number of correct node addresses from the correct node addresses as mapping node addresses of the wrong node addresses. Wherein the specified number is the number of erroneous node addresses.

Further, the error node address and the mapping node address are in a one-to-one correspondence relationship.

Furthermore, when the mapping node mapping address is selected from the correct node address, the mapping node mapping addresses can be selected from the tail of the storage space in sequence. For example, in a DRAM having 16 node memory spaces, where addresses 3, 8, and 12 fail the test, addresses 15, 14, and 13 may be selected as mapping addresses corresponding to addresses 3, 8, and 12, respectively.

In this embodiment, the storage space of the memory needs to be divided in units of nodes. Wherein a node size is determined by user access characteristics and DRAM characteristics, such as 32B, 64B, 512B, 1024B, etc. .

In an exemplary embodiment, before performing read-write test on the storage space of the dynamic memory by taking the node as a unit, the method further includes: setting a preset number of recording bits; the recording bit is used for recording the mapping relation between the error node address and the mapping node address.

In an exemplary embodiment, a valid flag is further recorded in the recording bit, wherein the valid flag is used to indicate whether this record is valid.

In this embodiment, each recording bit includes a valid flag. When the valid mark is in the first state, the record is indicated to be valid, and when the valid mark is in the second state, the record is indicated to be invalid. The first state and the second state may be designed according to the actual situation, for example: the first state may be "1" and the second state may be "0". That is, when the valid flag is 1, this record is indicated to be valid, and when the valid flag is 0, this record is indicated to be invalid.

In an exemplary embodiment, the establishing a mapping relationship between the error node address and the mapping node address includes: and under the condition that the number of the error node addresses is smaller than the number of the recording bits, sequentially recording the mapping relation between the error node addresses and the mapping node addresses in the corresponding recording bits.

In an exemplary embodiment, the number of recording bits is determined by an application.

In this embodiment, the number of recording bits is determined by the application side, which can be understood as the number of recording bits is determined by the extent of memory loss that the application side can afford. The tolerable storage loss degree can be understood as the occupation ratio of the allowable error byte addresses of the application end. For example: in a DRAM with 16 node storage spaces, the tolerable storage loss degree is 25%, and the identification application end can allow 4 wrong node addresses to exist, namely the number of the recording bits is 4.

Further, in the case that the number of the error node addresses is greater than the number of the recording bits, it indicates that the percentage of the error node addresses in the entire storage space has exceeded the tolerable storage loss of the application, i.e. the error node addresses are too many, and the application cannot effectively read data. Therefore, the access error caused by a large number of wrong node addresses in the storage space can be avoided.

In an exemplary embodiment, after the establishing a mapping relationship between the faulty node address and the mapping node address, the method further includes: and sending the number of the error node addresses to an application end.

In this embodiment, the number of the error node addresses is sent to the application side, the application side uses the node capacity that is successfully tested actually as an effective space, and the effective space is considered to be a continuous space from the DRAM start address.

In one exemplary embodiment, a method of determining a mapping relationship of an erroneous node address to the mapping node address and accessing memory is provided. In this embodiment, a DRAM is used as an example for description.

In the first step, the dynamic memory controller partitions the entire DRAM memory space at node granularity.

Wherein the node size is determined according to the user access characteristics and the characteristics of the DRAM, such as 32B, 64B, 512B, 1024B, etc.

And secondly, setting a corresponding number of recording corresponding bits according to the storage capacity loss degree which can be borne by the application end by the dynamic memory controller.

In this embodiment, the number of recording bits is determined by the application side, which can be understood as the number of recording bits is determined by the extent of memory loss that the application side can afford. The tolerable storage loss degree can be understood as the occupation ratio of the allowable error byte addresses of the application end. For example: in a DRAM with 16 node storage spaces, the tolerable storage loss degree is 25%, and the identification application end can allow 4 wrong node addresses to exist, namely the number of the recording bits is 4.

And thirdly, the dynamic memory controller performs read-write test on the whole DRAM storage space by taking the node as a unit and records the node address failed in the test.

And fourthly, if the number of the nodes which fail the test is less than the storage capacity loss degree which can be born by the application end, sequentially recording the mapping relation between the node address which fails the test and the node address which is used for replacing the tail part of the node address and succeeds the test in each recording bit.

Fifthly, informing the application end of the number of the nodes which fail the test.

Sixthly, the application end uses the node capacity which is tested successfully actually as an effective space, and the effective space is considered to be a continuous space from the DRAM starting address.

And seventhly, after receiving the access request of the application terminal, the dynamic memory controller judges whether the access address has a record in the record bit, if so, the corresponding node address is used for accessing the DRAM instead, otherwise, the original address of the application terminal is used for accessing the DRAM.

The memory access method provided by the embodiment achieves the effect of improving the utilization rate of the dynamic memory, saves the product cost and improves the product availability.

In an exemplary implementation manner, a recording manner of a mapping relationship between an error node address and the mapping node address is provided, and fig. 3 is a schematic diagram of the recording manner of the mapping relationship provided in the embodiment of the present application, as shown in fig. 3, a "valid flag" indicates whether a record is valid, an "error node address" indicates a node address failing to be tested, and a "mapping node address" indicates a node address succeeding to be tested and used to replace the node address.

In an application example, an application example of a memory access method is provided, and the specific processing steps are as follows:

1. assuming that the DRAM has 16 node storage spaces, the application end can accept that at most 4 nodes are unavailable.

If the DRAM test result shows that the node addresses 3,7,13 fail, a mapping table as shown in fig. 4 is generated, which indicates that the node 15, the node 14, and the node 12 are used to replace the wrong node 3, node 7, and node 13.

And 3, informing the DRAM test result to an application end, wherein the application end accesses the DRAM by using 13 nodes in the maximum space.

4. When the application accesses the node addresses 3,7 and 13, the dynamic memory controller will replace the node addresses 15, 14 and 12 respectively.

In one embodiment, the present application further provides a controller.

As shown in fig. 5, the controller includes a recording access unit, wherein,

the record access unit is configured to be the record access unit and configured to receive an access request sent by an application terminal, wherein the access request carries an access address; if any address contained in the access address is an error node address, determining a mapping node address based on a mapping relation between the error node address and the mapping node address; and accessing data based on the access request and the mapping node address.

In one embodiment, the controller further comprises: a test unit, wherein,

the test unit 5 is configured to perform read-write test on the storage space of the memory by taking the node as a unit, and transmit the node address failed in the test to the record access unit;

and the record access unit is configured to determine the node address failed in the test as the error node address, determine the node address successful in the tail test of the storage space as the mapping node address, and establish a mapping relation between the error node address and the mapping node address.

On the basis of the above embodiment, the test unit also transmits the node address of which the test is successful to the record accessing unit.

The test unit transmits the read-write test result to the record access unit to record the corresponding bit, records the mapping relation between the node address failed in the read-write test and the node address used for replacing the node address in the record access unit, and when the application terminal initiates read-write access, the record access unit judges whether to map and how to map according to the access address, and then accesses the DRAM chip by the final address.

The controller provided in the embodiment can execute the memory access method provided in any embodiment of the invention, and has corresponding functional modules and beneficial effects for executing the method. For technical details that are not described in detail in this embodiment, reference may be made to a memory access method provided by any embodiment of the present invention.

It should be noted that, in the embodiment of the controller, the included units and modules are merely divided according to functional logic, but are not limited to the above division as long as the corresponding functions can be implemented; in addition, specific names of the functional units are only used for distinguishing one functional unit from another, and are not used for limiting the protection scope of the application.

In an embodiment, an embodiment of the present application further provides a memory, where the memory includes any one of the controllers provided in the foregoing embodiments, and is capable of executing the memory access method provided in any embodiment of the present invention, and the memory access method includes functional modules and beneficial effects corresponding to the execution of the method. For technical details that are not described in detail in this embodiment, reference may be made to a memory access method provided by any embodiment of the present invention.

In an exemplary embodiment, the present application also provides a storage medium containing computer-executable instructions, which when executed by a computer processor, perform a data access method, including;

receiving an access request sent by an application terminal, wherein the access request carries an access address;

if any address contained in the access address is an error node address, determining a mapping node address based on a mapping relation between the error node address and the mapping node address;

and accessing data based on the access request and the mapping node address.

Of course, the storage medium provided in the embodiments of the present application contains computer-executable instructions, and the computer-executable instructions are not limited to the operations of the method described above, and may also perform related operations in the data access method provided in any embodiments of the present application.

From the above description of the embodiments, it is obvious for those skilled in the art that the present application can be implemented by software and necessary general hardware, and certainly can be implemented by hardware, but the former is a better embodiment in many cases. Based on such understanding, the technical solutions of the present application may be embodied in the form of a software product, which may be stored in a computer-readable storage medium, such as a floppy disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a FLASH Memory (FLASH), a hard disk or an optical disk of a computer, and includes several instructions for enabling a computer device (which may be a personal computer, a server, or a network device) to execute the methods described in the embodiments of the present application.

The above description is only exemplary embodiments of the present application, and is not intended to limit the scope of the present application.

It will be clear to a person skilled in the art that the term user terminal covers any suitable type of wireless user equipment, such as a mobile phone, a portable data processing device, a portable web browser or a car mounted mobile station.

In general, the various embodiments of the application may be implemented in hardware or special purpose circuits, software, logic or any combination thereof. For example, some aspects may be implemented in hardware, while other aspects may be implemented in firmware or software which may be executed by a controller, microprocessor or other computing device, although the application is not limited thereto.

Embodiments of the application may be implemented by a data processor of a mobile device executing computer program instructions, for example in a processor entity, or by hardware, or by a combination of software and hardware. The computer program instructions may be assembly instructions, Instruction Set Architecture (ISA) instructions, machine related instructions, microcode, firmware instructions, state setting data, or source code or object code written in any combination of one or more programming languages.

Any logic flow block diagrams in the figures of this application may represent program steps, or may represent interconnected logic circuits, modules, and functions, or may represent a combination of program steps and logic circuits, modules, and functions. The computer program may be stored on a memory. The memory may be of any type suitable to the local technical environment and may be implemented using any suitable data storage technology, such as, but not limited to, Read Only Memory (ROM), Random Access Memory (RAM), optical storage devices and systems (digital versatile disks, DVDs, or CD discs), etc. The computer readable medium may include a non-transitory storage medium. The data processor may be of any type suitable to the local technical environment, such as but not limited to general purpose computers, special purpose computers, microprocessors, Digital Signal Processors (DSPs), Application Specific Integrated Circuits (ASICs), programmable logic devices (FGPAs), and processors based on a multi-core processor architecture.

The foregoing has provided by way of exemplary and non-limiting examples a detailed description of exemplary embodiments of the present application. Various modifications and adaptations to the foregoing embodiments may become apparent to those skilled in the relevant arts in view of the following drawings and the appended claims without departing from the scope of the invention. Therefore, the proper scope of the invention is to be determined according to the claims.