阅读说明：本技术 三维存储器及其制造方法 (Three-dimensional memory and manufacturing method thereof ) 是由 吴亮 颜元 刘修忠 朱文琪 于 2021-08-26 设计创作，主要内容包括：本公开提供一种三维存储器的制造方法,包括：在衬底的第一表面形成延伸至衬底中的沟道柱；其中,沿沟道柱的径向,沟道柱包括：导电的沟道层以及围绕所述沟道层的绝缘的功能层；从衬底的第二表面去除衬底,以显露沟道柱的第一端部；其中,第二表面为衬底的第一表面的相反面；去除第一端部显露的功能层,以显露沟道层；其中,显露的沟道层被氧化形成氧化子层；形成覆盖氧化子层的第一导电层；在形成第一导电层后,对氧化子层进行第一离子注入,以破坏氧化子层的连续性；在进行第一离子注入后,对第一导电层和所述氧化子层进行热处理,以使沟道层与所述第一导电层电连接。(The present disclosure provides a method of manufacturing a three-dimensional memory, including: forming a channel pillar extending into the substrate at a first surface of the substrate; wherein, along the radial direction of channel post, the channel post includes: a conductive channel layer and an insulating functional layer surrounding the channel layer; removing the substrate from the second surface of the substrate to reveal the first end of the channel pillar; wherein the second surface is the opposite of the first surface of the substrate; removing the functional layer exposed from the first end part to expose the channel layer; wherein, the exposed channel layer is oxidized to form an oxide sublayer; forming a first conductive layer covering the oxide sublayer; after the first conductive layer is formed, carrying out first ion implantation on the oxide sublayer so as to destroy the continuity of the oxide sublayer; after the first ion implantation is performed, the first conductive layer and the oxide sublayer are subjected to heat treatment to electrically connect the channel layer with the first conductive layer.)

1. A method of fabricating a three-dimensional memory, comprising:

forming a channel pillar on a first surface of a substrate, the channel pillar extending into the substrate; wherein, along a radial direction of the channel pillar, the channel pillar includes: a conductive channel layer and an insulating functional layer surrounding the channel layer;

removing the substrate from the second surface of the substrate to reveal the first end of the channel pillar; wherein the second surface and the first surface are opposite surfaces of the substrate;

removing the functional layer exposed from the first end part to expose the channel layer; wherein the exposed channel layer is oxidized to form an oxide sublayer;

forming a first conductive layer covering the oxide sublayer;

after the first conductive layer is formed, carrying out first ion implantation on the oxide sublayer so as to destroy the continuity of the oxide sublayer;

after the first ion implantation is performed, heat treatment is performed on the first conductive layer and the oxide sublayer to electrically connect the channel layer and the first conductive layer.

2. The method of claim 1, further comprising:

before forming the first conductive layer, performing second ion implantation on the first end part on which the oxide sub-layer is formed to form a conductive first protective layer covering the first end part; wherein the first protective layer is to reduce oxygen particles from reacting with the remaining channel layer.

3. The method according to claim 1 or 2,

the forming a channel pillar on a first surface of a substrate extending into the substrate includes:

forming a channel hole through the stacked structure at the first surface of the substrate and extending into the substrate;

forming the functional layer covering the side wall and the bottom of the channel hole;

forming the channel layer overlying the functional layer;

prior to removing the substrate, the method further comprises:

performing third ion implantation on the bottom of the channel layer from the first surface of the substrate to form a conductive second protective layer between the bottom of the channel layer and the functional layer; wherein the second protective layer is to reduce oxygen particles from reacting with the channel layer.

4. The method of claim 1, wherein the constituent particles of the oxide sublayer include oxygen particles and first particles;

after the first conductive layer is formed, performing first ion implantation on the oxide sublayer to break continuity of the oxide sublayer, including:

and injecting second particles into the oxide sublayer, wherein the second particles bombard the oxide sublayer to break chemical bonds between the oxygen particles and the first particles and form gaps in the oxide sublayer.

5. The method of claim 1, wherein the implant elements of the first ion implantation comprise at least one of:

arsenic element; indium element; neon element; argon element; krypton element; a xenon element; and (4) nitrogen element.

6. The method of claim 1, wherein the first ion implantation has an implant element energy range of: 100 kilo-electron volts to 3 mega-electron volts.

7. The method of claim 1, wherein thermally treating the first conductive layer and the oxide sub-layer comprises:

and annealing the first conductive layer and the oxide sublayer so that the oxide sublayer and the first conductive layer after ion implantation form an integral structure, and at least part of implantation elements in the ion implantation process escape from the oxide sublayer and form a gas product.

8. The method of claim 7, wherein the annealing process comprises furnace tube annealing, laser annealing, or any combination thereof.

9. The method of claim 7,

the method further comprises the following steps: forming an insulating isolation layer covering the first surface of the substrate; forming a stacked structure covering the isolation layer;

the removing the functional layer exposed from the first end portion to expose the channel layer includes: removing the functional layer exposed from the first end portion to form a first recess that is recessed toward the stacked structure along a first direction perpendicular to the substrate; wherein an end portion of the remaining functional layer is in contact with the separator.

10. The method of claim 1,

after forming the channel pillar, the method further comprises:

forming a groove which penetrates through the laminated structure along a direction vertical to the substrate and exposes the substrate in the laminated structure of the first surface of the substrate; the laminated structure comprises a plurality of first insulating layers and a plurality of sacrificial layers which are sequentially and alternately laminated;

removing the plurality of sacrificial layers in the laminated structure based on the grooves to form gaps between the adjacent first insulating layers;

filling the gaps to form a plurality of second conductive layers;

forming a second insulating layer covering the side wall of the groove;

filling the trench including the second insulating layer with a conductive material.

11. A three-dimensional memory, comprising:

a first conductive layer;

a stacked structure stacked with the first conductive layer, the stacked structure including a plurality of second conductive layers and a plurality of first insulating layers stacked alternately; wherein one of the first insulating layers is in contact with the first conductive layer;

a channel pillar extending through the stacked structure and into the first conductive layer; in a radial direction of the channel pillar, the channel pillar includes: a conductive channel layer and an insulating functional layer surrounding the channel layer;

the channel pillar further includes: a second end portion within the first conductive layer, the second end portion comprising: the channel layer and an oxide layer between the channel layer and the first conductive layer; wherein the oxide layer has a slit through which the first conductive layer and the channel layer are electrically connected.

12. The three-dimensional memory according to claim 11, further comprising:

and the conductive first protective layer is positioned between the oxide sublayer and the first conductive layer, covers the second end part of the channel column and is used for reducing the reaction of oxygen particles and the channel layer at the second end part.

13. The three-dimensional memory according to claim 11 or 12, further comprising:

a second, electrically conductive, protective layer between the channel layer and the functional layer at the second end portion for reducing oxygen particle reaction with the channel layer.

Technical Field

The embodiment of the disclosure relates to the technical field of semiconductors, in particular to a three-dimensional memory and a manufacturing method thereof.

Background

With the continuous improvement of semiconductor manufacturing processes, the process feature size is smaller and smaller, and the storage density of the memory device is higher and higher. To meet the demand for higher memory density, memory devices with three-dimensional structures have been developed. The 3D NAND memory has the advantages of high writing speed, simple erasing operation, higher storage density and the like, and is widely applied.

The conventional 3D NAND memory, which includes a plurality of memory cells stacked in a vertical direction, can increase the memory density by a multiple on a unit area of a wafer while reducing the cost. In the related art, the storage density is usually increased by increasing the number of stacked memory cells, but the process is more and more complicated while the number of stacked memory chips is increased. However, during the multi-process conversion, the wafer is exposed to air for a long time to generate defects, which affect the performance parameters of the structures formed on the wafer, and finally cause the quality of the memory devices to be reduced. Therefore, when the process is continuously complicated, how to solve the influence of the external environment on the wafer process, optimize the influence among different processes, and reduce the occurrence of defects becomes an urgent problem to be solved.

Disclosure of Invention

In a first aspect of the embodiments of the present disclosure, a method for manufacturing a three-dimensional memory is provided, including:

forming a channel pillar on a first surface of a substrate, the channel pillar extending into the substrate; wherein, along a radial direction of the channel pillar, the channel pillar includes: a conductive channel layer and an insulating functional layer surrounding the channel layer;

removing the substrate from the second surface of the substrate to reveal the first end of the channel pillar; wherein the second surface and the first surface are opposite surfaces of the substrate;

removing the functional layer exposed from the first end part to expose the channel layer; wherein the exposed channel layer is oxidized to form an oxide sublayer;

forming a first conductive layer covering the oxide sublayer;

after the first conductive layer is formed, carrying out first ion implantation on the oxide sublayer so as to destroy the continuity of the oxide sublayer;

after the first ion implantation is performed, heat treatment is performed on the first conductive layer and the oxide sublayer to electrically connect the channel layer and the first conductive layer.

In some embodiments, the method further comprises:

before forming the first conductive layer, performing second ion implantation on the first end part on which the oxide sub-layer is formed to form a conductive first protective layer covering the first end part; wherein the first protective layer is to reduce oxygen particles from reacting with the remaining channel layer.

In some embodiments of the present invention, the,

the forming a channel pillar on a first surface of a substrate extending into the substrate includes:

forming a channel hole through the stacked structure at the first surface of the substrate and extending into the substrate;

forming the functional layer covering the side wall and the bottom of the channel hole;

forming the channel layer overlying the functional layer;

prior to removing the substrate, the method further comprises:

performing third ion implantation on the bottom of the channel layer from the first surface of the substrate to form a conductive second protective layer between the bottom of the channel layer and the functional layer; wherein the second protective layer is to reduce oxygen particles from reacting with the channel layer.

In some embodiments of the present invention, the,

the composition particles of the oxide sublayer comprise oxygen particles and first particles;

after the first conductive layer is formed, performing first ion implantation on the oxide sublayer to break continuity of the oxide sublayer, including:

and injecting second particles into the oxide sublayer, wherein the second particles bombard the oxide sublayer to break chemical bonds between the oxygen particles and the first particles and form gaps in the oxide sublayer.

In some embodiments of the present invention, the,

the implant elements of the first ion implantation include at least one of:

arsenic element; krypton element; a xenon element; and (4) nitrogen element.

In some embodiments of the present invention, the,

the energy range of the implanted elements of the first ion implantation is as follows: 100 kilo-electron volts to 3 mega-electron volts.

In some embodiments of the present invention, the,

the thermally treating the first conductive layer and the oxide sublayer includes:

and annealing the first conductive layer and the oxide sublayer so that the oxide sublayer and the first conductive layer after ion implantation form an integral structure, and at least part of implantation elements in the ion implantation process escape from the oxide sublayer and form a gas product.

In some embodiments of the present invention, the,

the annealing treatment comprises furnace tube annealing, laser annealing or any combination.

In some embodiments, the method further comprises:

the method further comprises the following steps: forming an insulating isolation layer covering the first surface of the substrate; forming a stacked structure covering the isolation layer;

the removing the functional layer exposed from the first end portion to expose the channel layer includes: removing the functional layer exposed from the first end portion to form a first recess that is recessed toward the stacked structure along a first direction perpendicular to the substrate; wherein an end portion of the remaining functional layer is in contact with the separator.

In some embodiments of the present invention, the,

after forming the channel pillar, the method further comprises:

forming a groove which penetrates through the laminated structure along a direction vertical to the substrate and exposes the substrate in the laminated structure of the first surface of the substrate; the laminated structure comprises a plurality of first insulating layers and a plurality of sacrificial layers which are sequentially and alternately laminated;

removing the plurality of sacrificial layers in the laminated structure based on the grooves to form gaps between the adjacent first insulating layers;

filling the gaps to form a plurality of second conductive layers;

forming a second insulating layer covering the side wall of the groove;

filling the trench including the second insulating layer with a conductive material.

In a second aspect of the embodiments of the present disclosure, there is provided a three-dimensional memory, including:

a first conductive layer;

a stacked structure stacked with the first conductive layer, the stacked structure including a plurality of second conductive layers and a plurality of first insulating layers stacked alternately; wherein one of the first insulating layers is in contact with the first conductive layer;

a channel pillar extending through the stacked structure and into the first conductive layer; in a radial direction of the channel pillar, the channel pillar includes: a conductive channel layer and an insulating functional layer surrounding the channel layer;

the channel pillar further includes: a second end portion within the first conductive layer, the second end portion comprising: the channel layer and an oxide layer between the channel layer and the first conductive layer; wherein the oxide layer has a slit through which the first conductive layer and the channel layer are electrically connected.

In some embodiments, the three-dimensional memory further comprises:

and the conductive first protective layer is positioned between the oxide sublayer and the first conductive layer, covers the second end part of the channel column and is used for reducing the reaction of oxygen particles and the channel layer at the second end part.

In some embodiments, the three-dimensional memory further comprises:

a second, electrically conductive, protective layer between the channel layer and the functional layer at the second end portion for reducing oxygen particle reaction with the channel layer.

In the related art, a wet etching process is generally performed on an oxide sublayer of an exposed channel layer, and then a conductive material is deposited. However, even if the oxide layer on the surface of the channel layer is removed by wet etching, the re-exposed channel layer continues to be oxidized to form an oxide layer after a long time, so that the time interval between processes needs to be strictly controlled, thereby increasing the throughput pressure and reducing the process window. Furthermore, the etchant used for wet etching may etch the second insulating layer in the gate gap structure, increasing the probability of electrical connection between the subsequently deposited conductive material and the conductive layer in the stacked structure, and thus increasing the probability of device failure due to electrical leakage.

According to the scheme provided by the embodiment of the disclosure, an ion implantation process is adopted to replace a wet etching process for removing the oxide sub-layer. The method comprises the steps of firstly forming a first conducting layer covering an oxide sublayer, then carrying out first ion implantation on the oxide sublayer to destroy the continuity of the oxide sublayer, and finally carrying out heat treatment on the first conducting layer and the oxide sublayer to enable a channel layer to be electrically connected with the first conducting layer.

Compared with the related art, the technical scheme provided by the embodiment of the disclosure does not need to perform a process of removing the oxide sub-layer by wet etching, and the gate gap structure cannot be damaged by the first ion implantation, so that the probability of electric leakage of the first conductive layer and the conductive layer of the stacked structure is reduced, and the yield of devices is improved. Moreover, the first ion implantation process is performed after the first conductive layer is formed, the first conductive layer can prevent the channel layer from contacting with the external atmospheric environment after the oxide sublayer is removed, and the probability of further oxidation of the channel layer is reduced.

Drawings

FIGS. 1a to 1d are schematic diagrams illustrating a method of fabricating a three-dimensional memory according to an exemplary embodiment;

FIG. 2 is a schematic flow chart diagram illustrating a method of fabricating a three-dimensional memory according to an embodiment of the present disclosure;

fig. 3a to 3g are schematic diagrams illustrating a method of fabricating a three-dimensional memory according to an embodiment of the present disclosure;

fig. 4a to 4d are schematic diagrams illustrating a method of fabricating a three-dimensional memory according to an embodiment of the present disclosure;

fig. 5a to 5b are schematic views illustrating a method of manufacturing a three-dimensional memory according to an embodiment of the present disclosure;

fig. 6a to 6c are schematic diagrams illustrating a structure of a three-dimensional memory according to an embodiment of the present disclosure.

Detailed Description

The technical solution of the present disclosure is further described in detail below with reference to the drawings and specific embodiments of the specification. While exemplary implementations of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited by the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

The present disclosure is more particularly described in the following paragraphs with reference to the accompanying drawings by way of example. Advantages and features of the present disclosure will become apparent from the following description and claims. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present disclosure.

It is to be understood that the meaning of "on … …," "over … …," and "over … …" of the present disclosure should be read in the broadest manner such that "on … …" not only means that it is "on" something without intervening features or layers therebetween (i.e., directly on something), but also includes the meaning of being "on" something with intervening features or layers therebetween.

In the embodiments of the present disclosure, the terms "first", "second", and the like are used for distinguishing similar objects, and are not necessarily used for describing a particular order or sequence.

In embodiments of the present disclosure, the term "layer" refers to a portion of material that includes a region having a thickness. A layer may extend over the entirety of the underlying or overlying structure or may have an extent that is less than the extent of the underlying or overlying structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure having a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of the continuous structure, or a layer may be between any horizontal pair at the top and bottom surfaces of the continuous structure. The layers may extend horizontally, vertically and/or along inclined surfaces.

Fig. 1a and 1b are schematic diagrams illustrating a method of fabricating a three-dimensional memory according to an exemplary embodiment, the method comprising the steps of:

the method comprises the following steps: referring to fig. 1a, a semiconductor structure is provided; the semiconductor structure includes: the semiconductor device includes a substrate 100, an isolation layer 120 and a stacked structure 110, a gate-gap structure 13 penetrating the stacked structure 110 and the isolation layer 120 and extending into the substrate 100, and a channel pillar 14; wherein, along the first direction, the stack structure 110 includes: a plurality of second conductive layers 111 and a plurality of first insulating layers 112 alternately stacked in this order;

step two: referring to fig. 1b, the channel pillar 14 includes, in a radial direction of the channel pillar 14: a conductive channel layer 142 and an insulating functional layer 143, the functional layer 143 may comprise a silicon oxide/silicon nitride/silicon oxide (ONO) composite layer. Etching away the substrate 100 to expose the first end portion 141 of the channel pillar 14, and etching away the functional layer 143 exposed by the first end portion 141 to expose the channel layer 142; wherein the exposed channel layer 142 is oxidized into the oxide sublayer 147.

Illustratively, the process of etching away the first end portion may be one of wet etching, dry etching or any combination thereof.

It is emphasized that the channel layer material comprises single crystal silicon and/or polycrystalline silicon material. After removing the channel pillar, the channel layer is exposed. In the process conversion process and the waiting process, the channel layer is in direct contact with air, and silicon of the channel layer is oxidized to generate an oxide layer. However, this oxide layer is not required for the process, and instead, the presence of the oxide layer may destroy the electrical connection between the first conductive layer formed in the fourth subsequent step and the channel layer, which may affect the electrical performance of the memory device.

Step three: referring to fig. 1c, the oxide sublayer 147 is etched away.

Illustratively, the process for etching away the oxide sublayer may be one of wet etching, dry etching or any combination thereof.

Step four: referring to fig. 1D, a conductive material covering the first end portion 141 and the stacked structure 110 forms a first conductive layer 170, which may be electrically connected to the channel layer 142 of the channel pillar 14 to supply power to the memory cell as an Array Common Source (ACS) of the 3D NAND. The conductive material may be polysilicon or monocrystalline silicon, and the embodiment is preferably polysilicon.

The first direction may be a Z direction in the drawing, the second direction may be an X direction in the drawing, and the radial direction of the channel pillar 14 may be parallel to the X direction.

However, in the actual memory manufacturing process, the mutual influence of the sequential processes can cause the generation of defects. Specifically, referring to fig. 1b, after removing the functional layer 143 exposed from the first end portion 141, the channel layer 142 is exposed, where the channel layer 142 may be polysilicon or monocrystalline silicon, and the embodiment is preferably a polysilicon material. The exposed channel layer 142 is exposed to air and oxidized to silicon oxide, so that a silicon oxide layer is formed on the surface of the exposed channel layer 142.

In order to make the first conductive layer 170 formed in the fourth step have good electrical connection with the channel layer 142, referring to fig. 1b, the oxide sub-layer 147 is removed by etching in the third step.

For example, the oxide sub-layer 147 may be removed using a hydrofluoric acid (HF) wet etch process. Specifically, the silicon oxide surface is treated by hydrofluoric acid to form a silicon-hydrogen interface on the channel layer 142, thereby suppressing the oxidation process.

However, if the time interval between the third step and the fourth step is too long (the process latency, Q-time), the channel layer 142 continues to be oxidized to form the oxide layer 147, which still affects the electrical connection between the first conductive layer 170 and the channel layer 142, and the too short process latency (Q-time) increases the throughput pressure and limits the process window.

Further, referring to fig. 1b and 1c, the gate gap structure 13 includes a second insulating layer 135 and a core 134, wherein the second insulating layer 135 includes a first sub-layer 132 and a second sub-layer 133, the first sub-layer 132 is a high dielectric material with a dielectric constant higher than that of silicon dioxide, and is preferably an aluminum oxide material in the embodiment of the present disclosure. The second sub-layer 133 is an insulating material, and includes a silicon oxide material and a silicon nitride material. Silicon oxide materials are preferred in the disclosed embodiments.

In step three, in the conventional hydrofluoric acid etching process, since hydrofluoric acid etches the first sub-layer 132 (aluminum oxide layer) and the second sub-layer 133 (silicon oxide layer) in the gate gap structure 13, the second recess 150 is formed to be recessed toward the stacked structure along the first direction. After the first conductive layer 170 is formed in the fourth step, the first conductive layer 170 and the second conductive layer 111 shown in fig. 1d may be brought into contact, which may cause a defect of bottom select gate leakage. Meanwhile, the surface treated by HF is also slowly oxidized, and a silicon oxide layer is formed on the surface after a long time, so that the process waiting time with strict control on the process is required, the capacity pressure is increased, and the process window is limited.

Based on this, the embodiment of the disclosure provides a manufacturing method of a three-dimensional memory.

Fig. 2 is a schematic flow chart illustrating a method for manufacturing a three-dimensional memory according to an embodiment of the present disclosure, and fig. 3a to 3g are schematic diagrams illustrating a method for manufacturing a three-dimensional memory according to an embodiment of the present disclosure. As shown in fig. 2 and fig. 3a to 3g, the method includes the following steps:

s100: referring to fig. 3a, a channel pillar 14 extending into a substrate 100 is formed at a first surface of the substrate 100; wherein, along the radial direction of the channel column 14, the channel column 14 includes: a conductive channel layer and an insulating functional layer surrounding the channel layer;

s200: referring to fig. 3b, the substrate 100 is removed from the second surface of the substrate 100 to reveal the first end 141 of the channel pillar 14; wherein the second surface and the first surface are opposite surfaces of the substrate 100;

s300: referring to fig. 3c, the functional layer 143 exposed at the first end portion 141 is removed to expose the channel layer 142; wherein, the exposed channel layer 142 is oxidized to form an oxide layer 147;

s400: referring to fig. 3d, a first conductive layer 170 is formed overlying the oxide sublayer 147;

s500: referring to fig. 3e, after the first conductive layer 170 is formed, a first ion implantation is performed on the oxide sublayer 147 to break the continuity of the oxide sublayer 147;

s600: referring to fig. 3e, after the first ion implantation is performed, the first conductive layer 170 and the oxide sub-layer 147 are heat-treated to electrically connect the channel layer 142 with the first conductive layer 170.

Specifically, referring to fig. 3a, exemplary constituent materials of the substrate 100 may include: elemental semiconductor materials (e.g., silicon, germanium), group iii-v compound semiconductor materials, group ii-vi compound semiconductor materials, organic semiconductor materials, or other semiconductor materials known in the art. Embodiments of the present disclosure are preferably polysilicon materials.

Illustratively, the constituent material of the channel layer 142 of the channel pillar 14 may include: monocrystalline silicon material, polycrystalline silicon material. Embodiments of the present disclosure are preferably polysilicon materials.

For example, the channel Layer, the functional Layer, and the first conductive Layer may be formed by any technique known to those skilled in the art, such as a Low Temperature Chemical Vapor Deposition (LTCVD) process, a Low Pressure Chemical Vapor Deposition (LPCVD) process, a Rapid Thermal Chemical Vapor Deposition (RTCVD) process, an Atomic Layer Deposition (ALD) process, or a Plasma Enhanced Chemical Vapor Deposition (PECVD) process.

Referring to FIG. 3b, shownFor example, the removing process of the substrate 100 may include: dry etching, wet etching, chemical mechanical polishing planarization or a combination thereof. The dry etching gas may include: CF (compact flash)₄，C₂F₆，NF₃，Cl₂，O₂，NH₃Or a combination of the above gases. The wet etchant may include: HF, H₃PO₄KOH or a combination of the above solutions.

After the substrate 100 is removed, a conductive layer can be reformed at the original substrate 100 to electrically connect the plurality of channel structures, forming an Array Common Source (ACS) that supplies power to the memory cells.

In some embodiments, the conductive layer includes a metal silicide layer in contact with the semiconductor channel of the channel structure to reduce contact resistance, and also includes a metal layer in contact with the metal silicide layer to further reduce overall resistance. As a result, the thickness of the semiconductor layer (N-type doped or P-type doped) that is part of the array common source can be reduced without affecting the array common source conduction.

It is emphasized that the second surface and the first surface are two opposite surfaces with respect to the substrate 100 in a first direction perpendicular to the surface of the substrate 100.

Referring to fig. 3c, after step S200 is performed, the channel layer 142 is exposed, the channel layer 142 loses the protection of the functional layer 143 and is directly in contact with the external environment, and during the conversion of the manufacturing process and the transfer of the wafer, the polysilicon or single crystal silicon material of the channel layer 142 is in contact with oxygen in the environment and is oxidized into silicon oxide, and an oxide layer 147 is formed on the exposed surface of the channel layer 142. The oxygen element may be oxygen from the atmospheric environment, an oxidizing etchant (hydrogen peroxide, nitric acid or any combination of other oxidizing etchants) in wet etching, or an oxidizing element involved in other processes.

Illustratively, the process of etching to remove the first end portion 141 may be one of wet etching, dry etching, or any combination thereof.

Referring to fig. 3d, the first conductive layer 170 includes a single crystal silicon material, a polysilicon material, and an amorphous silicon material.

Referring to fig. 3e, the oxide layer 147 isolates the exposed channel layer 142 from the first conductive layer 170, affecting the conductive contact of the channel layer 142 with the first conductive layer 170. The first ion implantation is performed on the oxide sublayer 147, and the oxide sublayer 147 is physically bombarded with energetic particles, so that the continuous and complete oxide sublayer 147 is cracked or gapped, thereby breaking the continuity of the oxide sublayer 147 and allowing the channel layer 142 to contact the first conductive layer 170. The angle of ion implantation may be 0 to 180 degrees with respect to the first conductive layer 170. The ion implantation element includes one or any combination of arsenic, indium, neon, argon, krypton, xenon, and nitrogen.

Referring to fig. 3e, after the first ion implantation is performed, the first conductive layer 170 and the oxide layer are subjected to a heat treatment to repair damage to silicon lattices of the first conductive layer 170 and the channel layer 142, so that the first conductive layer 170 and the channel layer 142 are in better contact, and conductive connection is optimized.

According to the embodiment of the disclosure, an ion implantation process is adopted to replace a wet etching process for removing the oxide sub-layer. The method comprises the steps of firstly forming a first conducting layer covering an oxide sublayer, then carrying out first ion implantation on the oxide sublayer to destroy the continuity of the oxide sublayer, and finally carrying out heat treatment on the first conducting layer and the oxide sublayer to enable a channel layer to be electrically connected with the first conducting layer.

According to the embodiment of the disclosure, the channel layer is removed, the gate gap structure is not damaged, the probability of electric leakage caused by electric connection of the first conducting layer and the conducting layer of the stacked structure is reduced, and the yield of devices is improved. Furthermore, the first ion implantation process is performed after the first conductive layer is formed, the channel layer after the oxide layer is removed cannot contact with the external environment, and the probability of further oxidation of the channel layer is reduced.

In some embodiments, as shown with reference to fig. 3c and 3f, the method further comprises:

after step S300 is performed and before step S400 is performed, performing a second ion implantation on the first end portion 141 on which the oxide sub-layer 147 is formed to form a conductive first protection layer 148 covering the first end portion 141; the first protection layer 148 is used to reduce oxygen particles from reacting with the remaining channel layer 142.

It is emphasized that the oxygen particles may include oxygen particles from the oxide sublayer or from the external environment.

In some embodiments, the second ion implantation may be ion implantation on the oxide sublayer, and the first protection layer with ion doping is formed on the surface of the oxide sublayer. The first protective layer may reduce a reaction of oxygen particles in the oxide layer with the remaining channel layer, and the first protective layer has conductivity and may achieve electrical connection with the first conductive layer and the channel layer so as not to affect electrical performance of the memory device.

In some embodiments, the second ion implantation may be ion implantation into the channel layer, and after the high-energy ions bombard the oxide layer to break the oxide layer, the high-energy ions penetrate through the oxide layer to reach the channel layer, so as to form the first protection layer with ion doping on the surface of the channel layer. The first protective layer may be formed to protect the remaining channel layer from reaction with oxygen particles in the oxide layer and the external environment, and has conductivity to enable electrical connection with the first conductive layer and the channel layer, thereby not affecting electrical performance of the memory device.

In some embodiments, the second ion implantation may be ion implantation of the channel layer and the oxide sublayer, ion doping the channel layer and the oxide sublayer, and forming the doped first protection layer on the surface of the oxide sublayer and the surface of the channel layer, respectively. The first protective layer may reduce a reaction of the remaining channel layer with the oxide layer and oxygen particles in an external environment, and the first protective layer has conductivity and may be electrically connected with the first conductive layer and the channel layer so as not to affect an electrical performance of the memory device.

The implantation element of the second ion implantation may include one or any combination of arsenic, indium, neon, argon, krypton, xenon, and nitrogen.

According to the assumption proposed by diels-glovef, the charge on the wafer or polysilicon surface affects the rate at which the oxidizing agent reaches the oxidation interface during subsequent oxidation, and thus affects the growth rate of the silicon oxide layer. The negative charges on the surface of the polysilicon in the subsequent oxidation reaction can accelerate the speed of the oxidizing agent reaching the oxidation interface in the oxidation process, so that the oxidation speed is accelerated, namely, the more negative charges on the surface of the wafer or the polysilicon layer are, the easier the oxidation is to generate a silicon oxide layer. Based on this, the amount of negative charges on the surface of the polysilicon can be controlled by ion implantation to suppress the generation of the silicon oxide film.

In the embodiment of the present disclosure, the conductive first protection layer 148 with ion doping is formed on the surface of the channel layer 142 and/or on the surface of the oxidized sub-layer 147 by performing the second ion implantation on the exposed channel layer 142 and/or the exposed oxide sub-layer 147. The protective layer may control the accumulation of negative charges, thereby inhibiting the growth of surface oxide films, reducing the oxidation degree of the remaining channel layer 142, maintaining the thickness of the channel layer, and reducing the probability of memory device failure. Further, the first protective layer has conductivity, and can be electrically connected with the first conductive layer and the channel layer without affecting the electrical performance of the memory device.

In some embodiments, the method further comprises:

referring to fig. 3g, forming a channel pillar 14 extending into the substrate 100 at a first surface of the substrate 100 includes:

forming a channel hole penetrating through the stacked structure 110 located at the first surface of the substrate 100 and extending into the substrate 100;

forming a functional layer 143 covering sidewalls and a bottom of the channel hole;

forming a channel layer 142 covering the functional layer 143;

before removing the substrate 100, the method further comprises:

performing a third ion implantation into the bottom of the channel layer 142 from the first surface of the substrate 100 to form a conductive second protective layer 149 between the bottom of the channel layer 142 and the functional layer 143; wherein the second protective layer 149 serves to reduce oxygen particles from reacting with the channel layer 142.

Along the radial direction of the channel pillar 14, the functional layer 143 includes a barrier sublayer 144, a storage sublayer 145, and a tunneling sublayer 146. Wherein barrier sublayer 144 may comprise silicon oxide, silicon oxynitride, high dielectric, or any combination thereof. The storage sublayer 145 may comprise silicon nitride, silicon oxynitride, silicon, or any combination thereof. The tunneling sublayer 146 may include silicon oxide, silicon oxynitride, or any combination thereof. In the embodiment of the present disclosure, the combination of the functional layer 143 is preferably a composite layer of silicon oxide/silicon nitride/silicon oxide (ONO).

In some embodiments, a tunneling sublayer is located between the channel layer and the storage sublayer. The storage sublayer, also known as the charge-trapping sublayer, determines the switching state of the semiconductor channel by the storage or removal of charge in the charge-trapping sublayer. The charges move between the storage sublayer and the channel layer through the tunneling effect of the tunneling sublayer to realize the conduction of the channel layer or not, and then the storage and the erasure are realized through programming. Furthermore, the storage sublayer can store charge, and when the memory is powered down, electrons are stored in the storage sublayer without being lost.

Furthermore, the blocking sublayer is located between the storage sublayer and the second conductive layer, plays an insulating and isolating role, and is used for blocking charges in the storage sublayer from moving to the second conductive layer, and ensuring that the performance of the memory is good.

In some embodiments, the stack structure 110 includes: a plurality of second conductive layers 111 and a plurality of first insulating layers 112 are alternately stacked in this order.

For example, the composition materials of the plurality of second conductive layers 111 may include: a single crystal silicon material, a polysilicon material, a metallic tungsten material, or other conductive materials known in the art. The disclosed embodiments are preferably metallic tungsten materials.

For example, the composition materials of the plurality of first insulating layers 112 may include: a silicon oxide material, a silicon nitride material, a silicon oxynitride material, or other insulating materials known in the art. Embodiments of the present disclosure are preferably silicon oxide materials.

It is emphasized that the composition materials of the different first conductive layers 170 may be different, and the composition materials of the different first insulating layers 112 may also be different.

After the channel layer 142 is formed, the third ion implantation is performed on the channel layer 142 from the top of the channel pillar 14 to reduce the amount of negative charges of the channel layer 142, and a second protective layer 149 having ion doping is formed between the bottom of the channel layer 142 and the functional layer 143. After performing the step S200, the second protective layer 149 may control the accumulation of negative charges on the surface of the channel layer 142, reducing the generation of an oxide film. The third ion implantation element includes one or any combination of arsenic, indium, neon, argon, krypton, xenon, and nitrogen.

In some embodiments, the method further comprises:

as described with reference to fig. 3e, the constituent particles of the oxide sublayer 147 include oxygen particles and first particles;

after the first conductive layer 170 is formed, the first ion implantation is performed on the oxide sublayer 147 to break the continuity of the oxide sublayer 147, including:

second particles are implanted into the oxide sublayer 147 and bombard the oxide sublayer 147 to break the chemical bonds between the oxygen particles and the first particles and form gaps in the oxide sublayer 147.

Illustratively, the oxide sublayer 147 constitutes a first particle of the particles, which may be a silicon particle of the channel layer 142, or other particles. The polysilicon layer in the channel layer 142 may be doped to optimize the conductivity of the channel layer 142, wherein the doping element may include one or any combination of boron, arsenic, phosphorus, germanium, gallium and antimony. Thus, the first particles of the oxide sublayer 147 are not only silicon particles, but the oxide sublayer 147 composition can also include other elemental particles that are susceptible to oxidation.

The first ion implanted energetic particles bombard the oxide layer 147, breaking the silicon-oxygen bonds of the silicon oxide, forming a gap in the oxide layer 147, such that the first conductive layer 170 forms an electrical connection with the channel layer 142.

In some embodiments, the implant elements of the first ion implantation comprise at least one of:

arsenic element; indium element; neon element; argon element; krypton element; a xenon element; and (4) nitrogen element.

The electrical connection between the first conductive layer 170 and the channel layer 142 is achieved by destroying the continuity of the oxide layer 147 through physical bombardment, the generation of an oxide layer can also be inhibited by reducing the accumulation of negative charges on the surface of the channel layer 142, and the channel layer 142 can also be protected from being oxidized or the partially oxidized channel layer 142 can be further oxidized by forming an ion-doped protective layer.

In some embodiments, the first ion implant has an implant element energy range of: 100 kilo-electron volts to 3 mega-electron volts.

In the embodiment of the disclosure, the ions that need to be implanted by the first ions reach the surface of the oxide sublayer, and a certain energy is needed to bombard the ions and break the continuity of the oxide sublayer, so that the first conductive layer and the channel layer form an electrical connection. Based on the requirements, the energy and the depth of the first ion implantation are required, and the depth of the ion implantation is controlled by controlling the energy of the first ion implantation, so that ions can contact the oxide sublayer to destroy the continuity of the oxide sublayer, and the ions implanted into the channel layer are not destroyed.

In some embodiments, the method further comprises:

the heat treatment of the first conductive layer 170 and the oxide sub-layer 147 includes:

the first conductive layer 170 and the oxide sublayer 147 are annealed to form the first ion-implanted oxide sublayer 147 and the first conductive layer 170 into an integral structure, and at least a portion of implanted elements of the ion implantation process are allowed to escape from the oxide sublayer 147 and form gaseous products.

The annealing process may repair damage to the silicon lattice of the first conductive layer 170 and the channel layer 142, so that the first conductive layer 170 and the channel layer 142 may be better contacted, and conductive connection may be optimized.

Further, the first ion implantation element includes krypton, xenon, nitrogen, or a combination thereof, and after the first conductive layer 170 is formed, through the annealing heat treatment process, a gas element may escape from the oxide sublayer 147 without affecting lattices of the first conductive layer 170 and the channel layer 142, so that the resistance of the first conductive layer is not changed, which is beneficial to ensuring the conductivity of the first conductive layer.

In some embodiments, the annealing process comprises furnace tube annealing, laser annealing, or any combination.

Illustratively, the furnace tube annealing process is performed in a furnace tube apparatus, the general process temperature is 700 ℃ to 1100 ℃, and pure nitrogen is used as the process gas for high-temperature annealing, so as to repair lattice damage, reduce resistance and improve conductivity.

For example, the laser annealing process may include: the surface of the first conductive layer 170 is irradiated with a laser beam to melt the amorphous silicon or polysilicon of the first conductive layer 170 and recrystallize the amorphous silicon or polysilicon into polysilicon, so that the damage of crystal lattices is repaired, the resistance is reduced, and the conductivity is improved.

In some embodiments, the method further comprises:

referring to fig. 4a, an insulating isolation layer 120 is formed covering the first surface of the substrate 100; forming a stacked structure 110 covering the isolation layer 120;

step S300 further includes: removing the exposed functional layer 143 of the first end portion 141 to expose the channel layer 142, including: removing the functional layer 143 exposed by the first end portion 141 to form a first recess 160 recessed toward the stacked structure 110 along a first direction perpendicular to the substrate 100; wherein the end of the remaining functional layer 143 is in contact with the spacer layer 120.

The isolation layer 120 is disposed between the substrate 100 and the stacked structure 110, and may include an insulating material layer, and may also include multiple material layers of an insulating material and a conductive material.

In some embodiments, as shown in fig. 4a, the isolation layer 120 may include: the first insulating sublayer 121, the first conductive sublayer 122 and the second insulating sublayer 123 are sequentially arranged along the first direction, the first insulating sublayer 121 is located between the first conductive sublayer 122 and the substrate 100, and the second insulating sublayer 123 is located between the first conductive sublayer 122 and the stacked structure 110.

The material of the first insulating sublayer 121 and the second insulating sublayer 123 may be one of silicon oxide, silicon nitride, and silicon oxynitride, and silicon oxide is preferred in this embodiment; the material of the first conductive sublayer 122 may be one of monocrystalline silicon and polycrystalline silicon, and polycrystalline silicon is preferred in this embodiment.

Illustratively, the removal process may include: dry etching, wet etching or any combination of the above processes.

In some embodiments, the method further comprises:

referring to fig. 4b, after forming the channel pillar 14, in the stacked structure of the first surface of the substrate 100, a trench 130 penetrating the stacked structure in a direction perpendicular to the substrate 100 and exposing the substrate 100 is formed; the stacked structure includes a plurality of first insulating layers 112 and a plurality of sacrificial layers 113 alternately stacked in sequence.

The first insulating layer 112 may be made of one of silicon oxide, silicon nitride, and silicon oxynitride, and the embodiment of the disclosure is preferably made of silicon oxide.

The sacrificial layer material may include one of silicon nitride, silicon oxynitride, single crystal silicon, and polysilicon materials, with silicon nitride materials being preferred in embodiments of the present disclosure.

Referring to fig. 4c, the plurality of sacrificial layers in the stacked structure 110 are removed based on the trench 130, forming a gap between the adjacent first insulating layers 112;

referring to fig. 4d, the gaps are filled to form a plurality of second conductive layers 111;

forming a second insulating layer 135 covering sidewalls of the trench 130;

the trench 130 including the second insulating layer 135 is filled with a conductive material.

The material of the second conductive layer 111 may be one of metal tungsten, monocrystalline silicon, and polycrystalline silicon, and in this embodiment, metal tungsten is preferred. The trench 130 is filled with a second insulating layer 135 and a core 134 to form the gate gap structure 13, wherein the second insulating layer 135 includes a first sub-layer 132 and a second sub-layer 133, and the first sub-layer 132 is a high dielectric material with a dielectric constant higher than that of silicon dioxide, and is preferably an aluminum oxide material in the embodiment of the present disclosure. The second sub-layer 133 is an insulating material, and includes a silicon oxide material and a silicon nitride material, and is preferably a silicon oxide material in the embodiment of the present disclosure. The core 134 material includes silicon oxide material, silicon nitride material, single crystal silicon material, polysilicon material, and metal tungsten material, and the insulating material and the conductive material are selected according to whether the gate-line-gap structure 13 is a common-source lead structure.

The specific application of the method for manufacturing a three-dimensional memory provided by the embodiment of the present disclosure in a wafer bonding process is described in detail below with reference to fig. 5a to 5 b.

In the manufacturing process of the three-dimensional memory, in order to stack more memory units on one wafer, a solution is adopted in which the memory units are manufactured on one wafer, the control circuit is manufactured on the other wafer, and finally the two wafers are bonded.

The method for manufacturing the three-dimensional memory provided by the embodiment of the disclosure can be applied to a wafer bonding process besides manufacturing the memory on a single wafer.

Referring to fig. 5a, steps S100, S200, S300, and S400 shown in fig. 2 are performed on the first wafer 10 to form a memory cell structure having the channel pillar 14 and the first conductive layer 170, and the channel layer 142 at the first end portion 141 of the channel pillar 14 forms an oxide layer 147; the first wafer 10 and the second wafer 20 are bonded through the first bonding surface 180 and the second bonding surface 190, and a control circuit structure may be formed on the second wafer 20.

Referring to fig. 5b, step S500 shown in fig. 2 is performed on the first wafer 10, and a first ion implantation is performed on the oxide sublayer 147 to break the continuity of the oxide sublayer 147;

s600: referring to fig. 3e, after the first ion implantation is performed, the first conductive layer 170 and the oxide sub-layer 147 are heat-treated, and then step S600 is performed to electrically connect the channel layer 142 with the first conductive layer 170.

It is to be understood that the application of the method for three-dimensional memory in wafer bonding according to the embodiments of the present disclosure is not limited to the embodiments shown in fig. 5a and 5b, and other embodiments of the method of the present disclosure can be used on the first wafer 10 because the bonding is between independent wafers.

The following describes a specific structure of a three-dimensional memory according to an embodiment of the present disclosure in detail with reference to fig. 6a to 6 c. Referring to fig. 6a, the three-dimensional memory 1000 includes:

a first conductive layer 170;

a stacked structure 110 stacked on the first conductive layer 170, wherein the stacked structure 110 includes a plurality of second conductive layers 111 and a plurality of first insulating layers 112 stacked alternately; wherein a first insulating layer is in contact with the first conductive layer;

a trench pillar 14 penetrating the stacked structure and extending into the first conductive layer 170; in the radial direction of the channel pillar, the channel pillar 14 includes: a conductive channel layer 142 and an insulating functional layer 143 surrounding the channel layer;

the channel pillar 14 further includes: a second end 140 within the first conductive layer 170, the second end comprising: a channel layer 142 and a seed layer of oxide 147 between the channel layer 142 and the first conductive layer 170; wherein the oxide layer has a slit, and the first conductive layer 170 is electrically connected to the channel layer 142 through the slit.

The constituent materials of the channel layer 142 and the first conductive layer 170 may include: monocrystalline silicon material, polycrystalline silicon material.

It is emphasized that, referring to fig. 1b and 3c, in the process of removing the functional layer at the second end portion to expose the channel layer, the polysilicon or single crystal silicon of the channel layer may be directly contacted with oxygen element in the external environment, oxidized into silicon oxide, and form a continuous oxide layer on the surface of the channel layer, which affects the electrical connection between the first conductive layer and the channel layer. The oxygen element may be oxygen from the atmospheric environment, an oxidizing etchant (hydrogen peroxide, nitric acid or any combination of other oxidizing etchants) in wet etching, or an oxidizing element involved in other processes.

In the embodiment of the disclosure, the oxide sublayer is a film layer with an intermittent gap and does not continuously cover the surface of the channel layer. A portion of the first conductive layer or a portion of the channel layer may extend into the slot where they contact each other to form an electrical connection.

In some embodiments, the first ion implantation process may be used to physically bombard the oxide sublayer with high energy particles, so that the oxide sublayer forms a gap. And performing heat treatment annealing on the silicon of the first conducting layer and the channel layer, and enabling the first conducting layer and the channel layer to extend to the gap to be electrically connected while repairing the lattice defects.

In some embodiments, as shown with reference to fig. 6b, the three-dimensional memory 1000 further comprises:

a conductive first protection layer 148 between the oxide layer 147 and the first conductive layer 170 and covering the second end 140 of the channel pillar for reducing oxygen particle reaction with the channel layer of the second end.

The first protection layer has ion doping, can be arranged on the surface of the oxide sublayer, reduces the reaction of the residual channel layer with the oxide sublayer and oxygen particles in the external environment by isolating the contact of the channel layer with the oxygen particles, and has conductivity, and can be electrically connected with the first conductive layer and the channel layer, so that the electrical performance of the memory device is not influenced.

In some embodiments, the first protection layer may be formed by performing a second ion implantation on the second end portion.

It is emphasized that the second end portion and the first end portion are both end portions of the channel pillar extending to the first conductive layer, and the second end portion is formed by performing steps S300, S400, S500, and S600 on the first end portion. Therefore, the two end structures are different structures formed by subjecting the same end of the channel pillar to different manufacturing steps, the first end including the conductive channel layer and the insulating functional layer surrounding the channel layer, and the second end including the conductive channel layer and the oxide layer having the gap.

In some embodiments, as shown with reference to fig. 6c, the three-dimensional memory 1000 further comprises:

and a conductive second protective layer 149 between the channel layer 142 and the functional layer 143 of the second end portion 140 for reducing oxygen particle reaction with the channel layer.

Illustratively, functional layer 143 includes a barrier sublayer 144, a storage sublayer 145, and a tunneling sublayer 146. Wherein barrier sublayer 144 may comprise silicon oxide, silicon oxynitride, high dielectric, or any combination thereof. The storage sublayer 145 may comprise silicon nitride, silicon oxynitride, silicon, or any combination thereof. The tunneling sublayer 146 may include silicon oxide, silicon oxynitride, or any combination thereof. In the embodiment of the present disclosure, the combination of the functional layer 143 is preferably a composite layer of silicon oxide/silicon nitride/silicon oxide (ONO).

In the embodiment of the present disclosure, the second protective layer 149 may be disposed between the tunneling sublayer 146 and the channel layer 142, and after the functional layer 143 is removed to expose the channel layer, the second protective layer may reduce negative charge accumulation on the surface of the channel layer, thereby reducing the generation of an oxide film, and reducing the probability of device failure caused by insufficient electrical connection between the first conductive layer and the channel layer.

In some embodiments, a third ion implantation may be performed on the channel layer at the second end portion along the top of the channel pillar, forming a second protective layer between the tunneling sublayer and the channel layer.

In the embodiments provided in the present disclosure, it should be understood that the disclosed apparatus and method may be implemented in other manners. The above description is only for the specific embodiments of the present disclosure, but the scope of the present disclosure is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present disclosure, and all the changes or substitutions should be covered within the scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.