阅读说明：本技术 半导体图像传感器 (Semiconductor image sensor having a plurality of pixels ) 是由 仓知郁生 高野纮 鹿岛保昌 于 2020-04-10 设计创作，主要内容包括：本发明提供一种对近红外光高灵敏度且实现小面积下的集成化的半导体图像传感器。本发明的半导体图像传感器包括：光接收元件,形成于SOI基板的所述绝缘膜下的硅基板,并且沿着与硅基板的主面垂直的方向形成,且包括对近红外光具有灵敏度的pn接合二极管,所述SOI基板包括硅基板、形成于所述硅基板上的绝缘膜及形成于绝缘膜上的半导体层；以及高电压产生电路,产生用来对pn接合二极管施加反向偏压的施加电压,硅基板的杂质浓度处于1×10～(12)/cm～(3)至1×10～(14)/cm～(3)的范围内,膜厚处于300μm至700μm的范围内,施加电压处于10V至60V的范围内。(The invention provides a semiconductor image sensor which has high sensitivity to near infrared light and realizes integration in a small area. The semiconductor image sensor of the present invention includes: a light-receiving element formed on a silicon substrate under the insulating film of an SOI substrate, the SOI substrate including a silicon substrate, an insulating film formed on the silicon substrate, and a semiconductor layer formed on the insulating film, and formed along a direction perpendicular to a main surface of the silicon substrate, and including a pn junction diode having sensitivity to near-infrared light; and a high voltage generating circuit for generating an applied voltage for applying a reverse bias to the pn junction diode, wherein the impurity concentration of the silicon substrate is 1 × 10 12 /cm 3 To 1X 10 14 /cm 3 In the range of 300 μm to 700 μm, and the applied voltage is in the range of 10V to 60V.)

1. A semiconductor image sensor, characterized in that: comprises that

A light-receiving element formed on a silicon substrate under an insulating film of a silicon-on-insulator substrate, the silicon-on-insulator substrate including the silicon substrate, the insulating film formed on the silicon substrate, and a semiconductor layer formed on the insulating film, the light-receiving element being formed along a direction perpendicular to a main surface of the silicon substrate and including a pn junction diode having sensitivity to near-infrared light; and

a high voltage generation circuit that generates an application voltage for applying a reverse bias voltage to the pn junction diode,

the impurity concentration of the silicon substrate is 1 × 10¹²/cm³To 1X 10¹⁴/cm³In the range of 300 μm to 700 μm, and the applied voltage is in the range of 10V to 60V.

2. The semiconductor image sensor according to claim 1, characterized by comprising: a buried oxide capacitor having the semiconductor layer as a first electrode and a diffusion layer formed on the silicon substrate as a second electrode with the insulating film interposed therebetween,

the first electrode is connected to an output end of the high voltage generation circuit.

3. The semiconductor image sensor according to claim 2, wherein a film thickness of the insulating film of the buried oxide capacitor is in a range of 100nm to 300 nm.

4. The semiconductor image sensor according to any one of claims 1 to 3, comprising a first region, a second region and a gate electrode, wherein the first region and the second region are formed in the semiconductor layer on the insulating film, are in contact with each other with a channel region therebetween, the gate electrode is formed on the channel region, and the first region and the channel region have the same conductivity type as each other,

the second region and the channel region have different conductivity types from each other,

the gate electrode is connected to the second region, the first region and the second region with the channel region therebetween are used as diodes, and a charge pump circuit is used as the high voltage generation circuit, the charge pump circuit connecting a plurality of the diodes in series and supplying a signal to each diode to output a high voltage.

5. The semiconductor image sensor according to any one of claims 1 to 4, wherein an impurity concentration of the semiconductor layer is at 1 x 10¹⁵/cm³To 3X 10¹⁸/cm³In the range of (1), the film thickness of the semiconductor layer is in the range of 10nm to 100 nm.

Technical Field

The present invention relates to a semiconductor image sensor, and more particularly, to a semiconductor image sensor having high sensitivity to near-infrared light and realizing integration in a small area.

Background

As a well-known semiconductor image sensor (hereinafter referred to as a photosensor), a semiconductor image sensor is known in which a pn junction diode formed on a silicon substrate is used as a light receiving element. In order to operate the photosensor, it is necessary to apply a reverse bias to the pn junction diode, that is, a negative bias to the p-type semiconductor layer and a positive bias to the n-type semiconductor layer. Thus, a carrier-free depletion layer is formed at the pn junction. When light is applied to the depletion layer, electron-hole pairs (carriers) are generated by the light energy (referred to as a photoelectric effect), electrons are pulled toward the n-type semiconductor layer to which a positive voltage is applied by an electric field in the depletion layer, and holes are pulled toward the p-type semiconductor layer to which a negative voltage is applied. Accordingly, the amount of charge between the terminals of the pn junction diode changes in accordance with the optical signal, and thus the optical signal can be converted into an electrical signal (referred to as photoelectric conversion).

In photoelectric conversion using a pn junction diode using a silicon substrate, the limit on the long wavelength side (the side where light energy is low) of detectable light is determined by the band gap width in silicon.

Since the band gap width of silicon is about 1.1eV, a photosensor using a pn junction diode of silicon can detect only light having a wavelength of about 1,100nm or less.

The wavelength (about 1,100nm) is in the near infrared region.

Fig. 1 shows the absorption coefficient of light using silicon as a medium, and the light absorption coefficient of near-infrared light having a wavelength of about 1,100nm is small, and the detection sensitivity is low. Therefore, the sensitivity to near-infrared light has been previously improved by taking some measure for silicon photosensors.

As one of the measures, patent document 1 or non-patent document 1 describes that the near-infrared light incident on the optical sensor is dispersed in the optical sensor, thereby extending the optical path of the near-infrared light passing through the optical sensor and improving the sensitivity. Specifically, this is achieved by forming pyramid-shaped irregularities on the surface of the silicon forming the light receiving element.

Further, by forming a special layer called a diffusion plate on the surface of the light receiving element, near infrared light is dispersed, and sensitivity is improved. However, these conventional methods result in an increase in manufacturing processes, with a concomitant increase in cost. Further, the sensitivity cannot be sufficiently improved by dispersing only near infrared light, and the effect is limited.

On the other hand, the method of thickening the depletion layer to be the photoelectric conversion region is effective for improving the sensitivity.

Fig. 2 shows the relationship between the depletion layer width and the light absorption rate for each light wavelength. As is clear from the above graph, if the depletion layer width can be controlled to 300 μm or more, sufficient light absorption can be obtained for light in the near infrared region.

Fig. 3 shows a relationship between a reverse bias voltage with respect to an impurity concentration of a silicon substrate forming a pn junction and a depletion layer width.

It can be seen that the concentration of the silicon substrate used in general is 1X 10¹⁵/cm³On the other hand, if a low-density substrate (about 1X 10) is used¹²/cm³) The depletion layer width is about an order of magnitude thicker at the same bias voltage.

Fig. 4 shows the relationship between the reverse bias voltage and the impurity concentration of the substrate for maintaining the sensitivity of the visible light to the same degree, using the wavelength of the light as a parameter.

It is known that the concentration of the substrate used is 2X 10¹²/cm³The left and right Float Zone (FZ) substrates are required to apply a bias voltage of about 50V to realize an optical sensor that maintains sensitivity of the visible light to near-infrared light having a wavelength of 940 nm.

Accordingly, the photosensor includes a high voltage generation circuit that generates a high voltage to apply a reverse bias to the pn junction diode. The high voltage generation circuit is generally a circuit for boosting a power supply Voltage (VCC) to obtain a specific high voltage, and a charge pump circuit is known.

The charge pump circuit is a circuit that is realized by switching an input signal (power supply voltage: VCC) on/off using a capacitor (capacitor) (C1 to C9) and diodes (D1 to D9), and various circuit configurations are known, and an example thereof is shown in fig. 5.

When the charge pump circuit is formed on a silicon substrate, the occupied area increases, and the size of the photosensor increases.

Therefore, as shown in patent document 2, it is also known to form a charge pump circuit in a semiconductor layer of a Silicon On Insulator (SOI) substrate including a Silicon substrate, an insulating film formed on the Silicon substrate, and the semiconductor layer formed on the insulating film. In the charge pump circuit disclosed in the document, a plurality of diodes independent of each other are formed by bonding a p-type region and an n-type region formed in the semiconductor layer, and the diodes are connected in series.

[ Prior art documents ]

[ patent document ]

Patent document 1: japanese patent laid-open No. 2017-108062

Patent document 2: japanese patent laid-open No. Hei 7-177729

[ non-patent document ]

Non-patent document 1: oshiyama et al (Oshiyama et al), Near-infrared sensitivity enhancement of a back-illuminated complementary metal oxide semiconductor image sensor with pyramid surfaces for diffractive structures (Near-infrared sensitivity enhancement with a back-illuminated complementary metal oxide semiconductor image sensor for a diffraction structure), IEEE tech. Digst.of IEDM 2017, page 397-.

Disclosure of Invention

[ problems to be solved by the invention ]

The present invention is intended to realize a semiconductor image sensor that can obtain a sufficiently thick (wide) depletion layer without increasing the area occupied by a high-voltage generation circuit when a high-voltage reverse bias is applied to a pn junction diode serving as a light-receiving element formed on a silicon substrate.

[ means for solving problems ]

The semiconductor image sensor of the present invention is characterized by comprising: a light-receiving element formed on a silicon substrate under an insulating film of an SOI substrate, the SOI substrate including the silicon substrate, the insulating film formed on the silicon substrate, and a semiconductor layer formed on the insulating film, the light-receiving element being formed along a direction perpendicular to a main surface of the silicon substrate and including a pn junction diode having sensitivity to near-infrared light; a high voltage generation circuit for generating an application voltage for applying a reverse bias to the pn junction diode, wherein the impurity concentration of the silicon substrate is 1 × 10¹²/cm³To 1X 10¹⁴/cm³In the range of 300 μm to 700 μm, and the applied voltage is in the range of 10V to 60V.

Further, a semiconductor image sensor according to the present invention is characterized in that: the high-voltage generating circuit includes a Buried Oxide (BOX) capacitor (capacitor) having the semiconductor layer as a first electrode and a diffusion layer formed on the silicon substrate as a second electrode with the insulating film interposed therebetween, the first electrode being connected to an output terminal of the high-voltage generating circuit.

Further, a semiconductor image sensor according to the present invention is characterized in that: the film thickness of the insulating film of the BOX capacitor (capacitor) is in the range of 100nm to 300 nm.

The semiconductor image sensor of the present invention is characterized in that: the semiconductor device includes a first region, a second region, and a gate electrode, wherein the first region and the second region are formed in the semiconductor layer on the insulating film, and are in contact with each other with a channel region interposed therebetween, the gate electrode is formed in the channel region, the first region and the channel region have the same conductivity type, the second region and the channel region have different conductivity types, the gate electrode and the second region are connected, the first region and the second region with the channel region interposed therebetween are used as diodes, a charge pump circuit is used as the high voltage generation circuit, the charge pump circuit connects a plurality of the diodes in series, supplies a signal to each diode, and outputs a high voltage.

Further, a semiconductor image sensor according to the present invention is characterized in that: the impurity concentration of the semiconductor layer is 1 × 10¹⁵/cm³To 3X 10¹⁸/cm³In the range of (1), the film thickness of the semiconductor layer is in the range of 10nm to 100 nm.

[ Effect of the invention ]

A high-sensitivity near-infrared sensor in which an increase in the process or area is suppressed even with a single power supply can be realized by using an SOI substrate having a low impurity concentration, forming a high-voltage generation circuit including a charge pump circuit in a semiconductor layer of the SOI substrate, and forming a light-receiving element including a pn junction diode having sensitivity to near-infrared light in the substrate.

Drawings

Fig. 1 is a graph showing a relationship between a wavelength of light using silicon as a medium and a light absorption coefficient.

Fig. 2 is a graph showing a relationship between a depletion layer width and a light absorption rate for each light wavelength.

Fig. 3 is a graph showing the relationship between the reverse bias and the depletion layer width, with the impurity concentration of the silicon substrate forming the pn junction as a parameter.

Fig. 4 is a graph showing a relationship between a reverse bias voltage for maintaining sensitivity of the same level as that of visible light and an impurity concentration of a substrate, with a wavelength of light as a parameter.

Fig. 5 is a diagram showing an example of a charge pump circuit implemented by switching an input signal on/off using a capacitor (capacitor) and a diode.

Fig. 6 is a schematic plan view showing the structure of an optical sensor according to a first embodiment of the present invention.

Fig. 7 is a schematic view of a cross section a-a 'schematically showing the cross section a-a' of fig. 6.

Fig. 8 is a cross-sectional structural view of a well-known metal-oxide-semiconductor field effect transistor (MOSFET) having a Lightly Doped Drain (LDD) structure.

Fig. 9 is a cross-sectional configuration diagram in the case where a MOSFET is formed in a bulk (silicon substrate).

Fig. 10 is a cross-sectional configuration diagram in the case where a MOSFET is formed by separating semiconductor layers on a buried oxide film (BOX) from each other.

Fig. 11 is (a) a manufacturing process diagram of a high-voltage generating circuit part according to a first embodiment of the present invention.

Fig. 12 is a manufacturing process diagram (second) of the high voltage generation circuit unit according to the first embodiment of the present invention.

Fig. 13 is a diagram (third) showing a manufacturing process of the high-voltage generating circuit unit according to the first embodiment of the present invention.

Fig. 14 is a manufacturing process diagram (fourth) of the high-voltage generation circuit unit according to the first embodiment of the present invention.

Fig. 15 is a manufacturing process diagram of the high voltage generation circuit unit according to the first embodiment of the present invention (the fifth step).

Fig. 16 is a manufacturing process diagram (sixth) of the high voltage generation circuit unit according to the first embodiment of the present invention.

Fig. 17 is a manufacturing process diagram (seventh) of the high voltage generation circuit unit according to the first embodiment of the present invention.

Fig. 18 is a cross-sectional configuration diagram of a diode used in the high-voltage generation circuit unit according to the second embodiment of the present invention.

Fig. 19 is a view showing a manufacturing step of the diode shown in fig. 18.

Fig. 20 is a graph showing the results obtained by measuring the quantum efficiency with respect to the wavelength of light when light is irradiated from the back surface to the light receiving element.

Fig. 21 is a diagram showing the structure of three types of diodes in comparison.

Fig. 22 is a diagram showing a relationship between a reverse bias voltage and a leakage current in the three diode structure shown in fig. 21.

Detailed Description

Hereinafter, an example of an embodiment of the present invention will be described in detail with reference to the drawings.

(first embodiment)

Fig. 6 is a schematic plan view showing the structure of an optical sensor according to a first embodiment of the present invention, and fig. 7 is a schematic sectional view of a-a 'schematically showing the section a-a' of fig. 6.

The optical sensor 1000 of the present invention includes a sensor circuit portion 100, a high voltage generation circuit portion 200, and a control circuit portion 300.

The sensor circuit portion 100 includes a light receiving element 100a and a metal-oxide-semiconductor (MOS) transistor 110a that detects a photocurrent flowing into the light receiving element 100 a. The light receiving element 100a is configured by arranging a plurality of single sensor pixels P including pn junction diodes in an array to form a sensor circuit section 100. As shown in fig. 7, the light receiving element 100a is formed as an N-type on the back surface of a low-concentration N-type silicon substrate 101⁺Diffusion layer 103[104 ]]A cathode electrode formed on the P-type silicon substrate 101 near the main surface⁺The diffusion layer 105 serves as an anode electrode.

As described above, the light receiving element 100a is formed along the direction perpendicular to the main surface of the silicon substrate 101 under the BOX 102 of the SOI substrate including the silicon substrate 101, the BOX 102 formed on the silicon substrate, and the semiconductor layer (SOI layer) 107 formed on the buried oxide film (BOX)102, and the impurity concentration of the silicon substrate 101 and the film thickness thereof are selected so as to have sufficient sensitivity to near-infrared light having a wavelength of about 800nm to 1000 nm. The MOS transistor 110a for detecting a photocurrent is formed in the SOI layer 107, and is a well-known MOSFET having an LDD structure as shown in fig. 8.

The impurity concentration of the silicon substrate 101 was 1 × 10¹²/cm³To 1X 10¹⁴/cm³Preferably 2X 10, in the above range¹²/cm³. The thickness of the silicon substrate 101 is selected so that the light receiving element 100a can be completely depleted in silicon, for example, the final wafer thickness is 300 μm to 700 μm, preferably 500 μm. Etching and removing silicon on the back surface, ion-implanting phosphorus (P) into the back surface, and irradiating the back surface with laser for activation (laser annealing) to form N on the back surface⁺Layer 103.

Forming the N⁺The layer 103 is provided to prevent the depletion layer from extending from the main surface to the lowermost portion of the back surface and to sufficiently reduce the back surface resistance of the entire pixel array。

The control circuit unit 300 controls the sensor circuit unit 100, and includes a vertical shift register 310, a noise canceller 320, a column analog-to-digital converter (column ADC)330, and a horizontal shift register 340, and is disposed around the sensor circuit unit.

Since the control circuit unit 300 is not directly related to the present invention, the structure and structure thereof will not be described.

As an example of the high voltage generation circuit section 200, a charge pump circuit using capacitors (capacitors) (C1 to C9) and diodes (D1 to D9) is configured as shown in fig. 5. Fig. 7 shows a part of the charge pump circuit shown in fig. 5, and two MOS transistors 110b and 110c formed in the SOI layer 107 and connected via a diode correspond to the diode D8 and the diode D9 shown in fig. 5, respectively.

A metal-insulator-metal (MIM) capacitor (capacitor)111 corresponds to the capacitor (capacitor) C8, and a BOX capacitor (capacitor)112 corresponds to the capacitor (capacitor) C9. The other diodes (D1 to D7) and capacitors (capacitors) (C1 to C7) shown in fig. 5 are omitted from illustration. The structure of the two MOS transistors 110b and 110c connected via a diode is a well-known LDD MOSFET shown in fig. 8, similarly to the MOS transistor 110 a.

The high voltage VO (5) generated by the high voltage generation circuit unit 200 shown in fig. 5 is supplied to N in the lower layer of the silicon substrate 101 provided in the periphery of the sensor circuit unit 100 via a metal wiring layer not shown⁺A layer 103 for holding the silicon substrate 101 at a high voltage and for removing P from the inside of the light receiving element part 100a⁺The diffusion layer 105 forms a depletion layer having a sufficient thickness in the silicon substrate 101 toward the back surface of the silicon substrate 101.

The capacitor (capacitor)111(C8) is formed as an MIM capacitor (capacitor) in which a SiON film to be an insulating layer is deposited on the underlying aluminum wiring 109a by a Chemical Vapor Deposition (CVD) method, and thereafter, TiN is deposited thereon and patterned to form the opposite electrode 109 b. Capacitor (capaci)tor)112(C9) is connected to an Output terminal (Output) of the high voltage generation circuit 200, and in order to increase the withstand voltage, a P-well layer 106 is formed by forming one electrode in an SOI layer 107 and the other electrode in a silicon substrate 101 using a buried oxide film (BOX)102 as an insulating layer⁺If the film thickness of the BOX is selected to be 100nm to 300nm, the diffusion layer 105 has a sufficiently high withstand voltage of 50V or more.

Fig. 5 shows a 5-stage charge pump circuit as an example, and outputs a DC voltage 5 times higher (High) than the input clock (Vcc).

When a clock signal of a power supply voltage VCC is inputted, an output voltage of the charge pump circuit of N stages becomes

Vout(N)＝VCC×N-Vf×2(N-1)···(1)。

Here, Vf is the threshold voltage of the diode-connected MOSFET.

As described above, by preparing the charge pump circuit of an appropriate order, the power supply voltage VCC can generate a desired high voltage (e.g., 10V to 60V).

In the circuit shown in fig. 5, the potential difference Vdiff of each step becomes

Vdiff＝Vcc-2Vf···(2)，

Therefore, a voltage equal to or lower than VCC can be applied only between both terminals of each of the diodes D1 to D9.

However, when a MOSFET is formed in a bulk (silicon substrate) as in a general Large Scale Integration (LSI), since a high voltage (for example, 30V) is directly applied to a drain junction of a Field Effect Transistor (FET) connected via a diode in a subsequent stage as shown in fig. 9 (further, a threshold voltage (1.8V) is applied between a gate (G) and a source (S)), in order to make the pn junction withstand the high voltage, measures such as inclining the junction to relax an electric field are required, additional processes are required, and the area of the MOSFET is increased.

In contrast, in the present invention, since the MOSFETs to be diodes are formed by being separated from each other into semiconductor layers on the buried oxide film (BOX) as shown in fig. 10, the diodes of the respective stages are completely separated, and a withstand voltage that can withstand the power supply voltage VCC is sufficient, and even in a high-voltage generation circuit, a MOSFET that can operate at the normal power supply voltage VCC can be used.

Since only a voltage equal to or less than VCC can be applied to the capacitors (capacitors) C1 through C8, the MIM capacitor (capacitor)111 shown in fig. 7 can be used.

However, since a high voltage is directly applied to the capacitor (capacitor) C9 for output voltage stabilization, it is necessary to secure a withstand voltage of the capacitor (capacitor). In the present invention, a BOX 102 having a thickness of 100nm to 300nm is used to ensure a sufficient withstand voltage.

In the high voltage generation circuit section 200 shown in fig. 7, the output high voltage is connected to one terminal (N) of the pn junction capacitor (capacitor) of the light receiving element 100a⁺Layer 103) and thus the capacitor (capacitor) C9 may also be omitted.

As described above, by combining the SOI substrate having a low impurity concentration and the high voltage generating circuit which constitutes the charge pump circuit in the semiconductor layer of the SOI substrate, a highly sensitive near-infrared sensor in which the increase in the process or the area is suppressed even with a single power supply can be manufactured.

Next, the manufacturing steps of the high voltage generation circuit section 200 according to the first embodiment of the optical sensor 1000 of the present invention will be described with reference to fig. 11 to 17.

First, as shown in fig. 11 (a), a silicon substrate having an impurity concentration of 1 × 10 was prepared as a Starting material (Starting material)¹²/cm³To 1X 10¹⁴/cm³Includes a buried oxide film (BOX)502 of 100nm to 300nm on an N-type phosphorus-doped low-concentration silicon substrate 501 and has thereon an impurity concentration of about 1 x 10 having a film thickness in the range of 10nm to 100nm¹⁵/cm³A boron doped thin silicon layer (SOI layer) 503.

Silicon substrates of such specifications are manufactured by a well-known smart cut (smart cut) method or a bonding method, and supplied from a wafer supplier.

Next, as shown in fig. 11 (B), the SOI layer 503 is patterned by photolithography using a photoresist and dry etching of silicon (Si) using the photoresist as a photomask, thereby forming an active region.

Further, an N-channel MOSFET is formed on the left side of the drawing, and a P-channel MOSFET is formed on the right side.

Then, as shown in fig. 11 (C), element separation is performed. The active SOI layer 503 is buried with a device Isolation oxide film 504 by using Shallow Trench Isolation (STI), which is a well-known device Isolation technique.

Then, as shown in fig. 11 (D), the upper layer of the SOI layer 503a on the N-channel MOSFET side is doped with Boron (BF) using photolithography and an ion implantation technique using a photoresist as a photomask₂ ⁺) The upper layer of the SOI layer 503b on the P-channel MOSFET side is doped with phosphorus (P)⁺) Ion implantation is performed at a desired doping amount and energy so as to obtain desired threshold values.

Then, as shown in fig. 12 (E), boron (B) is applied using the photoresist pattern 505 formed by photolithography as a photomask⁺) Is implanted into the underlying silicon substrate 501 to form a low-concentration P-well (well) layer 506. At this time, since boron is implanted only a little into the SOI layer 503a and the SOI layer 503b which are upper layers, the impurity concentration thereof is hardly changed. The photoresist pattern 505 is removed after ion implantation.

Then, as shown in fig. 12 (F), a gate oxide film (silicon oxide film) 507 is formed on the SOI layer 503a and the SOI layer 503b by thermal oxidation.

Next, as shown in fig. 12 (G), polysilicon to be a gate electrode is deposited over the entire surface by cvd (chemical Vapor deposition), and a gate electrode 508 including polysilicon is formed by photolithography and dry etching using a resist as a photomask.

Next, as shown in fig. 12 (H), in order to form a contact with the underlying silicon substrate 501, the element isolation oxide film 504 and the buried oxide film 502 at the contact portion are removed by photolithography and dry etching using a photoresist as a photomask, thereby forming a BOX window.

Then, as shown in fig. 13 (I), boron (B) is formed by general photolithography and using a resist as a photomask⁺) The ion implantation of (2) is performed,forming P as a sensing node⁺Layer 509. After ion implantation, the photoresist is removed.

Then, As shown in fig. 13 (J), source/drain N with arsenic (As) implanted therein is formed on the N-channel MOSFET side by photolithography and ion implantation using the gate electrode 508 As a photomask⁺Layer 510 with Boron (BF) implant formed on the P-channel MOSFET side₂) Source/drain p of⁺Layer 511. Furthermore, Sidewalls (SW) are formed on the gate electrode 508 by a well-known method to form source/drain n⁺Inner side of the layer forming n^-Layer of p + [ p ] at source/drain⁺]Inside the layer is formed p- [ p ]^-]Layer, and an LDD type MOSFET can be made.

To include a sensing node p⁺These diffusion layers (source/drain n) including layer 509⁺Layer 510 and source/drain p⁺Layer 511) while under nitrogen (N) at high temperature (around 1,000 deg.c)₂) The heat treatment (annealing) was performed in the atmosphere for about 10 seconds.

Then, as shown in fig. 13 (K), an interlayer insulating film (silicon oxide film) 512 is deposited over the entire surface by CVD, and chemical-mechanical polishing (CMP) is performed to planarize the surface.

Thereafter, as shown in fig. 13 (L), contact holes for electrical connection between the elements are formed in the interlayer insulating film by photolithography and dry etching using a resist as a photomask.

Then, as shown in fig. 14 (M), in order to fill the contact with a conductive material, a barrier metal (Ti/TiN) and tungsten (W), not shown, are deposited by CVD, and then the W and Ti/TiN on the interlayer insulating film 512 are removed by CMP, thereby forming a metal-insulator (MI) tungsten plug 513.

Then, as shown in fig. 14 (N), Ti/TiN/Al-Cu/Ti/TiN is sequentially sputtered, and by photolithography and dry etching using a photoresist as a photomask, M1 wiring 514 is formed. Thereafter, deposition of an insulating film (not shown), planarization (CMP), via formation, plug embedding, and patterning of a wiring layer are repeated, whereby a plurality of M1 wirings 514 can be formed on the upper layer of the interlayer insulating film 512.

Then, as shown in fig. 15 (O), in the case where a MIM capacitor (capacitor) is formed on the second layer M2 wiring 517 connected to the M2 tungsten plug 516, after patterning of the M2 wiring 517, a SiON film to be an insulating film of the capacitor (capacitor) is deposited on the M2 wiring 517 by CVD, and thereafter, a MIM electrode 519 containing TiN to be an opposite electrode of the capacitor (capacitor) is sputtered and patterned, thereby forming the MIM capacitor (capacitor).

Then, as shown in fig. 16 (P), an M2-M3 layer insulating film 520 is deposited on the entire surface, an M3 tungsten plug is sputtered in the contact hole, and the same process as described in fig. 14 (N) and 15 (O) is repeated to form an M3 wiring 522, and a desired opening is provided in the passivation film 523 to form a bonding pad, thereby completing the surface treatment.

Finally, in order to completely deplete the sensor, the back surface of the silicon substrate 501 is polished so that the final wafer thickness becomes 300 μm to 700 μm, and the damaged layer is removed by wet etching. Thereafter, phosphorus ions are implanted into the back surface, laser annealing is performed from the back surface for activation, and thereafter, n is formed on the back surface of the silicon substrate 501⁺Layer 524.

In the first embodiment, the diodes (D1 to D9) used in the high voltage generation circuit 200 are used by connecting the drain (D) and the gate (G) as shown in fig. 10 for the N-channel MOSFET formed in (J) of fig. 13.

In the second embodiment of the present invention, as shown in fig. 18, a first region 603b and a second region 603c which are in contact with each other through a channel region 603a are formed in an SOI layer 603 which is a semiconductor layer on a buried oxide film (BOX)502, a gate electrode 608 formed through a gate oxide film 607 is provided in the channel region 603a, the first region 603b and the channel region 603a have the same conductivity type, the second region 603c and the channel region 603a have different conductivity types, the gate electrode 608 and the second region 603c are connected, and the first region 603b and the second region 603c through the channel region 603a are used as diodes (D1 to D9).

The diode shown in fig. 18 is substantially equivalent to the SOI-MOSFET shown in fig. 10, and the flow described in fig. 11 to 17 itself is almost unchanged.

That is, only in fig. 11 (D), phosphorus (P) is doped into two layers of the SOI layer 503a and the SOI layer 503b⁺) In FIG. 13 (J), the source (S) of the right P-channel MOSFET is P-channel⁺/p^-Layer change to n⁺/n^-In the layer, when ion implantation is performed on the source and drain, arsenic (As) is formed at the midpoint of the gate 508 using the photoresist As a photomask As shown in fig. 19⁺) With Boron (BF)₂ ⁺) The diode shown in fig. 18 can be fabricated by dividing.

Fig. 20 is a graph showing the results obtained by measuring the quantum efficiency with respect to the wavelength of light when the light receiving element 100a shown in fig. 7 is irradiated from the back surface. Further, the reverse bias applied to the pn junction was 30V.

It is found that the sensor of the present invention can obtain a very high quantum efficiency for near-infrared light having a wavelength of 900nm to 1,000nm, as compared with the sensor shown in non-patent document 1.

Next, the leakage current in the reverse bias is considered for three types of diodes used in the SOI structure in the charge pump.

The reason for this is that: if the leakage current increases, the boosting effect of the charge pump circuit deteriorates, and the number of steps of a group of a diode and a capacitor (capacitor) must be increased in order to boost the voltage to a desired voltage, which causes an abnormality that the area increases.

Fig. 21 shows a comparison of the structures of three types of diodes, (a) is a diode described in patent document 2, (B) is a diode-connected MOSFET and used in the first embodiment of the present invention (see fig. 10), and (C) is a diode-connected MOSFET used in the second embodiment of the present invention (see fig. 18).

(A) The diode of the illustrated construction is susceptible to process damage in terms of construction and processing, and also cannot be oxidized to lower the surface energy level. Therefore, since the number of interface levels is large and the depletion layer is in contact with the interface in the reverse bias, there is a defect that the surface recombination current flows through the interface levels and the leakage current increases.

(B) The diode of the illustrated configuration has a gate oxide film formed on the channel region, and thus has less surface energy levels than (a). However, there is a drawback that so-called Gate Induced Drain Leakage (GIDL) causes an increase in Leakage current at the time of reverse bias.

(C) In the diode having the above structure, a portion of the interface between the silicon surface of the SOI and the oxide film where the depletion layer is formed is a portion of the gate oxide film, and thus the interface is good, and the interface level is small, so that the leak current through the level is suppressed.

When reverse bias is applied, n⁺/n^-Although there is a possibility that GIDL occurs in the/n portion, the n portion is n⁺/n^-The structure of/n, therefore, the depletion layer is easy to expand laterally, and the lateral electric field can be fully relaxed. Therefore, the amount of GIDL production is sufficiently suppressed.

Fig. 22 is a diagram showing a relationship between a reverse bias voltage and a leakage current in the three diode structure shown in fig. 21.

By setting the reverse bias voltage to-1.8V and using the diode shown in fig. 21 (C), the leakage current becomes a measurement limit or less, and the leakage current can be reduced by about two orders or more as compared with the diode shown in fig. 21 (a).

[ description of symbols ]

501: low concentration silicon substrate

502: buried oxide film

503: SOI layer

504: element separation oxide film

505: photoresist pattern

506: p well layer

507: gate oxide film

508: gate electrode

509: sensing node p⁺Layer(s)

510: source/drain n⁺Layer(s)

511: source/drain p⁺Layer(s)

512: interlayer insulating film

513: m1 tungsten plug

514: m1 wiring

515: M1-M2 interlayer insulating film

516: m2 tungsten plug

517: m2 wiring

518: MIM insulating film

519: MIM electrode

520: M2-M3 interlayer insulating film

521: m3 tungsten plug

522: m3 wiring

523: passivation film

524: back n⁺Layer(s)