阅读说明：本技术 上电检测电路、gpio接口电路及集成电路芯片 (Power-on detection circuit, GPIO interface circuit and integrated circuit chip ) 是由 不公告发明人 于 2021-08-30 设计创作，主要内容包括：本发明公开了一种上电检测电路、GPIO接口电路及集成电路芯片,涉及集成电路设计技术领域,其中上电检测电路包括RC模块、检测模块和上拉模块；所述检测模块的第一输入端连接所述RC模块的输出端,所述检测模块的第二输入端连接低压电源；所述上拉模块的第一端连接高压电源,所述上拉模块的第二端连接所述检测模块的输出端。上电检测电路能够在接口高压、数字低压的任意上电顺序下均输出有效的隔离信号。(The invention discloses a power-on detection circuit, a GPIO interface circuit and an integrated circuit chip, and relates to the technical field of integrated circuit design, wherein the power-on detection circuit comprises an RC module, a detection module and a pull-up module; the first input end of the detection module is connected with the output end of the RC module, and the second input end of the detection module is connected with a low-voltage power supply; the first end of the upward-drawing module is connected with a high-voltage power supply, and the second end of the upward-drawing module is connected with the output end of the detection module. The power-on detection circuit can output effective isolation signals under any power-on sequence of high-voltage interface and low-voltage digital interface.)

1. A power-up detection circuit, comprising:

an RC module;

the first input end of the detection module is connected with the output end of the RC module, and the second input end of the detection module is connected with the low-voltage power supply;

and the first end of the upward-drawing module is connected with a high-voltage power supply, and the second end of the upward-drawing module is connected with the output end of the detection module.

2. The power-on detection circuit according to claim 1, wherein the RC module comprises a resistor module and a capacitor module, a first end of the resistor module is connected to the high voltage power supply, and a second end of the resistor module is connected to a first end of the capacitor module.

3. The power-on detection circuit of claim 2, wherein the resistance module comprises at least one first PMOS transistor, a source terminal of the first PMOS transistor being connected to the high voltage power supply, a drain terminal of the first PMOS transistor being connected to the capacitance module;

or the first end of the first resistor is connected with the high-voltage power supply, and the second end of the first resistor is connected with the capacitor module.

4. The power-on detection circuit according to claim 2 or 3, wherein the capacitance module comprises a first capacitor, and a first end of the first capacitor is connected to the resistance module;

or the device comprises a field effect tube connected in a capacitance mode, and the field effect tube is connected with the resistance module.

5. The power-on detection circuit according to claim 1, wherein the detection module comprises a second PMOS transistor and a first NMOS transistor, a gate terminal of the second PMOS transistor is connected to the output terminal of the RC module as the first input terminal of the detection module, a drain terminal of the second PMOS transistor is connected to the drain terminal of the first NMOS transistor, a drain terminal of the first NMOS transistor is connected to the second terminal of the pull-up module as the output terminal of the detection module, and a gate of the first NMOS transistor is connected to the low voltage power supply as the second terminal of the detection module.

6. The power-on detection circuit of claim 5, wherein the second PMOS transistor is a proportional tube.

7. The power-up detection circuit of claim 1, wherein the pull-up module comprises a second resistor or a plurality of series-connected PMOS transistors.

8. The power-on detection circuit of claim 7, wherein the pull-up module comprises a third PMOS transistor, a fourth PMOS transistor and a fifth PMOS transistor, a drain terminal and a gate terminal of the third PMOS transistor are connected to the output terminal of the detection module, a source terminal of the third PMOS transistor is connected to a drain terminal and a gate terminal of the fourth PMOS transistor, a source terminal of the fourth PMOS transistor is connected to a drain terminal and a gate terminal of the fifth PMOS transistor, and a source terminal of the fifth PMOS transistor is connected to the high-voltage power supply.

9. A GPIO interface circuit including a power-up detection circuit as claimed in any one of claims 1 to 8.

10. An integrated circuit chip comprising the GPIO interface circuit of claim 9.

Technical Field

The invention relates to the technical field of integrated circuit design, in particular to a power-on detection circuit, a GPIO interface circuit and an integrated circuit chip.

Background

In an integrated circuit chip, which is usually a multi-power system, a GPIO (General-purpose input/output) interface circuit operates in a high voltage domain, such as 1.8V, and a digital core circuit operates in a low voltage domain, such as 0.9V. And the signal of the digital low-voltage domain is converted into an interface high-voltage domain through a level conversion circuit, and then the GPIO interface is communicated with the plate electrode system. In general, when a chip is powered on, the power-on sequence of high-voltage and low-voltage interfaces is uncertain. If the interface high voltage is firstly electrified and the digital low voltage is then electrified, a non-electric domain (digital low voltage domain) signal is controlled by an electric domain (interface high voltage domain) circuit, so that the GPIO interface is in an uncertain state before the digital low voltage is electrified, and an uncontrollable state can occur in a plate electrode system component controlled by the GPIO.

Therefore, a voltage detection circuit is generally required to be integrated in a GPIO interface circuit, and when the interface high voltage is powered on first and the digital low voltage is powered on later, the conventional voltage detection circuit (as shown in fig. 1) can effectively avoid the situation that no electronic control system is powered on, but when the interface high voltage and the digital low voltage are powered on simultaneously, the conventional voltage detection circuit is difficult to effectively isolate a level conversion circuit from a digital low voltage domain to the interface high voltage, so that output glitches of the GPIO interface are caused.

Disclosure of Invention

The present invention is directed to solving at least one of the problems of the prior art. Therefore, the invention provides a power-on detection circuit which can output effective isolation signals under any power-on sequence of high-voltage interface and low-voltage digital interface.

The invention also provides a GPIO interface circuit with the power-on detection circuit.

The invention also provides an integrated circuit chip with the GPIO interface circuit.

The power-on detection circuit comprises an RC module, a detection module and a pull-up module; the first input end of the detection module is connected with the output end of the RC module, and the second input end of the detection module is connected with a low-voltage power supply; the first end of the upward-drawing module is connected with a high-voltage power supply, and the second end of the upward-drawing module is connected with the output end of the detection module.

The power-on detection circuit provided by the embodiment of the invention at least has the following beneficial effects: the RC module has a time delay characteristic, the output of the RC module is connected to the first input end of the detection module to control the detection module, the pull-up module can reduce the power consumption of the circuit, and under the action of the RC module and the pull-up module, the power-on detection circuit can effectively isolate the level conversion from a digital low-voltage domain to an interface high-voltage domain under any power-on sequence, namely, an effective isolation signal can be output.

According to some embodiments of the invention, the RC module comprises a resistor module and a capacitor module, a first end of the resistor module is connected to the high voltage power supply, and a second end of the resistor module is connected to the first end of the capacitor module.

According to some embodiments of the invention, the resistance module comprises at least one first PMOS transistor, a source terminal of the first PMOS transistor being connected to the high voltage power supply, a drain terminal of the first PMOS transistor being connected to the capacitance module; or the first end of the first resistor is connected with the high-voltage power supply, and the second end of the first resistor is connected with the capacitor module.

According to some embodiments of the invention, the capacitance module comprises a first capacitance, a first end of the first capacitance being connected to the resistance module; or the device comprises a field effect tube connected in a capacitance mode, and the field effect tube is connected with the resistance module.

According to some embodiments of the present invention, the detection module includes a second PMOS transistor and a first NMOS transistor, a gate terminal of the second PMOS transistor is connected to the output terminal of the RC module as a first input terminal of the detection module, a drain terminal of the second PMOS transistor is connected to a drain terminal of the first NMOS transistor, a drain terminal of the first NMOS transistor is connected to the second terminal of the pull-up module as an output terminal of the detection module, and a gate of the first NMOS transistor is connected to the low voltage power supply as a second terminal of the detection module.

According to some embodiments of the invention, the second PMOS transistor is a proportional tube.

According to some embodiments of the invention, the pull-up module comprises a second resistor or a plurality of series-connected PMOS transistors.

According to some embodiments of the invention, the pull-up module comprises a third PMOS transistor, a fourth PMOS transistor and a fifth PMOS transistor, a drain terminal and a gate terminal of the third PMOS transistor are connected to the output terminal of the detection module, a source terminal of the third PMOS transistor is connected to a drain terminal and a gate terminal of the fourth PMOS transistor, a source terminal of the fourth PMOS transistor is connected to a drain terminal and a gate terminal of the fifth PMOS transistor, and a source terminal of the fifth PMOS transistor is connected to the high voltage power supply.

The GPIO interface circuit according to the second embodiment of the invention comprises the power-on detection circuit according to the first embodiment.

The GPIO interface circuit provided by the embodiment of the invention at least has the following beneficial effects: under the action of the power-on detection circuit, the GPIO interface circuit can effectively isolate the level conversion from a digital low-voltage domain to an interface high-voltage domain, and effectively avoids the generation of burrs.

An integrated circuit chip according to an embodiment of the third aspect of the present invention includes the GPIO interface circuit as described in the embodiment of the second aspect.

The integrated circuit chip according to the embodiment of the invention has at least the following beneficial effects: can all can effectively keep apart digital low voltage territory to the level transition in interface high voltage territory under arbitrary power-on order, avoid the GPIO interface burr to appear for the GPIO interface has definite state, and then makes integrated circuit chip can normally work.

Additional aspects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.

Drawings

The above and/or additional aspects and advantages of the present invention will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:

FIG. 1 is a schematic diagram of a conventional power-up detection circuit;

FIG. 2 is a timing diagram of a conventional power-on detection circuit in a situation where a high voltage is first powered on and a low voltage is then powered on;

FIG. 3 is a desirable timing diagram for a conventional power-up detection circuit with simultaneous power-up of high and low voltages;

FIG. 4 is a timing diagram illustrating the actual timing of a conventional power-up detection circuit during simultaneous power-up of high and low voltages;

FIG. 5 is a diagram of a power-up detection circuit according to an embodiment of the invention;

fig. 6 is a timing diagram of the power-up detection circuit shown in fig. 5 in the case where the high voltage and the low voltage are simultaneously powered up.

Reference numerals:

RC module 100, resistance module 110, capacitance module 120, detection module 200, pull-up module 300.

Detailed Description

Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the accompanying drawings are illustrative only for the purpose of explaining the present invention, and are not to be construed as limiting the present invention.

In the description of the present invention, the meaning of a plurality of means is one or more, the meaning of a plurality of means is two or more, and more than, less than, more than, etc. are understood as excluding the present number, and more than, less than, etc. are understood as including the present number. If the first and second are described for the purpose of distinguishing technical features, they are not to be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated or implicitly indicating the precedence of the technical features indicated.

In the description of the present invention, unless otherwise explicitly limited, terms such as arrangement, installation, connection and the like should be understood in a broad sense, and those skilled in the art can reasonably determine the specific meanings of the above terms in the present invention in combination with the specific contents of the technical solutions.

As shown in fig. 1, the conventional voltage detection circuit is connected by using a PMOS transistor MPt and an NMOS transistor MNt connected in an inverter manner, specifically, a source terminal of MPt is connected to a high voltage source vcc, a drain terminal of MPt is connected to a drain terminal of MNt and serves as an output terminal to output an isolation signal vddiso, a gate terminal of MPt is connected to a gate terminal of MNt and serves as an input terminal to input a low voltage source vdd, and a source terminal of MNt inputs a voltage vss, and if the source terminal of MNt is connected to a common ground terminal, 0V is input.

It should be noted that the voltage vss is a voltage of a common ground of the circuit or a negative power supply, and is 0V or a negative voltage.

For example, the voltage after vcc power-up is vh, and the voltage after vdd power-up is v1, where vh is 2 × v 1. When vcc is powered on first and vdd is powered on later, namely, the interface high voltage is powered on first and the digital low voltage is powered on later, the timing diagrams of vss, vdd and vddiso are shown in fig. 2, and vddiso is effective before vdd rises to 0.7v1, so that effective isolation of a level conversion circuit from a vdd domain (digital low voltage domain) to a vcc domain (interface high voltage domain) can be realized, and therefore burrs and uncertain states do not occur in GPIOs.

When vcc and vdd are powered up simultaneously, i.e. interface high voltage and digital low voltage are powered up simultaneously, the desired timing diagram for vss, vdd and vddiso should be as shown in fig. 3, but in practice the timing diagram is as shown in fig. 4, i.e. fig. 3 is the desired timing diagram for the ideal case, while fig. 4 is the actual timing diagram, in fig. 3, the Vgs of MPt is increased from 0V to 0.7(vh-V1) to 0.7V1 in the time range of 0 to t1, and the Vgs of MNt is also increased from 0V to 0.7V1, i.e. MPt and MNt have the same Vgs. On the other hand, MPt is usually designed as an inverted ratio tube (inverted ratio tube means that the width-to-length ratio of the transistor is less than 1, i.e. the width is less than the length), while MPt is a normal size tube. Therefore, the pull-down capability of MNt will be stronger than the pull-up capability of MPt in general, resulting in the output isolation signal vddiso being invalid, i.e., vddiso is shown in fig. 4.

The power-on detection circuit can enable the isolation signal of the level conversion circuit from the digital low-voltage domain to the interface high-voltage domain to be effective in any power-on sequence (such as the sequence that high voltage is firstly applied and low voltage is then applied or the sequence that high voltage and low voltage are simultaneously applied) so as to avoid the GPIO interface from generating burrs, and the output of the GPIO interface has a determined state.

In some embodiments of the present invention, the power-up detection circuit includes an RC module 100, a detection module 200, and a pull-up module 300. The RC module 100, the detection module 200 and the pull-up module 300 are all connected to a high voltage source vcc, the RC module 100 and the detection module 200 are commonly connected to vss, and the pull-up module 300 is further connected to the output end of the detection module 200. The output terminal of the RC module 100 is connected to the first input terminal of the detection module 200, and the second input terminal of the detection module 200 is connected to the low voltage power supply vdd.

The RC module 100 has a delay characteristic, the output of the RC module 100 is connected to the first input terminal of the detection module 200 to control the detection module 200, and the pull-up module 300 can reduce the power consumption of the circuit, and under the action of the RC module 100 and the pull-up module 300, the power-on detection circuit can effectively isolate the level conversion from the digital low voltage domain to the interface high voltage domain, i.e. can output an effective isolation signal, in any power-on sequence.

In some embodiments of the present invention, the RC module 100 includes a resistor module 110 and a capacitor module 120, the resistor module 110 and the capacitor module 120 are connected in series, wherein one end of the resistor module 110 is connected to a high voltage power supply, one end of the capacitor module 120 is connected to vss, and a connection between the resistor module 110 and the capacitor module 120 is used as an output end of the RC module 100 and connected to the detection module 200.

In some embodiments of the present invention, the resistance module 110 may adopt a first PMOS transistor, a gate terminal of the first PMOS transistor is grounded, a source terminal of the first PMOS transistor is connected to the high voltage source vcc, a drain terminal of the first PMOS transistor is connected to the capacitance module 120, and the drain terminal of the first PMOS transistor may be connected to the first input terminal of the detection module 200 as the output terminal of the RC module 100.

In some embodiments of the present invention, the resistance module 110 may further adopt a manner that a plurality of PMOS transistors are connected in series, for example, two PMOS transistors are adopted, that is, a PMOS transistor a and a PMOS transistor B, wherein a source terminal of the PMOS transistor a is connected to the high voltage power supply, a gate terminal and a drain terminal of the PMOS transistor a are connected to a source terminal of the PMOS transistor B, and a gate terminal and a drain terminal of the PMOS transistor B are connected to the capacitance module 120.

In some embodiments of the present invention, the resistor module 110 may further connect the high voltage power supply and the capacitor module 120 using a first resistor. It should be noted that the first resistance value can be set according to the time constant of the RC module 100, i.e., according to the requirement of the circuit design.

In some embodiments of the present invention, the capacitor module 120 may be implemented in a capacitive manner, for example, by using the first capacitor C1, the first terminal of the first capacitor C1 is connected to the resistor module 110, and the second terminal of the first capacitor C1 is connected to vss.

In some embodiments of the present invention, the capacitor module 120 may further employ a field effect transistor connected in a capacitor manner, it is understood that the field effect transistor connected in the capacitor manner is a field effect transistor whose gate terminal is used as the first terminal, and whose drain terminal and source terminal are connected as the second terminal, the field effect transistor connected in the above manner may function as a capacitor, the gate terminal of the field effect transistor may be connected to the resistor module 110, and the drain terminal and source terminal of the field effect transistor are connected to vss, it should be noted that the field effect transistor may be a PMOS transistor or an NMOS transistor.

For example, in an embodiment, the RC module 100 includes a first PMOS transistor and a first capacitor, that is, the first PMOS transistor is used as the resistor module 110, the first capacitor is used as the capacitor module 120, the gate terminal of the first PMOS transistor is grounded, the source terminal of the first PMOS transistor is connected to the high voltage source vcc, the drain terminal of the first PMOS transistor is connected to the first terminal of the first capacitor, and the second terminal of the first capacitor is connected to vss, it can be understood that the connection between the first PMOS transistor and the first capacitor is used as the output terminal of the RC module 100 to connect to the detection module 200.

It should be appreciated that the RC module 100 may also employ a series connection of the first resistor and the first capacitor, a series connection of the first resistor and the fet connected in a capacitor manner, a series connection of the first PMOS transistor and the fet connected in a capacitor manner, a series connection of a plurality of PMOS transistors and the fet connected in a capacitor manner, or a series connection of a plurality of PMOS transistors and the first capacitor. The resistance value of the first resistor is changed according to the requirement of the circuit design of practical application, and a single resistor or a plurality of resistors can be connected in series, in parallel or in combination of series and parallel; similarly, the value of the first capacitor is changed according to the requirement of the circuit design in practical application, and a single capacitor or a plurality of capacitors can be connected in series, in parallel or in a combination of series and parallel.

In some embodiments of the present invention, the detection module 200 includes a second PMOS transistor and a first NMOS transistor, a gate terminal of the second PMOS transistor is connected to the output terminal of the RC module 100 as a first input terminal of the detection module 200, a source terminal of the first PMOS transistor is connected to the high voltage power supply, a drain terminal of the first PMOS transistor is connected to a drain terminal of the first NMOS transistor, a gate terminal of the first NMOS transistor is connected to the low voltage power supply as a second input terminal of the detection module 200, and a source terminal of the first NMOS transistor is connected to vss.

In some embodiments of the present invention, the second PMOS transistor is a proportional transistor, so that the pull-up capability of the second PMOS transistor is stronger than the pull-down capability of the first NMOS transistor, thereby achieving effective release of the isolation signal. It should be noted that a proportional tube means that the width-to-length ratio of the transistor is greater than 1, i.e., the width is greater than the length.

In some embodiments of the present invention, the pull-up module 300 includes a plurality of series-connected PMOS transistors respectively connected to the output terminals of the high voltage power supply and the detection module 200.

For example, the pull-up module 300 includes a third PMOS transistor, a fourth PMOS transistor, and a fifth PMOS transistor, wherein the third PMOS transistor, the fourth PMOS transistor, and the fifth PMOS transistor are connected in series, it is understood that a drain terminal and a gate terminal of the third PMOS transistor are both connected to the output terminal of the detection module 200, a drain terminal and a gate terminal of the fourth PMOS transistor are both connected to the source terminal of the third PMOS transistor, a drain terminal and a gate terminal of the fifth PMOS transistor are both connected to the source terminal of the fourth PMOS transistor, and a source terminal of the fifth PMOS transistor is connected to the high voltage power supply.

It should be noted that the pull-up module 300 may also be a mode in which a plurality of PMOS transistors are connected in series, such as 4, 5, etc., and the specific number may be adjusted according to the power consumption requirement of the circuit.

In some embodiments of the present invention, the pull-up module 300 may further adopt a second resistor, that is, two ends of the second resistor are respectively connected to the high voltage power supply and the output end of the detection module 200. It should be noted that the resistance of the second resistor changes according to the requirements of the circuit design of the practical application, and a single resistor or a plurality of resistors can be connected in series, in parallel, or in a combination of series and parallel.

In some embodiments of the present invention, the power-up detection circuit comprises an RC module 100, a detection module 200, and a pull-up module 300, wherein the RC module 100 comprises a first PMOS transistor and a first capacitor, the detection module 200 comprises a second PMOS transistor and a first NMOS transistor, and the pull-up module 300 comprises a third PMOS transistor, a fourth PMOS transistor, and a fifth PMOS transistor.

Specifically, as shown in fig. 5, the first PMOS transistor MP1 serves as the resistor module 110, the first capacitor C1 serves as the capacitor module 120, the gate terminal of the first PMOS transistor MP1 is grounded, the source terminal of the first PMOS transistor MP1 is connected to the high voltage source vcc, the drain terminal of the first PMOS transistor MP1 is connected to the first terminal of the first capacitor C1, the second terminal of the first capacitor C1 is connected to the vss, the output voltage vst of the first PMOS transistor MP1 is connected to the gate terminal of the second PMOS transistor MP2, that is, the drain terminal of the first PMOS transistor MP1 serves as the output terminal of the RC module 100, and the gate terminal of the second PMOS transistor MP2 serves as the first input terminal of the detection module 200.

The gate terminal of the first NMOS transistor MN1 is used as the second input terminal of the detection module 200 to connect to the low voltage source vdd, the source terminal of the first NMOS transistor MN1 is connected to vss, the drain terminal of the first NMOS transistor MN1 is connected to the drain terminal of the second PMOS transistor MP2, the source terminal of the second PMOS transistor MP2 is connected to the high voltage source, and the drain terminal of the second PMOS transistor MP2 is used as the output terminal of the detection module 200.

The drain terminal and the gate terminal of the third PMOS transistor MP3 are both connected to the output terminal of the detection module 200, the drain terminal and the gate terminal of the fourth PMOS transistor MP4 are both connected to the source terminal of the third PMOS transistor MP3, the drain terminal and the gate terminal of the fifth PMOS transistor MP5 are both connected to the source terminal of the fourth PMOS transistor MP4, and the source terminal of the fifth PMOS transistor MP5 is connected to the high voltage power supply. Under the action of the pull-up module 300, the detection module 200 outputs an isolation signal vddiso.

The gate of the second PMOS transistor MP2 and the gate of the first NMOS transistor MN1 in the detection module 200 are respectively connected to the output vst of the RC module 100 and the digital low voltage power supply vdd, i.e. controlled by vst and vdd. Due to the delay effect of the RC module 100, the size of the first PMOS transistor MP1 and the capacitance of the first capacitor C1 are adjusted, so that the Vgs of the second PMOS transistor MP2 is larger than the Vgs of the first NMOS transistor MN1 during the simultaneous power-up of vcc and vdd.

As shown in fig. 6, since vh is 2 × v1, Vgs of the second PMOS transistor MP2 is 2 times Vgs of the first NMOS transistor MN 1. In addition, since the second PMOS transistor MP2 and the first NMOS transistor MN1 can be controlled separately, the second PMOS transistor MP2 can be designed as a proportional transistor, so that the size thereof is larger than the first NMOS transistor MN1, i.e., the pull-up capability of the second PMOS transistor MP2 is further stronger than the pull-down capability of the first NMOS transistor MN 1. When the vst voltage rises to a sufficiently high value to turn off the second PMOS transistor MP2, vddiso is pulled down to release, i.e., switch from active to inactive, as shown at time t2 in fig. 6.

In addition, the pull-up module 300 provides a weaker pull-up, which can be understood as that the equivalent resistance value of the pull-up module 300 is larger, and the power consumption is lower, so that under the power-up sequence of vcc first power-up and vdd second power-up, the isolation state of vdd can be kept until vdd rises to 0.7v1, that is, the requirement of the isolation state of vdd in the power-up sequence of vcc first power-up and vdd second power-up is met.

The power-on detection circuit provided by the invention utilizes the delay characteristic of the RC module 100 to improve the traditional detection circuit, the second PMOS transistor and the first NMOS transistor are respectively controlled, and the pull-up module 300 provides pull-up, so that the power consumption is reduced, and meanwhile, the isolation signal from a digital low-voltage domain to an interface high-voltage domain is effective under any power-on sequence of high voltage and low voltage, further, the GPIO burr is avoided, and the GPIO interface has a determined state.

In some embodiments of the present invention, a GPIO interface circuit is provided. The GPIO interface circuit comprises the power-on detection circuit of the embodiment, and under the action of the power-on detection circuit, the GPIO interface circuit can effectively isolate the level conversion from a digital low-voltage domain to an interface high-voltage domain, so that the generation of burrs is effectively avoided.

In some embodiments of the present invention, an integrated circuit chip is also provided. The integrated circuit chip comprises the GPIO interface circuit of the embodiment, the power-on detection circuit in the embodiment of the invention is arranged in the GPIO interface circuit, and can effectively isolate the level conversion from the digital low-voltage domain to the interface high-voltage domain under any power-on sequence, thereby avoiding the burr of the GPIO interface, enabling the GPIO interface to have a determined state and further enabling the integrated circuit chip to work normally.

The embodiments of the present invention have been described in detail with reference to the accompanying drawings, but the present invention is not limited to the above embodiments, and various changes can be made within the knowledge of those skilled in the art without departing from the gist of the present invention.