阅读说明：本技术 配备有电源门控电路的驱动电路 (Drive circuit equipped with power supply gate control circuit ) 是由 小岛美枝子 于 2020-04-01 设计创作，主要内容包括：本文公开一种设备,其包含第一缓冲电路、被配置成驱动所述第一缓冲电路的多个第一驱动电路,以及被配置成分别将操作电压供应到所述第一驱动电路的多个第一开关电路。所述第一驱动电路共同布置于第一区中呈矩阵形式,且所述第一开关电路共同布置于不同于所述第一区的第二区中。(Disclosed herein is an apparatus including a first buffer circuit, a plurality of first driving circuits configured to drive the first buffer circuit, and a plurality of first switching circuits configured to supply operating voltages to the first driving circuits, respectively. The first drive circuits are commonly arranged in a first region in a matrix form, and the first switch circuits are commonly arranged in a second region different from the first region.)

1. An apparatus, comprising:

a first buffer circuit;

a plurality of first driving circuits configured to drive the first buffer circuits; and

a plurality of first switching circuits configured to supply operating voltages to the first driving circuits, respectively,

wherein the first drive circuits are commonly arranged in a first region in a matrix form, and

wherein the first switch circuits are commonly arranged in a second region different from the first region.

2. The apparatus of claim 1, wherein the second region is adjacent to the first region.

3. The apparatus of claim 2, wherein each of the first switch circuits includes a first transistor configured to supply a first potential to an associated one of the first drive circuits, and a second transistor configured to supply a second potential to an associated one of the first drive circuits.

4. The apparatus as set forth in claim 3, wherein,

wherein the second region comprises a first sub-region and a second sub-region,

wherein the first transistors are arranged in common in the first sub-region, and

wherein the second transistors are commonly arranged in the second sub-region.

5. The apparatus of claim 4, further comprising:

a second buffer circuit;

a plurality of second driving circuits configured to drive the second buffer circuits; and

a plurality of second switching circuits configured to supply operating voltages to the second driving circuits, respectively,

wherein the second drive circuits are arranged in common in the third region in a matrix form, and

wherein the second switch circuits are commonly arranged in a fourth region different from the third region.

6. The apparatus of claim 5, wherein the fourth zone is adjacent to the third zone.

7. The apparatus of claim 6, wherein the first zone is adjacent to the third zone.

8. The apparatus of claim 7, wherein the first and third zones are disposed between the second and fourth zones.

9. The apparatus of claim 8, wherein each of the second switch circuits includes a third transistor configured to supply a first potential to an associated one of the second drive circuits and a fourth transistor configured to supply a second potential to an associated one of the second drive circuits.

10. The apparatus as set forth in claim 9, wherein,

wherein the fourth region comprises a third sub-region and a fourth sub-region,

wherein the third transistors are arranged in common in the third sub-region, and

wherein the fourth transistors are arranged in common in the fourth sub-region.

11. The apparatus of claim 10, further comprising an external end electrode,

wherein the first and second buffer circuits are commonly connected to the external terminal electrode.

12. The apparatus of claim 11, wherein the first and second buffer circuits are configured to be uniquely activated.

13. An apparatus, comprising:

an external terminal electrode;

a first buffer circuit connected between a first power line and the external terminal electrode;

a second buffer circuit connected between a second power line and the external terminal electrode;

a first driving circuit configured to drive the first buffer circuit;

a second driving circuit configured to drive the second buffer circuit;

a first switching circuit configured to supply an operating voltage to the first driving circuit; and

a second switching circuit configured to supply an operating voltage to the second driving circuit,

wherein the first and second drive circuits are arranged between the first and second switch circuits.

14. The apparatus as set forth in claim 13, wherein,

wherein the first driving circuit includes a first transistor and a second transistor connected in series between a third power supply line and a fourth power supply line,

wherein the second drive circuit includes a third transistor and a fourth transistor connected in series between the third power supply line and a fourth power supply line,

wherein the first buffer circuit has an input node connected to a first connection node between the first transistor and the second transistor, and

wherein the second buffer circuit has an input node connected to a second connection node between the third transistor and the fourth transistor.

15. The apparatus as set forth in claim 14, wherein,

wherein the first switch circuit includes a fifth transistor connected between the third power line and the first connection node, and

wherein the second switching circuit includes a sixth transistor connected between the third power supply line and the second connection node.

16. The apparatus as set forth in claim 15, wherein,

wherein the first switch circuit further comprises a seventh transistor connected between the fourth power line and the first connection node, an

Wherein the second switch circuit further includes an eighth transistor connected between the fourth power supply line and the second connection node.

17. An apparatus, comprising:

a buffer circuit;

a plurality of driving circuits configured to drive the buffer circuits, the driving circuits being arranged in a first direction, each of the driving circuits including a first MOS transistor of a first conductivity type and a second MOS transistor of a second conductivity type;

a first switch circuit connected to a source of the first MOS transistor via a first source line; and

a second switch circuit connected to a source of the second MOS transistor via a second source line,

wherein the first and second source lines extend in a second direction such that the first source line crosses the second MOS transistor.

18. The apparatus of claim 17, wherein the second source line crosses the first switching circuit.

19. The apparatus of claim 18, further comprising a signal line commonly connected to an input node of the drive circuit,

wherein the signal line extends between the first MOS transistor and the second MOS transistor along a first direction.

20. The apparatus of claim 19, wherein the signal line crosses the first source line.

Background

A semiconductor device such as a Dynamic Random Access Memory (DRAM) drives read data read from a memory cell array using an output buffer and outputs the data to the outside via a data terminal. A plurality of driving circuits for driving the output buffer are provided in a stage preceding the output buffer. In order to reduce off-state leakage current, there is a case where a switch circuit is provided in each of the drive circuits between the source of the transistor constituting the drive circuit and the power supply line. However, when a plurality of driving circuits are arranged in an array, there is a problem as to where to place the switching circuit.

Disclosure of Invention

Example apparatus for a semiconductor device are disclosed herein. In an aspect of the present disclosure, an apparatus includes a first buffer circuit, a plurality of first driving circuits configured to drive the first buffer circuit, and a plurality of first switching circuits configured to supply operating voltages to the first driving circuits, respectively. The first drive circuits are arranged in common in a matrix form in the first region. The first switch circuits are commonly arranged in a second region different from the first region.

In another aspect of the present disclosure, an apparatus includes an external terminal electrode, a first buffer circuit connected between a first power line and the external terminal electrode, and a second buffer circuit connected between a second power line and the external terminal electrode. The apparatus additionally includes a first drive circuit configured to drive the first buffer circuit, a second drive circuit configured to drive the second buffer circuit, a first switch circuit configured to supply an operating voltage to the first drive circuit, and a second switch circuit configured to supply the operating voltage to the second drive circuit. The first and second drive circuits are arranged between the first and second switch circuits.

In another aspect of the present disclosure, an apparatus includes a buffer circuit and a plurality of driving circuits configured to drive the buffer circuit, the driving circuits being arranged in a first direction, each of the driving circuits including a first MOS transistor of a first conductivity type and a second MOS transistor of a second conductivity type. The apparatus additionally includes a first switch circuit connected to the source of the first MOS transistor via a first source line, and a second switch circuit connected to the source of the second MOS transistor via a second source line. The first source line and the second source line extend in the second direction such that the first source line crosses the second MOS transistor.

Drawings

Fig. 1 is a schematic plan view showing the layout of a semiconductor device according to the present disclosure.

Fig. 2 is a layout diagram showing the configuration of the I/O control circuit.

Fig. 3 is a waveform diagram of a read clock signal.

Fig. 4 is a block diagram showing the configuration of the I/O control circuit.

Fig. 5 is a circuit diagram showing the configuration of a relevant part of the read clock synchronizing circuit.

Fig. 6 is a timing chart for explaining the operation of the read clock synchronizing circuit.

Fig. 7 is a circuit diagram of an output buffer.

Fig. 8 is a circuit block of a driving circuit and an output buffer corresponding to one data terminal.

Fig. 9 is a block diagram showing the configuration of the pull-up circuit.

Fig. 10 is a block diagram showing the configuration of the pull-down circuit.

Fig. 11 is a block diagram showing the configuration of a pull-up pre-emphasis circuit.

Fig. 12 is a block diagram showing the configuration of the pull-down pre-emphasis circuit.

Fig. 13 is a circuit diagram of the speed selector.

Fig. 14 is a circuit diagram of a pull-up driver or a pull-down driver.

Fig. 15 is a layout diagram of the drive circuit.

Fig. 16 is a diagram showing a power supply line formed on a drive circuit.

Fig. 17 is a diagram showing the layout of the drive circuit in more detail.

Detailed Description

Various embodiments of the present invention will be described in detail below with reference to the accompanying drawings. The following detailed description refers to the accompanying drawings that show, by way of illustration, specific aspects and embodiments of the invention that may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the present invention. In the following, a layout or a floorplan may be defined to show a physical arrangement of circuits and/or circuit blocks that is different from the logical diagram. The various embodiments disclosed herein are not necessarily mutually exclusive, as some disclosed embodiments may be combined with one or more other disclosed embodiments to form new embodiments.

The semiconductor device 10 according to the present disclosure is a low power double data rate 5(LPDDR5) DRAM, and as shown in fig. 1, has a memory cell array 11, a plurality of data terminals 12, and a plurality of command address terminals 13. The terminals 12 and 13 are arranged along one side extending in the x direction of the semiconductor device 10. Other terminals, such as power supply terminals, are also present. The data terminals 12 are arranged in two separate orientations with the command address terminals 13 arranged therebetween. The memory cell array 11 and the data terminal 12 are connected via an I/O control circuit 14, and the memory cell array 11 and the command address terminal 13 are connected via an access control circuit 15. When a read command and an address signal corresponding thereto are input from the command address terminal 13, read data read from the memory cell array 11 is output to the data terminal 12 via the I/O control circuit 14. When a write command and an address signal corresponding thereto are input from the command address terminal 13, write data input to the data terminal 12 is written to the memory cell array 11 via the I/O control circuit 14.

As shown in FIG. 2, the data terminal 12 includes a terminal 12 for inputting and outputting data DQ0 through DQ7, respectively₀To 12₇A terminal 12M to which the data mask signal is input and output, a terminal 12S to which the complementary strobe signals DQST and DQSB are input and output, respectively, and a terminal 12C to which the complementary clock signals WCKt and WCKc are input, respectively. I/O control circuits 20 are respectively assigned to the terminals 12₀To 12₇And 12M. The I/O control circuit 20 is connected to the memory cell array 11 via a read/write bus 16. The I/O control circuit 20 includes a read system circuit including a read data storage circuit 21, a read clock synchronization circuit (parallel-to-serial conversion circuit) 22, a drive circuit 23, and an output buffer 24, and a write system circuit including an input buffer 25, a timing adjustment circuit 26, a write clock synchronization circuit (serial-to-parallel conversion circuit) 27, and a write data output circuit 28. I/O control circuit 20 is responsive to the correspondence of data terminals 12, respectivelyThe x-coordinate of the data terminal is arranged in the y-direction so that read data and data write can flow in the y-direction.

The clock signals WCKt and WCKc are input to the clock signal generation circuit 30. The clock signal generation circuit 30 generates read clock signals R0 through R3 and write clock signals W0 through W3 based on clock signals WCKt and WCKc. As shown in fig. 3, the read clock signals R0 through R3 are four-phase clock signals having twice the period as long as the phases of the clock signals WCKt and WCKc are different from each other by 90 degrees. The read clock signals R0 through R3 are supplied to the read clock synchronizing circuit 22 via read clock lines RL0 through RL3, respectively. The read clock synchronizing circuit 22 performs a parallel-serial conversion operation of read data in synchronization with the read clock signals R0 to R3. The write clock signals W0-W3 are 90 degrees out of phase with each other and are supplied to the input buffer 25 via the write clock lines WL 0-WL 3, respectively. The input buffer 25 performs a serial-to-parallel conversion operation of write data in synchronization with the write clock signals W0 to W3. The read clock lines RL 0-RL 3 and the write clock lines WL 0-WL 3 all extend in the x-direction.

Fig. 4 is a block diagram showing the configuration of the I/O control circuit 20. The read data storage circuit 21, the read clock synchronizing circuit 22, the drive circuit 23, and the output buffer 24 constitute a read system circuit and are connected between the read/write bus 16 and the data terminal 12 in this order. An output electrostatic discharge (ESD) protection circuit 29A is disposed near the output buffer 24. The input buffer 25, timing adjustment circuit 26, write clock synchronization circuit 27, and write data output circuit 28 constitute a write system circuit and are connected in this order between the data terminal 12 and the read/write bus 16. The input ESD protection circuit 29B is disposed near the input buffer 25.

The read data storage circuit 21 stores therein the parallel read data supplied from the read/write bus 16 and supplies the read data to the read clock synchronization circuit 22. The read clock synchronizing circuit 22 converts the parallel read data into serial data based on the read clock signals R0 to R3 to generate complementary pull-up data DATAu and pull-down data DATAd. The drive circuit 23 drives the output buffer 24 based on the pull-up data DATAu and the pull-down data DATAd, thereby outputting the serial write data DQ from the data terminal 12. The impedance, drive strength and slew rate of the output buffer 24 are adjusted by the drive circuit 23.

Fig. 5 is a circuit diagram showing the configuration of a relevant part of the read clock synchronizing circuit 22. As shown in fig. 5, the read clock synchronizing circuit 22 has four tri-state buffer circuits 110 to 113. One of the tri-state buffer circuits 110 to 113 is activated, and the remaining three tri-state buffer circuits have outputs in a high impedance state based on the read clock signals R0 to R3. The output nodes of the tri-state buffer circuits 110 to 113 are commonly connected to the signal node 101. As shown in fig. 6, the read clock signals R0 through R3 are four-phase clock signals that are 90 degrees out of phase with each other. The tri-state buffer circuits 110 to 113 output the read data D0 to D3 to the signal node 101 in response to rising edges of the read clock signals R0 to R3, respectively. Therefore, the frequency of the serial read data D0 through D3 presented on the signal node 101 is four times higher than the frequency of the parallel read data D0 through D3 input to the tri-state buffer circuits 110 through 113, respectively.

The inverter circuits 102 and 103 are cascade-connected at a stage subsequent to the signal node 101. The output of the inverter circuit 103 serves as pull-up data DATAu and the output of the inverter circuit 102 serves as pull-down data DATAd. The pull-up data DATAu and the pull-down data DATAd are supplied to the driving circuit 23. The drive circuit 23 is a circuit that drives the output buffer 24. As shown in fig. 7, the output buffer 24 includes a switching transistor 130, an output transistor 131, and an output transistor 132 connected in series. The switching transistor 130 is an N-channel MOS transistor having a thickened gate dielectric film, and a reset signal/SCr is supplied to its gate electrode. The reset signal/SCr becomes high level at the time of the read operation. The output transistors 131 and 132 are N-channel MOS transistors and have their gate electrodes driven by the drive circuit 23.

Fig. 8 is a circuit block of the drive circuit 23 and the output buffer 24 corresponding to one data terminal 12. As shown in fig. 8, the pull-up data DATAu is supplied to the pull-up circuit 71 and the pre-emphasis circuit 73. At the time of the pull-up operation, that is, when the high-level read data DQ is to be output from the data terminal 12, the pull-up circuit 71 is activated. The pull-up circuit 71 has three speed selectors 41H to 43H belonging to the high-speed path, and three speed selectors 41L to 43L belonging to the low-speed path, as shown in fig. 9. To select whether the high speed path or the low speed path is to be used by the speed mode signal Hs input to the drive circuit 40. When the high speed path is selected, one or two or more of the speed selectors 41H to 43H are selected based on the driver strength selection signal. When the low speed path is selected, one or two or more of the speed selectors 41L to 43L are selected based on the driver strength selection signal. The driver sizes of the speed selectors 41H to 43H may be different from each other. Similarly, the driver sizes of the speed selectors 41L to 43L may be different from each other. Speed selectors 41H, 42H, 43H, 41L, 42L, and 43L have pull-up drive circuits 411H to 414H, 421H to 424H, 431H to 434H, 411L to 414L, 421L to 424L, and 431L to 434L, respectively. These pull-up drive circuits 411H 414H, 421H to 424H, 431H to 434H, 411L to 414L, 421L to 424L, and 431L to 434L are the following circuits: the circuit equally selectively drives the adjusting MOS transistors respectively included in the plurality of output stage circuits having equal impedance so as to correct the impedance of each of the output stage circuits to a desired value based on the impedance selection signal ZQ. The number of output stage circuits manipulated by the speed selectors 41H/L to 43H/L is different from each other. For example, circuit 41H/L handles three output stage circuits, circuit 42H/L handles two output stage circuits, and circuit 43H/L handles one output stage circuit. In this case, the pull-up driving circuits 411H to 414H or 411L to 414L in the circuit 41H/L each drive an adjustment MOS transistor corresponding to three output stage circuits, the pull-up driving circuits 421H to 424H or 421L to 424L in the circuit 42H/L each drive an adjustment MOS transistor corresponding to two output stage circuits, and the pull-up driving circuits 431H to 434H or 431L to 434L in the circuit 43H/L each drive an adjustment MOS transistor corresponding to one output stage circuit. Thus, the output impedance at the time of the pull-up operation can be selected with an accurate impedance at the desired driver strength. The speed mode signal Hs and the slew rate selection signal SR are also commonly supplied to the pull-up driving circuit.

The pull-down data DATAd is supplied to the pull-down circuit 72 and the pre-emphasis circuit 74. At the time of the pull-down operation, that is, when the low-level read data DQ is to be output from the data terminal 12, the pull-down circuit 72 is activated. When a non-target on-die termination (ODT) operation is performed, the driving circuit 59 included in the pull-down circuit 72 is activated. As shown in fig. 10, the pull-down circuit 72 has three speed selectors 51H to 53H belonging to the high-speed path, and three speed selectors 51L to 53L belonging to the low-speed path. Fig. 10 also shows driver circuit 59 performing non-targeted ODT operations. The speed mode signal Hs input to the drive circuit 50 selects whether the high speed path or the low speed path is to be used. When the high speed path is selected, one or two or more of the speed selectors 51H to 53H are selected based on the driver strength selection signal. When the low speed path is selected, one or two or more of the speed selectors 51L to 53L are selected based on the driver strength selection signal. The driver sizes of the speed selectors 51H to 53H may be different from each other. Similarly, the driver sizes of the speed selectors 51L to 53L may be different from each other. The speed selectors 51H, 52H, 53H, 51L, 52L, and 53L have pull-down driving circuits 511H to 514H, 521H to 524H, 531H to 534H, 511L to 514L, 521L to 524L, and 531L to 534L, respectively. These pull-down driving circuits 511H to 514H, 521H to 524H, 531H to 534H, 511L to 514L, 521L to 524L, and 531L to 534L are the following circuits: the circuit equally selectively drives the adjusting MOS transistors respectively included in the plurality of output stage circuits having equal impedance so as to correct the impedance of each of the output stage circuits to a desired value based on the impedance selection signal ZQ. The number of output stage circuits manipulated by the speed selectors 51H/L to 53H/L is different from each other. For example, circuit 51H/L handles three output stage circuits, circuit 52H/L handles two output stage circuits, and circuit 53H/L handles one output stage circuit. In this case, the pull-down driving circuits 511H to 514H or 511L to 514L in the circuit 51H/L each drive an adjustment MOS transistor corresponding to three output stage circuits, the pull-down driving circuits 521H to 524H or 521L to 524L in the circuit 52H/L each drive an adjustment MOS transistor corresponding to two output stage circuits, and the pull-down driving circuits 531H to 534H or 531L to 534L in the circuit 53H/L each drive an adjustment MOS transistor corresponding to one output stage circuit. Thus, the output impedance at the pull-down operation time can be selected with an accurate impedance at the desired driver strength. The speed mode signal Hs and the slew rate selection signal SR are also commonly supplied to the pull-down driving circuit.

The pull-down circuit 72 includes a drive circuit 59 that performs a non-targeted ODT operation. The driving circuit 59 is constituted by parts of the speed selectors 51H/L to 53H/L and the pull-down driving circuits 511H/L to 514H/L, 521H/L to 524H/L, and 531H/L to 534H/L, and is activated regardless of the speed mode signal Hs when the non-target ODT operation is performed. Which of the speed selectors 51H/L through 53H/L is to be activated at the time of the non-target ODT operation is selected by a driver strength selection signal DSnt dedicated to the non-target ODT operation. The impedances of the pull-down driving circuits 511H/L to 514H/L, 521H/L to 524H/L, and 531H/L to 534H/L at the time of the non-target ODT operation are specified by the impedance selection signal ZQ.

The pre-emphasis circuits 73 and 74 provide a function of compensating for skin resistance loss or dielectric loss occurring at a high frequency operation time by temporarily lowering the output resistance only during a period in which data transition occurs. Accordingly, data may transition at an appropriate slew rate also at times of high frequency operation, and the data terminal 12 may be driven with a set resistance in a steady state.

When the read data DQ transitions to a high level, the pre-emphasis circuit 73 is activated to steepen the rising edge of the read data DQ. As shown in fig. 11, the pre-emphasis circuit 73 has a one-shot pulse generation circuit 45, speed selectors 44H and 46 belonging to a high-speed path, and a speed selector 44L belonging to a low-speed path. The speed selector 44H controls the three pull-up drive circuits 441H to 443H and the speed selector 44L controls the three pull-up drive circuits 441L to 443L.

When the read data DQ transitions to the low level, the pre-emphasis circuit 74 is activated to steepen the falling edge of the read data DQ. As shown in fig. 12, the pre-emphasis circuit 74 has the one-shot pulse generation circuit 55, the speed selectors 54H and 56 belonging to the high-speed path, and the speed selector 54L belonging to the low-speed path. The speed selector 54H controls the three pull-up driving circuits 541H to 543H and the speed selector 54L controls the three pull-up driving circuits 541L to 543L.

Fig. 13 is a circuit diagram of the speed selector. Each of the speed selectors includes a NAND gate 140 and a NOR gate 150. The NAND gate circuit 140 is based on the pull-up data DATAu or the pull-down data DATAd and the control signal ctrl¹And ctrl²Generating the data signal DATAp. High-speed transistors having a reduced threshold voltage are used as the transistors 141 to 145 constituting the NAND gate circuit 140. The NOR gate circuit 150 is based on the pull-up data DATAu or the pull-down data DATAd and the control signal ctrl³To ctrl⁵Generating a data signal DATAn. High-speed transistors having a lowered threshold voltage are also used as the transistors 151 to 156 constituting the NOR gate circuit 150. Control signal ctrl¹To ctrl⁵Is a speed mode signal, a timing signal, a non-targeted ODT enable signal, or a signal obtained by a logical combination of these signals.

Fig. 14 is a circuit diagram of a pull-up driver or a pull-down driver. The pull-up driver or the pull-down driver is a tri-state buffer having transistors 161 to 166 connected in series, and outputs a driving signal DRV from a connection point between the transistor 163 and the transistor 164. The data signal DATAp is supplied to the gate electrode of the transistor 163, and the data signal DATAn is supplied to the gate electrode of the transistor 164. The transistors 161 and 166 are transistors for activating the relevant pull-up driver or pull-down driver, and a control signal ctrl obtained by logical combination of the speed pattern signal and the timing signal⁶To the gate electrode thereof. The transistors 161 and 166 may be high voltage transistors with thickened gate dielectric films. When the transistors 161 and 166 are turned off, the relevant pull-up driver or pull-down driver is deactivated and its output node becomes a high impedance state. The transistor 162 is formed by connecting a plurality of transistors 162 in parallel₀To 162₂The transistor 165 is composed of a plurality of transistors 165 connected in parallel₀To 165₂And (4) forming. The inverted signals of the bits SR0 to SR2 (e.g.,/SR 0 to/SR 2) constituting the slew rate code signal SR are supplied to the transistors 162 respectively₀To 162₂A gate electrode of (1). The bits SR0 to SR2 constituting the slew rate code signal SR are supplied to the transistor 165, respectively₀To 165₂A gate electrode of (1). The slew rate code signal SR may contain impedance code information.

With this configuration, one of the transistors 131 and 132 constituting the output buffer 24 is turned on based on the pull-up data DATAu and the pull-down data DATAd, and the read data DQ of high level or low level is output from the data terminal 12 at the time of the read operation. On the other hand, at the time of the write operation, the write data DQ input to the data terminal 12 is supplied to the input buffer 25. The input buffer 25 converts the serial write data DQ into parallel four-bit write data DQ based on the write clock signals W0 to W3. The timing of the parallel four-bit write data DQ is adjusted by the timing adjustment circuit 26. Thereafter, the parallel four-bit write data DQ is additionally converted into parallel 16-bit write data DQ by the write clock synchronizing circuit 27 and output to the read/write bus 16 via the write data output circuit 28.

Fig. 15 is a layout diagram of the drive circuit 23. As shown in fig. 15, the speed selectors 41H to 44H and 41L to 44L and the pull-up drive circuits 411H to 414H, 421H to 424H, 431H to 434H, 441H to 444H, 411L to 414L, 421L to 424L, 431L to 434L, and 441L to 444L are collectively arranged as an array in the region 400, and the speed selectors 51H to 54H and 51L to 54L and the pull-down drive circuits 511H to 514H, 521H to 524H, 531H to 534H, 541H to 544H, 511L to 514L, 521L to 524L, 531L to 534L, and 544L to 444L are collectively arranged as an array in the region 500. Among the transistors constituting the pull-up drive circuit, the transistors 161 and 166 shown in fig. 14 are commonly arranged in the region 600 and are not arranged in the region 400. Similarly, among the transistors constituting the pull-down driving circuit, the transistors 161 and 166 shown in fig. 14 are commonly arranged in the region 700 and are not arranged in the region 500. The regions 600, 400, 500, and 700 are arranged in this order along the x-direction. Region 600 includes regions 601 and 602 arranged in the x-direction. Some of the transistors 161 and 166 constituting the pull-up drive circuit are arranged in common in the region 601 and the other of the transistors 161 and 166 constituting the pull-up drive circuit are arranged in common in the region 602. Similarly, region 700 includes regions 701 and 702 arranged along the x-direction. Some of the transistors 161 and 166 constituting the pull-down driving circuit are arranged in common in the region 701 and the other of the transistors 161 and 166 constituting the pull-down driving circuit are arranged in common in the region 702.

Symbols 411H/L to 414H/L, 421H/L to 424H/L, 431H/L to 434H/L, and 441H/L to 444H/L shown in FIG. 15 denote areas in which the driving circuits shown in FIGS. 9 and 11 are located. The driver circuit included in the high-speed path and the driver circuit included in the low-speed path are arranged adjacently in the x direction. For example, the driving circuit 411L and the driving circuit 411H are adjacently arranged in the x direction. The outputs of these drive circuits are used to control a common output transistor (not shown). The driver circuit 421H included in the high-speed path is located on the opposite side of the driver circuit 411L with respect to the driver circuit 411H. The drive circuit with the larger size is located closer to region 600. Similarly, symbols 511H/L to 514H/L, 521H/L to 524H/L, 531H/L to 534H/L, and 541H/L to 544H/L shown in FIG. 15 denote regions in which the driving circuits shown in FIGS. 10 and 12 are located. The driver circuit included in the high-speed path and the driver circuit included in the low-speed path are arranged adjacently in the x direction. For example, the driver circuit 511L and the driver circuit 511H are adjacently arranged in the x direction. The driver circuit 521H included in the high-speed path is located on the opposite side of the driver circuit 511L from the driver circuit 511H. The drive circuits with larger sizes are located closer to region 700. The layout of the circuits arranged in the regions 400 and 600 and the layout of the circuits arranged in the regions 500 and 700 are symmetrical with respect to a straight line Ly extending in the y direction. The speed selectors 41H/L to 44H/L and the speed selectors 51H/L to 54H/L are also symmetrically arranged with respect to the straight line Ly.

As shown in fig. 16, the driver circuits 411H/L to 414H/L, 421H/L to 424H/L, 431H/L to 434H/L, and 441H/L to 444H/L arranged in the region 400 are connected to the transistors 161 and 166 arranged in the region 600 via the power supply line 800 extending in the x direction. Similarly, the driver circuits 511H/L to 514H/L, 521H/L to 524H/L, 531H/L to 534H/L, and 541H/L to 544H/L arranged in the region 500 are connected to the transistors 161 and 166 arranged in the region 700 via the power supply line 800 extending in the x direction. In this way, according to the present invention, the transistors 161 and 166 serving as power switches are commonly arranged in the regions 600 and 700, and the other transistors are commonly arranged in the regions 400 and 500 sandwiched by the regions 600 and 700. If the transistors serving as the switches are dispersedly arranged in the corresponding driving circuits, the sizes of the driving circuits increase in at least one of the x-direction and the y-direction and the paths of the data signal lines are correspondingly elongated. With the layout of the transistors arranged in common as described above, the path of the data signal line is shortened, which contributes to high-speed operation of the circuit.

Fig. 17 is a diagram illustrating the layout of the region 520 shown in fig. 15 in more detail. As shown in fig. 17, a block 521 including drive circuits 521H and 521L, a block 522 including drive circuits 522H and 522L, a block 523 including drive circuits 523H and 523L, and a block 524 including drive circuits 524H and 524L are arranged in the region 520. These blocks 521 to 524 are arranged in the y direction. Region 520 has a region 520P in which P-channel MOS transistors 162 and 163 shown in fig. 14 are arranged, and a region 520N in which N-channel MOS transistors 164 and 165 shown in fig. 14 are arranged. The region 520P is shared by the driver circuits 521H to 524H and the driver circuits 521L to 524L. The data signal INH is input to the driver circuits 521H to 524H via the signal lines 801P and 801N extending along the boundary between the region 520P and the region 520N in the y direction, and the data signal INL is input to the driver circuits 521L to 524L via the signal lines 802P and 802N extending along the boundary between the region 520P and the region 520N in the y direction. Therefore, the signal lines 801P and 801N cross the power supply line 803 that supplies a power supply potential to the P-channel MOS transistors 162 and 163 located in the region 520P, and cross the power supply line 804 that supplies a power supply potential to the N-channel MOS transistors 164 and 165 of the driver circuits 521H to 524H located in the region 520N. Meanwhile, the signal lines 802P and 802N do not cross the power supply line 803 but cross the power supply line 804.

Although the present invention has been disclosed in the context of certain preferred embodiments and examples, it will be understood by those skilled in the art that the present invention extends beyond the specifically disclosed embodiments to other alternative embodiments and/or uses of the invention and obvious modifications and equivalents thereof. In addition, other modifications within the scope of the invention will be apparent to those skilled in the art based upon this disclosure. It is also contemplated that various combinations or sub-combinations of the specific features and aspects of the embodiments may be made and still fall within the scope of the invention. It should be understood that various features and aspects of the disclosed embodiments can be combined with, or substituted for, one another in order to form varying modes of the invention. Thus, it is intended that the scope of at least some of the inventions disclosed herein should not be limited by the particular disclosed embodiments described above.