阅读说明：本技术 低电感组件 (Low inductance assembly ) 是由 迈克尔·W·柯克 玛丽安·贝罗里尼 于 2020-04-17 设计创作，主要内容包括：一种低电感组件可以包括多层单片设备,该多层单片设备包括第一有源终端、第二有源终端、至少一个接地终端和一对电容器,该对电容器串联连接在第一有源终端与第二有源终端之间。引线可以与第一有源终端、第二有源终端和/或至少一个接地终端耦合。引线可以具有各自的长度和最大宽度。引线的长度与各自的最大宽度之比可小于约20。(A low inductance component may include a multilayer monolithic device including a first active terminal, a second active terminal, at least one ground terminal, and a pair of capacitors connected in series between the first active terminal and the second active terminal. The leads may be coupled with the first active terminal, the second active terminal, and/or the at least one ground terminal. The leads may have respective lengths and maximum widths. The ratio of the length of the leads to the respective maximum width may be less than about 20.)

1. A low inductance assembly, comprising:

a multilayer monolithic device comprising a first active terminal, a second active terminal, at least one ground terminal, and a pair of capacitors connected in series between the first active terminal and the second active terminal; and

at least one lead coupled with at least one of the first active terminal, the second active terminal, or the at least one ground terminal, wherein the at least one lead has a length and a maximum width, and wherein a ratio of the length to the maximum width of the at least one lead is less than about 20.

2. The low inductance assembly of claim 1, wherein the at least one lead has an approximately rectangular cross-section with a maximum width in a first direction and a minimum width in a second direction perpendicular to the first direction.

3. The low inductance assembly of claim 2, wherein a ratio of the maximum width to the minimum width is greater than about 2.

4. The low inductance element according to claim 1, wherein the at least one lead includes a first active lead, a second active lead, and at least one ground lead connected to the first active terminal, the second active terminal, and the at least one ground terminal, respectively.

5. The low inductance assembly as claimed in claim 1, further comprising a discrete varistor comprising first and second external varistor terminals, and wherein the at least one lead comprises a first lead coupled with each of the first active terminal and the first external varistor terminal.

6. The low inductance assembly of claim 1, wherein the at least one lead comprises a plurality of braided elongate conductive members.

7. The assembly of claim 1, wherein the multi-layer monolithic device further comprises:

a body comprising a plurality of dielectric layers;

a first plurality of electrode layers disposed within the body and connected to the first active terminal;

a second plurality of electrode layers disposed within the body and connected to the second active terminal; and

a third plurality of electrode layers connected with the at least one ground terminal and capacitively coupled with each of the first and second plurality of electrode layers to form the first capacitor between the first and third plurality of electrode layers and the second capacitor between the second and third plurality of electrode layers.

8. The assembly of claim 7, wherein the third plurality of electrode layers is generally cross-shaped.

9. The assembly of claim 7, wherein the at least one ground terminal comprises a first ground terminal and a second ground terminal.

10. The assembly of claim 9, wherein each of the third plurality of electrode layers includes a pair of opposing edges, one of the opposing edges connected with the first ground terminal and the other of the opposing edges connected with the second ground terminal.

11. The assembly of claim 9, wherein the first ground terminal is positioned opposite the second ground terminal.

12. The assembly of claim 1, wherein the first capacitor has a first capacitance and the second capacitor has a second capacitance approximately equal to the first capacitance.

13. The assembly of claim 1, wherein at least one of the first capacitance or the second capacitance is in a range from about 10nF to about 3 μ Ρ.

14. The assembly of claim 1, wherein,

the third plurality of electrode layers overlaps the first plurality of electrode layers along a first overlap region; and

the third plurality of electrode layers overlaps the second plurality of electrode layers along a second overlap region that is approximately equal to the first overlap region.

15. The assembly of claim 1, wherein the discrete varistor is stacked relative to the multilayer monolithic device.

16. The assembly of claim 1, further comprising an overmold layer encapsulating the discrete varistor and the multilayer monolithic device.

17. The assembly of claim 1, wherein a ratio of a thickness of the electrode stack to a thickness of the monolithic body is greater than about 0.4.

18. The assembly of claim 1, further comprising a fourth plurality of electrodes connected with the first external terminal and a fifth plurality of electrodes connected with the second external terminal and interleaved with the fourth plurality of electrodes to form a third capacitor.

19. A method for forming a low inductance component, the method comprising:

providing a multilayer monolithic device body including electrodes forming a pair of capacitors;

forming a first active terminal, a second active terminal, and at least one ground terminal outside the multilayer monolithic device body such that the pair of capacitors are connected in series between the first active terminal and the second active terminal; and

coupling at least one lead with at least one of the first active terminal, the second active terminal, or the at least one ground terminal, wherein the at least one lead has a length and a maximum width, and wherein the length to width ratio of the at least one lead is less than about 20.

Background

For some time, the design of various electronic components has been driven by a general industry trend toward miniaturization and increased functionality. Multilayer ceramic devices (such as multilayer ceramic capacitors or varistors) are sometimes constructed from multiple dielectric electrode layers. During the manufacturing process, the layers may be pressed and formed into a vertically stacked structure. The multilayer ceramic device may include a single capacitor or a plurality of capacitors. Such devices may be provided with lead wires for connection with other electrical components. However, the lead wires exhibit a self-inductance that undesirably increases the overall inductance of the assembly.

Disclosure of Invention

According to one embodiment of the present invention, a low inductance component may include a multilayer monolithic device including a first active terminal, a second active terminal, at least one ground terminal, and a pair of capacitors connected in series between the first active terminal and the second active terminal. The leads may be coupled with the first active terminal, the second active terminal, and/or the at least one ground terminal. The leads may have respective lengths and maximum widths. The ratio of the length of the leads to the respective maximum width may be less than about 20.

According to another embodiment of the present invention, a method for forming a low inductance component may include providing a multi-layer monolithic device body including electrodes forming a pair of capacitors; forming a first active terminal, a second active terminal, and at least one ground terminal outside the multilayer monolithic device body such that the pair of capacitors are connected in series between the first active terminal and the second active terminal; and connecting at least one lead with at least one of the first active terminal, the second active terminal, or the at least one ground terminal, wherein the at least one lead has a length and a maximum width, and wherein a ratio of the length to the width of the at least one lead is less than about 20.

Other features and aspects of the present invention are discussed in more detail below.

Drawings

A full and enabling disclosure of the subject matter disclosed herein, including the best mode thereof, directed to one of ordinary skill in the art, is set forth in the specification, which makes reference to the appended figures, in which:

fig. 1A illustrates an external perspective view of an exemplary embodiment of a low inductance assembly including leads according to the presently disclosed subject matter;

fig. 1B illustrates another embodiment of a lead of the device of fig. 1A, in accordance with aspects of the present disclosure;

fig. 2 illustrates an external perspective view of another embodiment of a low inductance component including a discrete varistor (discrete varistor) in accordance with the presently disclosed subject matter;

fig. 3A and 3B illustrate a first electrode layer and a second electrode layer, respectively, of the assembly of fig. 1A in accordance with aspects of the presently disclosed subject matter;

FIG. 3C illustrates an electrode stack including the first electrode layer of FIG. 3A and the second electrode layer of FIG. 3B;

FIG. 3D illustrates a schematic diagram of the apparatus of FIG. 1A;

FIG. 3E illustrates a schematic diagram of the apparatus of FIG. 2;

fig. 4A and 4B illustrate a first electrode layer and a second electrode layer, respectively, of an electrode configuration of another embodiment of a low inductance component in accordance with aspects of the present disclosure;

FIG. 4C illustrates an electrode stack including the first electrode layer of FIG. 4A and the second electrode layer of FIG. 4B;

fig. 5A illustrates an additional electrode configuration including an additional capacitor compared to the electrode configuration described above with reference to fig. 3A-4C;

fig. 5B illustrates another additional electrode configuration including an additional capacitor compared to the electrode configuration described above with reference to fig. 3A-4C;

FIG. 6A illustrates a schematic diagram of the apparatus of FIG. 5A;

FIG. 6B illustrates a schematic diagram of the apparatus of FIG. 5B; and

fig. 7 is a flow chart of a method for forming a low inductance component according to the presently disclosed subject matter.

Repeat use of reference characters throughout the present specification and appended drawings is intended to represent same or analogous features, elements, or steps thereof.

Detailed Description

Reference now will be made in detail to various embodiments of the invention, one or more examples of which are set forth below. Each embodiment is provided by way of explanation of the invention, not limitation of the invention. In fact, it will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the scope or spirit of the invention. For instance, features illustrated or described as part of one embodiment, can be used on another embodiment to yield a still further embodiment. Thus, it is intended that the present invention cover the modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents.

Generally, the present invention relates to a low inductance assembly. The low inductance component may include one or more capacitors. Without being limited by theory, a capacitor is an electrical component that stores electrical energy in an electric field. In some embodiments, the assembly may also include a discrete varistor connected to one or more capacitors. Without being limited by theory, a varistor is an electrical component that has a resistance that varies with applied voltage, making the electrical component a voltage-dependent resistor.

The assembly may include one or more leads configured to exhibit a low inductance. Low inductance may be highly desirable in certain applications. For example, aspects of the present disclosure may be particularly useful in automotive applications, such as motor start stop applications.

The low inductance lead may be coupled to the first active terminal, the second active terminal, and/or the ground terminal of the component. The leads may have respective lengths and maximum widths. The ratio of the length of the leads to the respective maximum width may be less than about 50, in some embodiments less than about 30, in some embodiments less than about 20, in some embodiments less than about 15, in some embodiments less than about 10, in some embodiments less than about 8, in some embodiments less than about 5, in some embodiments less than about 4, and in some embodiments less than about 2.

The leads may have various suitable cross-sectional shapes. For example, one or more of the leads may have an approximately rectangular cross-section. The approximately rectangular cross-section may have a maximum width in a first direction and a minimum width in a second direction perpendicular to the first direction. The ratio of the maximum width to the minimum width may be greater than about 2, in some embodiments greater than about 3, in some embodiments greater than about 4, in some embodiments greater than about 5, in some embodiments greater than about 8, in some embodiments greater than about 10, in some embodiments greater than about 20, in some embodiments greater than about 50, and in some embodiments greater than about 100. However, in other embodiments, the leads may have a cross-sectional shape that is circular, oval, polygonal, or any other suitable shape.

In some embodiments, one or more of the leads may include a plurality of elongate conductive members braided (woven), braided (braided), or otherwise arranged together to form the lead.

The above features may result in a low inductance component, which may include one or more capacitors. For example, the first and second capacitors may be arranged in a split feed type configuration (split feed type configuration) with respect to the first active terminal, the second active terminal, and the at least one ground terminal. The first capacitor and the second capacitor may be formed by internal electrodes separated by a dielectric layer.

In some embodiments, discrete varistors may be coupled to a multilayer monolithic device to form a low inductance integrated component having both capacitor and varistor functionality. The discrete varistor may include a first external varistor terminal connected with the first active terminal of the multilayer capacitor and a second external varistor terminal connected with the second active terminal of the multilayer capacitor. For example, discrete varistors and multilayer capacitors may be stacked to form a single monolithic assembly. The combination of capacitors and varistors may provide low inductance filtering, and EMI and/or EMI/ESD circuit protection in a single package (single package), which may be particularly useful when space is limited. Furthermore, integrating the capacitor and varistor functionality in a single component provides reduced inductance compared to two separate components that would each present their own respective parasitic inductance (e.g., parasitic inductance caused by the respective leads).

In some embodiments, the leads may be connected with external terminals and/or the assembly may be overmolded (over-mold). Thus, the overmold may encapsulate the discrete varistor and the multilayer monolithic capacitor device. The overmold may protect the assembly from damage such as impact or moisture.

As described above, the first and second capacitors may be arranged in a split feed type configuration. For example, a first plurality of electrode layers may be disposed within the body and connected with the first active terminal. A second plurality of electrode layers may be disposed within the body and connected with the second active terminal. The third plurality of electrode layers may be connected with a ground terminal and capacitively coupled with each of the first and second plurality of electrode layers (e.g., in a separate feed-through arrangement). The first capacitor may be formed at a first overlap region between the first plurality of electrode layers and the third plurality of electrode layers. The second capacitor may be formed at a second overlap region between the second plurality of electrode layers and the third plurality of electrode layers.

In one embodiment, the first capacitor may have a first capacitance and the second capacitor may have a second capacitance. In some embodiments, the first overlap region and the second overlap region may be approximately equal such that the second capacitance may be approximately equal to the first capacitance. However, in other embodiments, the first and second overlap regions may be different such that the first capacitance may be greater than or less than the second capacitance.

For example, at least one of the second capacitance and the first capacitance may be in a range from about 10nF to about 3 μ F, in some embodiments from about 200nF to about 2 μ F, and in some embodiments, from about 400nF to about 1.5 μ F. The second capacitance may be in the range of about 5% to about 500%, in some embodiments in the range of about 10% to about 300%, in some embodiments in the range of about 25% to about 200%, and in some embodiments in the range of about 50% to about 150% of the first capacitance.

In some embodiments, the third plurality of electrode layers may be generally cross-shaped and may be connected to a pair of opposing ground terminals. For example, the third plurality of electrode layers may each include a pair of opposing edges. One of the opposing edges may be connected with a first ground terminal, and the other of the opposing edges may be connected with a second ground terminal.

The multilayer monolithic capacitor device may not form any additional capacitors within the monolithic body. For example, the first, second, and third pluralities of electrodes may be arranged in an electrode stack that extends through a majority of the thickness of the monolithic body. For example, the ratio of the thickness of the electrode stack to the thickness of the monolithic body may be in the range of from about 0.5 to about 0.97, in some embodiments from about 0.6 to about 0.95, and in some embodiments, from about 0.7 to about 0.9.

In general, the dielectric layers of a multilayer monolithic device can be made of any material commonly employed in the art. For example, the dielectric layer may be made of a ceramic material including titanate as a main component. Titanates may include, but are not limited to, barium titanate (BaTiO)₃). The ceramic material may further contain an oxide of a rare earth metal and/or a compound of an acceptor type element(s) such as Mn, V, Cr, Mo, Fe, Ni, Cu, Co, etc. The titanate may further contain MgO, CaO, Mn₃O₄、Y₂O₃、V₂O₅、ZnO、ZrO₂、Nb₂O₅、Cr₂O₃、Fe₂O₃、P₂O₅、SrO、Na₂O、K₂O、Li₂O、SiO₂、WO₃And the like. The ceramic material may include other additives, organic solvents, plasticizers, binders, dispersants, etc., in addition to the ceramic powder.

In general, the internal electrodes of the multilayer monolithic device may be made of any material commonly employed in the art. For example, the internal electrodes may be formed by sintering a conductive paste, the main component of which is a noble metal material. These materials may include, but are not limited to, palladium-silver alloys, nickel and copper. For example, in one embodiment, the electrodes may be made of nickel or a nickel alloy. The alloy may contain one or more of Mn, Cr, Co, Al, W, etc., and the content of Ni in the alloy is preferably 95 wt% or more. The Ni or Ni alloy may contain various minor components such as P, C, Nb, Fe, Cl, B, Li, Na, K, F, S, etc. in an amount of 0.1% by weight or less.

The ceramic body of the multilayer monolithic device may be formed using any method known in the art. For example, the ceramic body may be formed by forming a laminated body having ceramic sheets and patterned internal electrodes alternately stacked, removing an adhesive from the laminated body, sintering the adhesive-removed laminated body in a non-oxidizing atmosphere at a high temperature of 1200 ℃ to 1300 ℃, and re-oxidizing the sintered laminated body in an oxidizing atmosphere.

Generally, a varistor may be configured to divert a surge to ground. For example, the clamping voltage of the varistor may be in the range of from about 3 volts to about 150 volts, in some embodiments from about 5 volts to about 100 volts, in some embodiments from about 10 volts to about 50 volts, and in some embodiments, from about 15 volts to about 30 volts.

The varistor may comprise a ceramic body with external electrodes. The ceramic body is manufactured by sintering a laminated body formed of alternately stacked ceramic layers and internal electrodes. Each pair of adjacent internal electrodes face each other with a ceramic layer therebetween, and may be electrically coupled to different external electrodes, respectively.

In general, the dielectric layer may comprise any suitable dielectric material, such as barium titanate, zinc oxide, or any other suitable dielectric material. Various additives may be included in the dielectric material, for example, additives that create or enhance the voltage-dependent resistance of the dielectric material. For example, in some embodiments, the additive may include an oxide of cobalt, bismuth, manganese, or a combination thereof. In some embodiments, the additive may include an oxide of gallium, aluminum, antimony, chromium, boron, titanium, lead, barium, nickel, vanadium, tin, or combinations thereof. The dielectric material may be doped with an additive in a range from about 0.5 mole percent to about 3 mole percent, and in some embodiments, in a range from about 1 mole percent to about 2 mole percent. The average grain size of the dielectric material may contribute to the nonlinear properties of the dielectric material. In some embodiments, the average grain size may be in a range from about 10 microns to 100 microns, and in some embodiments, from about 20 microns to 80 microns. The varistor may further comprise two terminals and each electrode may be connected to a respective terminal. The electrodes may provide resistance along the length of the electrodes and/or at the connection between the electrodes and the terminals.

In general, the inner electrode may be made of any material commonly used in the art. For example, the internal electrodes may be formed by sintering a conductive paste, the main component of which is a noble metal material. These materials may include, but are not limited to, palladium-silver alloys, silver, nickel, and copper. For example, in one embodiment, the electrodes may be made of nickel or a nickel alloy. The alloy may contain one or more of Mn, Cr, Co, Al, W, etc., and the content of Ni in the alloy is preferably 95 wt% or more. The Ni or Ni alloy may contain various minor components such as P, C, Nb, Fe, Cl, B, Li, Na, K, F, S, etc. in an amount of 0.1% by weight or less.

The components may have a variety of sizes. For example, the housing size of the assembly ranges from EIA0504 or smaller to EIA2920 or larger. Example housing dimensions include 0805, 1206, 1806, 2020, and the like.

Example embodiments will now be discussed with reference to the accompanying drawings. Fig. 1A illustrates an external perspective view of an exemplary embodiment of a low inductance assembly 100 generally in accordance with the presently disclosed subject matter. As shown, the assembly 100 may include a body 102, such as a six-sided body. Component 100 may include a first active terminal 104, a second active terminal 106, a first ground terminal 108, and a second ground terminal 110.

The first and second active leads 112, 114 may be connected with the first and second active terminals 104, 106, respectively. The first and second ground leads 116, 118 may be connected with the first and second ground terminals 108, 110, respectively.

One or more of the leads 112, 114, 116, 118 may have a length and a maximum width. The ratio of the length to the maximum width of the at least one lead may be less than about 20. For example, the first active lead 112 may have a length 120 in the Z-direction 122, a maximum width 124 in the X-direction 126, and a minimum width 127 in the Y-direction 128. The ratio of the maximum width 124 to the minimum width 127 may be greater than about 2. The first active lead 112 may have an approximately rectangular cross-sectional shape, for example, the first active lead 112 may be generally flat or ribbon-shaped. In some implementations, the ratio of the length to the maximum width of one or more of the leads 112, 114, 116, 118 can be less than about 20. In some embodiments, each lead may have a respective length and width, with a respective ratio of the respective length to the width being less than about 20.

Fig. 1B illustrates another embodiment of a lead 132 according to aspects of the present disclosure. The lead 132 may have a substantially circular or oval cross-sectional shape. The leads 132 may have a maximum width 134 and a minimum width 136. In other embodiments, the lead may include a plurality of elongate braided conductive members.

Fig. 2 illustrates an external perspective view of another embodiment of an assembly 200 according to the presently disclosed subject matter. The assembly 200 may include a multilayer monolithic device 201 that may include a body 202 (such as a six-sided body), a first active terminal 204, a second active terminal 206, a first ground terminal 208, and a second ground terminal 210, e.g., as described above with reference to fig. 1A.

The assembly 200 may include a discrete varistor 240 having a first external varistor terminal 242 and a second external varistor terminal 244. The assembly 200 may include a first active lead 246 coupled with each of the first active terminal 204, and the first external varistor terminal 242 of the multilayer monolithic capacitor device 201. The assembly 200 may include a second active lead 248 coupled with each of the second active terminal 206, and the second external varistor terminal 244 of the multi-layer monolithic capacitor device 201.

One or more of the leads 246, 248, 250, 251 can have a length and a maximum width, e.g., as described above with reference to fig. 1A. The ratio of the length to the maximum width of one or more of the leads 246, 248, 250, 251 may be less than about 20. For example, referring to fig. 2, the first active lead 248 may have a length 252 in the Z-direction 122, a maximum width 254 in the X-direction 126, and a minimum width 256 in the Y-direction 128. The ratio of the maximum width 254 to the minimum width 256 may be greater than about 2. The first active lead 248 may have an approximately rectangular cross-sectional shape. For example, the first active lead 248 may be generally flat (e.g., ribbon-shaped). In some embodiments, each of the leads 246, 248, 250, 251, respectively, may have a width that is at least 20 times greater than a respective maximum width of the leads 246, 248, 250, 251.

The low inductance component 100 of fig. 1A and/or the multilayer, monolithic capacitor device 201 of fig. 2 may include two capacitors formed in series between a first terminal and a second terminal, e.g., as described herein. As understood by one of ordinary skill in the art with respect to all embodiments described herein, the cooperating layers in the subject multilayer configuration comprise electrode layers that in turn form an integrated capacitive structure.

Fig. 3A illustrates the first electrode layer 320. The first electrode layer 320 will be described with reference to the assembly 100 of fig. 1A. However, it should be understood that the multilayer monolithic capacitor device 201 of fig. 2 may be similarly configured. The first electrode layer 320 may include a cross-shaped electrode 322 having a pair of opposing edges 324, 326 connected to the first and second ground terminals 108, 110, respectively, of the assembly 100 of fig. 1A. Fig. 3B illustrates a second electrode layer 328, the second electrode layer 328 including a first electrode 330 connected to the first active terminal 104 (fig. 1A) and a second electrode 332 connected to the second active terminal 106 (fig. 1A). Fig. 3C illustrates a stack of alternating first electrode layers 320 and second electrode layers 328.

Fig. 3D illustrates a schematic diagram 300 of the device 100 of fig. 1A. The device 100 may be arranged for a single device solution containing both series and parallel capacitors. The device 100 may include a first capacitor 338 and a second capacitor 340. Referring again to fig. 3A and 3B, a first capacitor 338 may be formed between the cross-shaped electrode 322 and the first electrode 330 at the first overlap region 334. A second capacitor 356 may be formed between the cross-shaped electrode 322 and the second electrode 332 at the second overlapping area 336. The first overlap region 334 may be approximately equal to the second overlap region 336 such that the first capacitor and the second capacitor exhibit approximately equal capacitances. However, in other embodiments, the first overlap region 334 may be greater than or less than the second overlap region 336, such that the first capacitance may be greater than or less than the second capacitance. One or both of the first and second capacitances may range from about 10nF to about 3 μ F.

The first active lead 112 may be connected with a first capacitor 338 (e.g., via the first active terminal 104 shown in fig. 1). The second active lead 114 may be connected (e.g., via the second active terminal 106 shown in fig. 1) with a second capacitor 340. The first and second ground leads 116, 118 may be connected at a location between the first and second capacitors 338, 340 in a split feed-through configuration. For example, the first ground lead 116 and the second ground lead 118 may be connected with the ground terminals 180, 110 (fig. 1A), respectively.

Fig. 3E illustrates a schematic diagram 350 of the device 200 of fig. 2. The varistor 352 may be electrically connected between the active lead 112 and the active lead 114.

Fig. 4A and 4B illustrate electrode configurations of another embodiment of a multilayer capacitor according to aspects of the present disclosure. Referring to fig. 4A, the first electrode layer 420 may include a cross-shaped electrode 222 having a pair of opposing edges 424, 426 that may be connected with the first and second ground terminals 108, 110 (fig. 1A), respectively. Fig. 4B illustrates a second electrode layer 428 comprising a first electrode 430 connected to the first active terminal 104 and a second electrode 432 connected to the second active terminal 106. Fig. 4C illustrates a stack of alternating first electrode layers 420 and second electrode layers 428. Referring again to fig. 4A, the cross-shaped electrode 422 may overlap the first electrode 430 along a first overlap region 434 to form a first capacitor 438, and may overlap the second electrode 432 along a second overlap region 436 to form a second capacitor 440.

Fig. 5A and 5B illustrate respective additional electrode configurations including additional capacitors as compared to the electrode configurations described above with reference to fig. 3A to 4C. The electrode configuration of fig. 5A and 5B will be described with reference to the assembly 100 of fig. 1A. However, it should be understood that the multilayer monolithic capacitor device 201 of fig. 2 may be similarly configured. Referring to fig. 5A, the first electrode configuration 500 may include a first region 501 and a second region 508. The first region may include a cross-shaped electrode 502, a first electrode 504, and a second electrode 506, for example as described above with reference to fig. 3A-3C.

The second region 508 may include a third capacitor formed by a plurality of third electrodes 510 interleaved with a plurality of fourth electrodes 512. The third electrode 510 may be connected to the first active terminal 104 (fig. 1A), and the fourth electrode 512 may be connected to the second active terminal 106 (fig. 1A).

Fig. 5B illustrates a second electrode configuration 550 including a first region 552, a second region 554, and a third region 556. First region 552 may include an electrode stack including one or more cruciform electrodes 558, one or more first electrodes 560, and one or more second electrodes 562, e.g., as described above with reference to fig. 3A-3C.

The second region 554 may include a plurality of third electrodes 564 interleaved with a plurality of fourth electrodes 566. The third electrode 564 may be connected with the first active terminal 104 (fig. 1A) and the fourth electrode 556 may be connected with the second active terminal 106 (fig. 1A).

The third region may comprise an electrode stack comprising a cross-shaped electrode 568, a first electrode 570 and a second electrode 572, for example as described above with reference to fig. 3A to 3C.

Fig. 6A illustrates a schematic diagram 600 of the device 500 of fig. 5A. More specifically, the device 500 may include active leads 602, 603. The first capacitor 604 and the second capacitor 606 may be formed in the first region 607, for example as described above with reference to fig. 5A. A ground lead 610 may be connected at a location between the first capacitor 604 and the second capacitor 606 (e.g., to the cross-shaped electrode 502 described above with reference to fig. 5A). A third capacitor 608 may be electrically connected between the active leads 602, 603 and in parallel with the first capacitor 604 and the second capacitor 606 in the second region 609, e.g., as described above with reference to fig. 5A.

Fig. 6B illustrates a schematic 650 of the device 550 of fig. 5B. The device 550 may be generally configured similarly to the device 500 of fig. 5A. Further, a varistor 660 may be connected between the active lead 648 and the active lead 652 and in parallel with the capacitors 654, 656, 658.

Fig. 7 is a flow diagram of a method 700 for forming a low inductance component. In general, the method 700 will be described herein with reference to the assemblies 100, 200 of fig. 1A and 2. However, it should be understood that the disclosed method 700 may be implemented with any suitable components. Moreover, although fig. 7 depicts steps performed in a particular order for purposes of illustration and discussion, the methods discussed herein are not limited to any particular order or arrangement. Using the disclosure provided herein, those of skill in the art will understand that various steps of the methods disclosed herein may be omitted, rearranged, combined, and/or adapted in various ways without departing from the scope of the present disclosure.

Method 700 may include, at (702), providing a multilayer capacitor body including electrodes forming a pair of capacitors, e.g., as described above with reference to fig. 1A-6B.

Method 700 may include, at (704), forming a first active terminal, a second active terminal, and at least one ground terminal outside of a multilayer capacitor body such that the pair of capacitors are connected in series between the first active terminal and the second active terminal, e.g., as described above with reference to fig. 1A-6B.

The method 700 may include, at (706), connecting at least one lead with at least one of the first active terminal, the second active terminal, or the at least one ground terminal. The leads may have respective lengths and maximum widths. The ratio of the length of at least one lead (if more than one lead is present) to the respective width may be less than about 20.

It should be understood that the individual steps of implementing the disclosed configurations are intended only as representatives of the present disclosure, and do not represent required uses beyond other aspects of the general nature of the present disclosure, otherwise indicated. For example, one of ordinary skill in the art will recognize that selected steps may be implemented to produce a particular design selected for a given application of the presently disclosed subject matter.

While the presently disclosed subject matter has been described in detail with respect to specific embodiments thereof, it will be appreciated that those skilled in the art, upon attaining an understanding of the foregoing may readily produce alterations to, variations of, and equivalents to such embodiments. Accordingly, the scope of the present disclosure is by way of example rather than by way of limitation, and the subject disclosure does not preclude inclusion of such modifications, variations and/or additions to the presently disclosed subject matter as would be readily apparent to one of ordinary skill in the art.