阅读说明：本技术 用于目标刷新操作的交错时序的设备及方法 (Apparatus and method for staggered timing of targeted refresh operations ) 是由 N·J·迈尔 J·S·雷赫迈耶 于 2020-04-03 设计创作，主要内容包括：本公开的实施例涉及用于交错目标刷新操作的时序的设备及方法。一种存储器装置可包含数个存储体,其中的至少若干者可同时进入到刷新模式中。给定存储体可执行自动刷新操作或可比所述自动刷新操作汲取更少功率的目标刷新操作。所述目标刷新操作的所述时序可在所述刷新存储体之间交错,使得所述刷新存储体的一部分执行目标刷新操作,同时所述刷新存储体的一部分执行自动刷新操作。(Embodiments of the present disclosure relate to apparatus and methods for interleaving the timing of target refresh operations. A memory device may include a number of banks, at least some of which may be simultaneously entered into a refresh mode. A given bank may perform an auto-refresh operation or a targeted refresh operation that may draw less power than the auto-refresh operation. The timing of the targeted refresh operations may be staggered among the refresh banks such that a portion of the refresh banks perform targeted refresh operations while a portion of the refresh banks perform auto-refresh operations.)

1. An apparatus, comprising:

a first group of memory cells comprising a plurality of word lines;

a first refresh control circuit configured to provide a first refresh address associated with a first number of the plurality of word lines of the first set of memory cells in response to a refresh signal;

a second group of memory cells comprising a plurality of word lines; and

a second refresh control circuit configured to provide a second refresh address associated with a second number of the plurality of word lines of the second set of memory cells in response to the refresh signal, wherein the first number is different from the second number.

2. The apparatus of claim 1, wherein the first set of memory cells comprises a first bank and the second set of memory cells comprises a second bank.

3. The apparatus of claim 1, further comprising:

a first row control circuit configured to refresh the first number of the plurality of word lines of the first set of memory cells associated with the first refresh address; and

a second row control circuit configured to refresh the second number of the plurality of word lines of the second set of memory cells associated with the second refresh address.

4. The apparatus of claim 3, wherein the first refresh address comprises a target refresh address and the second refresh address comprises an auto-refresh address.

5. The apparatus of claim 1, wherein the first refresh control circuit provides the first refresh address while the second refresh control circuit provides the second refresh address.

6. The apparatus of claim 1, wherein in response to the refresh signal, the first and second refresh control circuits are configured to provide multiple activations of respective pump signals, and wherein the first and second refresh addresses are provided in response to a particular activation of the respective pump signals.

7. The apparatus of claim 6, wherein in response to different activations of the respective pump signals, the first refresh control circuit is configured to provide a third refresh address associated with the second number of the plurality of word lines of the first set of memory cells and the second refresh control circuit is configured to provide a fourth refresh address associated with the first number of the plurality of word lines of the second set of memory cells.

8. An apparatus, comprising:

a first bank configured to perform a first type of refresh operation and configured to perform a second type of refresh operation at a first time; and

a second bank configured to perform the first type of refresh operation and configured to perform the second type of refresh operation at a second time different from the first time.

9. The apparatus of claim 8, wherein the first and second banks are configured to perform a number of refresh operations in response to refresh signals, and wherein a portion of the refresh operations are the first type of refresh operation and remaining refresh operations are the second type of refresh operation.

10. The apparatus of claim 9, wherein the first and second banks are each configured to determine a number of refresh operations of the first type to be performed and are each configured to perform the determined number of refresh operations of the first type.

11. The apparatus of claim 8, wherein the first type of refresh operation comprises an auto-refresh operation and the second type of refresh operation comprises a target operation.

12. The apparatus of claim 8, wherein the first bank begins performing the first type of refresh operation again after performing the second type of refresh operation.

13. The apparatus of claim 8, wherein the first and second banks are configured to perform the first and second types of refresh operations in a time sequential manner based on an occurrence of a refresh signal.

14. An apparatus, comprising:

a plurality of banks each configured to refresh one or more word lines associated with a refresh address;

a plurality of refresh control circuits, each of the plurality of refresh control circuits associated with one of the plurality of memory banks, each of the plurality of refresh control circuits configured to cause the associated memory bank to perform a first type of refresh operation or a second type of refresh operation, wherein at least one of the plurality of memory banks performs the first type of refresh operation while at least another one of the plurality of memory banks performs the second type of refresh operation.

15. The apparatus of claim 14, wherein the first type of refresh operation is associated with a first number of word lines, and wherein the second type of refresh operation is associated with a second number of word lines greater than the first number.

16. The apparatus of claim 15, wherein the first type of refresh operation comprises a target refresh operation, and wherein the second type of refresh operation comprises an auto-refresh operation.

17. The apparatus of claim 14, wherein the plurality of refresh control circuits collectively receive a refresh signal and provide at least one refresh address in response to the refresh signal, wherein the at least one refresh address is a first type of refresh address associated with the first type of refresh operation or a second type of refresh address associated with the second type of refresh operation.

18. The apparatus of claim 17, wherein each of the plurality of refresh control circuits generates a number of activations of a pump signal in response to the refresh signal and provides a refresh address in response to each activation of the pump signal.

19. The apparatus of claim 17, wherein, in response to the refresh signal, a portion of the plurality of refresh control circuits provide the first type of refresh address and a remainder of the plurality of refresh control circuits provide the second type of refresh address.

20. The apparatus of claim 14, wherein the plurality of memory banks is a subset of a number of memory banks in a memory device.

Background

Information may be stored on individual memory cells of a memory as physical signals (e.g., charges on capacitive elements). The memory may be volatile memory and the physical signals may decay over time (which may degrade or destroy information stored in the memory cells). The information in the memory cells needs to be periodically refreshed by, for example, rewriting the information to restore the physical signal to an initial value.

As the size of memory components decreases, the density of memory cells increases dramatically. An auto-refresh operation may be implemented when a sequence of memory cells is periodically refreshed. Repeated accesses to a particular memory cell or group of memory cells, commonly referred to as a 'row hammer', can cause the rate of data degradation in adjacent memory cells to be accelerated. It is desirable to identify and refresh memory cells affected by the row hammer in both targeted and auto-refresh operations. The targeted refresh operations may occur at a timing that is interspersed between the auto-refresh operations.

Disclosure of Invention

In at least one aspect, the present disclosure relates to an apparatus comprising: a first group of memory cells including a plurality of word lines; a first refresh control circuit; a second group of memory cells including a plurality of word lines; and a second refresh control circuit. The first refresh control circuit provides a first refresh address associated with a first number of the plurality of word lines of the first group of memory cells in response to a refresh signal. The second refresh control circuit provides a second refresh address associated with a second number of the plurality of word lines of the second group of memory cells in response to the refresh signal, wherein the first number is different from the second number.

The first set of memory cells may include a first bank and the second set of memory cells may include a second bank. The apparatus may also include: a first row control circuit that can refresh the first number of the plurality of word lines of the first group of memory cells associated with the first refresh address; a second row control circuit that can refresh the second number of the plurality of word lines of the second group of memory cells associated with the second refresh address. The first refresh address may include a target refresh address and the second refresh address may include an auto-refresh address.

The first refresh control circuit may provide the first refresh address while the second refresh control circuit provides the second refresh address. In response to the refresh signals, the first and second refresh control circuits may provide multiple activations of respective pump signals, and the first and second refresh addresses may be provided in response to particular activations of the respective pump signals. In response to different activations of the respective pump signals, the first refresh control circuit can provide a third refresh address associated with the second number of the plurality of word lines of the first group of memory cells, and the second refresh control circuit can provide a fourth refresh address associated with the first number of the plurality of word lines of the second group of memory cells.

In at least one aspect, the present disclosure is directed to an apparatus including a first bank and a second bank. The first bank performs a first type of refresh operation and a second type of refresh operation at a first time. The second bank performs the first type of refresh operation and the second type of refresh operation at a second time different from the first time.

The first and second banks may perform a number of refresh operations in response to refresh signals, and a portion of the refresh operations may be the first type of refresh operation while the remaining refresh operations may be the second type of refresh operation. The first and second banks may each determine a number of refresh operations of the first type to be performed and may each perform the determined number of refresh operations of the first type.

The first type of refresh operation may include an auto-refresh operation, and the second type of refresh operation may include a target operation. After performing the second type of refresh operation, the first bank may begin performing the first type of refresh operation again. The first and second banks are configured to perform the first and second types of refresh operations in a time sequential manner based on an occurrence of a refresh signal.

In at least one aspect, the present disclosure relates to an apparatus comprising: a plurality of banks, each of which can refresh one or more word lines associated with a refresh address; and a plurality of refresh control circuits. Each of the plurality of refresh control circuits is associated with one of the plurality of memory banks. Each of the plurality of refresh control circuits causes the associated bank to perform a first type of refresh operation or a second type of refresh operation, wherein at least one of the plurality of banks performs the first type of refresh operation while at least another one of the plurality of banks performs the second type of refresh operation.

The first type of refresh operation can be associated with a first number of word lines, and the second type of refresh operation can be associated with a second number of word lines greater than the first number. The first type of refresh operation may include a target refresh operation, and the second type of refresh operation may include an auto-refresh operation.

The plurality of refresh control circuits may collectively receive a refresh signal and provide at least one refresh address in response to the refresh signal. The at least one refresh address may be a first type of refresh address associated with the first type of refresh operation or a second type of refresh address associated with the second type of refresh operation. In response to the refresh signal, each of the plurality of refresh control circuits may generate a number of activations of a pump signal and provide a refresh address in response to each activation of the pump signal. In response to the refresh signal, a portion of the plurality of refresh control circuits may provide the first type of refresh address while the remaining of the plurality of refresh control circuits provide the second type of refresh address. The plurality of memory banks may be a subset of a number of memory banks in the memory device.

Drawings

Fig. 1 is a block diagram of a semiconductor device according to an embodiment of the present disclosure.

FIG. 2 is a block diagram of a memory array according to an embodiment of the present disclosure.

Fig. 3 is a timing diagram of a refresh operation in a memory device according to an embodiment of the present disclosure.

FIG. 4 is a block diagram of a refresh control circuit according to an embodiment of the present disclosure.

Fig. 5 is a block diagram of a row decoder according to an embodiment of the present disclosure.

Detailed Description

The following description of specific embodiments is merely exemplary in nature and is in no way intended to limit the scope of the disclosure, its application, or uses. In the following detailed description of embodiments of the present systems and methods, reference is made to the accompanying drawings that form a part hereof, and in which is shown by way of illustration specific embodiments in which the described systems and methods may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the presently disclosed systems and methods, and it is to be understood that other embodiments may be utilized and that structural and logical changes may be made without departing from the spirit and scope of the present disclosure. Furthermore, for the purpose of clarity, detailed descriptions of specific features that are apparent to those of ordinary skill in the art are not discussed so as not to obscure the description of the embodiments of the present disclosure. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present disclosure is defined only by the appended claims.

A memory device may include a plurality of memory cells. Memory cells may store information (e.g., as one or more bits) and may be organized at intersections of word lines (rows) and bit lines (columns). A number of word lines and bit lines may be organized into banks. The memory device may include a number of different banks. The memory device may receive one or more command signals that may indicate operations in one or more banks of one or more memory packages. The memory device may enter a refresh mode in which word lines in one or more banks are refreshed.

The information in the memory cells may decay over time. The memory cells may be refreshed row by row to preserve information in the memory cells. During a refresh operation, information in one or more rows may be rewritten back to the respective row to restore the initial value of the information. The refresh signal may control the timing of the refresh operation. In response to the refresh signal, the memory bank is capable of performing more than one type of refresh operation. The first type of refresh operation may refresh fewer rows simultaneously than the second type of refresh operation. Thus, a first type of refresh operation may draw more power than a second type. It may be important to control the amount of power used during refresh operations and to reduce the amount of peak power drawn.

The present disclosure relates to apparatus, systems, and methods for interleaving the timing of refresh operations. A bank of the device may perform one or more refresh operations that are synchronized by activating a refresh signal. Each bank may receive a refresh address indicating one or more word lines of the bank, and then the word lines may be refreshed. Some banks may receive refresh addresses indicating a second type of refresh operation at different times from each other. In this way, some banks may perform a first type of refresh operation while one or more banks perform a second type of refresh operation. This may reduce the peak power drawn during refresh operations on the memory device.

Fig. 1 is a block diagram of a semiconductor device according to at least one embodiment of the present disclosure. The semiconductor device 100 may be a semiconductor memory device, such as a DRAM device integrated on a single semiconductor chip.

The semiconductor device 100 includes a memory array 112. In some embodiments, memory array 112 may include multiple banks. Each bank includes a plurality of word lines WL, a plurality of bit lines BL and/BL, and a plurality of memory cells MC arranged at intersections of the plurality of word lines WL and the plurality of bit lines BL and/BL. Selection of the word line WL is performed by a row control 108, and selection of the bit lines BL and/BL may be performed by a column control 110. In some embodiments, there may be a row control 108 and a column control 110 for each of the banks.

Bit lines BL and/BL are coupled to respective Sense Amplifiers (SAMP) 117. Data read from bit line BL or/BL is amplified by sense amplifier SAMP 117 and transferred to read/write amplifier 120 through complementary local data line (LIOT/B), Transfer Gate (TG)118, and complementary main data line (MIO). Conversely, the write data output from the read/write amplifier 120 is transferred to the sense amplifier 117 through the complementary main data line MIO, the transfer gate 118, and the complementary local data line LIOT/B, and is written in the memory cell MC coupled to the bit line BL or/BL.

The semiconductor device 100 may employ a plurality of external terminals including a command and address (C/a) terminal coupled to a command and address bus to receive commands and addresses, a clock terminal for receiving clocks CK and/CK, a data terminal DQ for providing data, and a power supply terminal for receiving power supply potentials VDD, VSS, VDDQ, and VSSQ.

The clock terminal is supplied with the external clocks CK and/CK supplied to the clock input circuit 122. The external clocks may be complementary. The clock input circuit 122 generates the internal clock ICLK based on the CK and/CK clocks. The ICLK clock is provided to the command control 106 and the internal clock generator 124. The internal clock generator 124 provides various internal clocks LCLK based on the ICLK clock. The LCLK clock may be used for timing operations of various internal circuits. The internal data clock LCLK is provided to the input/output circuitry 126 to clock the operation of the circuitry included in the input/output circuitry 126, such as to a data receiver to clock the reception of write data.

The C/a terminal may be supplied with a memory address. The memory address supplied to the C/a terminal is transmitted to the address decoder 104 via the command/address input circuit 102. The address decoder 104 receives the address and supplies a decoded row address XADD to a row control 108 and a decoded column address YADD to a column control 110. The address decoder 104 may also supply a decoded bank address BADD, which may indicate a bank of the memory array 118 that contains a decoded row address XADD and a column address YADD. The C/a terminal may be supplied with a command. Examples of commands include timing commands for controlling the timing of various operations, access commands for accessing the memory, such as read commands for performing read operations and write commands for performing write operations, and other commands and operations. An access command may be associated with one or more row addresses XADD, column addresses YADD, and bank addresses BADD to indicate a memory cell to be accessed.

Commands may be provided as internal command signals to command control 106 via command/address input circuitry 102. Command control 106 includes circuitry for decoding internal command signals to generate various internal signals and commands for performing operations. For example, command control 106 may provide a row command signal for selecting a word line and a column command signal for selecting a bit line.

The device 100 may receive an access command which is a row activate command ACT. When receiving a row activate command ACT, the bank address BADD and the row address XADD are timely supplied with the row activate command ACT.

The device 100 may receive an access command that is a read command. When a read command is received, a bank address and a column address are supplied in time with the read command, reading read data from memory cells in the memory array 112 corresponding to the row address and the column address. The read command is received by command control 106, and command control 106 provides internal commands such that data read from memory array 112 is provided to read/write amplifiers 120. The read data is output from the data terminal DQ to the outside via the input/output circuit 126.

Device 100 may receive an access command that is a write command. When a write command is received, a bank address and a column address are supplied with the write command in time, and write data supplied to the data terminal DQ is written to memory cells in the memory array 112 corresponding to the row address and the column address. The write command is received by command control 106, and command control 106 provides internal commands to cause the write data to be received by a data receiver in input/output circuit 126. The write clock may also be provided to an external clock terminal for clocking receipt of write data by a data receiver of the input/output circuit 126. Write data is supplied to the read/write amplifiers 120 via the input/output circuits 126 and is supplied by the read/write amplifiers 120 to the memory array 112 for writing into the memory cells MC.

The device 100 may also receive commands that cause it to perform refresh operations. The refresh signal AREF may be a pulse signal that is activated when the command control 106 receives a signal indicating a refresh mode. In some embodiments, the refresh command may be issued externally to the memory device 100. In some embodiments, the refresh command may be generated periodically by a component of the device. In some embodiments, the refresh signal AREF may also be activated when the external signal indicates a refresh entry command. The refresh signal AREF may be activated once immediately after a command input, and may thereafter be cycled according to the desired internal timing. Thus, the refresh operation may automatically continue. The self-refresh exit command may cause the automatic activation of the refresh signal AREF to stop and return to the IDLE state.

The refresh signal AREF is supplied to the refresh control circuit 116. There may be a refresh control circuit 116 associated with each bank. The refresh control circuit 116 can collectively receive a refresh signal AREF, and can generate and provide one or more refresh row addresses RXADD to perform one or more refresh operations in an associated bank. In some embodiments, a subset of the memory banks may be given a refresh command. For example, the one or more additional signals may indicate which refresh control circuits 116 should provide refresh addresses in response to AREFs. In another example, AREF may only be provided to the refresh control circuit 116 associated with the subset of memory banks being refreshed.

Focusing on the operation of a given refresh control circuit, the refresh control circuit 116 supplies a refresh row address RXADD to the row control 108, and the row control 108 can refresh one or more word lines WL indicated by the refresh row address RXADD. The refresh control circuit 116 may control the timing of the refresh operation based on the refresh signal AREF. In some embodiments, in response to an AREF activation, the refresh control circuit 116 can generate one or more activations of the pump signal and can generate and provide a refresh address RXADD for each activation (e.g., each pump) of the pump signal.

Because the various refresh control circuits are commonly coupled to the AREFs, multiple banks of the device 100 may perform refresh operations simultaneously. Each refresh control circuit 116 may be controlled to change the details of the refresh address RXADD (e.g., how the refresh address is calculated, the timing of the refresh address), or may be based on internal logic operations. The refresh control circuit 116 can direct the associated bank to perform different types of refresh operations based on the provided refresh address RXADD.

One type of refresh operation may be an auto-refresh operation. In response to an auto-refresh operation, a bank may refresh a group of rows of memory, and then a next group of rows of the bank may be refreshed in response to a next auto-refresh operation. The refresh control circuit 116 can provide a refresh address RXADD indicating a group of word lines in the bank. The refresh control circuit 116 may generate a sequence of refresh addresses RXADD such that over time an auto-refresh operation may cycle through all word lines WL of a bank. The timing of the refresh operations may be such that each word line is refreshed at a frequency based on the normal data degradation rate in the memory cell.

Another type of refresh operation may be a targeted refresh operation. Repeated accesses to a particular row of memory (e.g., an aggressor row) can cause the decay rate in an adjacent row (e.g., a victim row) to increase due to, for example, electromagnetic coupling between the rows. In some embodiments, the victim row may include a row that is physically adjacent to the aggressor row. In some embodiments, the victim row may include rows further away from the aggressor row. The information in the victim row may decay at a rate such that data is lost if it is not refreshed prior to the next auto-refresh operation of the row. To prevent information loss, it is desirable to identify aggressor rows and then implement a targeted refresh operation in which the refresh address RXADD associated with one or more associated victim rows is refreshed.

An auto-refresh operation may draw more power than a targeted refresh operation because more rows in a given bank may be refreshed simultaneously during the auto-refresh operation than during the targeted refresh operation. Different refresh control circuits 116 may provide the refresh address RXADD such that different banks interleave the target refresh and auto-refresh operations in time. For example, a portion of the banks performing the refresh operation may perform the targeted refresh operation while the remaining ones of the banks performing the refresh operation may perform the auto-refresh operation. In some embodiments, interleaving of targeted refresh and auto-refresh operations may be accomplished by having particular banks perform targeted refresh operations while other banks perform auto-refresh operations in response to a given occurrence of AREF.

In some embodiments, the refresh control circuit 116 may perform multiple refresh operations in response to each occurrence of AREF. Each refresh control circuit 116 may generate a number of 'pumps' (e.g., activations of pump signals) in response to receiving AREF activations. Each pump, in turn, can cause the refresh control circuit 116 to provide a refresh address RXADD and trigger a refresh operation indicated by the refresh address RXADD. A given refresh control circuit 116 may provide an auto-refresh address in response to some pumps and a target refresh address in response to some pumps resulting from a given activation of AREF. In some embodiments, targeted refresh operations may be interleaved between banks by controlling which pumps are associated with auto-refresh operations and which pumps are associated with targeted refresh operations between different banks.

Interleaving target and auto-refresh operations among the banks may help control the power drawn by the banks during refresh operations. The amount of power drawn by the refresh operation may depend on the number of word lines being refreshed simultaneously. Interleaving the target refresh operations among the banks may, in some embodiments, maintain the total number of word lines that are simultaneously refreshed between a maximum value and a minimum value if all banks simultaneously performing the auto-refresh operation represents the maximum number of word lines that can be simultaneously refreshed and all banks simultaneously performing the target refresh operation represents the minimum number of word lines. This may both reduce the peak power drawn by the refresh operation (e.g., because less than the maximum number of word lines are refreshed) and may increase the minimum power drawn during the refresh operation (because more than the minimum number of word lines are refreshed).

The power supply terminals are supplied with power supply potentials VDD and VSS. The power supply potentials VDD and VSS are supplied to the internal voltage generator circuit 128. The internal voltage generator circuit 128 generates various internal potentials VPP, VOD, VARY, VPERI, and the like based on the power supply potentials VDD and VSS supplied to the power supply terminals. Internal potential VPP is primarily used in row control 108, internal potentials VOD and VARY are primarily used in sense amplifier SAMP included in memory array 112, and internal potential VPERI is used in many peripheral circuit blocks.

The power supply terminal is also supplied with power supply potentials VDDQ and VSSQ. The power supply potentials VDDQ and VSSQ are supplied to the input/output circuit 126. In the embodiments of the present disclosure, the power supply potentials VDDQ and VSSQ supplied to the power supply terminals may be the same potential as the power supply potentials VDD and VSS supplied to the power supply terminals. In another embodiment of the present disclosure, the power supply potentials VDDQ and VSSQ supplied to the power supply terminals may be potentials different from the power supply potentials VDD and VSS supplied to the power supply terminals. The power supply potentials VDDQ and VSSQ supplied to the power supply terminal are used for the input/output circuit 126 so that the power supply noise generated by the input/output circuit 126 is not propagated to other circuit blocks.

FIG. 2 is a block diagram of a memory array according to an embodiment of the present disclosure. In some embodiments, memory array 200 may implement memory array 112 of FIG. 1. The memory array 200 includes a number of memory banks 232 arranged in a bank group 230. The memory groups may be physically separated from each other by a peripheral region 234 of the memory device. Although the example memory device 200 of FIG. 2 includes four groups 230 each having four banks 232 (and thus includes a total of sixteen banks 232), it should be understood that other embodiments may have more or fewer banks 232, which may be organized into more or fewer memory groups 230. These banks 232 and/or bank groups 230 may or may not be located in physical proximity to each other.

Each bank 232 includes a number of word lines and bit lines with a number of memory cells arranged at intersections. In some embodiments, the rows (word lines) and columns (bit lines) may be further organized within the memory banks 232. For example, each bank 232 may include a number of memory pads each containing a number of rows and columns. The pads may be organized into pad groups. In some embodiments, during an auto-refresh operation, an address may be provided that causes the word lines in a particular pad in each group in each bank 232 to refresh.

In some embodiments, the refresh command may be issued to all of the banks 232 in common, and all of the banks 232 may perform the refresh operation simultaneously. In some embodiments, a refresh command specifying a subset of the memory banks 232 may be issued. For example, a particular group (or groups) 230 of banks 232 may begin refreshing. In another example, a portion of the banks 232 in each group 230 (or subset of groups) may begin to refresh (e.g., the first bank 232 in each group 230). Once the refresh command has been issued to one or more banks 232, each of the indicated banks 232 may perform one or more refresh operations simultaneously. The timing of the target and auto-refresh operations may be staggered in the indicated bank such that a portion of the indicated bank performs the target refresh operation while a portion of the indicated bank performs the auto-refresh operation.

The banks being refreshed may have logic and/or programming that allows some of the banks 232 to perform auto-refresh operations while other banks perform targeted refresh operations. In some embodiments, the logic/programming may be inherent to the design of the memory device rather than based on settings programmed after assembly of the device.

Each of the banks 232 may be associated with a refresh control circuit (e.g., 116 of fig. 1) that may issue refresh addresses to the banks 232. Each refresh control circuit may receive an activation of an AREF and may use internal logic to determine whether a provided refresh address should indicate an auto-refresh operation or a target refresh operation. For example, each refresh control circuit may count the number of auto-refresh operations and perform a target refresh operation after performing a particular number of auto-refresh operations. Counters in different refresh control circuits may be initialized to different values, which may interleave target refresh operations across different banks.

Fig. 3 is a timing diagram of a refresh operation in a memory device according to an embodiment of the present disclosure. Timing diagram 300 shows refresh operations of various different banks over time (along the x-axis). The bank may be a bank described as part of memory array 112 of FIG. 1 or bank 232 of FIG. 2. Timing diagram 300 shows an example of how a target refresh operation can be interleaved between four different BANKs (BANK 0-BANK 3). Other modes of interleaving targeted refresh operations among more or fewer banks may be used in other examples.

Timing diagram 300 shows an example embodiment in which five refresh operations are performed in response to each activation of refresh signal AREF. In particular, in response to each activation of AREF, there may be five pumps (e.g., activation of a pump signal in each refresh control circuit), and each pump may be associated with an auto-refresh operation or a targeted refresh operation. The pumping is represented by vertical lines in the timing diagram 300. The pumps are in the group of 5 to indicate that five pumps are activated per AREF. Thus, there is activation of AREF for each group pump. The solid line represents the auto-refresh operation, and the dotted line represents the target refresh operation. As discussed herein, more word lines may be refreshed simultaneously in a bank during an auto-refresh operation than during a target refresh operation, and the auto-refresh operation may therefore draw more power than the target refresh operation.

A given bank may perform a refresh operation in response to each pump. Since the banks generate pumping in response to their commonly received refresh signal (e.g., AREF), the pumping can generally be synchronized. Thus, each bank may perform a first pump at the same time, then perform a second pump at the same time, and so on. Each bank may typically perform an auto-refresh operation in response to a pump, and then may perform several target refresh operations in response to several pumps, and then repeat the cycle. The target refresh operations may be interleaved between the banks such that a first bank may begin performing the target refresh operations at a first time and a second bank may begin performing the target refresh operations at a second time different from the first time. In some embodiments, each bank may operate on the same cycle of auto and target refresh operations (e.g., n auto refresh operations followed by m target refresh operations), and the only difference may be the phase of the cycle between different banks.

In the example embodiment of fig. 3, there may be 3 auto-refresh operations and 2 targeted refresh operations during a group of pumps for each bank (e.g., five pumps activated in response to each AREF). For example, the first BANK (BANK0) performs 3 auto-refresh operations in response to the first 3 pumps, and then performs two target refresh operations on pumps 3 and 4. BANK1 performs targeted refresh operations on pumps 3 and 4. BANK2 performs targeted refresh operations on pumps 2 and 3. BANK3 performs targeted refresh operations on pumps 1 and 2. It should be noted that in the example embodiment of FIG. 3, there is overlap such that the second BANK (e.g., BANK2) performs its first target refresh operation while the first BANK (e.g., BANK3) simultaneously performs its second target refresh operation.

As can be seen from the total number shown below the timing diagram 300, there may be 3 auto-refresh pumps and 1 target refresh pump during the first and fifth pumps in each group (e.g., first pump: corresponding auto-refresh pumps for BANK 0-2 and 1 target refresh pump for BANK 3; fifth pump: corresponding auto-refresh pumps for BANK 1-3 and 1 target refresh pump for BANK 0). During the second, third and fourth pumps in each group, 2 target refresh operations and 2 auto-refresh operations may be performed. Thus, in each simultaneous pumping across different banks, a portion of the banks may perform a targeted refresh operation while the remaining portion performs an auto-refresh operation. For example, there is no point where all four banks perform any type of refresh operation simultaneously.

The memory BANKs BANK 0-BANK 3 of fig. 3 are shown as having refresh cycles of the same length as the number of pumps generated in response to each AREF. In some embodiments, the refresh cycle may be longer or shorter than the number of pumps generated in response to each AREF. Similarly, the example embodiment of FIG. 3 shows that each group of pumps includes a mix of targeted and auto-refresh operations. In some embodiments, a bank may perform only one type of refresh operation in response to a given AREF.

In this embodiment, different types of refresh operations may be interleaved between different activations of AREF rather than between different pumps. For example, in response to a first activation of AREF, BANK0 may perform a number of pumps, one or more of which are used to perform a targeted refresh operation, while BANKs 1-3 may perform a number of pumps, each of which are used to perform an auto-refresh operation. Upon activation of AREF a second time, BANK1 may perform one or more target refresh operations, while BANK0 and BANKs 2-3 perform auto-refresh operations. On a third activation of AREF, BANK2 may perform one or more target refresh operations, while BANKs 0-1 and BANK3 may perform auto-refresh operations. Upon a fourth activation of AREF, BANK3 may perform one or more targeted refresh operations, while BANKs 0-2 perform auto-refresh operations.

FIG. 4 is a block diagram of a refresh control circuit according to an embodiment of the present disclosure. In some embodiments, the refresh control circuitry 416 may implement the refresh control circuitry 116 of FIG. 1. Specific internal components and signals of the refresh address control circuit 416 are shown to illustrate the operation of the refresh address control circuit 416. Dashed line 432 is shown to indicate that in a particular embodiment, each component (e.g., refresh address control circuit 416 and row decoder 408) may correspond to a particular bank of memory, and these components may be reused for each bank of memory. Thus, there may be multiple refresh address control circuits 416 and row decoders 408. For the sake of brevity, only the components of a single memory bank will be described.

The interface 431 may provide one or more signals to the address refresh control circuit 416 and the row decoder 408. The refresh address control circuit 416 may include a sampling timing generator 438, an address sampler 437, a Row Hammer Refresh (RHR) state controller 436, and a refresh address generator 439. The interface 431 may provide one or more control signals, such as an auto-refresh signal AREF and a row address XADD. The RHR state control 436 may determine whether an auto-refresh or a targeted refresh operation should be performed. The RHR state control circuit 436 may direct different refresh operations in different banks to interleave target and auto-refresh operations between banks. The RHR bank interleave circuitry 435 can control the RHR state control circuitry 436 to interleave targets and auto-refresh operations.

The refresh address control circuit 416 shows components associated with a particular implementation that detects aggressor addresses by sampling incoming values of the row address XADD in a random or semi-random timing. Other methods of detecting aggressor addresses may be used in other embodiments, and other components may be provided in the refresh address control circuit 416.

The address sampler 437 may sample (e.g., latch) the current row address XADD in response to activation of ArmSample. The address sampler 437 may also provide one or more of the latched addresses to the refresh address generator 439 as the matched address HitXADD. The RHR state controller 436 may provide a signal RHR to indicate that a row hammer refresh operation (e.g., a refresh of a victim row corresponding to an identified aggressor row) should occur. The RHR state controller 436 may also provide an internal refresh signal IREF to indicate that an auto-refresh operation should occur. The RHR state controller 436 may be used to control the timing of targeted refresh operations and auto-refresh operations. Activation of IREF and RHR may represent activation of the pump signal.

There may be an RHR state controller 436 for each of the different banks. Each RHR state controller 436 may include internal logic that determines the timing at which the RHR state controller 436 provides a signal (e.g., RHR) to indicate whether a targeted refresh or auto-refresh operation should be performed in the associated bank. In some embodiments, each RHR state controller 436 may include a counter and may provide the signal RHR based on the number of occurrences of the refresh signal AREF (and/or the number of occurrences of IREF). The counters in each RHR state controller 436 in each of the different banks may be initialized to different values to interleave refresh operations. Thus, each RHR state controller 436 may generate the same mode of targeted and auto-refresh operations, however, the modes may be out of phase with each other such that they are staggered in time.

In some embodiments, the RHR bank interleave circuitry 435 can provide signals to control interleaving to the RHR state control circuitry 436. For example, the RHR bank interleave circuitry 435 may provide a signal to each RHR state control circuit 436 associated with a different bank that may indicate when a targeted refresh operation should be performed. In some embodiments, there may be a single RHR bank interleave circuit 435 coupled to all refresh address control circuits 416 of different banks. The RHR bank interleave circuitry 435 may contain internal logic (e.g., a counter initialized to a different value) that allows it to direct interleaving between different banks.

In response to the RHR activation, the refresh address generator 439 may provide a refresh address RXADD, which may be an auto-refresh address or may be one or more victim addresses corresponding to a victim row corresponding to an aggressor row matching the address HitXADD. The row decoder 408 may perform a refresh operation in response to a refresh address RXADD and a row hammer refresh signal RHR. The row decoder 408 may perform an auto-refresh operation based on the refresh address RXADD and the internal refresh signal IREF.

In some embodiments, the refresh address control circuitry 416 may determine whether one or more targeted refresh operations are currently needed, and may provide a targeted refresh address when needed. The refresh address control circuits 416 associated with different banks may each determine a number of targeted refresh operations to be performed based on characteristics of accesses to the row address XADD, such as the number, frequency, and/or mode of accesses. For example, the first refresh address control circuitry 416 associated with a first bank containing a plurality of rows that are hammered may determine that more targeted refresh operations are required than the second refresh address control circuitry 416 associated with a second bank containing fewer rows that are hammered. In some embodiments, refresh operations may occur cyclically (e.g., a particular number of pumps and/or a particular number of AREFs occurring), and the refresh address control circuit 416 may determine a number of targeted refresh operations to perform in each cycle. The remainder of the refresh operations in the cycle may be used for auto-refresh operations or other scheduled operations. Although different banks may determine different numbers of targeted refresh operations to be performed, the targeted refresh operations may still be interleaved between different banks.

Interface 431 may represent one or more components of a component that provides signals to a bank. For example, the interface 431 may represent components such as the command address input circuit 102, the address decoder 104, and/or the command control 106 of FIG. 1. The interface 431 may provide a row address XADD, an auto-refresh signal AREF, an activation signal ACT, and a precharge signal Pre. The auto-refresh signal AREF may be a periodic signal that may indicate when an auto-refresh operation is to occur. An activation signal ACT may be provided to activate a given bank of the memory. The precharge signal Pre may be provided to precharge a given bank of the memory. The row address XADD may be a signal including multiple bits (which may be transmitted serially or in parallel) and may correspond to a particular row of an activated bank.

The sampling timing generator 438 provides a sampling signal ArmSample. ArmSample may alternate between a low logic level and a high logic level. The ArmSample activation may be a 'pulse' in which ArmSample is raised to a high logic level and then returned to a low logic level. The intervals between ArmSample pulses may be random, pseudorandom, and/or device based on one or more signals (e.g., AREF).

The address sampler 437 may receive a row address XADD from the interface 431 and an ArmSample from the sample timing generator 438. The row address XADD may change as the interface 431 directs access operations, such as read and write operations, to different rows of a memory cell array, such as the memory cell array 112 of fig. 1. Whenever the address sampler 437 receives an ArmSample activation (e.g., a pulse), the address sampler 437 can sample the current value of the XADD. In some embodiments, address sampler 532 may provide the current sample value of XADD as the matching address, HitXADD. The refresh address generator 439 can provide one or more victim addresses associated with the matching address HitXADD as the refresh address RXADD.

In some embodiments, in response to the ArmSample activation, address sampler 437 may determine whether one or more rows are aggressor rows based on the sampled row address XADD, and may provide the identified aggressor row as the matching address HitXADD. As part of this determination, the address sampler 437 can record the current value of XADD (e.g., by latching and/or storing in a register) in response to ArmSample activation. The current value of the XADD may be compared to previously recorded addresses in the address sampler 437 (e.g., addresses stored in latches/registers) to determine the access pattern of the sampled addresses over time. The ArmSample activation may also cause the address sampler 437 to provide the address of the aggressor row as the matching address HitXADD if the address sampler 437 determines that the current row address XADD is repeatedly accessed (e.g., is an aggressor row). In some embodiments, the matching address (e.g., aggressor address) HitXADD may be stored in a latch circuit for later retrieval by the refresh address generator 439. For example, the values of one or more matching addresses HitXADD may be stored until signal RHR indicates a targeted refresh operation.

The RHR state controller 436 may receive the auto-refresh signal AREF and provide a row hammer refresh signal RHR and an internal refresh signal IREF. The signal RHR may indicate that a target refresh operation should occur (e.g., one or more victim rows associated with the identified aggressor, HitXADD, should be refreshed). Signal IREF may indicate that an auto-refresh operation should occur. The RHR state controller 436 may provide the RHR signal using internal logic. In some embodiments, the RHR state controller 436 may include a counter and may provide the RHR signal based on a particular number of AREF activations (e.g., every fourth AREF activation). The counter may be initialized to a particular value (e.g., when the memory is powered on). The particular value may vary from refresh control circuit to refresh control circuit between memory banks.

The RHR state controller 436 may also provide an internal refresh signal IREF that may control the timing of refresh operations. In some embodiments, there may be multiple IREF activations per activation of the refresh signal AREF. In some embodiments, the internal refresh signal IREF may be used as a refresh pump signal to control refresh pump activation. In some embodiments, each activation of AREF may be associated with a number of activations of IREF, which may be associated with a number of refresh operations, which may be a mix of targeted and auto-refresh operations. For example, each activation of IREF may be associated with a refresh operation on the refresh address RXADD, while the state of RHR may determine whether the refresh address RXADD is associated with an auto-refresh operation or a target refresh operation. In some embodiments, signal REF may be used to indicate that an auto-refresh operation should occur, while signal RHR is used to indicate that a targeted refresh operation should occur. For example, signals RHR and IREF may be generated such that they are not active at the same time (e.g., both are not at a high logic level at the same time), and each activation of IREF may be associated with an auto-refresh operation while each activation of RHR may be associated with a target refresh operation.

In some embodiments, the RHR state controller 436 may count IREF activations and use the IREF (e.g., pump) counts to determine when the signal RHR should be provided. Similar to the previous description, the counter may be initialized to different values for different refresh control circuits. In some embodiments, the RHR state controller 436 may receive one or more signals from the RHR bank interleave circuitry 435 that may direct a different RHR state controller 436 to provide the signal RHR. In either of these ways, the targeted and auto-refresh operations may be interleaved between the banks.

The refresh address generator 439 may receive a row hammer refresh signal RHR and a matching address HitXADD. The matching address HitXADD may represent an aggressor row. The refresh address generator 439 can determine the location of one or more victim rows based on the matching address HitXADD and provide them as a refresh address RXAADD. In some embodiments, the victim row may include rows (e.g., HitXADD +1 and HitXADD-1) that are physically adjacent to the aggressor row. In some embodiments, the victim row may also include rows that are physically adjacent to the physically adjacent rows of the aggressor row (e.g., HitXADD +2 and HitXADD-2). Other relationships between the victim row and the identified aggressor row may be used in other examples.

The refresh address generator 439 may determine the value of the refresh address RXADD based on the row hammer refresh signal RHR. In some embodiments, the refresh address generator 439 may provide one of a sequence of auto-refresh addresses as the refresh address RXADD when the signal RHR is not active. When signal RHR is active, refresh address generator 439 may provide a target refresh address (e.g. a victim address) as refresh address RXADD.

The row decoder 408 may perform one or more operations on a memory array (not shown) based on received signals and addresses. For example, in response to the activation signal ACT and the row address XADD (and IREF and RHR at low logic levels), the row decoder 408 may direct one or more access operations (e.g., read operations) to the specified row address XADD. In response to the RHR signal being asserted, the row decoder 408 may refresh the refresh address RXADD.

Fig. 5 is a block diagram of a row decoder according to an embodiment of the present disclosure. In some embodiments of the present disclosure, the row decoder 500 may implement the row control 108 of fig. 1 and/or the row decoder 408 of fig. 4. The row decoder 500 can determine whether to activate a word line of a bank (e.g., a bank of the memory array 112 of fig. 1) corresponding to the row address XADD or the refresh address RXADD.

As shown in fig. 5, the row decoder 500 has a row activation timing generator 542 that receives an internal refresh signal IREF and a row hammer refresh signal RHR, an active signal ACT, and a precharge signal Pre and provides a state signal RefPD, a word line actuation signal wdEn, a sense amplifier actuation signal saEn, and a bit line equalization signal BLEQ. In some embodiments, signals IREF and RHR may be auto-refresh signals AREF. The state signal RefPD is supplied to a multiplexer 540, the multiplexer 540 selecting one of a row address XADD and a refresh address RXADD. The address XADDi selected by multiplexer 540 is supplied to row redundancy control circuit 544. If the word line indicated by the address XADDi is replaced by a redundant word line, a hit signal RedMatch is activated and a row address XADDd1 that is a replacement destination is generated. Addresses XADDi and XADDd1 are supplied to multiplexer 546; wherein if the hit signal RedMatch is not activated, then the address XADDi is selected; and if the hit signal RedMatch is activated, the address XADDd1 is selected. The selected address XADD2 is supplied to an X address decoder 548. The address decoder 548 controls the operation of the word line indicated by the address XADD2, the sense amplifier corresponding thereto, the equalizing circuit, and the like, based on the word line actuation signal wdEn, the sense amplifier actuation signal saEn, and the bit line equalizing signal BLEQ.

Of course, it should be understood that any of the examples, embodiments, or processes described herein may be combined with one or more other examples, embodiments, and/or processes, or may be separated and/or executed in separate devices or device portions, in accordance with the present systems, devices, and methods.

Finally, the above-discussion is intended to be merely illustrative of the present system and should not be construed as limiting the appended claims to any particular embodiment or group of embodiments. Thus, while the present system has been described in particular detail with reference to exemplary embodiments, it should also be appreciated that numerous modifications and alternative embodiments may be devised by those having ordinary skill in the art without departing from the broader and intended spirit and scope of the present system as set forth in the claims that follow. The specification and drawings are accordingly to be regarded in an illustrative manner and are not intended to limit the scope of the appended claims.