阅读说明：本技术 在读取一次性可编程存储器时提高性能的方法和装置 (Method and apparatus for improving performance when reading otp memory ) 是由 S·巴利苏布兰马尼安 S·W·斯普里格斯 G·B·贾米森 于 2020-02-14 设计创作，主要内容包括：本发明公开了在读取存储器时提高性能的方法、装置、系统和制品。示例方法包括：将感测电路(218)的输出(288)初始化为第一逻辑高值,从存储器(202或204)获得对应于存储在存储器(202或204)中的存储器位的第一电流(I-(BIT)),复制第一电流(I-(BIT)),确定复制的第一电流(I-(BIT))是否大于第二电流(I-(REF)),以及响应于确定复制的第一电流(I-(BIT))大于第二电流(I-(REF)),在感测电路(218)的输出(288)处生成第二逻辑高值。(Methods, apparatus, systems, and articles of manufacture to improve performance when reading memory are disclosed. An example method includes: initializing an output (288) of a sensing circuit (218) to a first logic high value, obtaining a first current (I) from a memory (202 or 204) corresponding to a memory bit stored in the memory (202 or 204) BIT ) Copying the first current (I) BIT ) Determining a first current (I) of the replica BIT ) Whether or not it is greater than the second current (I) REF ) To do so byAnd responsive to determining the replicated first current (I) BIT ) Greater than the second current (I) REF ) A second logic high value is generated at the output (288) of the sensing circuit (218).)

1. An apparatus, comprising:

a current mirror comprising a first terminal and a second terminal, the first terminal configured to be coupled to a memory;

a logic gate comprising an input terminal coupled to the second terminal of the current mirror;

a first transistor comprising a first current terminal and a second current terminal, the first current terminal of the first transistor being coupled to the input terminal of the logic gate, the second current terminal of the first transistor being coupled to a ground rail; and

a second transistor comprising a first current terminal and a second current terminal, the first current terminal of the second transistor configured to be coupled to a power supply rail, the second current terminal of the second transistor coupled to the input terminal of the logic gate.

2. The apparatus of claim 1, wherein the current mirror comprises: a third transistor comprising a first current terminal, a second current terminal, and a gate terminal, the first current terminal of the third transistor being coupled to the first terminal of the current mirror; and

a fourth transistor comprising a first current terminal, a second current terminal, and a gate terminal, the second current terminal of the fourth transistor being coupled to the second terminal of the current mirror, and the gate terminal of the fourth transistor being coupled to the gate terminal of the third transistor.

3. The apparatus of claim 2, wherein the first current terminal of the third transistor is coupled to the gate terminal of the third transistor.

4. The apparatus of claim 1, wherein the current mirror is configured to boost a bit current obtained from the memory.

5. The apparatus of claim 1, wherein the logic gate further comprises an output terminal configured to be coupled to a computing system.

6. The apparatus of claim 1, wherein the first transistor further comprises a gate terminal configured to be coupled to a controller.

7. The apparatus of claim 1, wherein the second transistor further comprises a gate terminal configured to be coupled to a controller.

8. The apparatus of claim 1, wherein the logic gate is configured to compare a first current conducted through the current mirror to a second current conducted through the second transistor.

9. The apparatus of claim 8, wherein the first current is a bit current obtained from the memory, and wherein the second current is a reference current.

10. The apparatus of claim 1, wherein the first transistor is configured to initialize the input terminal of the logic gate to a logic low value.

11. The apparatus of claim 1, wherein the memory is rated for a first voltage, and wherein the current mirror, the first transistor, the second transistor, and the logic gate are rated for a second voltage.

12. The apparatus of claim 11, wherein the first voltage is greater than the second voltage.

13. The device of claim 1, wherein the memory is a one-time programmable (OTP) memory.

14. A method of sensing a memory, the method comprising:

initializing an output of the sensing circuit to a first logic high value;

obtaining a first current from the memory corresponding to a memory bit stored in the memory;

replicating the first current;

determining whether the replicated first current is greater than the second current, an

Generating a second logic high value at the output of the sensing circuit in response to determining that the replicated first current is greater than the second current.

15. The method of claim 14, wherein the second current is a reference current.

16. The method of claim 14, wherein the output of the sensing circuit is initialized to the first logic high value by initializing an input of a logic gate to a logic low value.

17. The method of claim 14, further comprising generating a logic low value at the output of the sensing circuit in response to determining that the replicated first current is less than the second current.

18. The method of claim 14, wherein the memory is a one-time programmable (OTP) memory.

19. The method of claim 14, wherein the first current is replicated using a current mirror.

20. The method of claim 14, further comprising transmitting the second logic high value at the output of the sensing circuit to a computing system.

Technical Field

The present disclosure relates generally to memories and, more particularly, to methods and apparatus to improve performance when reading one-time programmable memories.

Background

A memory typically includes an array of memory cells, each of which is accessible via enabling a corresponding pair of word lines and bit lines. A memory cell typically includes a word line switching device and a storage element. In one-time programmable (OTP) memories, the word line switching devices are Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) and the storage elements are floating gate MOSFETs (fgmos).

Drawings

FIG. 1 is a schematic diagram of an OTP memory cell and a corresponding sensing circuit that reads the OTP memory cell.

FIG. 2 is a schematic diagram of an example OTP memory and an example sensing circuit to read the OTP memory.

Fig. 3 is a block diagram illustrating the example controller of fig. 2.

FIG. 4 is a graphical illustration depicting example cycle times measured with and without the use of the sensing circuit of FIG. 2.

FIG. 5 is a graphical illustration depicting example access times measured with and without the use of the sensing circuit of FIG. 2.

FIG. 6 is a graphical illustration depicting example areas measured with and without the use of the sensing circuit of FIG. 2.

FIG. 7 is a signal graph depicting various signals occurring in the sensing circuit of FIG. 2.

FIG. 8 is a flow diagram representative of a process that may be implemented using logic or machine readable instructions executable to implement the controller of FIG. 2.

FIG. 9 is a flow diagram representative of a process that may be implemented using logic or machine readable instructions executable to implement the sensing circuitry of FIG. 2.

Fig. 10 shows the schematic of fig. 2, including additional logic circuitry.

FIG. 11 is a signal graph depicting various voltage signals occurring in the system of FIG. 10 when reading a logic low value.

FIG. 12 is a signal graph depicting various voltage signals occurring in the system of FIG. 10 when reading a logic high value.

Fig. 13 illustrates another example implementation of the schematic of fig. 2, which includes additional logic circuitry.

Fig. 14 is a block diagram of an example processing platform configured to execute the instructions of fig. 8 and 9 to implement the sensing circuit of fig. 2 and the controller of fig. 2 and 3.

The figures are not drawn to scale. Generally, the same reference numbers will be used throughout the drawings and the following written description to refer to the same or like parts. Joinder references (e.g., attached, coupled, connected, and joined) are to be construed broadly and may include intermediate members between a collection of elements and relative movement between elements unless otherwise indicated. Thus, joinder references do not necessarily infer that two elements are directly connected and in fixed relation to each other.

In this document, the descriptors "first", "second", "third", etc. are used when identifying a plurality of elements or components that may be referred to individually. Unless otherwise specified or understood based on their context of use, such descriptors are not intended to give priority, any meaning of physical order or arrangement in a list or temporal ordering, but are merely used as labels to refer individually to a plurality of elements or components to facilitate understanding of the disclosed examples. In some examples, the descriptor "first" may be used to refer to an element in a particular embodiment, while the same element may be referred to in the claims by a different descriptor, such as "second" or "third". In such cases, it should be understood that the use of such descriptors is merely for ease of reference to multiple elements or components.

Detailed Description

The memory cells are used to store binary digital data (e.g., a bit value of 1 or a bit value of 0, a logic high value or a logic low value, etc.) in a computing device and/or any suitable computing architecture (e.g., a microcontroller, etc.). The memory cells may be included in an array of memory cells located in volatile memory (e.g., Random Access Memory (RAM), Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), etc.) or in non-volatile memory (e.g., Read Only Memory (ROM), mask ROM, Programmable Read Only Memory (PROM), OTP memory, Erasable Programmable Read Only Memory (EPROM), Electrically Erasable Programmable Read Only Memory (EEPROM), flash memory, etc.).

As previously mentioned, OTP memory is a type of non-volatile memory that can be programmed by an end user. The OTP memory array may include one or more memory cells, each memory cell including one or more memory devices (e.g., FGMOS). Non-volatile memory, such as OTP memory, stores binary data representing firmware code and/or low-level programs for read-only access. Where such firmware code and/or any low-level programs are to be utilized, corresponding memory bits stored in the memory cells may be sensed and/or otherwise read for use in volatile memory or elsewhere in the computing system and/or computing device.

Methods of reading a memory cell in an OTP memory (e.g., sensing a value of a memory bit stored in the memory cell) involve a comparison of a bit current (e.g., a current generated by a memory bit stored in the memory cell) to a reference current. Based on such a comparison, a determination may be made of the bit value stored in the memory cell (e.g., either a 1 bit value or a 0 bit value). For example, such a comparison determines whether the memory cell stores a bit value of 1 or a bit value of 0. As described below, fig. 1 shows an OTP memory along with a conventional sensing circuit.

FIG. 1 is a schematic diagram 100 of a first OTP memory array 102, a second OTP memory array 104, a multiplexer 106, and a sense circuit 108. In fig. 1, first OTP memory array 102 includes a first OTP memory cell 110 and a second OTP memory cell 112. Also, in fig. 1, second OTP memory array 104 includes a third OTP memory cell 114 and a fourth OTP memory cell 116. In addition, the sensing circuit 108 includes a first reference switch 118, a first logic gate 120, a second logic gate 122, and a second reference switch 124.

In fig. 1, the first OTP memory cell 110, the second OTP memory cell 112, the third OTP memory cell 114 and the fourth OTP memory cell 116 include respective p-channel mosfets (pmos)126, 128, 130, 132. Furthermore, the first OTP memory cell 110, the second OTP memory cell 112, the third OTP memory cell 114 and the fourth OTP memory cell 116 comprise respective FGMOS switches 134, 136, 138, 140. In fig. 1, controller 142 is operable to load a respective memory bit in any of first OTP memory cell 110, second OTP memory cell 112, third OTP memory cell 114, and/or fourth OTP memory cell 116 via a first word line (line 105) or a second word line (line 107).

In fig. 1, multiplexer 106 is a two-to-one through multiplexer that includes a first array of PMOS switches 146, a first array of n-channel mosfet (NMOS) switches 148, a second array of PMOS switches 150, a second array of NMOS switches 152, and a decoder 154. The multiplexer 106 may operate based on the memory address value decoded by the decoder 154 associated with the control signal (line 113) to conduct current through the first array PMOS switch 146 and the first array NMOS switch 148, or to conduct current through the second array PMOS switch 150 and the second array NMOS switch 152.

To read a bit value stored in a selected one of the first OTP memory cell 110, the second OTP memory cell 112, the third OTP memory cell 114 or the fourth OTP memory cell 116, the controller 142 generates a control signal (line 113) for the multiplexer 106 to enable and/or disable the respective first array PMOS switch 146, first array NMOS switch 148, second array PMOS switch 150 or second array NMOS switch 152. At substantially the same time (e.g., within microseconds), the reference signal (line 115) is transmitted to the reference current generator 156. In operation, the reference signal (line 115) is directed toThe reference current generator 156 indicates the activation of the first reference switch 118. Thus, the reference current (I)_REF) Will be conducted through the first reference switch 118. Likewise, the multiplexer 106 conducts a bit current (I) based on a memory address value associated with the control signal (line 113) and whether a memory bit is stored in a selected one of the first OTP memory cell 110, the second OTP memory cell 112, the third OTP memory cell 114, or the fourth OTP memory cell 116_BIT). In fig. 1, a bit current (I) when a memory bit is stored in a selected one of the first OTP memory cell 110, the second OTP memory cell 112, the third OTP memory cell 114, or the fourth OTP memory cell 116_BIT) Is a fixed current. In fig. 1, the voltage rating of each of the multiplexer 106, the first OTP memory cell 110, the second OTP memory cell 112, the third OTP memory cell 114, and the fourth OTP memory cell 116 is much higher than the voltage of the sensing circuit 108, the reference current generator 156, and the computing system 158 (e.g., 5V versus 1.5V).

In fig. 1, the polarity of the input of the second logic gate 122 is initialized to a high value via the enabling of the second reference switch 124. An initialization signal (line 117) is sent to the second reference switch 124 to enable the second reference switch 124. In operation, if bit current (I)_BIT) And a reference current (I)_REF) The comparison is higher then the voltage at the input terminal of the first logic gate 120 will be pulled to a logic high value. Thus, the first logic gate 120 will obtain a high input voltage value. The output of the first logic gate 120, and therefore the input of the second logic gate 122, will be a low output value. Thus, the output of the second logic gate 122 will be a high output value. Such output of the second logic gate 122 indicates that a memory bit is stored in a selected one of the first OTP memory cell 110, the second OTP memory cell 112, the third OTP memory cell 114, or the fourth OTP memory cell 116. Current if bit (I)_BIT) And a reference current (I)_REF) Relatively low, the voltage at the input terminal of the first logic gate 120 will be dominated by a large reference current (I)_REF) The effect of conduction to ground, thus causing the input terminal of the first logic gate 120 to be a logic low value. Thus, the first logic gate 120 will obtainLow input voltage value. Thus, the output of the first logic gate 120, and therefore the input of the second logic gate 122, will be a high output value. Thus, the output of the second logic gate 122 will be a low output value. Such output of the second logic gate 122 indicates that a memory bit is not stored in a selected one of the first OTP memory cell 110, the second OTP memory cell 112, the third OTP memory cell 114, or the fourth OTP memory cell 116.

In FIG. 1, the bit current (I)_BIT) And a reference current (I)_REF) Is inefficient and time consuming. In FIG. 1, when a memory bit "1" is read, the bit current (I)_BIT) And a reference current (I)_REF) The difference between determines the rate of change of the voltage at the input terminal of the first logic gate 120. In fig. 1, the access time (e.g., the time it takes to read and/or sense data, instructions, and information stored in the first OTP memory array 102 and/or the second OTP memory array 104) and the cycle time (e.g., the time between one access to the first OTP memory array 102 or the second OTP memory array 104 and a subsequent access to the first OTP memory array 102 or the second OTP memory array 104) depend on the available bit current (I) I_BIT) And/or other quantities. Thus, the access time and cycle time depend on the bit current (I)_BIT) The time it takes to cause the voltage at the input terminal of logic gate 120 to rise to a logic high value is limited due to this time. In FIG. 1, the access time and cycle time of 1024 16-bit words is slow (e.g., an access time of about 58 nanoseconds (ns) and a cycle time of 125 ns).

As shown in fig. 1, the time to access the first OTP memory unit 110, the second OTP memory unit 112, the third OTP memory unit 114, and/or the fourth OTP memory unit 116 is lengthy, and a processor, a Central Processing Unit (CPU), and/or other computing system cannot reliably utilize the memory bits, instructions, and/or other information stored in the first OTP memory unit 110, the second OTP memory unit 112, the third OTP memory unit 114, and/or the fourth OTP memory unit 116. Thus, the memory bits, instructions, and/or other information stored in first OTP memory unit 110, second OTP memory unit 112, third OTP memory unit 114, and/or fourth OTP memory unit 116 are loaded into computing system 158 for use by a processor, CPU, and/or other computing system.

Examples disclosed herein include methods and apparatus to improve efficiency when sensing and/or otherwise reading bits stored in memory. In examples disclosed herein, a current mirror is utilized to boost the incoming bit current to improve access and cycle times when sensing and/or otherwise reading bits stored in OTP memory. For example, not the bit current (I) as in FIG. 1_BIT) Is a source current, but a current mirror may be utilized in the sense circuit to cause a bit current (I) obtained from the OTP memory_BIT) Replication and promotion. In this way, the bit current (I)_BIT) May be sensed as a perfusion (sink) current. Such an example current mirror may include a combination of switching devices (e.g., transistors) selected in a manner to ensure an incoming bit current (I) at the time of replication_BIT) Is lifted. For example, switching devices (e.g., transistors) in a current mirror may be selected to have specified characteristics (e.g., transistor size, etc.) to ensure the bit current (I)_BIT) The desired lift rate. In the examples disclosed herein, the boosted, replicated bit current (I) conducted as a perfusion current_BIT) Is used for comparison with a reference current. Thus, the operating characteristics of the sensing circuit, such as cycle time and access time, are reduced and improved. Further operational descriptions are described below.

In some examples disclosed herein, the improved access time and cycle time enables efficient operation of the OTP memory, whether or not shadow (shadow) volatile memory is utilized, when sensing, comparing, and/or otherwise reading bits stored in the OTP memory.

Fig. 2 is a schematic diagram 200 of an example first OTP memory array 202, an example second OTP memory array 204, an example multiplexer 206, and an example sense circuit 208. In fig. 2, first OTP memory array 202 includes an example first OTP memory cell 210 and an example second OTP memory cell 212. Also, in fig. 2, second OTP memory array 204 includes an example third OTP memory cell 214 and an example fourth OTP memory cell 216. Further, the sensing circuit 208 includes an example current mirror 218 that includes an example first switch 220 having an example first drain terminal 222, an example first gate terminal 224, and an example first source terminal 226. The current mirror 218 further includes an example second switch 228 including an example second drain terminal 230, an example second gate terminal 232, and an example second source terminal 234. The sensing circuit 208 further includes an example logic gate 236, an example initialization switch 238 having an example third drain terminal 240, an example third gate terminal 242, and an example third source terminal 244. Further, the sensing circuit 208 includes an example reference switch 246 having an example fourth source terminal 248, an example fourth gate terminal 250, and an example fourth drain terminal 252. The first switch 220, the second switch 228, and the initialization switch 238 are NMOS transistors. The reference switch 246 is a PMOS transistor. In other examples disclosed herein, the first switch 220, the second switch 228, the initialization switch 238, and/or the reference switch 246 can be any suitable switching device (e.g., a PMOS transistor, an NMOS transistor, a bipolar junction gate transistor (BJT), etc.).

Further, the schematic diagram 200 of fig. 2 includes an example boost circuit 253 and an example inverter 255. In examples disclosed herein, any of first drain terminal 222, first source terminal 226, second drain terminal 230, second source terminal 234, third drain terminal 240, third source terminal 244, fourth drain terminal 252, and/or fourth source terminal 248 may be referred to as a respective current terminal. In other examples disclosed herein, any suitable logic device and/or circuitry may be used in combination with the system of fig. 2. An example additional embodiment including additional logic circuitry is depicted in fig. 10 below.

In fig. 2, first OTP memory cell 210, second OTP memory cell 212, third OTP memory cell 214, and fourth OTP memory cell 216 include respective p-channel metal-oxide-semiconductor field-effect transistors (PMOS)254, 256, 258, 260. Further, first OTP memory cell 210, second OTP memory cell 212, third OTP memory cell 214, and fourth OTP memory cell 216 include respective FGMOS switches 262, 264, 266, 268. In fig. 2, controller 270 is operable to load a respective memory bit in any of first OTP memory cell 210, second OTP memory cell 212, third OTP memory cell 214, and/or fourth OTP memory cell 216 via an example first word line (line 205) or an example second word line (line 207). In the example shown in fig. 2, charge is stored in the floating gates of the respective FGMOS switches 262, 264, 266, 268 in response to the generation of either the first word line (line 205) or the second word line (line 207).

In the example of FIG. 2, the voltage rating (e.g., 5 volts) of first OTP memory array 202, second OTP memory array 204, and multiplexer 206 is higher than the voltage rating (e.g., 1.5 volts) of sensing circuit 208. Although fig. 2 shows the voltage rating (e.g., 5 volts) of first OTP memory array 202, second OTP memory array 204, and multiplexer 206 being higher than the voltage rating (e.g., 1.5 volts) of sense circuitry 208, first OTP memory array 202, second OTP memory array 204, multiplexer 206, and/or sense circuitry 208 may be implemented with any suitable voltage rating.

The schematic diagram 200 of fig. 2 also includes an example controller 270, an example reference current generator 272, and an example computing system 274. In other examples disclosed herein, any number of OTP memory arrays may be configured in schematic diagram 200.

In fig. 2, the multiplexer 206 is a two-to-one straight-through multiplexer that includes an example first array of PMOS switches 276, an example first array of NMOS switches 278, an example second array of PMOS switches 280, and an example second array of NMOS switches 282. The multiplexer 206 may operate based on the polarity of the example select signals (lines 221, 223) generated by the example decoder 284 and/or the example boosted control signal (line 219a) and the example supplemented (compensated) boosted control signal (line 219b) generated by the boost circuit 253. In operation, the controller 270 transmits the example control signal (line 213), and the boost circuit 253 generates and transmits the example boosted control signal (line 219a) and/or the example supplemental boosted control signal (line 219b) to the multiplexer 206 based on the polarity of the select signals (lines 221, 223). Further, the controller 270 transmits the example decoded signal (line 231) to the decoder 284. As a result, the decoder 284 generates select signals (lines 221, 223) based on the decoded signal (line 231) to cause current to be passed through the first array PMOS switch 276 and the first array NMOS switch 278 in conjunction with the boosted control signal (line 219a) and/or the supplemental boosted control signal (line 219b), or to cause current to be passed through the second array PMOS switch 280 and the second array NMOS switch 282 in conjunction with the boosted control signal (line 219a) and/or the supplemental boosted control signal (line 219 b).

For example, if the first word line (line 205) is a logic low value, the second word line (line 207) is a logic high value, the first select signal (line 221) is a logic high value, the second select signal (line 223) is a logic low value, and the control signal (line 213) is a logic high value, then the boosted control signal (line 219a) is a logic low value, the voltage level of the supplemental boosted control signal (line 219b) is boosted, and the memory bit (if any) stored in the third OTP memory cell 214 is to be sensed and/or otherwise read. Further in such an example, if a memory bit is stored in third OTP memory cell 214 and the select signal (lines 221, 223) and/or the control signal (line 213) indicate sensing and/or otherwise reading the memory bit stored in third OTP memory cell 214, then an example bit current (I) is illustrated_BIT) Will pass through the second array PMOS switch 280 and the second array NMOS switch 282.

Alternatively, in another example disclosed herein, if the first word line (line 205) is a logic high value, the second word line (line 207) is a logic low value, the first select signal (line 221) is a logic low value, the second select signal (line 223) is a logic high value, and the control signal (line 213) is a logic high value, then the voltage level of the boosted control signal (line 219a) is boosted, the supplemental boosted control signal (line 219b) is a logic low value, and the memory bit (if any) stored in the second OTP memory cell 212 will be sensed and/or otherwise read. Further in such an example, if a memory bit is stored in second OTP memory cell 212, and the signal is selected (line 2)21. 223) and/or a control signal (line 213) indicates sensing and/or otherwise reading a memory bit stored in the second OTP memory cell 212, then the bit current (I) is set_BIT) Will conduct through the first array PMOS switch 276 and the first array NMOS switch 278. In examples disclosed herein, the bit current (I) is if the memory bit is stored in a selected one of the first OTP memory cell 210, the second OTP memory cell 212, the third OTP memory cell 214, or the fourth OTP memory cell 216_BIT) May be 0.5 milliamps, 1.0 milliamps, etc. Table 1 below shows example voltage values when reading memory cells of first OTP memory array 202.

Signal	Voltage level (volt)
		Control signal (line 213)	1.5
Boosted control signal (line 219a)	2.4
		Supplemental boosted control signal (line 219b)	0
First selection signal (line 221)	0
		Second selection signal (line 223)	1.5
Decoding signal (line 231)	0

TABLE 1

Table 2 below shows example voltage values when reading memory cells of second OTP memory array 204.

Signal	Voltage level (volt)
		Control signal (line 213)	1.5
Boosted control signal (line 219a)	0
		Supplemental boosted control signal (line 219b)	2.4
First selection signal (line 221)	1.5
		Second selection signal (line 223)	0
Decoding signal (line 231)	1

TABLE 2

In the example shown in fig. 2, sensing circuit 208 is operable to sense and/or otherwise read the data stored at the first OTPA memory bit, if any, in a selected one of memory cell 210, second OTP memory cell 212, third OTP memory cell 214, or fourth OTP memory cell 216. In the example of fig. 2, if a memory bit is stored in a selected one of first OTP memory cell 210, second OTP memory cell 212, third OTP memory cell 214, or fourth OTP memory cell 216, and such corresponding memory cell is selected to be sensed and/or otherwise read via a select signal (lines 221, 223), the bit current (I) is_BIT) Passes through the multiplexer 206.

In fig. 2, the current mirror 218 of the sensing circuit 208 is coupled to the multiplexer 206 (e.g., the first drain terminal 222 of the first switch 220 is coupled to the multiplexer 206) to obtain and/or otherwise receive a bit current (I) from the first OTP memory array 202 or the second OTP memory array 204_BIT). In this example, the bit current (I)_BIT) Mirrored and/or otherwise duplicated to conduct through the first switch 220 and the second switch 228. Further, in fig. 2, the first switch 220 and the second switch 228 of the current mirror 218 are selected to ensure a specified boost rate of the current mirror 218. For example, a first switch 220 having a first operating characteristic (e.g., a first switch size, etc.) may be selected, and a second switch 228 having a second operating characteristic (e.g., a second switch size, etc.) may be selected to ensure an incoming bit current (I) at the time of replication_BIT) Is boosted to a higher current value while conducting through the second switch 228.

In FIG. 2, because the input terminal 286 of the logic gate 236 is initialized to a logic low value, the access time and cycle time of the sensing circuit 208 depend on the reference current (I)_REF) To pull high the voltage at the input terminal 286 of the logic gate 236. In the topology of FIG. 2, when reading a memory bit "0", the reference current (I)_REF) Sum current (I)_BIT) The difference between the two will affect the rate of change of the voltage at the input terminal 286 of the logic gate 236. Because the current mirror 218 is configured to cause the bit current (I)_BIT) Is raised so that a higher reference current (I) can be utilized_REF). Due to the higher reference current (I)_REF) The rate of change of the voltage at the input terminal 286 of the logic gate 236 is improved (e.g., the rate of change of the voltage at the input terminal 286 of the logic gate 236 is increased). Thus, characteristics of the sensing circuit 208, such as access time and cycle time, are improved. The description of the improved operating characteristics is explained below in conjunction with at least fig. 4, 5, and/or 6. Although in fig. 2, the first switch 220 and the second switch 228 form the current mirror 218, the current mirror may be implemented using any suitable number of logic devices and/or logic circuitry. For example, the current mirror 218 may be implemented using a Bipolar Junction Transistor (BJT) current mirror, a feedback auxiliary current mirror, or the like. Although the example of fig. 2 shows the first switch 220 as a diode-connected switch coupled to the multiplexer 206, the first switch 220 may be implemented using any suitable logic gates, logic devices, and/or circuits. Further, in examples disclosed herein, the sensing circuit 208 may be coupled to the multiplexer 206 via an example first terminal 294 of a current mirror 218 of the sensing circuit 208. In examples disclosed herein, the first drain terminal 222 of the first switch 220, the first gate terminal 224 of the first switch 220, and the second gate terminal 232 of the second switch 228 are coupled to the first terminal 294. Further, the input terminal 286 of the logic gate 236, the fourth drain terminal 252 of the reference switch 246, and the third drain terminal 240 of the initialization switch 238 are coupled to the example second terminal 296 of the current mirror 218.

In the example shown in fig. 2, the logic gate 236 is an inverting gate. In fig. 2, the logic gate 236 includes an example input terminal 286 and an example output terminal 288. Input terminal 286 is coupled to second drain terminal 230, third drain terminal 240, and fourth drain terminal 252. The voltage value at output terminal 288 will be the inverse of the voltage value at input terminal 286. For example, if the voltage value at input terminal 286 is a logic low, then the voltage value at output terminal 288 will be a logic high. Alternatively, in another example disclosed herein, if the voltage value at the input terminal 286 is a logic high, then the voltage value at the output terminal 288 will be a logic low.

In the example shown in fig. 2, the initialization switch 238 is coupled to the logic gate 236, the current mirror 218, and the controller 270. The initialization switch 238 is an NMOS transistor. In other examples disclosed herein, the initialization switch 238 may be any suitable switching device (e.g., a PMOS transistor, a bipolar junction gate transistor (BJT), etc.). In fig. 2, the controller 270 generates and/or otherwise provides an example enable signal (line 215) to cause the initialization switch 238 to conduct current. In examples disclosed herein, controller 270 provides an enable signal (line 215) to initialization switch 238 prior to sensing and/or otherwise reading a memory bit, if any, stored in a selected one of first OTP memory cell 210, second OTP memory cell 212, third OTP memory cell 214, or fourth OTP memory cell 216 (e.g., prior to generating a control signal (line 213)). Thus, initializing switch 238 causes current to be conducted from input terminal 286 of logic gate 236 to exemplary ground rail 290 of current mirror 218. Thus, the voltage value at the input terminal 286 of the logic gate 236 is initialized to a logic low value. Thus, the output terminal 288 of the logic gate 236 is initialized to a logic high value.

In fig. 2, the example reference switch 246 is coupled to the current mirror 218, the input terminal 286 of the logic gate 236, the reference current generator 272, and the example power rail 292. In the example of fig. 2, the reference switch 246 is a PMOS transistor. In other examples disclosed herein, the reference switch 246 can be any suitable switching device (e.g., NMOS, BJT, etc.). In the example disclosed herein, the reference switch 246 is turned on, thus causing the voltage at the input terminal 286 of the logic gate 236 to be equal to or substantially similar to the voltage at the power rail 292. The reference switch 246 is configured to conduct an example reference current (I) from the power rail 292 to the input terminal 286 of the logic gate 236_REF). In the examples disclosed herein, the power rail 292 provides a suitable voltage (e.g., 1.5 volts) to the reference switch 246. In the examples disclosed herein, the reference switch 246 is enabled in response to an example reference signal (line 217) generated and/or otherwise provided by the controller 270. In the example shown in FIG. 2, the reference current (I)_REF) May be 3 microamps, 5 microamps, etc., and is set and/or otherwise caused due to the voltage of the reference signal (line 217).

In the illustrated example of fig. 2, the voltage boosting circuit 253 is a circuit that applies boosting to the voltage level of the control signal (line 213). For example, if the voltage level of the control signal (line 213) is 1.5V, the boost circuit 253 applies a voltage boost of about 500 and 900 millivolts (mV) to the control signal (line 213). The voltage level of the resulting control signal (e.g., the boosted control signal (line 219a) and/or the supplemental boosted control signal (line 219b)) is between 2.0V and 2.4V.

In operation, the sense circuit 208 passes a bit current (I)_BIT) And a reference current (I)_REF) To sense and/or otherwise read a memory bit (if any) stored in a selected one of first OTP memory cell 210, second OTP memory cell 212, third OTP memory cell 214, or fourth OTP memory cell 216. For example, if a memory bit is stored in a selected memory cell to be sensed and/or otherwise read, the bit current (I)_BIT) Will be high (e.g., 7 microamps, 50 microamps). In this case, because of the bit current (I)_BIT) Much higher than the reference current (I)_REF) (e.g., a bit current (I) of 7 or 50 microamps_BIT) Reference current (I) much higher than 2 or 5 microamperes_REF) The voltage at input terminal 286 will be substantially similar to the voltage of ground rail 290. For example, current (I) in bit_BIT) Greater than the reference current (I)_REF) The voltage at the input terminal 286 of the logic gate 263 will be pulled to a logic low value. As a result, the voltage at input terminal 286 will be substantially similar to the voltage and/or current at ground rail 290 (e.g., 0 volts or logic low). Thus, the output terminal 288 of the logic gate 236 will be a logic high, and thus indicate that the memory bit is stored in the selected memory cell.

In yet another example, the bit current (I) is if the memory bit is not stored in the selected memory cell to be sensed and/or otherwise read_BIT) Will be low (e.g., 1.0 nanoamperes, 0.5 nanoamperes). In this case, because of the reference current (I)_REF) Much higher than the on-bit current (I)_BIT) (e.g., a reference current (I) of 3 or 5 microamperes_REF) Bit current (I) well above 1.0 nanoAmp or 0.5 nanoAmp_BIT) Then the voltage at the input terminal 286 will be substantially similar to the voltage of the power rail 292 (e.g., a logic high value). Thus, the voltage at the input terminal 286 will be substantially similar to the voltage at the power rail 292 (e.g., 1.5 volts or logic high). Thus, the output terminal 288 of the logic gate 236 will be a logic low, and thus indicate that the memory bit is not stored in the selected memory cell.

In the example shown in fig. 2, controller 270 is coupled to multiplexer 206, first OTP memory cell 210, second OTP memory cell 212, third OTP memory cell 214, fourth OTP memory cell 216, initialization switch 238, reference current generator 272, and decoder 284. In the embodiments disclosed herein, the controller 270 is implemented as a single controller operable to at least: loading a memory bit in any of first OTP memory cell 210, second OTP memory cell 212, third OTP memory cell 214, and/or fourth OTP memory cell 216, selecting which of first OTP memory cell 210, second OTP memory cell 212, third OTP memory cell 214, or fourth OTP memory cell 216 to sense and/or otherwise read via a control signal (line 213) and a decode signal (line 231), initializing sensing circuit 208 via an enable signal (line 215), and/or generating and/or otherwise causing a generation of a reference current via a reference signal (line 217). In the example of fig. 2, controller 270 is a Central Processing Unit (CPU) that includes a memory controller. In other examples disclosed herein, any number of suitable controllers may be configured to perform the operations of controller 270.

In fig. 2, controller 270 is operable to load a memory bit into any of first OTP memory cell 210, second OTP memory cell 212, third OTP memory cell 214, and/or fourth OTP memory cell 216 based on a logic value of either the first word line (line 205) or the second word line (line 207). In such an example, a user may indicate that certain programs and/or low-level codes are converted to binary digital data by controller 270 and stored in a selected one of first OTP memory unit 210, second OTP memory unit 212, third OTP memory unit 214, or fourth OTP memory unit 216. Controller 270 is operable to generate and/or otherwise provide a control signal (line 213) to boost circuit 253 and a decode signal (line 231) to decoder 284 to indicate which of first OTP memory cell 210, second OTP memory cell 212, third OTP memory cell 214, or fourth OTP memory cell 216 is to be sensed and/or otherwise read (e.g., sense a memory bit, if any). Further, the controller 270 is operable to generate and/or otherwise provide an enable signal (line 215) to the initialization switch 238 to cause the initialization switch 238 to conduct and thus initialize the input terminal 286 to a logic low. Further, the controller 270 is operable to generate and/or otherwise provide a reference signal (line 217) to the reference current generator 272 to indicate activation of the reference switch 246 and, thus, cause the reference current (I)_REF) Conduction of (3). Further operation of the controller 270 is explained in further detail below in conjunction with fig. 3.

In fig. 2, an example reference current generator 272 is coupled to the reference switch 246 and the controller 270. In the examples disclosed herein, the reference current generator 272 is implemented external to the controller 270. Alternatively, in other examples disclosed herein, the reference current generator 272 may be implemented internally to the controller 270. The reference current generator is configured to obtain and/or otherwise receive an indication of a reference current (I)_REF) A reference signal of desired amplitude (line 217). For example, the reference signal (line 217) may indicate a desired reference current (I)_REF) Is 0.1 microamperes and thus reference current generator 272 is configured to generate an example gate reference signal (line 233) that includes a drain to source resistance (R) that will cause reference switch 246 to open_DS) A varying specified voltage. As a result, current (e.g., I) is conducted through the reference switch 246 due to the fixed voltage of the power rail 292_REF) Will be adjusted accordingly (e.g., to 0.1 ma).

In some examples disclosed herein, the sensing circuit 208 (e.g., the current mirror 218, the first switch 220, the second switch 228, the logic gate 236, the initialization switch 238, and the reference switch 246), the reference current generator 272, and/or the decoder 284 may be included in the controller 270.

In the example shown in fig. 2, the computing system 274 is coupled to the output terminal 288 of the logic gate 236. In examples disclosed herein, the computing system 274 may be volatile memory configured to receive indications of sensed and/or otherwise read memory bits. In such examples disclosed herein, computing system 274 may download and/or otherwise load memory bits from any of first OTP memory cell 210, second OTP memory cell 212, third OTP memory cell 214, and/or fourth OTP memory cell 216 for reprogramming, use, and/or any other suitable application. In other examples disclosed herein, computing system 274 may be a processor and/or suitable processing device configured to obtain memory bits stored in a selected one of first OTP memory cell 210, second OTP memory cell 212, third OTP memory cell 214, or fourth OTP memory cell 216.

Fig. 3 is a block diagram 300 illustrating the example controller 270 of fig. 2. The controller 270 of fig. 3 includes an example signal analyzer 302, an example initializer 304, an example signal generator 306, and an example sensing interface 308. In examples disclosed herein, any of signal analyzer 302, initializer 304, signal generator 306, and/or sensing interface 308 can communicate wired and/or wireless communications to a respective device internal to controller 270 and/or external to controller 270 via any suitable method.

In the example shown in fig. 3, signal analyzer 302 is configured to determine whether an indication of a sensed and/or read memory bit is obtained and/or otherwise received. In fig. 3, the signal analyzer 302 operates in the controller 270 based on a pre-initialization command that indicates sensing and/or otherwise reading a memory bit. For example, during a boot-up of controller 270, signal analyzer 302 may respond to a pre-initialization command that instructs sensing and/or otherwise reading of memory bits stored in non-volatile memory (e.g., first OTP memory cell 210, second OTP memory cell 212, third OTP memory cell 214, or fourth OTP memory cell 216). In other examples disclosed herein, the signal analyzer 302 may be configured to determine whether to obtain an indication of sensing and/or reading a memory bit based on communication with a user interface and/or any suitable input device. In response to an indication to sense and/or read a memory bit, signal analyzer 302 analyzes the indication to determine which of first OTP memory cell 210, second OTP memory cell 212, third OTP memory cell 214, or fourth OTP memory cell 216 is to be accessed for sensing and/or reading. In examples disclosed herein, the signal analyzer 302 may be a signal analyzer controller.

In the example shown in fig. 3, the initializer 304 is configured to determine whether the sensing circuit 208 of fig. 2 is initialized. For example, the initializer 304 determines whether the input terminal 286 of the logic gate 236 is initialized to a logic low value. If the initializer 304 determines that the sensing circuit 208 of FIG. 2 is not initialized, the initializer 304 generates the enable signal (line 215) of FIG. 2 for use by the initialization switch 238 of FIG. 2. If the initializer determines that the sensing circuit 208 of FIG. 2 is initialized, the initializer 304 ensures that the enable signal (line 215) is off and/or indicates that the initialization switch 238 of FIG. 2 is not turned on. In examples disclosed herein, the initializer 304 may be an initializer controller.

In the example shown in fig. 3, signal generator 306 is configured to obtain an indication and/or determination from signal analyzer 302 to generate a corresponding logical value on a signal associated with a word line of a selected memory cell to be read. For example, the signal generator may generate example word lines (e.g., a first word line (line 205) and a second word line (line 207)) to store memory bits in any of the first OTP memory cell 210, the second OTP memory cell 212, the third OTP memory cell 214, and/or the fourth OTP memory cell 216, respectively. Further, the signal generator 306 may generate the example reference signal of fig. 2 (line 217) for use by the reference current generator 272 of fig. 2. In examples disclosed herein, the signal generator 306 may be a signal generator controller.

In the example shown in fig. 3, the sense interface 308 is configured to generate the example control signal (line 213) of fig. 2 for use by the boost circuit 253 of fig. 2. Further, the sensing interface 308 is configured to generate the example decoded signal of fig. 2 (line 231) for use by the decoder 284 of fig. 2. In examples disclosed herein, the sensing interface 308 is configured to generate a control signal (line 213) and a decode signal (line 231) to cause the boost circuit 253 to generate a boosted control signal (line 219a) and/or a supplemental boosted control signal (line 219 b). In examples disclosed herein, the sensing interface 308 may be a sensing interface controller.

In some examples disclosed herein, the initializer 304, the signal generator 306, and/or the sensing interface 308 can be included in a memory controller. Alternatively, in other examples disclosed herein, the controller 270 may include the sensing circuit 208 of fig. 2 (e.g., the current mirror 218, the first switch 220, the second switch 228, the logic gate 236, the initialization switch 238, and the reference switch 246), the boost circuit 253, the reference current generator 272, and/or the decoder 284.

FIG. 4 is a graphical illustration 400 depicting example cycle times measured with and without the use of the sensing circuit 208 of FIG. 2. As used herein, cycle time refers to the time between one access of the OTP memory array and a subsequent access of the OTP memory array. The illustration 400 of fig. 4 includes an example first data segment (line 402) and an example second data segment (line 404). The first data segment (line 402) represents the trend of the periodic time log measured in units of time (e.g., nanoseconds) when the sensing circuitry 208 of FIG. 2 is not utilized (e.g., based on the sensing circuitry 108 of FIG. 1). The second data segment (line 404) represents the trend of the cycle time log measured in units of time (e.g., nanoseconds) when the sensing circuitry 208 of FIG. 2 is utilized.

As shown in the illustration 400 of fig. 4, at the example first data point 406, when 1024 16-bit words are accessed, the cycle time is 125 nanoseconds. Further, at the example second data point 408, when 1024 16-bit words are accessed, the cycle time is 42 nanoseconds. As clearly shown in FIG. 4, the cycle time of the sensing circuit is improved when using the sensing circuit 208 of FIG. 2 (e.g., 42 nanoseconds versus 125 nanoseconds when 1024 16-bit words are accessed).

FIG. 5 is a graphical illustration 500 depicting example access times measured with and without use of the sensing circuit 208 of FIG. 2. As used herein, access time refers to the time it takes to read and/or sense data, instructions and information stored in an OTP memory array. The illustration 500 of fig. 5 includes an example first data segment (line 502) and an example second data segment (line 504). The first data segment (line 502) represents the trend of the access time pair word measured in units of time (e.g., nanoseconds) when the sensing circuitry 208 of FIG. 2 is not utilized (e.g., based on the sensing circuitry 108 of FIG. 1). The second data segment (line 504) represents the trend of access time pairs measured in units of time (e.g., nanoseconds) when the sensing circuitry 208 of FIG. 2 is utilized.

As shown in the illustration 500 of fig. 5, at an example first data point 506, when 1024 16-bit words are accessed, the access time is 58 nanoseconds. Further, at example second data point 508, when 1024 16-bit words are accessed, the access time is 38 nanoseconds. As clearly shown in FIG. 4, the access time of the sensing circuitry is improved when the sensing circuitry 208 of FIG. 2 is utilized (e.g., when 1024 16-bit words are accessed, the access time is 38 nanoseconds versus 58 nanoseconds).

FIG. 6 is a graphical illustration 600 depicting example areas measured with and without the use of the sensing circuit 208 of FIG. 2. As used herein, area refers to the physical size of the corresponding sensing circuit measured in square millimeters. The illustration 600 of fig. 6 includes an example first data segment (line 602) and an example second data segment (line 604). The first data field (line 602) represents area trends for varying levels of 16-bit words when the sensing circuit 208 of FIG. 2 is not utilized (e.g., based on the sensing circuit 108 of FIG. 1). A second data field (line 404) represents area trends for varying 16-bit word levels when utilizing sensing circuit 208 of FIG. 2.

As shown in the illustration 600 of FIG. 6, the area or physical size of the sensing circuitry 208 is not significantly increased compared to the area or physical size of the sensing circuitry 108 of FIG. 1.

FIG. 7 is a signal graph 700 depicting various signals occurring in the sensing circuit 208 of FIG. 2. Signal graph 700 of FIG. 7 includes an example initialization signalA sign (line 702), an example input signal (line 704), an example output signal (line 706), an example reference current signal (line 708), and an example bit current signal (line 710). In fig. 7, the initialization signal (line 702) may represent the enable signal (line 215) of fig. 2, the input signal (line 704) may represent the signal at the input terminal 286 of the logic gate 236, the output signal (line 706) may represent the signal at the output terminal 288 of the logic gate 236, and the reference current signal (line 708) may represent the reference current (I) of fig. 2_REF) And the bit current signal (line 710) may represent the bit current (I) of FIG. 2_BIT). In the signal plot 700 of fig. 7, the amplitude of any of the signals may be any suitable value.

Between example first time interval 712 and example second time interval 714, the initialization signal (line 702) is a logic high value, the input signal (line 704) is a logic low value, the output signal (line 706) is a logic high value, the reference current signal (line 708) is zero amps, and the bit current signal (line 710) is zero amps. At a second time interval 714, the reference current signal (line 708) is generated and the initialization signal (line 702) is logic low (e.g., off). Thus, between the second time interval 714 and the example third time interval 716, the initialization signal (line 702) is a logic low value, the input signal (line 704) is a logic high value, the output signal (line 706) is a logic low value, the reference current signal (line 708) is 1 milliamp, and the bit current signal (line 710) is zero amps

At a third time interval 716, the memory bit is sensed and/or otherwise read, and thus the bit current becomes 1 amp. Thus, at the third time interval 716, the initialization signal (line 702) is a logic low value, the input signal (line 704) is a logic low value, the output signal (line 706) is a logic high value, the reference current signal (line 708) is 1 milliamp, and the bit current signal (line 710) is 1 amp.

Although an example manner of implementing the sensing circuitry 208 and/or the controller 270 of fig. 2 is shown in fig. 2 and 3, one or more of the elements, processes and/or devices shown in fig. 2 and 3 may be combined, divided, rearranged, omitted, eliminated and/or implemented in any other way. Further, the example first switch 220, the example second switch 228, the example logic gate 236, the example initialization switch 238, the example reference switch 246, and/or, more generally, the example sensing circuit 208, the example signal analyzer 302, the example initializer 304, the example signal generator 306, the example sensing interface 308 of fig. 2, and/or, more generally, the example controller 270 of fig. 2 and 3 may be implemented by hardware, software, firmware, and/or any combination of hardware, software, and/or firmware. Thus, for example, the example first switch 220, the example second switch 228, the example logic gate 236, the example initialization switch 238, the example reference switch 246, and/or, more generally, any of the example sensing circuitry 208, the example signal analyzer 302, the example initializer 304, the example signal generator 306, the example sensing interface 308 of fig. 2, and/or, more generally, the example controller 270 of fig. 2 and 3 may be implemented by one or more analog or digital circuits, logic circuits, programmable processors, programmable controllers, Graphics Processing Units (GPUs), Digital Signal Processors (DSPs), Application Specific Integrated Circuits (ASICs), Programmable Logic Devices (PLDs), and/or Field Programmable Logic Devices (FPLDs). When reading any of the device or system claims of this patent to encompass a purely software and/or firmware implementation, at least one of the example first switch 220, the example second switch 228, the example logic gate 236, the example initialization switch 238, the example reference switch 246, and/or, more generally, the example sensing circuit 208, the example signal analyzer 302, the example initializer 304, the example signal generator 306, the example sensing interface 308 of fig. 2, and/or, more generally, the example controller 270 of fig. 2 and 3 is expressly defined herein to include a non-transitory computer-readable storage device or storage disk, such as a memory, a Digital Versatile Disk (DVD), a Compact Disk (CD), a blu-ray disk, etc., that includes software and/or firmware. Further, the example sensing circuitry 208 of fig. 2 and/or the example controller 270 of fig. 2 and 3 may include one or more elements, processes, and/or devices in addition to, or instead of, those elements, processes, and/or devices shown in fig. 2 and 3, and/or may include more than one of any or all of the illustrated elements, processes, and devices. As used herein, the phrase "communicate," including variations thereof, encompasses direct communication and/or indirect communication through one or more intermediate components, and does not require direct physical (e.g., wired) communication and/or continuous communication, but additionally includes selective communication at regular intervals, predetermined intervals, non-regular intervals, and/or one-time events.

Flowcharts representative of example hardware logic, machine readable instructions, hardware implemented state machines, and/or any combination thereof to implement the example sensing circuitry 208 of fig. 2 and/or the example controller 270 of fig. 2 and 3 are shown in fig. 8 and 9. Further, flowcharts representative of example hardware logic, machine readable instructions, hardware implemented state machines, and/or any combination thereof to implement the example system 1000 of fig. 10 and/or the system 1300 of fig. 13 are shown in fig. 8 and 9. The machine-readable instructions may be one or more executable programs or portion(s) of executable programs for execution by a computer processor, such as processor 1412 shown in the example processor platform 1400 discussed below in connection with fig. 14. The program may be embodied in software stored on a non-transitory computer readable storage medium such as a CD-ROM, a floppy disk, a hard drive, a DVD, a blu-ray disk, or a memory associated with the processor 1412, but the entire program and/or parts thereof could alternatively be executed by a device other than the processor 1412 and/or embodied in firmware or dedicated hardware. Further, although the example program is described with reference to the flowcharts shown in fig. 8 and 9, many other methods of implementing the example sensing circuit 208 of fig. 2, the example controller 270 of fig. 2 and 3, the system 1000 of fig. 10, and/or the system 1300 of fig. 13 may alternatively be used. For example, the order of execution of the blocks may be changed, and/or some of the blocks described may be changed, eliminated, or combined. Additionally or alternatively, any or all of the blocks may be implemented by one or more hardware circuits (e.g., discrete and/or integrated analog and/or digital circuitry, FPGAs, ASICs, comparators, operational amplifiers (opamps), logic circuits, etc.) configured to perform the corresponding operations without the execution of software or firmware.

The machine-readable instructions described herein may be stored in one or more of a compressed format, an encrypted format, a fragmented format, a packed format, and so forth. Machine-readable instructions as described herein may be stored as data (e.g., portions of instructions, code, representations of code, etc.) that may be utilized to create, fabricate, and/or generate machine-executable instructions. For example, machine-readable instructions may be fragmented and stored on one or more storage devices and/or computing devices (e.g., servers). The machine-readable instructions may require one or more of installation, modification, adaptation, updating, combining, supplementing, configuring, decrypting, decompressing, unpacking, distributing, redistributing, etc., in order to be directly readable and/or executable by the computing device and/or other machine. For example, machine-readable instructions may be stored in multiple parts that are separately compressed, encrypted, and stored on separate computing devices, where the parts, when decrypted, decompressed, and combined, form a set of executable instructions that implement a program such as that described herein. In another example, the machine-readable instructions may be stored in a state in which they are readable by a computer, but require the addition of libraries (e.g., Dynamic Link Libraries (DLLs)), Software Development Kits (SDKs), Application Programming Interfaces (APIs), and the like, in order to execute the instructions on a particular computing device or other device. In another example, machine readable instructions may need to be configured (e.g., stored settings, data input, recorded network address, etc.) before the machine readable instructions and/or corresponding program(s) can be executed in whole or in part. Accordingly, the disclosed machine readable instructions and/or corresponding program(s) are intended to encompass such machine readable instructions and/or program(s), regardless of the particular format or state of the machine readable instructions and/or program(s) as stored or otherwise at rest or as transmitted.

The machine-readable instructions described herein may be represented by any past, present, or future instruction language, scripting language, programming language, or the like. For example, the machine-readable instructions may be represented using any of the following languages: C. c + +, Java, C #, Perl, Python, JavaScript, HyperText markup language (HTML), Structured Query Language (SQL), Swift, and the like.

As described above, the example processes of fig. 8 and 9 may be implemented using executable instructions (e.g., computer and/or machine readable instructions) stored on a non-transitory computer and/or machine readable medium, such as a hard disk drive, a flash memory, a read-only memory, a compact disc, a digital versatile disc, a cache, a random access memory, and/or any other storage device or storage disk, in which information is stored for any duration (e.g., for extended periods of time, permanently, brief instances, for temporarily buffering, and/or for caching of the information). As used herein, the term non-transitory computer readable medium is expressly defined to include any type of computer readable storage device and/or storage disk and to exclude propagating signals and to exclude transmission media.

The terms "including" and "comprising" (as well as all forms and tenses thereof) are used herein as open-ended terms. Thus, whenever a claim recitations in any form "comprise" or "comprise" (e.g., comprise, include, have, etc.) as a preface or within the recitations of any kind, it is to be understood that additional elements, terms, etc. may be present without departing from the scope of the corresponding claim or recitations. As used herein, the phrase "at least" when used as a transitional term, such as in the preamble of the claims, is open-ended in the same manner that the terms "comprising" and "including" are open-ended. The term "and/or," when used, for example, in a form such as A, B and/or C, refers to any combination or subset of A, B, C, such as (1) a only, (2) B only, (3) C only, (4) a and B, (5) a and C, (6) B and C, and (7) a and B and C. As used herein in the context of describing structures, components, items, objects, and/or things, the phrase "at least one of a and B" means an embodiment that includes any one of the following: (1) at least one a, (2) at least one B, and (3) at least one a and at least one B. Similarly, as used herein in the context of describing structures, components, items, objects, and/or things, the phrase "at least one of a or B" means an embodiment that includes any one of the following: (1) at least one a, (2) at least one B, and (3) at least one a and at least one B. As used herein in the context of describing the execution or performance of processes, instructions, actions, activities, and/or steps, the phrase "at least one of a and B" means an embodiment that includes any of the following: (1) at least one a, (2) at least one B, and (3) at least one a and at least one B. Similarly, as used herein in the context of describing the execution or performance of processes, instructions, actions, activities, and/or steps, the phrase "at least one of a or B" means an embodiment that includes any of the following: (1) at least one a, (2) at least one B, and (3) at least one a and at least one B.

As used herein, singular references (e.g., "a," "an," "first," "second," etc.) do not exclude a plurality. The term "a" or "an" entity, as used herein, refers to one or more of that entity. The terms "a" (or "an"), "one or more" and "at least one" may be used interchangeably herein. Furthermore, although individually listed, a plurality of means, elements or method acts may be implemented by e.g. a single unit or processor. Furthermore, although individual features may be included in different examples or claims, these may possibly be combined, and the inclusion in different examples or claims does not imply that a combination of features is not feasible and/or advantageous.

Fig. 8 is a flow diagram representative of a process 800 that may be implemented using logic or machine readable instructions that may be executed to implement the controller 270 of fig. 2. In the example shown in fig. 8, the signal analyzer 302 of fig. 3 determines whether an indication to sense and/or read a memory bit is obtained and/or otherwise received (block 802). If control of block 802 returns no (e.g., if no indication to sense and/or read a memory bit is obtained or received), control proceeds to block 802 and waits. Alternatively, if control of block 802 returns yes (e.g., if an indication to sense and/or read a memory bit is obtained or received by signal analyzer 302), signal analyzer 302 determines which memory cells (e.g., first OTP memory cell 210, second OTP memory cell 212, third OTP memory cell 214, and/or fourth OTP memory cell 216) are to be accessed based on the received indication (block 804).

In response to performing the control of block 804, the initializer 304 determines whether the sensing circuit 208 of fig. 2 is initialized (block 806). If the control of block 806 returns no, the initializer 304 generates an enable signal (e.g., enable signal (line 215)) to turn on the initialization switch 238 (block 808). Further, in response to executing the control of block 808, control returns to 806 where the initializer 304 determines whether the sensing circuit 208 of FIG. 2 is initialized.

Alternatively, if the control of block 806 returns yes, the initializer 304 generates a signal (e.g., an enable signal (line 215)) to stop the conduction of the initialization switch 238 (block 810). In another example, the initializer 304 may not generate a signal (e.g., the enable signal (line 215)) to stop the conduction of the initialization switch 238 and, alternatively, stop the generation of the previously generated enable signal of block 808.

In response to performing the control of block 810, the sense interface 308 generates an enable signal (e.g., control signal (line 213)) for the boost circuit 253 and a decode signal (line 231) for the decoder 284 (block 812). In response, the controller 270 of fig. 2 and 3 determines whether to continue operation (block 814). If control of block 814 returns yes (e.g., controller 270 determines to continue operation), control returns to block 802. Alternatively, if control of block 814 returns no (e.g., controller 270 determines not to continue operation), then the process stops.

FIG. 9 is a flow diagram representative of a process 900 that may be implemented using logic or machine readable instructions that may be executed to implement the sensing circuitry 208 of FIG. 2. In fig. 9, the sensing circuit 208 initializes the output terminal 288 of the logic gate 236 to a first logic high value (block 902). In response, the current mirror 218 of FIG. 2 obtains (e.g., conducts) a bit current (I)_BIT) (block 904). In addition, the current mirror 218 replicates the bit current (I)_BIT) (block 906). In addition, the current mirror 218 drives the bit current (I)_BIT) And (block 908). In addition, reference switch 246 obtains (e.g., conducts) a reference current(I_REF) (block 910). In response, logic gate 236 determines the bit current (I)_BIT) (e.g., replicated bit current (I)_BIT) Whether or not it is larger than the reference current (I)_REF) (block 912).

Control returns yes in response to block 912 (e.g., bit current (I)_BIT) Greater than the reference current (I)_REF) Then the logic gate 236 indicates that the memory bit is stored (block 914). Further, the logic gate 236 generates a second logic high value at the output terminal 288 (block 916).

Alternatively, control returns no (e.g., bit current (I) in response to block 912_BIT) Less than or equal to the reference current (I)_REF) Then the logic gate 236 indicates that the memory bit is not stored (block 918). Further, the logic gate 236 generates a logic low value at the output terminal 288 (block 920). In response to performing the control illustrated by blocks 916 or 920, some examples disclosed herein include transmitting the logical value to a computing system (e.g., computing system 274 of fig. 2). In response to performing the control of blocks 916 or 920, the sensing circuit 208 determines whether to continue operation (block 922). If the sensing circuitry 208 determines to continue operation (e.g., execution of block 922 returns yes), control returns to block 902. Alternatively, in response to the sensing circuitry 208 determining not to continue operation (e.g., execution of block 922 returns no), then the process stops.

Fig. 10 shows the schematic diagram 200 of fig. 2, which includes additional logic circuitry. The example system 1000 of fig. 10 further includes an example first transistor 1002 and an example second transistor 1004. The first transistor 1002 is a PMOS transistor. The second transistor 1004 is an NMOS transistor. In operation, the first transistor 1002 and the second transistor 1004 obtain an example power-up signal (line 1001) from the controller 270. The first transistor 1002 and/or the second transistor 1004 allow for improved control of the sensing circuit 208. For example, when a read operation is not desired, the power-up signal (line 1001) goes to logic low and thus causes the second transistor 1004 to not conduct. In this example, power is saved because the path to the example ground rail 290 is open. In other examples disclosed herein, the control of the sensing circuit 208 may be improved with any suitable number of logic circuits and/or devices to save power, improve performance, and the like. Although fig. 2 illustrates an example power-on signal (line 1001) obtained from controller 270, such an example power-on signal (line 1001) may be obtained from any suitable device internal or external to system 1000.

FIG. 11 is a signal graph 1100 depicting various voltage signals occurring in the system 1000 of FIG. 10 when reading a logic low value. The signal graph 1100 includes an example clock signal (line 1102), an example power-up signal (line 1104), an example first voltage signal (line 1106), an example second voltage signal (line 1108), and an example third voltage signal (line 1110). The clock signal (line 1102) may be the example decoded signal (line 231) of fig. 2 and/or 10, the power-up signal (line 1104) may be the example power-up signal (line 1001) of fig. 10, the example first voltage signal (line 1106) may correspond to a voltage at the first terminal 294 (e.g., the first drain terminal 222 of the first switch 220) of the current mirror 218 of the sensing circuit 208 of fig. 2 and/or 10, the example second voltage signal (line 1108) may correspond to a voltage at the input terminal 286 of the logic gate 236 of fig. 2 and/or 10, and the example third voltage signal (line 1110) may correspond to a voltage at the output terminal 288 of the logic gate 236 of fig. 2 and/or 10.

At an example first time 1112, the clock signal (line 1102) goes to logic high. After a slight delay, the power-up signal (line 1104) goes to logic high, thereby causing the first voltage signal (line 1106) to decrease. However, between the first time 1112 and the example second time 1114, the second voltage signal (line 1108) begins to increase. For example, when reading a logic low value, the reference current (I)_REF) Greater than bit current (I)_BIT) And thus the second voltage signal (line 1108) increases to a voltage equivalent to or substantially similar to the example power rail 292 (fig. 2 and/or fig. 10). As a result, the third voltage signal (line 1110) decreases.

Fig. 12 is a signal graph 1200 depicting various voltage signals occurring in the system 1000 of fig. 10 when a logic high value is read. The signal graph 1200 includes an example clock signal (line 1202), an example power-up signal (1204 line), an example first voltage signal (line 1206), an example second voltage signal (1208 line), and an example third voltage signal (line 1210). The clock signal (line 1202) may be the example decoded signal (line 231) of fig. 2 and/or 10, the power-up signal (line 1204) may be the example power-up signal (line 1001) of fig. 10, the example first voltage signal (line 1206) may correspond to a voltage at the first drain terminal 222 of the first switch 220 of fig. 2 and/or 10, the example second voltage signal (line 1128) may correspond to a voltage at the input terminal 286 of the logic gate 236 of fig. 2 and/or 10, and the example third voltage signal (line 1210) may correspond to a voltage at the output terminal 288 of the logic gate 236 of fig. 2 and/or 10.

At an example first time 1212, the clock signal (line 1202) goes to logic high. After a slight delay, the power-up signal (line 1204) goes to logic high, thereby causing the first voltage signal (line 1206) to decrease. However, between the first time 1212 and the example second time 1214, the second voltage signal (line 1208) remains substantially constant. For example, when reading a logic high value, the reference current (I)_REF) Not greater than bit current (I)_BIT) And thus the second voltage signal (line 1108) is a voltage equivalent or substantially similar to the example ground rail 290 (fig. 2 and/or fig. 10). As a result, the third voltage signal (line 1110) remains at logic high.

Fig. 13 illustrates another example implementation of the schematic diagram 200 of fig. 2, which includes additional logic circuitry. The system 1300 of fig. 13 includes the example current mirror 218 (fig. 2 and/or 10) including the example first switch 220 (fig. 2 and/or 10) and the example second switch 228 (fig. 2 and/or 10), the example logic gate 236 (fig. 2 and/or 10), the example initialization switch 238 (fig. 2 and/or 10), and the example reference switch 246 (fig. 2 and/or 10). Additionally, the system 1300 of fig. 13 further includes an example first switch 1302, an example second switch 1304, an example third switch 1306, an example fourth switch 1308, an example fifth switch 1310, and an example sixth switch 1312.

The system 1300, in operation, performs substantially similar functions as the sensing circuit 208 of fig. 2 and/or 10. However, the first switch 1302 and the sixth switch 1312 may be implemented to improve manufacturability. For example, the first switch 1302 and/or the sixth switch 1312 may be coupled to the first switch 220 and/or the second switch 228, respectively, to reduce mismatch variation during manufacturing. However, the first switch 1302, the second switch 1304, the third switch 1306, the fourth switch 1308, the fifth switch 1310, and/or the sixth switch 1312 may be controlled by respective control signals to improve the capabilities of the control system 1300. For example, the first switch 1302, the second switch 1304, the third switch 1306, the fourth switch 1308, the fifth switch 1310, and/or the sixth switch 1312 may be enabled to enable conduction of current or disabled to save power. Further in such an example, the fourth switch 1308 and/or the fifth switch 1310 may be deactivated to facilitate blocking reference current generation. In other examples disclosed herein, any number of logic devices and/or logic circuits may be utilized to control operation and conserve power in the system 1300.

Fig. 14 is a block diagram of an example processing platform configured to execute the instructions of fig. 8 and 9 to implement the sensing circuitry 208 of fig. 2, the controller 270 of fig. 2 and/or 3, the system 1000 of fig. 10, and/or the system 1300 of fig. 13. Processor platform 1400 may be, for example, a server, a personal computer, a workstation, a self-learning machine (e.g., a neural network), a mobile device (e.g., a cell phone, a smart phone, a tablet computer such as an iPad), a mobile device, a smart phone, a tablet computer, a smart phone, a tablet, a smart phone, a computer, a smart phone, a computer^TM) Personal Digital Assistants (PDAs), internet appliances, DVD players, CD players, digital video recorders, blu-ray players, game consoles, personal video recorders, set-top boxes, headsets or other wearable devices, or any other type of computing device.

The processor platform 1400 of the illustrated example includes a processor 1412. The processor 1412 of the illustrated example is hardware. For example, the processor 1412 may be implemented by one or more integrated circuits, logic circuits, microprocessors, GPUs, DSPs, or controllers from any desired family or manufacturer. The hardware processor may be a semiconductor-based (e.g., silicon-based) device. In this example, the processor implements the example first switch 220, the example second switch 228, the example logic gate 236, the example initialization switch 238, the example reference switch 246, and/or, more generally, the example sensing circuit 208, the example signal analyzer 302, the example initializer 304, the example signal generator 306, the example sensing interface 308 of fig. 2, and/or, more generally, the example controller 270, the example first switch 220, the example second switch 228, the example logic gate 236, the example initialization switch 238, the example reference switch 246, the example first transistor 1002, the example second transistor 1004 of fig. 2 and/or 3, and/or, more generally, the example system 1000, the example current mirror 218, the example logic gate 236, the example initialization switch 238, the example reference switch 246, the example first switch 1302, the example second switch 1304, An example third switch 1306, an example fourth switch 1308, an example fifth switch 1310, an example sixth switch 1312, and/or more generally, the example system 1300 of fig. 13.

The processor 1412 of the illustrated example includes local memory 1413 (e.g., cache). The processor 1412 of the illustrated example communicates with main memory including a volatile memory 1414 and a non-volatile memory 1416 via a bus 1418. The volatile memory 1414 may be comprised of Synchronous Dynamic Random Access Memory (SDRAM), Dynamic Random Access Memory (DRAM),Dynamic random access memoryAnd/or any other type of random access memory device implementation. The non-volatile memory 1416 may be implemented by flash memory and/or any other desired type of memory device. Access to the main memory 1414, 1416 is controlled by a memory controller.

The processor platform 1400 of the illustrated example also includes interface circuitry 1420. The interface circuit 1420 may be implemented by any type of interface standard, such as an Ethernet interface, Universal Serial Bus (USB), Interface, near field communication(NFC) interface and/or PCI express interface.

In the illustrated example, one or more input devices 1422 are connected to the interface circuit 1420. Input device(s) 1422 allow a user to enter data and/or commands to processor 1412. The input device(s) may be implemented by, for example, an audio sensor, a microphone, a camera (still or video), a keyboard, a button, a mouse, a touch screen, a track pad, a track ball, an isopoint, and/or a voice recognition system.

One or more output devices 1424 are also connected to the interface circuit 1420 of the illustrated example. The output devices 1424 may be implemented, for example, by display devices (e.g., Light Emitting Diodes (LEDs), Organic Light Emitting Diodes (OLEDs), Liquid Crystal Displays (LCDs), cathode ray tube displays (CRTs), in-situ switch (IPS) displays, touch screens, etc.), tactile output devices, printers, and/or speakers. Thus, the interface circuit 1420 of the illustrated example generally includes a graphics driver card, a graphics driver chip, and/or a graphics driver processor.

The interface circuit 1420 of the illustrated example also includes communication devices, such as transmitters, receivers, transceivers, modems, residential gateways, wireless access points, and/or network interfaces to facilitate the exchange of data with external machines (e.g., any kind of computing device) via the network 1426. The communication may be via, for example, an ethernet connection, a Digital Subscriber Line (DSL) connection, a telephone line connection, a coaxial cable system, a satellite system, a line-of-site (line-of-site) wireless system, a cellular telephone system, or the like.

The processor platform 1400 of the illustrated example also includes one or more mass storage devices 1428 for storing software and/or data. Examples of such mass storage devices 1428 include floppy disk drives, hard disk drives, compact disk drives, blu-ray disk drives, Redundant Array of Independent Disks (RAID) systems, and Digital Versatile Disk (DVD) drives.

The machine-executable instructions 1432 of fig. 8 and 9 may be stored in the mass storage device 1428, in the volatile memory 1414, in the non-volatile memory 1416, and/or on a removable, non-transitory computer-readable storage medium, such as a CD or DVD.

From the foregoing, it should be appreciated that example methods, apparatus, and articles of manufacture have been disclosed that improve the efficiency in sensing and/or otherwise reading bits stored in a memory. In examples disclosed herein, access time and cycle time are improved when sensing and/or otherwise reading bits stored in OTP memory. Thus, in some examples disclosed herein, improved access times and cycle times allow for efficient operation of OTP memory when sensing and/or otherwise reading bits stored in OTP memory, regardless of whether shadow volatile memory is utilized. The disclosed methods, apparatus, and articles of manufacture improve the efficiency of using a computing device by replicating a bit current and sensing a memory bit in an OTP memory compared to a reference current. Further, the sensing circuit is initialized to read a logic high value. By replicating the bit current using a current mirror, the sensing time (e.g., access time and/or cycle time) of the OTP memory is improved. The disclosed methods, apparatus, and articles of manufacture are accordingly directed to one or more improvements in the operation of computers.

Example methods, apparatus, systems, and articles of manufacture to improve performance when reading one-time programmable memory are disclosed herein. Further examples and combinations thereof include the following:

example 1 includes an apparatus comprising: a current mirror comprising a first terminal and a second terminal, the first terminal configured to be coupled to a memory; a logic gate including an input terminal coupled to the second terminal of the current mirror; a first transistor comprising a first current terminal and a second current terminal, the first current terminal of the first transistor being coupled to the input terminal of the logic gate, the second current terminal of the first transistor being coupled to the ground rail; and a second transistor comprising a first current terminal and a second current terminal, the first current terminal of the second transistor configured to be coupled to a power supply rail, the second current terminal of the second transistor coupled to the input terminal of the logic gate.

Example 2 includes the apparatus of example 1, wherein the current mirror comprises: a third transistor comprising a first current terminal, a second current terminal, and a gate terminal, the first current terminal of the third transistor being coupled to the first terminal of the current mirror; and a fourth transistor comprising a first current terminal, a second current terminal, and a gate terminal, the second current terminal of the fourth transistor being coupled to the second terminal of the current mirror, and the gate terminal of the fourth transistor being coupled to the gate terminal of the third transistor.

Example 3 includes the apparatus of example 2, wherein the first current terminal of the third transistor is coupled to a gate terminal of the third transistor.

Example 4 includes the apparatus of example 1, wherein the current mirror is configured to boost a bit current obtained from the memory.

Example 5 includes the apparatus of example 1, wherein the logic gate further comprises an output terminal configured to be coupled to a computing system.

Example 6 includes the apparatus of example 1, wherein the first transistor further comprises a gate terminal configured to be coupled to the controller.

Example 7 includes the apparatus of example 1, wherein the second transistor further comprises a gate terminal configured to be coupled to a controller.

Example 8 includes the apparatus of example 1, wherein the logic gate is configured to compare the first current conducted through the current mirror to the second current conducted through the second transistor.

Example 9 includes the apparatus of example 8, wherein the first current is a bit current obtained from a memory, and wherein the second current is a reference current.

Example 10 includes the apparatus of example 1, wherein the first transistor is configured to initialize the input terminal of the logic gate to a logic low value.

Example 11 includes the apparatus of example 1, wherein the memory is rated for a first voltage, and wherein the current mirror, the first transistor, the second transistor, and the logic gate are rated for a second voltage.

Example 12 includes the apparatus of example 11, wherein the first voltage is greater than the second voltage.

Example 13 includes the apparatus of example 1, wherein the memory is a one-time programmable (OTP) memory.

Example 14 includes a method of sensing a memory, the method including initializing an output of a sensing circuit to a first logic high value, obtaining a first current from the memory corresponding to a memory bit stored in the memory, copying the first current, determining whether the copied first current is greater than a second current, and generating a second logic high value at the output of the sensing circuit in response to determining that the copied first current is greater than the second current.

Example 15 includes the method of example 14, wherein the second current is a reference current.

Example 16 includes the method of example 14, wherein the output of the sensing circuit is initialized to the first logic high value by initializing an input of the logic gate to a logic low value.

Example 17 includes the method of example 14, further comprising generating a logic low value at an output of the sensing circuit in response to determining that the replicated first current is less than the second current.

Example 18 includes the method of example 14, wherein the memory is a one-time programmable (OTP) memory.

Example 19 includes the method of example 14, wherein the first current is replicated using a current mirror.

Example 20 includes the method of example 14, further comprising transmitting a second logic high value at the output of the sensing circuit to the computing system.

Although certain example methods, apparatus, and articles of manufacture have been disclosed herein, the scope of coverage of this patent is not limited thereto. On the contrary, this patent covers all methods, apparatus, and articles of manufacture fairly falling within the scope of the appended claims either literally or under the doctrine of equivalents.