阅读说明：本技术 实现互连冗余的嵌入式快闪存储器体系结构 (Embedded flash memory architecture for implementing interconnect redundancy ) 是由 A·特罗亚 A·蒙代洛 于 2019-05-31 设计创作，主要内容包括：本公开涉及一种存储器体系结构,包括多个存储单元子阵列、多个连接到所述子阵列的读出放大器；多个原始焊盘；至少一个冗余焊盘；多条数据线；和连接到所述多个原始焊盘、所述多个冗余焊盘和所述数据线的冗余寄存器,当发现寻址的原始焊盘有缺陷时,所述冗余寄存器实现互连冗余并且将所述冗余焊盘的中一个连接到所述数据线。本公开还涉及包括存储器体系结构的片上系统SoC组件和包含在所述存储器体系结构中的互连冗余管理块。还描述了一种用于管理所述存储器体系结构和/或SoC的互连冗余的方法。(The present disclosure relates to a memory architecture comprising a plurality of sub-arrays of memory cells, a plurality of sense amplifiers connected to the sub-arrays; a plurality of original pads; at least one redundant pad; a plurality of data lines; and a redundancy register coupled to the plurality of original pads, the plurality of redundancy pads, and the data line, the redundancy register implementing interconnection redundancy and coupling one of the redundancy pads to the data line when the addressed original pad is found to be defective. The present disclosure also relates to a system-on-chip SoC component comprising a memory architecture and an interconnect redundancy management block comprised in said memory architecture. A method for managing interconnect redundancy of the memory architecture and/or SoC is also described.)

1. A memory architecture, comprising:

-a plurality of sub-arrays of memory cells,

-a plurality of sense amplifiers connected to said sub-arrays;

-a plurality of original pads;

-at least one redundant pad;

-a plurality of data lines; and

a redundancy register connected to the plurality of original pads, the plurality of redundant pads and the data line,

the redundancy register is configured to implement interconnect redundancy and connect the at least one redundancy pad to the data line when the addressed original pad is found to be defective.

2. The memory architecture of claim 1, wherein said redundancy register includes a first portion for indicating usage of said at least one redundancy pad by storing a redundancy flag.

3. The memory architecture of claim 2, wherein the redundancy register further comprises a second portion for storing an address of a defective original pad to be switched with one of the redundant pads.

4. The memory architecture of claim 3, wherein said redundancy register further comprises a third portion for storing an address of said at least one redundancy pad.

5. The memory architecture of claim 4, further comprising a selection circuit connected to said redundancy register, said original pad, and said at least one redundancy pad to implement said interconnect redundancy.

6. The memory architecture of claim 5, wherein the selection circuit comprises:

-a first switch interposed between said data line and one of said original pads;

-a second switch interposed between said data line and said at least one redundancy pad;

-an inverting gate receiving a first redundancy signal associated with the redundancy flag stored in the first portion of the redundancy register and asserting an inverted value to command the first switch;

-an and logic gate receiving the first and second redundant signals associated with the address stored in the third portion of the redundant register and providing a combined value to command the second switch.

7. The memory architecture of claim 6, further comprising a MUX that receives the address stored in the third portion of the redundancy register to replace the defective pad whose address is stored in the second portion of the redundancy register.

8. An interconnect redundancy management block comprising:

-an interconnect redundancy management block connected to a plurality of original pads, one or more redundant pads and a plurality of data lines for memory cells; and

-a selection circuit connected to the redundancy register, the original pad and the one or more redundancy pads,

the interconnect redundancy management block is configured to replace an original pad found to be defective with a redundant pad of the one or more redundant pads.

9. The interconnect redundancy management block of claim 8, wherein the redundancy register comprises:

-a first portion for indicating a usage of at least one of the one or more redundant pads by storing a redundancy flag;

-a second part for storing an address of a defective original pad to be switched with one of the redundant pads; and

-a third portion for storing an address of one of the one or more redundant pads.

10. The interconnect redundancy management block of claim 9, wherein the selection circuit comprises:

-a first switch interposed between said data line and one of said original pads;

-a second switch interposed between the data line and one of the one or more redundancy pads;

-an inverting gate receiving a first redundancy signal associated with the redundancy flag stored in the first portion of the redundancy register and asserting an inverted value to command the first switch;

-an and logic gate receiving the first and second redundant signals associated with the address stored in the third portion of the redundant register and providing a combined value to command the second switch.

11. The interconnect redundancy management block of claim 10, further comprising a MUX to receive the redundant pad address stored in the third portion of the redundancy register to replace the defective pad address stored in the second portion of the redundancy register.

12. A method for managing interconnect redundancy for a memory architecture including a plurality of sub-arrays of memory cells and a plurality of primitive pads, comprising the steps of:

-verifying whether one of said original pads is functioning correctly; and is

-connecting the original pad to a plurality of data lines if the original pad is functioning correctly; or

-connecting a redundant pad to said data line if said original pad is not functioning correctly.

13. The method of claim 12, further comprising the steps of:

-storing a redundancy flag in a first portion of the redundancy register to indicate the usage of redundant pads;

-storing in a second part of the redundancy register the address of a defective original pad to be switched with the redundant pad; and

-storing an address of the redundant pad in a third portion of the redundant register to address the redundant pad when the original pad is defective due to incorrect operation.

14. A system-on-chip, SoC, component comprising a memory device, and the memory device in turn comprising:

-a plurality of sub-arrays of memory cells,

-a plurality of sense amplifiers connected to said sub-arrays;

-a plurality of original pads;

-a plurality of redundant pads;

-a plurality of data lines; and

a redundancy register connected to the plurality of original pads, the plurality of redundant pads and the data line,

the redundancy register implements interconnect redundancy and connects one of the redundancy pads to the data line when the addressed original pad is found to be defective.

15. The SoC component of claim 14, wherein the redundancy register comprises:

-a first portion for indicating the usage of one of said redundant pads by storing a redundancy flag;

-a second part for storing an address of a defective original pad to be switched with one of the redundant pads; and

-a third portion for storing an address of one of said redundant pads for addressing said one of said redundant pads.

16. The SoC component of claim 15, further comprising a selection circuit coupled to the redundancy register, the original pad, and the redundant pad to implement the interconnect redundancy.

17. The SoC component of claim 16, wherein the selection circuit comprises:

-a first switch interposed between said data line and one of said original pads;

-a second switch interposed between the data line and one of the redundancy pads;

-an inverting gate receiving a first redundancy signal associated with the redundancy flag stored in the first portion of the redundancy register and asserting an inverted value to command the first switch;

-an and logic gate receiving the first and second redundant signals associated with the address stored in the third portion of the redundant register and providing a combined value to command the second switch.

18. The SoC component of claim 17, further comprising a MUX to receive the redundant pad address stored in the third portion of the redundancy register to replace the defective pad address stored in the second portion of the redundancy register.

Technical Field

The present disclosure relates to flash memory architectures, and more particularly to flash memory architectures that implement interconnect redundancy.

Background

Non-volatile memory may provide persistent data by retaining stored data when not powered, and may include NAND flash memory, NOR flash memory, Read Only Memory (ROM), electrically erasable programmable ROM (eeprom), erasable programmable ROM (eprom), and variable resistance memory, such as Phase Change Random Access Memory (PCRAM), self-selecting chalcogenide-based memory, Resistive Random Access Memory (RRAM), and 3DXPoint memory (3DXP) and Magnetoresistive Random Access Memory (MRAM), among others.

More specifically, flash memory is a type of non-volatile memory that retains stored data and is characterized by very fast access times. Furthermore, it can be erased in blocks, rather than one byte at a time. Each erasable memory block includes a plurality of non-volatile memory cells arranged in a matrix of rows and columns. Each cell is coupled to an access line and/or a plurality of data lines. Cells are programmed and erased by manipulating the voltages on the access lines and the data lines.

Non-volatile flash memory is one of the basic building blocks of modern electronic systems today, particularly the real-time operating system (RTOS). The operation of non-volatile flash memory is managed by a controller containing embedded firmware, such controller performing the required write/read/erase operations.

The memory cells are prone to defects, i.e. in very active lithography nodes. Redundancy is used to bypass defective cells and repair memory architectures that fail during the test phase or show failure in the field to achieve so-called immediate redundancy. The root cause of the defects may be different, i.e. depleted cells, defective oxides in the cells, defects in the connection with the physical cell, e.g. due to via breakage, shorted end cups, oxide defects, etc.

In NOR memory devices, redundancy is typically done column-wise. Specifically, redundancy repairs a local defect by changing a physical column including one cell or a plurality of cells having the defect to another physical column having no defects, the redundant column being generally located at a boundary area of the memory array.

The implementation of redundancy may be accomplished by linking the defective column address with the target new address of the redundant column, so that when the defective column is addressed, the memory device will enable redundancy to store/read the contents of a different redundant column that is not defective.

Currently, complex semiconductor architecture technology known as system on a chip (SoC) integrates at least one embedded non-volatile memory in the system. However, with current technology, embedded memory is becoming a large macro instruction in the SoC, and increasing the size (e.g., beyond 128Mbit) is ineffective. In other words, embedded memories today exhibit a minimum non-integratable density.

In other words, embedded memory in a SoC is increasingly difficult to manage when the lithography node is below a technology limit (e.g., below 28 nm).

The connection between the embedded memory and the rest of the SoC also causes defect problems related to the contact between the memory pads and the system.

Therefore, regardless of the redundancy strategy applied to flash memory architectures, large connected devices that are flash memory within SoC (also known as embedded flash memory replacement) can be defective due to interconnectivity.

The presence of interconnect pad defects can completely compromise the operation of the SoC including the flash memory, wasting a significant amount of money because the SoC, embedded flash memory, and package will be discarded, and the corresponding silicon costs are completely wasted.

Therefore, there is a need to provide a solution to the defects associated with the interconnect pads of embedded flash memories and socs, allowing for the repair of already stacked devices and increasing the yield of the manufacturing process of such systems.

Drawings

FIG. 1A shows a block diagram of a flash memory sub-array including sense amplifiers and boundary cells;

FIG. 1B shows an enlarged view of a detail of the flash memory sub-array of FIG. 1A;

FIG. 2A illustrates a redundancy register implementing single pad interconnect redundancy in accordance with an embodiment of the present disclosure;

FIG. 2B illustrates a redundancy register implementing multi-pad interconnect redundancy in accordance with an embodiment of the present disclosure;

FIG. 2C illustrates a flash memory architecture implementing interconnect redundancy using the redundancy registers of FIG. 2A, according to an embodiment of the present disclosure;

FIGS. 3A and 3B illustrate different operating states of a selection circuit of a flash memory architecture implementing interconnect redundancy using the redundancy register of FIG. 2A, according to an embodiment of the present disclosure;

fig. 4 and 5 illustrate exemplary methods for managing interconnect redundancy for a memory architecture according to embodiments of the present disclosure.

Detailed Description

Referring to those figures, a memory architecture including an array of memory cells, particularly a flash memory array provided with selection circuitry to implement interconnect redundancy, will be disclosed herein.

The example embodiment of FIG. 1A is a memory architecture 100 including a flash memory sub-array 110 that includes a plurality of sub-arrays each having the same structure.

More specifically, the flash memory sub-array 110 is connected to a sense amplifier 120, which is in turn connected to a boundary or Jtag cell 130, capable of managing input and output serial data SIN and SOUT, and input and output parallel data PIN and POUT, respectively.

The output parallel data POUT is provided to a SoC (not shown) that includes the memory architecture 100. Memory architecture 100 is connected to the SoC using any packaging technique.

As shown in fig. 1B, a low signal count interface 140 with the ability to modify the internal contents of flash memory sub-array 110, particularly one that uses functional pins and corresponding signals TDI, TDO, tms, tck, trst according to the Jtag protocol, may also be included within memory architecture 100, between sense amplifier 120 and the SoC, connected to a Jtag cell 130, whose parallel output POUT forms an interconnect channel 150 with the SoC.

As will be explained in the following description, memory architecture 100 implements interconnect redundancy that is capable of remedying the defects associated with the interconnect between memory architecture 100 and the Soc that includes it. Redundancy is duplicated for each sub-array of the memory architecture, the sub-array output being an interconnect channel 150 with SoC, not shown.

Specifically, interconnect defects are associated with defective pads or connections between defective pads, and the memory architecture 100 according to embodiments of the present disclosure provides redundancy for all pads that may have defective or defective connections.

According to the subdivision of the memory architecture into multiple sub-arrays, 168 pads per channel is the current target implementation for embedding the flash memory architecture in the SoC. Suitably, the present disclosure is directed to a memory architecture 100 that manages one or more defects on any of 168 pads.

To implement interconnect redundancy, memory architecture 100 suitably includes redundancy registers 200, shown schematically in FIG. 2A. The redundancy register 200 is addressed using the Jtag port in the case of factory redundancy and the flash controller or host in the case of field redundancy to properly set the redundancy with or without the low pin count interface 140 (such as the Jtag interface).

Specifically, as shown in FIG. 2A, for each extended page of the flash memory sub-array 110, the redundancy register 200 receives from the communication channel the bit address of the addressed memory cell of the flash memory sub-array 110 connected to the corresponding addressed pad by a number of bits (e.g., 8 bits) sufficient to identify the defective pad to be able to address 256 potentially defective pads, which is sufficient for the example embodiment of 168 pads per channel, so that one defective pad can be managed. The bond pad bar for each flash memory sub-array 110 is shown as 210 in figure 2A.

Redundancy register 200 uses the Jtag interface to store information that enables redundancy; when field redundancy (also referred to as immediate redundancy) is implemented and available, the registers may be programmed at the factory and/or by the flash memory controller and/or the SoC. More specifically, when instant redundancy is implemented, the Jtag and/or SoC and/or host may be used to program the registers.

Further, when latched, the address bus serves as a read address in the original data buffer associated with the original address buffer.

As will be apparent from the following description, the redundancy register 200 implements a logic interception flaw that is always on and compares any address used by each flash memory sub-array 110 of the memory architecture 100 and the SoC in which it is embedded to ensure that data is properly routed to the SoC.

When single pad redundancy is implemented, according to the embodiment shown in fig. 2A, redundancy register 200 includes a first portion 220 to store a 1-bit redundancy flag (on/off) indicating the use of redundancy, a second portion 230 to store the location or address of a defective pad among 168 pads, and a third portion 240 to store yet another location or address of a spare pad used as a redundancy resource.

When implementing multi-pad redundancy, according to the embodiment shown in fig. 2B for up to 4-pad redundancy, redundancy register 200 includes a first portion 220, a 1-bit redundancy flag (on/off) to indicate the use of redundancy, a second portion 230, including 4 (in the example described herein) bit groups to store four locations or addresses of defective ones of the 168 pads (e.g., each group containing 8 bits to be able to address 256 possible combinations to address one of the 168 potentially defective pads), and a third portion 240 to store yet another location or address of four spare pads for use as redundancy resources.

It can be noted that multi-pad redundancy is thus achieved by adding the defective pad location field of the second part 230 and by adding the redundant resource bits of the third part 240; according to an example, referring to the embodiment shown in fig. 2B, the defective pad location field is 8 bits, so the second portion 230 is 8 bits by 4, i.e. the number of pads available for redundancy, and likewise, the redundant resource bits are up to 4, each bit can intercept a failing pad in the channel according to the following logic:

bit 0: redundant resource pad 0

Bit 1: redundant resource pad 1

Bit 2: redundant resource pad 2

Bit 3: redundant resource pad 3

More specifically, according to the single pad redundancy embodiment of the present disclosure, only spare pads are used, and the third portion 240 is a 1-bit field, which is essentially a further flag. In some embodiments, such a third portion or further flag is not used, and the unique redundant resource pad is activated directly; for example, the pads may be hard wired. According to a multi-pad redundancy embodiment, using more than one spare pad, third portion 240 is larger than one bit, e.g., a 4-bit field enables up to four redundant locations or addresses of spare pads, and four 8-bit fields of second portion 230.

It can therefore be noted that the first portion 220 of redundancy register 200 is a flag indicating that redundancy is on, the second portion 230 of redundancy register 200 is a defective area of the pad, and the third portion 240 of redundancy register 200 is a redundant resource field.

According to this embodiment, when a pad is found to be defective, its address is stored in the second portion 230 and the redundancy flag of the first portion 220 is enabled (turned on), so that one of the redundancy pads that has been enabled by a further enable signal stored in the third portion 240 is switched with the defective pad. In other words, when the redundancy flag of the first portion 220 is on, the corresponding logic intercept defect is always on, and any address used by each flash memory sub-array 110 is compared to replace the address of the memory cell corresponding to the pad found to be defective.

Specifically, the redundancy flag of the first portion 220 is on, and the contents of the third portion 240, which is a redundant resource, are used to send data to the SoC.

During normal operation, monitoring the range of the pads and comparing the range with the range of the defective pad location segment of the entire enabled redundancy register; when addressing a defective location, a switch with redundant resources is performed, checking the self-status of the redundant flag of the first part 220: enabled or disabled, i.e., turned on or off.

With the enable state set (on), the redundant pads whose addresses are stored in the third portion 240 are routed using the multi-channel MUX to replace the defective pads whose addresses are stored in the second portion 230.

The redundancy register 200 is duplicated in each sub-array, and the contents of the respective portions 220, 230, and 240 are stored in the flash memory configuration area because the respective storage data is stored only once as other setting data.

As already noted, according to embodiments of the present disclosure, after the flash memory architecture 100 and its embedded SoC are powered on, redundancy is always turned on in order to continuously monitor the communication channel, i.e., taking 168 pads as an example in this description.

In the case of the multi-layer memory structure 100, a defective pad will replace all levels or pages connected to the defective pad.

For example, in the case of an embedded flash memory replacement architecture, as schematically shown in FIG. 2C, redundancy register 200 (also denoted as Red _ R) is typically divided into a high page 200H and a low page 200L.

According to the interconnect redundancy mechanism described above, if a defective pad is found and the redundancy flag of the first portion 220 is enabled (turned on), the redundancy register 200 is used to replace the original cell address 230H with the redundant cell address 240H in the upper page 200H and the original cell address 230L with the redundant cell address 240L in the lower page 200L. Pad redundancy applies to all extended pages of a sub-array and any data therein in terms of flexible TDI if defects exist in the pads used.

Specifically, when the redundancy flag 220 is enabled or turned on, the MUX 250 will receive the output parallel data POUT of the redundant cells 240H and 240L instead of the output parallel data POUT of the original cells 230H and 230L. The MUX 250 functionality is described below with reference to fig. 3A and 3B.

As shown in fig. 3A, the memory architecture 100 may specifically include a selection circuit 300 for implementing interconnect redundancy in accordance with embodiments of the present disclosure.

Specifically, selection circuit 300 is connected to pads of memory architecture 100, represented as original pad OP and at least one redundant pad RP, and receives address and enable signals from redundancy register 200.

More specifically, the selection circuit 300 includes a first switch SW1 interposed between the plurality of data lines DL and the original pad OP and a second switch SW2 interposed between the data lines DL and the redundant pad RP. The first switch SW1 is driven by a first redundant signal RS1, which is the inverted value of the redundant flag stored in the first portion 220 of the redundant register 200 obtained by the inverting gate INV, and the second switch SW2 is driven by a combination between the first redundant signal RS1 and a second redundant signal RS2 stored in the third portion 240 of the redundant register 200 obtained by a logic gate LG, which is an and gate.

In the example embodiment of fig. 3A, the communication channel provides an address to the redundancy register 200, which corresponds to the bit found connected to the original pad OP in correct operation, whose address AddOP is stored in the second portion 230 of the redundancy register 200. Specifically, bit #4(000 … … 1000) of the memory page is connected to the "correct" pad, i.e., the original pad OP without defects.

In this case, the enable flag stored in the first portion 220 is set equal to 1, such that the first redundancy signal RS1 is set equal to 0 and the first switch SW1 is closed by an inverted value equal to 1. Further, independently of the value of the second redundancy signal RS2, the logic gate LG opens the second switch SW2 as the first redundancy signal RS1 is set equal to 0.

Thus, the data of the data line DL is supplied to the original pad OP in a correct operation.

In the example embodiment of fig. 3B, the communication channel provides an address to the redundancy register 200, which corresponds to the bit found connected to the defective original pad OP, whose address AddOP is stored in the second portion 230 of the redundancy register 200. Specifically, bit #4(000 … … 1000) of the memory page is connected to a "bad" pad, i.e., the defective original pad OP.

In this case, the enable flag stored in the first portion 220 is set equal to 0, so that the first redundancy signal RS1 is set equal to 1 and the first switch SW1 is opened by an inverted value equal to 0. Further, the value of the second redundant signal RS2 is set equal to 1, so that the logic gate LG, which also receives the first redundant signal RS1 set equal to 1, closes the second switch SW 2.

In this way, the data of the data line DL is supplied to the redundant pad RP, thus effectively bypassing the original pad OP that is not operating correctly.

Redundancy register 200 and selection circuit 300 thus form an interconnect redundancy management block included in memory architecture 100.

Although the exemplary configuration shown in fig. 3A and 3B involves a single defective pad, immediately verifying whether the selection circuit 300 can implement the proposed interconnect redundancy for any number of defective pads (up to 168) by increasing the number of registers to store the defective pads and new pads.

Memory architecture 100 may be included in, inter alia, embedded, system-on-a-chip (SoC) components, and interconnect redundancy may be applicable to pads connected to the SoC.

FIG. 4 schematically illustrates an exemplary method for managing interconnect redundancy for a memory architecture 100 including a plurality of sub-arrays of memory cells and a plurality of original pads OP, the method 400 including the steps of:

-step 410: verifying whether one of the original pads OP is operating correctly; and

-step 420: connecting the original pad OP to the plurality of data lines DL if the original pad OP is operating correctly; or

-step 430: if the original pad OP is not functioning properly, the redundant pad RP is connected to the data line DL.

More specifically, referring to fig. 5, the method 500 includes the steps of:

-step 510: storing redundancy-enabled information using a Jtag interface;

-step 520: storing a redundancy flag in a first portion 220 of redundancy register 200 to indicate the use of redundancy pad RP; the first redundancy signal RS1 is associated with a redundancy flag;

-step 530: the address of the defective original pad OP to be switched with the redundancy pad RP is stored in the second part 230 of the redundancy register 200; and

-step 540: will be stored in the third portion 240 of the redundancy register 200 to address the redundancy pad RP when the original pad OP is defective due to incorrect functioning; the second redundancy signal RS2 is associated with the address stored in the third portion 240.

It should be noted that redundancy register 200 includes only one redundancy flag per flash memory sub-array 110. In particular, in the event that multiple locations are defective, redundant flags of redundancy are not repeatedly enabled.

In summary, the present disclosure provides a memory architecture comprising a plurality of sub-arrays, each having an interconnect redundancy mechanism implemented by a selection circuit connected to a redundancy register.

In this way, potential defects and/or lifetime defects may be repaired on-the-fly by the SoC, including the memory architecture, using firmware routines that are capable of properly controlling the redundancy registers and thus the selection circuitry coupled thereto.

It is emphasized that the number of redundant pads used can be customized as desired by simply managing the addresses and enable flags to be stored.

The exemplary memory architecture that implements interconnect redundancy also improves the security of the memory and Soc; in particular, interconnect redundancy allows errors due to defective or defectively connected pads to be reset, thereby increasing ECC coverage, which protects the system from single defects.

In addition, interconnect redundancy is replicated as appropriate for each subarray of the memory architecture.

It should also be noted that the redundancy registers (particularly those implemented in embedded flash memory replacement devices) are located in the SoC where the bits of the read page are rerouted elsewhere.

Thus, interconnect redundancy is a transparent strategy.

In addition, the use of the low signal count interface 140 or the Jtag interface to address redundant registers, with or without the flexible TDI, is a programmable option to improve the performance of the overall memory architecture.

The size of the redundancy register will depend on the number of possible redundancy pads, full interconnect redundancy being theoretically possible.

In practical implementations, the number of possible redundant pads and defects that can be repaired is limited in view of yield studies and/or pad topology. In some embodiments, each channel (150 or 210) has its own redundant pad resource to repair one or more defective pads (of the 168 pads in the above example). In other embodiments, the redundant pad resources may be shared between different channels; for example, spare pad resources for redundancy may be addressed to redundancy defective pads in any interconnect channel of the system. For example, redundancy registers 200 for different channels may flag that redundancy is enabled (in first portion 220), store the address of the failing pad (in second portion 230), and store (in third portion 240) the location or address of the spare pad that is used as a redundant resource, which is a shared resource.

Finally, it is emphasized that the defective pads are also stored in the SoC, so that the content of the defective pads in the redundant pads can be read instead of the content of the original pads.

In the foregoing detailed description, reference is made to the accompanying drawings that form a part hereof, and in which is shown by way of illustration specific examples. In the drawings, like numerals describe substantially similar components throughout the several views. Other examples may be utilized and structural, logical, and/or electrical changes may be made without departing from the scope of the present disclosure.

Similar elements or components between different figures may be identified by the use of similar digits. It should be understood that elements shown in the various embodiments herein may be added, exchanged, and/or eliminated so as to provide a number of additional embodiments of the present disclosure. Furthermore, as will be understood, the proportion and the relative scale of the elements provided in the figures are intended to illustrate the various embodiments of the present disclosure, and should not be taken as limiting.

As used herein, "a," "an," or "a plurality" may sometimes refer to one or more of such things. "plurality" of things means two or more. As used herein, the term "coupled" may include electrically coupled, directly coupled, and/or directly connected (e.g., through direct physical contact) without intervening elements or indirectly coupled and/or connected using intervening elements. The term coupled may also encompass two or more elements cooperating or interacting with each other (e.g., in a causal relationship).

Although specific examples have been illustrated and described herein, those of ordinary skill in the art appreciate that an arrangement calculated to achieve the same results can be substituted for the specific embodiments shown. This disclosure is intended to cover adaptations or variations of one or more embodiments of the present disclosure. It is to be understood that the above description is intended to be illustrative, and not restrictive. The scope of one or more examples of the disclosure should be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.