阅读说明：本技术 用于存储器子系统的低功率数据传递 (Low power data transfer for memory subsystems ) 是由 J·徐 D·全 H-J·洛 于 2017-06-28 设计创作，主要内容包括：本公开涉及用于存储器子系统的低功率数据传递。各系统和方法涉及降低处理器与存储器之间的数据传递的功耗。检查要在处理器与存储器之间的数据总线上传递的数据以试图获得第一数据模式,并且如果第一数据模式存在,则第一数据模式在数据总线上的传递被抑制。相反,对应于第一数据模式的第一地址在处理器与存储器之间的第二总线上被传递。第一地址小于第一数据模式。该处理器包括处理器侧先进先出(FIFO),并且该存储器包括存储器侧FIFO,其中第一数据模式存在于处理器侧FIFO中的第一地址处以及存储器侧FIFO中的第一地址处。(The present disclosure relates to low power data transfers for memory subsystems. Systems and methods are directed to reducing power consumption for data transfers between a processor and a memory. Data to be transferred on a data bus between the processor and the memory is checked in an attempt to obtain a first data pattern, and if the first data pattern exists, the transfer of the first data pattern on the data bus is suppressed. Instead, a first address corresponding to the first data pattern is communicated on a second bus between the processor and the memory. The first address is less than the first data pattern. The processor includes a processor-side first-in-first-out (FIFO), and the memory includes a memory-side FIFO, wherein the first data pattern exists at a first address in the processor-side FIFO and at a first address in the memory-side FIFO.)