阅读说明：本技术 具有横向尺寸不同的子鳍延伸区的带鳍ic结构 (Finned IC structure with sub-fin extension regions of different lateral dimensions ) 是由 谷曼 李文君 S·纳拉亚南 于 2021-06-22 设计创作，主要内容包括：本发明涉及具有横向尺寸不同的子鳍延伸区的带鳍IC结构。一种集成电路(IC)结构包括具有第一纵向延伸区和第二纵向延伸区的半导体鳍。该半导体鳍具有：上鳍部,其在第一纵向延伸区和第二纵向延伸区中具有统一的横向尺寸；位于上鳍部下方的第一子鳍部,其在第一纵向延伸区中且具有第一横向尺寸；以及位于上鳍部下方的第二子鳍部,其在第二纵向延伸区中且具有不同于第一横向尺寸的第二横向尺寸。第二子鳍可用于横向扩散金属氧化物半导体(LDMOS)器件的漏极扩展区中。无论LDMOS器件的类型如何,第二子鳍都减小了子鳍电流,并且提高了HCI可靠性。(The invention relates to a finned IC structure having sub-fin extensions of different lateral dimensions. An Integrated Circuit (IC) structure includes a semiconductor fin having a first longitudinally extending region and a second longitudinally extending region. The semiconductor fin has: an upper fin portion having a uniform lateral dimension in the first and second longitudinally extending regions; a first sub-fin portion located below the upper fin portion, in the first longitudinally extending region, and having a first lateral dimension; and a second sub-fin portion located below the upper fin portion, in the second longitudinally extending region, and having a second lateral dimension different from the first lateral dimension. The second sub-fin may be used in a drain extension region of a Laterally Diffused Metal Oxide Semiconductor (LDMOS) device. The second sub-fin reduces sub-fin current and improves HCI reliability regardless of the type of LDMOS device.)

1. An Integrated Circuit (IC) structure, comprising:

a semiconductor fin having a first longitudinally extending region and a second longitudinally extending region, the semiconductor fin having:

an upper fin having a uniform lateral dimension in the first longitudinally extending region and the second longitudinally extending region,

a first sub-fin portion located below the upper fin portion, in the first longitudinally extending region, and having a first lateral dimension, an

A second sub-fin located below the upper fin in the second longitudinally extending region and having a second lateral dimension different from the first lateral dimension.

2. The IC structure of claim 1, wherein the second lateral dimension is less than the first lateral dimension.

3. The IC structure of claim 2, wherein the second sub-fin has an outer surface that curves inward.

4. The IC structure of claim 1, wherein each sub-fin is located within a trench isolation, wherein the trench isolation has a bulbous cross-sectional shape adjacent to the second sub-fin.

5. The IC structure of claim 1, wherein the second sub-fin is located within a drain extension region of a fin Laterally Diffused Metal Oxide Semiconductor (LDMOS) device.

6. The IC structure of claim 5, wherein a portion of the first sub-fin is located within the drain extension region.

7. The IC structure of claim 5, wherein the LDMOS device comprises a first gate structure and a second floating gate structure, wherein the second floating gate structure is located over the drain extension region.

8. The IC structure of claim 5, wherein the LDMOS device comprises trench isolation in an n-well within the drain extension region and adjacent to the drain region.

9. The IC structure of claim 1, wherein the semiconductor fin comprises a plurality of fins.

10. A FinFET LDMOS device comprising:

a semiconductor fin having a first longitudinally extending region and a second longitudinally extending region, the semiconductor fin having:

an upper fin having a uniform lateral dimension in the first longitudinally extending region and the second longitudinally extending region,

a first sub-fin portion located below the upper fin portion, in the first longitudinally extending region, and having a first lateral dimension, an

A second sub-fin portion located below the upper fin portion, in the second longitudinally extending region, and having a second lateral dimension different from the first lateral dimension;

a p-well located in a portion of the first longitudinally extending region;

an n-well located at least in the second longitudinally extending region;

a source region in the p-well;

a drain region in the n-well;

a drain extension region in the n-well, wherein the second sub-fin is located within the drain extension region; and

a first gate structure extending over the p-well and the n-well.

11. The FinFET LDMOS device of claim 10, wherein the second lateral dimension is less than the first lateral dimension.

12. The FinFET LDMOS device of claim 10, wherein the second sub-fin portion has an outer surface that is curved inward.

13. The FinFET LDMOS device of claim 10, wherein each sub-fin is located within a trench isolation, wherein the trench isolation has a bulbous cross-sectional shape adjacent the second sub-fin.

14. The FinFET LDMOS device of claim 10, wherein a portion of the first sub-fin is located within the drain extension region.

15. The FinFET LDMOS device set forth in claim 10 further including a second floating gate structure spaced from said first gate structure, wherein said second floating gate structure is located above said drain extension region.

16. The FinFET LDMOS device set forth in claim 10 further including trench isolation in said n-well within said drain extension region and adjacent said drain region.

17. A method, comprising:

forming a semiconductor fin having a first longitudinally extending region and a second longitudinally extending region, the semiconductor fin having:

an upper fin having a uniform lateral dimension in the first longitudinally extending region and the second longitudinally extending region,

a first sub-fin portion located below the upper fin portion, in the first longitudinally extending region, and having a first lateral dimension, an

A second sub-fin portion located below the upper fin portion, in the second longitudinally extending region, and having a second lateral dimension different from the first lateral dimension; and

a metal gate structure is formed over the semiconductor fin.

18. The method of claim 17, wherein forming the semiconductor fin comprises:

forming a pair of trenches to a first depth in a substrate, the pair of trenches forming the semiconductor fin therebetween;

forming a first mask over the second longitudinally extending region, exposing the first longitudinally extending region;

etching the pair of trenches in the first longitudinally extending region to a second depth deeper than the first depth, thereby forming the first sub-fin having the first lateral dimension;

removing the first mask over the second longitudinally extending region;

forming a spacer layer over the first longitudinally extending region and the second longitudinally extending region;

forming a second mask over the first longitudinally extending region, exposing the second longitudinally extending region;

etching the pair of trenches in the second longitudinally extending region to a third depth deeper than the first depth;

etching the pair of trenches in the second longitudinally extending region to widen the pair of trenches and form the second sub-fin having the second lateral dimension less than the first lateral dimension;

removing the second mask; and

filling the pair of trenches adjacent to the first sub-fin and the second sub-fin with a dielectric.

19. The method of claim 18, wherein the dielectric adjacent to the second sub-fin has a bulbous cross-sectional shape.

20. The method of claim 17, further comprising, prior to forming the metal gate structure:

forming a p-well in a portion of the first longitudinally extending region;

forming an n-well at least in the second longitudinally extending region;

forming a source region in the p-well;

forming a drain region in the n-well; and

a drain extension region is formed in the n-well,

wherein the second sub-fin portion is located within the drain extension region.

Technical Field

The present disclosure relates to power amplifier devices, and more particularly, to Integrated Circuit (IC) structures having semiconductor fins with different longitudinal sub-fin extensions (longitudinal extensions) and with different lateral dimensions.

Background

Radio Frequency (RF) devices employ Laterally Diffused Metal Oxide Semiconductor (LDMOS) devices. An LDMOS device includes a p-well having a source region therein and an n-well having a drain region therein within a semiconductor fin. The gate extends over the p-well and the n-well, with the channel in the p-well and the drain extension in the n-well. LDMOS devices come in many different forms. For example, an LDMOS shallow trench isolation (LDMOS-STI) device includes a Shallow Trench Isolation (STI) within a drain extension region in an n-well of the device, while an LDMOS dummy (dummy) gate (LDMOS-DP) device does not have an STI in the n-well, but includes a second floating (dummy) gate over the drain extension region in the n-well of the device.

For example, LDMOS FinFETs are used as wireless network power amplifiers with 3.3-5 volts of power. One challenge facing these devices is controlling Hot Carrier Injection (HCI). HCI is a condition in electronic devices where electrons (holes) gain enough energy to break interface states to overcome a potential barrier. In an LDMOS FinFET device, carriers may be trapped within the sub-fin region of a fin that is located under the transistor gate and the adjacent trench isolation between adjacent fins. The trapped charged carriers may generate excessive current in the drain extension region and may permanently alter the operating characteristics (e.g., switching characteristics) of the device. HCI therefore presents challenges to the performance and reliability of devices. Current approaches attempt to improve HCI reliability by providing various implants or local trench isolations to reduce sub-fin current. These approaches are complex to implement and may not fully address the issues of all types of LDMOS FinFET devices.

Disclosure of Invention

An aspect of the present disclosure relates to an Integrated Circuit (IC) structure, comprising: a semiconductor fin having a first longitudinally extending region and a second longitudinally extending region, the semiconductor fin having: an upper fin having a uniform lateral dimension in the first and second longitudinally extending regions; a first sub-fin portion located below the upper fin portion, in the first longitudinally extending region, and having a first lateral dimension; and a second sub-fin located below the upper fin, in the second longitudinally extending region, and having a second lateral dimension different from the first lateral dimension.

Another aspect of the present disclosure includes a fin field effect transistor (FinFET) Laterally Diffused Metal Oxide Semiconductor (LDMOS) device comprising: a semiconductor fin having a first longitudinally extending region and a second longitudinally extending region, the semiconductor fin having: an upper fin having a uniform lateral dimension in the first and second longitudinally extending regions; a first sub-fin portion located below the upper fin portion, in the first longitudinally extending region, and having a first lateral dimension; and a second sub-fin portion located below the upper fin portion, in the second longitudinally extending region, and having a second lateral dimension different from the first lateral dimension; a p-well located in a portion of the first longitudinally extending region; an n-well located at least within the second longitudinally extending region; a source region in the p-well; a drain region in the n-well; a drain extension region in the n-well, wherein the second sub-fin is located within the drain extension region; and a first gate structure extending over the p-well and n-well.

Another aspect of the present disclosure relates to a method, comprising: forming a semiconductor fin having a first longitudinally extending region and a second longitudinally extending region, the semiconductor fin having: an upper fin having a uniform lateral dimension in the first and second longitudinally extending regions; a first sub-fin portion located below the upper fin portion, in the first longitudinally extending region, and having a first lateral dimension; and a second sub-fin portion located below the upper fin portion, in the second longitudinally extending region, and having a second lateral dimension different from the first lateral dimension; and forming a metal gate structure over the semiconductor fin.

The foregoing and other features of the disclosure will be apparent from the following more particular description of embodiments of the disclosure.

Drawings

Embodiments of the present disclosure will be described in detail with reference to the following drawings, wherein like reference numerals represent like elements, and wherein:

fig. 1 shows a schematic plan view of an overall layout of an IC structure for describing embodiments of the present disclosure.

Fig. 2A-2B illustrate cross-sectional views of forming a trench pair in a semiconductor substrate according to an embodiment of the present disclosure.

Fig. 3A-3B illustrate cross-sectional views of forming a sub-fin portion within a first longitudinally extending region of a semiconductor fin, according to an embodiment of the present disclosure.

Fig. 4A-4B illustrate cross-sectional views of forming a spacer layer within first and second longitudinally extending regions of a semiconductor fin according to an embodiment of the present disclosure.

Fig. 5A-5B illustrate cross-sectional views of a first etch for forming a second sub-fin portion within a second longitudinally extending region of a semiconductor fin, according to an embodiment of the present disclosure.

Fig. 6A-6B illustrate cross-sectional views of a second etch for forming a second sub-fin portion within a second longitudinally extending region of a semiconductor fin, according to an embodiment of the present disclosure.

Fig. 7A-7B illustrate cross-sectional views of forming a dielectric around a semiconductor fin within first and second longitudinally extending regions of the semiconductor fin according to an embodiment of the present disclosure.

Fig. 8A-8B illustrate cross-sectional views of planarizing and recessing a semiconductor fin according to embodiments of the present disclosure.

Fig. 9 illustrates a cross-sectional view of an IC structure, FinFET and LDMOS device, in accordance with an embodiment of the present disclosure.

Fig. 10 illustrates a cross-sectional view of an IC structure, FinFET and LDMOS device, in accordance with other embodiments of the present disclosure.

It should be noted that the drawings of the present disclosure are not necessarily drawn to scale. The drawings are intended to depict only typical aspects of the disclosure, and therefore should not be considered as limiting the scope of the disclosure. In the drawings, like numbering represents like elements between the drawings.

Detailed Description

In the following description, reference is made to the accompanying drawings which form a part hereof, and in which is shown by way of illustration specific exemplary embodiments in which the present teachings may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the present teachings, and it is to be understood that other embodiments may be utilized and that changes may be made without departing from the scope of the present teachings. Accordingly, the following description is merely illustrative.

It will be understood that when an element such as a layer, region or substrate is referred to as being "on" or "over" another element, it can be directly on the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or "directly over" another element, there are no intervening elements present. It will also be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.

Reference in the specification to "one embodiment" or "an embodiment" of the present disclosure and other variations thereof means that a particular feature, structure, characteristic, and so forth described in connection with the embodiment is included in at least one embodiment of the present disclosure. Thus, the phrases "in one embodiment" or "in an embodiment," as well as any other variations that appear throughout the specification, do not necessarily all refer to the same embodiment. It will be understood that the use of any of the terms "/", "and/or" and "at least one", for example in the context of "a/B", "a and/or B" and "at least one of a and B", is intended to encompass the selection of only the first listed option (a), or only the second listed option (B), or both options (a and B). As other examples, in the case of "A, B and/or C" and "at least one of A, B and C," these phrases are intended to encompass the selection of only the first listed option (a), or only the second listed option (B), or only the third listed option (C), or only the first and second listed options (a and B), or only the first and third listed options (a and C), or only the second and third listed options (B and C), or all three options (a and B and C). This case can be extended for many of the listed items, as will be apparent to those of ordinary skill in the art.

Embodiments of the present disclosure provide an Integrated Circuit (IC) structure for use in, for example, a fin field effect transistor (FinFET). The structure may be used in Laterally Diffused Metal Oxide Semiconductor (LDMOS) devices having advantages suitable for Radio Frequency (RF) applications, such as wireless network power amplifiers. The IC structure includes a semiconductor fin having a first longitudinally extending region and a second longitudinally extending region. The semiconductor fin has an upper fin portion having a uniform lateral dimension in a first longitudinally extending region and a second longitudinally extending region; a first sub-fin portion located below the upper fin portion, in the first longitudinally extending region, and having a first lateral dimension; a second sub-fin located below the upper fin, in the second longitudinally extending region, and having a second lateral dimension different from (e.g., less than) the first lateral dimension. Thus, the semiconductor fin has two sub-fin portions with different lateral dimensions. The sub-fins are within a trench isolation having a bulbous cross-section adjacent to the second sub-fin. The second sub-fin portion reduces sub-fin current in a drain extension region of the LDMOS FinFET regardless of the type of LDMOS device, and thus improves HCI reliability.

Fig. 1-10 are illustrations of methods of forming an Integrated Circuit (IC) structure 100 (fig. 9 and 10) and LDMOS devices 104, 204 (fig. 9 and 10) according to various embodiments of the present disclosure. For purposes of description, the IC structure 100 may be implemented as part of a FinFET 102 (fig. 9 and 10) in the form of LDMOS devices 104, 204 (in fig. 9 and 10, respectively) (i.e., a fin-type LDMOS device). As will be described, embodiments of the present disclosure may be applied to any of a variety of FinFET LDMOS devices, including FinFET LDMOS-STI devices and FinFET LDMOS-DP devices. It is emphasized that the teachings of the present disclosure are also applicable to other types of MOS devices.

Fig. 1 shows a schematic plan view of an overall layout of an IC structure for describing embodiments of the present disclosure. FIG. 1 includes a set of view lines A-A, B-B and C-C that will be referred to for purposes of describing the present disclosure. Fig. 1 shows a semiconductor fin 110 (four fins are actually shown) extending across the page, and a metal gate structure 112 (two portions in this example) extending across the semiconductor fin 110. View line a-a spans the region 114 (denoted by a rectangular box) where a lateral dimension of a sub-fin (not shown in fig. 1) of a longitudinally extending region 118 of the semiconductor fin 110 is different from (i.e., smaller than) a sub-fin in another longitudinally extending region 116 of the semiconductor fin 110. View line B-B spans the semiconductor fin 110 outside of the region 114, where the semiconductor fin 110 does not have sub-fins with varying lateral dimensions, i.e., where the sub-fins have regular lateral dimensions. View line C-C is a cross-sectional view across the semiconductor fin 110, see fig. 9. For any particular stage of the method, the figure number indicates the particular stage, and the figure with the symbol "A" crosses the view line A-A, which shows the longitudinally extending region 118; the drawing with the symbol "B" crosses the line B-B, which shows any longitudinally extending regions 116. Note that the figure with the symbol "B" showing the longitudinally extending region 116 may be a structure of the semiconductor fin 110 on either side of the longitudinally extending region 118, as shown in fig. 1. The figures do not use the symbol "C" because it is not necessary.

Fig. 2A-8B illustrate cross-sectional views of forming a semiconductor fin 110 according to embodiments of the present disclosure. The semiconductor fin 110 has a first longitudinally extending region 116 (in the figure with the symbol "a") and a second longitudinally extending region 118 (in the figure with the symbol "B"). As will be described, the semiconductor fin 110 will eventually have: an upper fin having a uniform lateral dimension in the first and second longitudinally extending regions 116, 118; a first sub-fin located below the upper fin, in the first longitudinally extending region 116, and having a first lateral dimension; a second sub-fin located below the upper fin, in the second longitudinally extending region 118, and having a second lateral dimension different from (e.g., less than) the first lateral dimension. As used herein, the "lateral" dimension indicates a dimension in a non-vertical, perpendicular direction relative to the longitudinal or long axis of the fin. As used herein, "sub-fin" refers to a lower portion of a semiconductor fin to be positioned within trench isolation.

Referring to fig. 2A-2B, a hard mask 120 is formed over a (bulk) semiconductor substrate 122. The hard mask 120 may comprise any now known or later developed layer of masking material, such as Medium Temperature Oxide (MTO) and silicon nitride. The hard mask 120 is patterned to form one or more semiconductor fins 110 (fig. 8A-8B), i.e., includes openings therein to guide the etching of the semiconductor substrate 122 to form the fins. The semiconductor substrate 122 may include, but is not limited to, silicon, germanium, silicon carbide, and substantially composed of one or more of Al, Si, Ge, Si-Ge, SiC, and a combination thereof_X1Ga_X2In_X3As_Y1P_Y2N_Y3Sb_Y4A III-V compound semiconductor constituent material of defined composition, wherein X1, X2, X3, Y1, Y2, Y3 and Y4 represent relative proportions which are respectively greater than or equal to zero and X1+ X2+ X3+ Y1+ Y2+ Y3+ Y4 are 1(1 is the total relative molar amount). Other suitable substrates include those having a composition Zn_A1Cd_A2Se_B1Te_B2Wherein a1, a2, B1, and B2 are relative proportions that are greater than or equal to zero, respectively, and a1+ a2+ B1+ B2 is 1(1 is the total molar amount). Furthermore, part or the whole of the semiconductor substrate may be strained.

Fig. 2A-2B also illustrate cross-sectional views of a pair of trenches 124 formed in semiconductor substrate 122 to a first depth D1. The pair of trenches 124 forms the semiconductor fin 110 therebetween. It should be understood that any number of trenches 124 may be formed to form any number of semiconductor fins 110. In contrast to conventional processing, the first depth D1 is not as deep as the complete semiconductor fin 110. As will be described herein, the first depth D1 is selected to be a depth that: the upper part of the sub-fins with different lateral dimensions will be positioned at this depth. The trench 124 may be formed by etching. The hard mask 120 patterning and trench 124 etching may be selected to define an upper fin 126 having a uniform lateral dimension ULD in the first and second longitudinally extending regions 116, 118. That is, the upper fin portion 126 of the semiconductor fin 110 (fig. 1) has a uniform lateral dimension regardless of position along its length.

Etching generally refers to the removal of material from a substrate (or a structure formed on a substrate) and is typically performed with a mask in place to selectively remove material from certain regions of the substrate while leaving material in other regions of the substrate unaffected. There are generally two types of etching: (i) wet etching and (ii) dry etching. Wet etching is performed with a solvent (e.g., an acid) whose ability to selectively dissolve a given material (e.g., an oxide) while leaving another material (e.g., polysilicon) relatively intact may be selected. This ability to selectively etch a given material is fundamental to many semiconductor manufacturing processes. Wet etching typically etches a homogeneous material (e.g., oxide) isotropically, but wet etching can also etch a single crystal material (e.g., silicon wafer) anisotropically. The dry etching may be performed using plasma. Plasma systems can operate in several modes by adjusting plasma parameters. Conventional plasma etching generates neutrally charged energetic radicals that react at the wafer surface. The process is isotropic as neutral particles attack the wafer from various angles. Ion milling or sputter etching bombards the wafer with energetic ions of a noble gas that approach the wafer from approximately one direction, so the process is highly anisotropic. Reactive Ion Etching (RIE), operating at conditions intermediate between sputtering and plasma etching, can be used to create deep, narrow features, such as trenches 124.

Fig. 3A-3B illustrate cross-sectional views of forming a first mask 130 over the second longitudinally extending region 118 and exposing the first longitudinally extending region 116. The first mask 130 may comprise any now known or later developed mask material, such as a spin-on hard mask (SOH). Fig. 3A-3B also illustrate etching the pair of trenches 124 in the first longitudinally extending region 116 to a second depth D2 that is deeper than the first depth D1 (fig. 2A-2B), thereby forming the first sub-fin 132 having the first lateral dimension LD 1. The second depth D2 is selected as the depth to which the "regular" sub-fins will extend. The first lateral dimension LD1 is comparable in size to the upper fin portion 126, i.e., similar to the etching of a fin that is expected to be completed in one step.

Fig. 4A-4B show cross-sectional views of the first mask 130 removed over the second longitudinally extending region 118. The first mask 130 may be removed using any suitable ashing process and wet strip process. Fig. 4A-4B also illustrate the formation of a spacer layer 134 over the first and second longitudinally extending regions 116, 118. Spacer layer 134 may comprise any now known or later developed spacer material, such as, but not limited to, silicon nitride. The spacer layer 134 may be formed by deposition. "deposition" may include any now known or later developed technique suitable for the material to be deposited, including but not limited to, for example: chemical Vapor Deposition (CVD), low pressure CVD (lpcvd), plasma enhanced CVD (pecvd), sub-atmospheric CVD (sacvd), and high density plasma CVD (hdpcvd), rapid thermal CVD (rtcvd), ultra-high vacuum CVD (uhvcvd), limited reaction processing CVD (lrpcvd), metalorganic CVD (mocvd), sputter deposition, ion beam deposition, electron beam deposition, laser assisted deposition, thermal oxidation, thermal nitridation, spin-on coating, Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), chemical oxidation, Molecular Beam Epitaxy (MBE), plating, evaporation. Here, the spacer layer 134 may be deposited by ALD, for example. As will be described, the spacer layer 134 will also be used to form a collar (collar)136 (fig. 5A).

Fig. 5A-5B illustrate cross-sectional views of forming a second mask 140 over the first longitudinally extending regions 116 and exposing the second longitudinally extending regions 118. The second mask 140 may comprise any now known or later developed mask material, such as a spin-on hard mask (SOH). Fig. 5A shows etching of the trench 124 in the second longitudinally extending region 118 to a third depth D3 that is deeper than the first depth D1 (fig. 2A-2B). The third depth D3 may be deeper or shallower than the second depth D2 (fig. 3B). This etch forms a collar 136 from the spacer layer 134, which then protects the upper fin 126 in the second longitudinally extending region 118. The etch may comprise any suitable anisotropic etch chemistry.

Fig. 6A shows a cross-sectional view of further etching the pair of trenches 124 in the second longitudinally extending region 118 to widen the pair of trenches 124 and form the second sub-fin 142 having a second lateral dimension LD2 that is less than the first lateral dimension LD1 (fig. 3B). The second lateral dimension is also less than the uniform lateral dimension ULD of the upper fin 126. As shown in fig. 6B, the semiconductor fin 110 in the first longitudinally extending region 116 is unchanged during this process. Thus, the semiconductor fins 110 in the first longitudinally extending region 116 have the form of regular semiconductor fins, while the semiconductor fins 110 in the second longitudinally extending region 118 have different lateral dimensions in their sub-fin portions 142 (LD 2). As illustrated in fig. 6A, the trench 124, which is enlarged by the additional etching, has a lower portion with a bulbous cross-sectional shape that forms the narrow sub-fin 142. The etch may include any isotropic etch chemistry and may be controlled in terms of, for example, chemistry, duration, operating parameters, etc., to control the dimensions of the sub-fins 142.

Fig. 7A-7B illustrate cross-sectional views after removal of the second mask 140 (and spacer layer 134) (fig. 5B, 6B), for example, by any suitable ashing process and wet strip process. Fig. 7A-7B also illustrate filling the pair of trenches 124 at least adjacent to the first and second sub-fins 132, 142 with a dielectric 144. As will be described, the dielectric 144 ultimately forms trench isolations 146 (fig. 8A-8B), such as Shallow Trench Isolations (STIs) between the semiconductor fins 110. Dielectric 144 may comprise any now known or later developed interlayer dielectric. Suitable dielectric materials may include, but are not limited to: a carbon-doped silica material; fluorinated Silicate Glass (FSG); an organic polymeric thermoset material; silicon oxycarbide; a SiCOH dielectric; fluorine-doped silicon oxide; spin-coating glass; silsesquioxanes including Hydrogen Silsesquioxane (HSQ), Methyl Silsesquioxane (MSQ), and mixtures or copolymers of HSQ and MSQ; benzocyclobutene (BCB) based polymer dielectrics, as well as any silicon-containing low-k dielectrics. Examples of spin-on low-k films with SiCOH type compositions using silsesquioxane chemistry include HOSP^TM(available from Honeywell), JSR 5109 and 5108 (available from Japan Synthetic Rubber), Zirkon^TM(available from Rohm and Haas division of Shipley Microelectronics), and porous low-k (ELk) Materials (available from Applied Materials). Examples of carbon-doped silica materials or organosilanes include Black Diamond^TM(available from Applied Materials) and Coral^TM(available from Lam Research). Of HSQ materialAn example is FOx^TM(available from Dow Corning). In one non-limiting example, the formation of the dielectric 144 can include performing in-situ steam generation (ISSG) oxidation, polysilicon liner (liner) deposition, Flowable Chemical Vapor Deposition (FCVD) of the dielectric 144, and annealing to improve the quality of the dielectric material. As shown in fig. 7A, the dielectric 144 adjacent to the second sub-fin 142 has a bulbous cross-sectional shape, i.e. it takes the shape of the lower portion of the trench 124 in the second longitudinally extending region 118. In contrast, as is generally contemplated, the dielectric 144 in the first longitudinally extending region 116 will be the straight-walled first sub-fin 132.

Fig. 8A to 8B show sectional views taken along view lines a-a and B-B, respectively, and fig. 9 shows a sectional view taken along view line C-C in fig. 1. Fig. 8A-8B partially illustrate stages after conventional processing, such as, but not limited to, planarization, active area patterning, well implantation, semiconductor fin recessing, and junction annealing (not all shown in fig. 8A-8B). More specifically, the method may include (shown in final form in fig. 9) forming a p-well 152 in a portion of the first longitudinally extending region 116, forming an n-well 154 in at least the second longitudinally extending region 118, forming a source region 160 in the p-well 152, forming a drain region 162 in the n-well 154, and forming a drain extension region 164 in the n-well. The second sub-fin portion 142 (sub-fin shown by dashed box) is within the drain extension region 164. The p-well 152 may include a p-type dopant, which may include, but is not limited to: boron (B), indium (In), and gallium (Ga); the n-well 154 may include n-type dopants, which may include, but are not limited to: phosphorus (P), arsenic (As) or antimony (Sb). The wells 152, 154 may be formed using any now known or later developed semiconductor doping technique (e.g., ion implantation, in-situ doping, etc.). The source/drain regions 160, 162 may be formed using any now known or later developed semiconductor doping technique. For example, the source/drain regions 160, 162 may be formed by masked directional doping, in which ion implantation is performed followed by an anneal to drive in dopants. The source/drain regions 160, 162 may be doped with an n-type dopant, for example, an n-type dopant having a higher dopant concentration than the n-well 154. Since these implantation steps are well known in the art, no further details are provided. In another example, the source/drain regions 160, 162 may be formed by epitaxial growth on the semiconductor fin 110, e.g., after forming the semiconductor fin 110 and a poly gate but before forming a Replacement Metal Gate (RMG). A drain extension region 164 extends from the interface 153 between the p-well 152 and the n-well 154 to the drain region 162. As shown in fig. 8A-8B, after recessing the fins, the dielectric 144 creates trench isolations 146 between the semiconductor fins 110. The cross-section of the trench isolation 146 is bulbous in the second longitudinally extending region 118, but is generally straight-walled in the first longitudinally extending region 116.

Fig. 9 shows a stage after an additional formation of a metal gate structure 112 (e.g., using a Replacement Metal Gate (RMG) process) over the semiconductor fin 110. In fig. 9, the metal gate structure 112 includes a first active gate structure 166 located over a channel 168 in the p-well 152, and a second floating (dummy) gate structure 170 spaced apart from the first gate structure 166 and located over the drain extension region 164. Each metal gate structure 112 may be made of any now known or later developed gate material including, for example, a gate dielectric, a workfunction metal, and a gate conductor (not all shown). It should be understood that additional processing may also be performed, such as, but not limited to, mid-line and back-line interconnect processing.

Fig. 9 also shows an IC structure 100, a FinFET 102, and an LDMOS device 104, in accordance with an embodiment of the present disclosure. Fig. 10 illustrates a cross-sectional view (similar to view line C-C in fig. 1) of another embodiment of an IC structure 100, a FinFET 102, and an LDMOS device 204. In this embodiment, the gate structure 212 is formed with only a single active gate 266 located over the channel 168 and the drain extension region 164. Furthermore, the method may further include forming trench isolation 180 within the drain extension region 164 and adjacent to the drain region 162 in the semiconductor fin 110, i.e., prior to formation of the gate structure, well, and source/drain regions. Trench isolation 180 may take the form of any trench isolation structure to electrically isolate active regions. Trench isolation 180 may be formed using any now known or later developed semiconductor fabrication technique. Typically, trenches 182 are etched in the semiconductor fin 110 and filled with an insulating material such as oxide182 to isolate one region of the semiconductor fin 110 from an adjacent region. Trench isolation 180 may be formed of any now known or later developed substance for providing electrical isolation, and may include, for example: silicon nitride (Si)₃N₄) Silicon oxide (SiO)₂) Fluorinated SiO₂(FSG), hydrogenated silicon oxycarbide (SiCOH), porous SiCOH, borophosphosilicate glass (BPSG), silsesquioxanes, carbon (C) doped oxides (i.e., organosilicates) containing silicon (Si), carbon (C), oxygen (O), and/or hydrogen (H), thermosetting polyarylene ethers, spin-on silicon-containing carbon polymer materials, Near Frictionless Carbon (NFC), or multilayers thereof.

Referring to fig. 9 and 10, the IC structure 100 may include a semiconductor fin 110 having a first longitudinally extending region 116 and a second longitudinally extending region 118. The semiconductor fin 110 may include a single fin or multiple fins. The semiconductor fin 110 also has an upper fin portion 126 having a uniform lateral dimension ULD in the first and second longitudinally extending regions 116, 118 (fig. 8A-8B). The semiconductor fin 110 further includes a first sub-fin portion 132 located below the upper fin portion 126, in the first longitudinally extending region 116 and having a first lateral dimension LD 1; and a second sub-fin 142 located below the upper fin 126, in the second longitudinally extending region 118, and having a second lateral dimension LD2 different from the first lateral dimension LD 1. For example, second transverse dimension LD2 may be less than first transverse dimension LD 1. As shown in fig. 8A, the second sub-fin 142 may have an outer surface 184 that is curved inward, i.e., bulbous in shape due to the lower portion of the trench 124 (fig. 6A). Each sub-fin 132, 142 is within a trench isolation 146. As shown in fig. 8A, the trench isolation 146 may have a bulbous cross-sectional shape adjacent to the second sub-fin 142.

The IC structure 100 may be advantageously used for FinFET LDMOS devices 104, 204 (shown in fig. 9 and 10, respectively). The LDMOS device 104, 204 may comprise a p-well 152 located in a portion of the first longitudinally extending region 116, an n-well 154 located in at least the second longitudinally extending region 118, a source region 160 in the p-well 152, a drain region 162 in the n-well 154, and a drain extension region 164 in the n-well 154. The second sub-fin 142 is located within the drain extension region 164. It should be noted that the second longitudinally extending region 118 and thus the second sub-fin 142 are located within the drain extension region 164, but the drain extension region 164 may extend beyond the second longitudinally extending region 118 and partially into the first longitudinally extending region 116 (on the left side of fig. 9 and 10). That is, the second sub-fin 142 may be located only within a portion of the drain extension region 164, but a portion of the first sub-fin 132 may be located within the drain extension region 164 (see the edge of the drain extension region not covered by the dashed-line box in fig. 9 and 10). In fig. 9 and 10, the first gate structures 166, 266 extend over the p-well 152 and the n-well 154. The LDMOS device 104 of fig. 9 includes a first gate structure 166 and a second floating gate structure 170 located over the drain extension region 164, i.e., the device 104 is an LDMOS-DP device. In contrast, the LDMOS device 204 in fig. 10 includes only the first gate structure 266, but includes the trench isolation 180 located in the n-well 154 within the drain extension region 164 and adjacent to the drain region 162. Each of the longitudinally extending regions 116, 118 may be any desired location along the length of the semiconductor fin 110. However, in LDMOS devices 104, 204, the second longitudinally extending region 118 may be located within the drain extension region 164.

During operation of the FinFET LDMOS device 104, 204, the narrower sub-fin 142 within the drain extension region 164 reduces the current in the second sub-fin 142, thereby improving the LDMOS HCI, for example, for wireless network power amplifier applications. That is, the current through the second sub-fin portion 142 is smaller than the sub-fin current in a conventional LDMOS device designed to have a single lateral dimension (i.e., the first sub-fin portion 132 is within the drain extension region 164), because the second lateral dimension LD2 (fig. 8A) is smaller than the first lateral dimension LD1 (fig. 8B). Thus, the IC structure 100 provides a 20% -30% smaller impact ionization rate with a smaller depletion region and a larger potential drop across the n-well 154. Thus, the IC structure 100 with the narrower sub-fins 142 improves HCI reliability regardless of the type of LDMOS device.

The method is used for manufacturing integrated circuit chips. The resulting integrated circuit chips may be distributed by the manufacturer in raw wafer form (i.e., as a single wafer having a plurality of unpackaged chips), as a die, or in a packaged form. In the latter case, the chip is mounted in the form of a single chip package (e.g., a plastic carrier with leads that are affixed to a motherboard or other higher level carrier) or a multi-chip package (e.g., a ceramic carrier with surface interconnections and/or buried interconnections). In any case, the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product (e.g., a motherboard) or (b) an end product. The end product may be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. "optional" or "optionally" means that the subsequently described event or circumstance may or may not occur, and that the description includes instances where the event occurs and instances where it does not.

Approximating language, as used herein throughout the specification and claims, may be applied to modify any quantitative representation that could permissibly vary without resulting in a change in the basic function to which it is related. Accordingly, a value modified by a term or terms, such as "about", "about" and "substantially", are not to be limited to the precise value specified. In at least some cases, the approximating language may correspond to the precision of an instrument for measuring the value. Range limitations may be combined and/or interchanged throughout the present specification and claims, such ranges are identified and include all the sub-ranges contained therein unless context or language indicates otherwise. "approximation" of a particular value applied to a range applies to both values and may indicate +/-10% of the value unless otherwise dependent on the accuracy of the instrument measuring the value.

The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The description of the present disclosure has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the disclosure in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the disclosure. The embodiment was chosen and described in order to best explain the principles of the disclosure and the practical application, and to enable others of ordinary skill in the art to understand the disclosure for various embodiments with various modifications as are suited to the particular use contemplated.