阅读说明：本技术 半导体装置 (Semiconductor device with a plurality of semiconductor chips ) 是由 张书维 林士尧 古淑瑗 于 2021-08-11 设计创作，主要内容包括：本公开提出一种半导体装置。半导体装置包括第一、第二、第三、与第四晶体管。操作第一与第二晶体管的栅极电压,低于操作第三与第四晶体管的栅极电压。第一与第二晶体管分别具有第一与第二主动栅极结构。第一与第二主动栅极结构沿着第一方向彼此隔有第一栅极隔离结构。第三与第四晶体管分别具有第三与第四主动栅极结构。第三与第四主动栅极结构沿着第一方向彼此隔有第二栅极隔离结构。第一栅极隔离结构的个别侧壁之间沿着第一方向的第一距离的变异,等于第二栅极隔离结构的个别侧壁之间沿着第一方向的第二距离的变异。(The present disclosure provides a semiconductor device. The semiconductor device includes first, second, third, and fourth transistors. The gate voltages of the first and second transistors are operated to be lower than the gate voltages of the third and fourth transistors. The first and second transistors have first and second active gate structures, respectively. The first and second active gate structures are separated from each other along a first direction by a first gate isolation structure. The third and fourth transistors have third and fourth active gate structures, respectively. The third and fourth active gate structures are separated from each other along the first direction by a second gate isolation structure. The variation of a first distance between the respective sidewalls of the first gate isolation structures along the first direction is equal to the variation of a second distance between the respective sidewalls of the second gate isolation structures along the first direction.)

1. A semiconductor device, comprising:

a substrate including a first region and a second region, wherein a first density of transistors formed in the first region is greater than a second density of transistors formed in the second region;

wherein the semiconductor device in the first region comprises:

a first semiconductor fin and a second semiconductor fin extending along a first direction;

a first dielectric fin extending along the first direction and located between the first semiconductor fin and the second semiconductor fin, wherein sidewalls of the first dielectric fin are separated by a first distance along a second direction, the second direction being perpendicular to the first direction; and

a first gate isolation structure vertically on the first dielectric fin, wherein sidewalls of the first gate isolation structure are spaced apart a second distance along the second direction, and the first distance is equal to the second distance; and

wherein the semiconductor device in the second region comprises:

a third semiconductor fin and a fourth semiconductor fin extending along the first direction;

a second dielectric fin extending along the first direction and located between the third semiconductor fin and the fourth semiconductor fin, wherein sidewalls of the second dielectric fin are spaced apart a third distance along a second direction; and

a second gate isolation structure vertically on the second dielectric fin, wherein sidewalls of the second gate isolation structure are spaced apart a fourth distance along the second direction, and the fourth distance is less than the third distance.

Technical Field

Embodiments of the present invention relate to semiconductor devices, and more particularly, to methods of fabricating non-planar transistor devices.

Background

The semiconductor industry has experienced rapid growth due to continued improvements in the integration density of various electronic components, such as transistors, diodes, resistors, capacitors, and the like. The main improvement in integration density comes from the continuous reduction of the minimum feature size to integrate more components into a given area.

Disclosure of Invention

An embodiment of the invention discloses a semiconductor device. The semiconductor device includes: the substrate comprises a first area and a second area. A first density of transistors formed in the first region is greater than a second density of transistors formed in the second region. The semiconductor device in the first region includes: first and second semiconductor fins extending along a first direction; a first dielectric fin extending along a first direction and located between the first semiconductor fin and the second semiconductor fin, wherein sidewalls of the first dielectric fin are separated by a first distance along a second direction, and the second direction is perpendicular to the first direction; and a first gate isolation structure vertically on the first dielectric fin, wherein sidewalls of the first gate isolation structure are spaced apart a second distance along a second direction, and the first distance is equal to the second distance. The semiconductor device in the second region includes: a third semiconductor fin and a fourth semiconductor fin extending along a first direction; a second dielectric fin extending along the first direction and located between the third semiconductor fin and the fourth semiconductor fin, wherein sidewalls of the second dielectric fin are spaced apart a third distance along the second direction; and a second gate isolation structure vertically on the second dielectric fin, wherein sidewalls of the second gate isolation structure are spaced apart a fourth distance along the second direction, and the fourth distance is less than the third distance.

Another embodiment of the invention discloses a semiconductor device. The semiconductor device includes: a first group of a plurality of transistors and a second group of a plurality of transistors. The gate voltage of the plurality of transistors operating the first group is set to be lower than the gate voltage of the plurality of transistors operating the second group. The first group of the plurality of transistors includes a first transistor having a first active gate structure and a second transistor having a second active gate structure. The first and second active gate structures are spaced apart from each other along a first direction by a first dielectric fin having a first width along the first direction and a first gate isolation structure having a second width along the first direction, the first width being equal to the second width. The second group of the plurality of transistors includes a third transistor having a third active gate structure and a fourth transistor having a fourth active gate structure. The third and fourth active gate structures are spaced apart from each other along the first direction by a second dielectric fin having a third width along the first direction and a second gate isolation structure having a fourth width along the first direction, the third width being greater than the fourth width.

In another embodiment of the invention, a method of forming a semiconductor device is disclosed. The method includes forming a first semiconductor fin and a second semiconductor fin on a substrate extending along a first direction. The method includes forming a dielectric fin extending along a first direction and between a first semiconductor fin and a second semiconductor fin. The dielectric fin has a first width along a second direction, and the second direction is perpendicular to the first direction. The method includes forming a dummy gate structure extending along a second direction and across the first semiconductor fin, the second semiconductor fin, and the dielectric fin. The method includes confirming that the first width is greater than a predetermined threshold. The method includes removing a portion of the dummy gate structure on the dielectric fin to form a trench, and the trench has a second width along a second direction. The second width is less than the first width. The method includes filling the trench with a dielectric material.

Drawings

Figure 1 is a perspective view of a finfet device in some embodiments.

Fig. 2 is a flow diagram of a method of fabricating a non-planar transistor device in some embodiments.

Fig. 3, 4, 5, 6,7, 8, 9, 10, 11, 12, 13, 14A, 14B, 14C, 14D, 15A, 15B, 15C, 15D, 16A, 16B, 16C, and 16D are cross-sectional views of the finfet device (or portion thereof) fabricated by the method of fig. 2 at various stages of fabrication, in some embodiments.

Fig. 17A, 17B, and 17C are top views of finfet devices (or portions thereof) fabricated by the method of fig. 2 at particular stages of fabrication, in some embodiments.

The reference numbers are as follows:

A-A, B-B cross section

d is distance

W₁,W₂601A,601B Width

200 method

100,300 finfet device

102,302 base plate

104 fins

106,700 isolation region

108,1602,1602A,1602B,1622,1622A,1622B Gate dielectric layer

110: grid

112D drain region

112S source region

202,204,206,208,210,212,214,216,218,220,222 step

302A input/output area

302B core area

303: partition

404A,404B,404C,404D active fins

406 pad oxide layer

408 pad nitride layer

410,1006,1026,1403 mask

411 trench

417 first interval

419 second interval

500 virtual channel layer

600A,600B dummy fins

1000,1020 dummy gate structure

1002,1022 dummy gate dielectric layer

1004,1024 dummy gate

1100 gate spacer

1200 epitaxial source/drain structures

1300 interlayer dielectric layer

1302 etch stop layer

1304 dielectric layer

1400,1450 Trench Gate cut

1500,1550 Gate isolation Structure

1600,1620 active gate structure

1600A,1600B,1620A,1620B part

1604,1604A,1604B,1624,1624A,1624B metal gate layer

Detailed Description

The following detailed description may be read with reference to the drawings to facilitate understanding of various aspects of the invention. It is noted that the various structures are for illustrative purposes only and are not drawn to scale as is normal in the industry. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of presentation.

The different embodiments or examples provided below may implement different configurations of the present invention. The following embodiments of specific components and arrangements are provided to simplify the present disclosure and not to limit the same. For example, the description of forming a first element on a second element includes embodiments in which the two are in direct contact, or embodiments in which the two are separated by additional elements other than direct contact. Moreover, various examples of the invention may be repeated using the same reference numerals for brevity, but elements having the same reference numerals in the various embodiments and/or arrangements do not necessarily have the same correspondence.

Furthermore, spatially relative terms such as "below," "lower," "above," "upper," or the like may be used for ease of description to refer to one element relative to another in the figures. Spatially relative terms may be extended to elements used in other orientations than the orientation illustrated. The elements may also be rotated 90 or other angles, and thus directional terms are used only to describe directions in the drawings.

Embodiments of the present invention provide methods of forming finfet devices, and in particular, replacement gates for finfet devices. In some embodiments, a dummy gate structure is formed on the plurality of fins. The fins may include one or more active fins and one or more dummy fins. The term "active fin" may then be referred to as an active channel, which when properly configured and charged, may electrically conduct current in a final semiconductor device, such as finfet device 300 shown below. The term "dummy fin" may then be considered as an inactive channel (if desired) that does not electrically conduct current in the final semiconductor device (e.g., finfet device 300 shown below). A gate spacer is then formed around the dummy gate structure. After forming an interlevel dielectric layer around the gate spacers to cover respective portions of the fins, a portion of the dummy gate structure on at least one dummy fin is removed to form a gate cut trench. In various embodiments, the width of the gate cut trench need not be proportional to (e.g., smaller than) the width of the dummy fin. The gate isolation structure may then be filled into the gate cut trench. The remaining portion of the dummy gate structure may then be replaced with an active gate structure, which may include one or more metal gate layers.

Forming a metal gate layer over multiple fins in the manner described above may provide various advantages in advanced process nodes. A gate isolation structure is formed on the dummy fin to separate, cut, or otherwise separate the metal gate layer. Forming a gate isolation structure to cut the metal gate layer may electrically couple different portions of the metal gate layer to respective active fins.

Active fins may be more distributed in certain areas on the substrate, resulting in dummy fins having greater widths in these areas. Active fins may be tighter in certain areas on the substrate, resulting in dummy fins in those areas having smaller widths. The critical dimension (e.g., width) of the gate cut trench formed in the prior art is generally proportional to the width of the dummy fin exposed by the gate cut trench, which causes various problems. For example, in forming gate cut trenches in these different regions, it may not be possible to successfully form wider gate cut trenches (e.g., with the remaining dummy gate structure remaining on the dummy fins). In summary, the gate isolation structure filled in the gate cut trench cannot successfully cut (e.g., isolate) the metal gate layer.

Various embodiments of the present invention provide a semiconductor device and a method for forming the same to solve the above-mentioned problems. In various embodiments, wider dummy fins and narrower dummy fins may be formed on the substrate. Depending on the width of the wider dummy fins, the width of the gate cut trench may or may not be proportional to the width of the wider dummy fins. For example, when the width of the wider dummy fin is determined to be greater than a predetermined threshold, the gate cut trench may not be proportional to (or smaller than) the width of the dummy fin. On the other hand, when the width of the wider dummy fin is determined to be equal to or less than the predetermined threshold, the gate cut trench may be proportional to the width of the dummy fin. In this manner, individual gate cut trenches of different dimensions on dummy fins may be formed simultaneously, which significantly improves upon the problems encountered in the prior art.

Fig. 1 is a perspective view of a finfet device 100 in various embodiments. The finfet device 100 includes a substrate 102 and a fin 104 raised above the substrate 102. Isolation regions 106 are formed on both sides of fin 104, and fin 104 is raised above isolation regions 106. Gate dielectric 108 is along the sidewalls and top surface of fin 104, and gate 110 is situated on gate dielectric 108. Source region 112S and drain region 112D extend from fin 104 (or are located in fin 104) and are located on both sides of gate dielectric 108 and gate 110. Fig. 1 provides a number of reference sections for subsequent figures. For example, the section B-B extends along a longitudinal axis of the gate 110 of the finfet device 100. Cross section a-a is perpendicular to cross section B-B and along the longitudinal axis of fin 104 and in the direction of current flow between source region 112S and drain region 112D. The following figures may be based on these reference profiles for clarity.

Fig. 2 illustrates a flow chart of a method 200 of forming a non-planar transistor device in accordance with one or more embodiments of the present invention. For example, at least some of the steps of method 200 may be used to form a finfet device (such as finfet device 100), a nanosheet transistor device, a nanowire transistor device, a vertical transistor device, a wrap-around gate transistor device, or the like. It should be noted that the method 200 is only an example and not a limitation of the embodiment of the present invention. In view of the above, it should be understood that additional steps may be provided before, during, or after the method of fig. 2, and only some of the other steps are briefly described herein. In some embodiments, the steps of the method 200 may relate to cross-sectional views of the finfet device of fig. 3, 4, 5, 6,7, 8, 9, 10, 11, 12, 13, 14A, 14B, 14C, 14D, 15A, 15B, 15C, 15D, 16A, 16B, 16C, and 16D, respectively, at various stages of fabrication, which will be described in detail below.

Generally, the method 200 begins with providing a substrate at step 202. Step 204 of method 200 is followed by forming active fins. Step 206 of method 200 then forms dummy fins. Step 208 of method 200 is followed by forming isolation regions. Step 210 of method 200 is followed by forming a dummy gate structure on the fin. Step 212 of method 200 is followed by forming gate spacers. Step 214 of the method 200 is followed by growing the source/drain structure. Step 216 of method 200 is followed by forming an interlevel dielectric layer. Step 218 of the method 200 is followed by cutting the dummy gate structure. Step 220 of method 200 is followed by forming a gate isolation structure. Step 222 of the method 200 is followed by forming an active gate structure.

As described above, fig. 3-16D each show cross-sectional views of a portion of the finfet device 300 at various stages of fabrication of the method 200 of fig. 2. Finfet device 300 is similar to finfet device 100 of fig. 1, but has multiple fins. For example, fig. 3-10 and 14A-16D are cross-sectional views of the finfet device 300 along section B-B (see fig. 1). Fig. 11 to 13 are cross-sectional views of the finfet device 300 along the section a-a (see fig. 1). Although fig. 3-16D show finfet device 300, it should be understood that finfet device 300 may include a variety of other devices such as inductors, fuses, capacitors, coils, or the like, which are not shown in fig. 3-16D for clarity of the drawings.

Fig. 3 is a cross-sectional view of a finfet device 300 in one of various stages of fabrication, corresponding to step 202 of fig. 2, that includes a semiconductor substrate 302. The cross-sectional view of fig. 3 is along the length of an active or dummy gate structure of finfet device 300 (e.g., cross-section B-B of fig. 1).

The substrate 302 may be a semiconductor substrate such as a bulk semiconductor, a semiconductor-on-insulator substrate, or the like, which may be doped (e.g., with p-type or n-type dopants) or undoped. The substrate 302 may be a wafer such as a silicon wafer. Generally, a semiconductor-on-insulator substrate may include a layer of semiconductor material formed on an insulating layer. For example, the insulating layer may be a buried oxide layer, a silicon oxide layer, or the like. An insulating layer may be provided on a substrate, typically a silicon substrate or a glass substrate. Other substrates such as multilayer substrates or compositionally graded substrates may also be employed. In some embodiments, the semiconductor material of the substrate 302 may include silicon, germanium, a semiconductor compound (e.g., silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, and/or indium antimonide), a semiconductor alloy (e.g., silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, indium gallium phosphide, and/or indium gallium arsenide phosphide), or a combination thereof.

In some embodiments, finfet device 300 may include an input/output region 302A and a core region 302B. The input/output region 302A may be configured to form a plurality of input/output transistors and the core region 302B may be configured to form a plurality of core transistors. The terms "input/output transistor" and "core transistor" as used herein generally refer to a transistor configured to operate at a higher voltage (e.g., a higher gate-source threshold voltage) and a transistor configured to operate at a lower voltage (e.g., a lower gate-source threshold voltage), respectively. It should therefore be understood that the i/o regions may include any of a variety of other transistors operating at higher voltages, while the core transistors may include any of a variety of other transistors operating at lower voltages, and remain within the scope of embodiments of the present invention. The input/output transistors may have thicker gate dielectric layers when properly configured, while the core transistors may have thinner gate dielectric layers when properly configured. In addition, the density of transistors in which i/o transistors are formed in a first region of the substrate (e.g., i/o region 302A) is low, while the density of transistors in which core transistors are formed in a second region of the substrate (e.g., core region 302B) is high. As such, the structures (e.g., fins) in the i/o region 302A may be more dispersed than the structures (e.g., fins) in the core region 302B.

As shown in fig. 3 (and subsequent figures), the i/o region 302A and the core region 302B are separated from each other by a partition 303, which may include additional structures, components, or devices, but is omitted from the figures to simplify the drawings. It should be understood that some steps of the method 200 may be performed simultaneously in the input/output region 302A and the core region 302B. For illustrative purposes, some of the structures formed in the I/O region 302A and the core region 302B may be represented later by the same figure, which corresponds to one of the steps of the method 200.

Fig. 4, which corresponds to step 204 of fig. 2, is a cross-sectional view of finfet device 300 at one of several stages of fabrication, including semiconductor fins such as active fins 404A,404B,404C, and 404D. The cross-sectional view of fig. 4 is along the length direction of the active or dummy gate structure of the finfet device 300 (e.g., the cross-section B-B shown in fig. 1).

Semiconductor fins, such as active fins 404A and 404B, are formed in input/output region 302A, and semiconductor fins, such as active fins 404C and 404D, are formed in core region 302B. Although the figures illustrate two semiconductor fins in each of i/o region 302A and core region 302B, it should be understood that finfet device 300 may include any number of semiconductor fins in i/o region 302A and core region 302B and remain within the scope of the present embodiments.

The semiconductor fins may each be provided as active fins 404A-404D, which may serve as channels or active (e.g., electrically functional) fins in a completed finfet. Further, semiconductor fins such as active fin 404A may be disposed as an active channel (sometimes referred to as active input/output fins) of a first input/output transistor of finfet device 300, semiconductor fins such as active fin 404B may be disposed as an active channel (sometimes referred to as active input/output fins) of a second input/output transistor of finfet device 300, semiconductor fins such as active fin 404C may be disposed as an active channel (sometimes referred to as active core fins) of a first core transistor of finfet device 300, and semiconductor fins such as active fin 404D may be disposed as an active channel (sometimes referred to as active core fins) of a second core transistor of finfet device 300.

For example, semiconductor fins such as active fins 404A-404D may be formed by patterning substrate 302 using photolithography and etching techniques. For example, a mask layer, such as a pad oxide layer 406 and an overlying pad nitride layer 408, may be formed on the substrate 302. The pad oxide layer 406 may be a silicon oxide-containing film formed by a thermal oxidation process. The pad oxide layer 406 may serve as an adhesion layer between the substrate 302 and the overlying pad nitride layer 408. In some embodiments, the composition of the pad nitride layer 408 is silicon nitride, silicon oxynitride, silicon carbonitride, the like, or combinations thereof. Although only one pad nitride layer 408 is shown in the drawings, a multi-layer structure (e.g., a silicon nitride layer and a silicon oxide layer thereon) may be formed as the pad nitride layer 408. For example, the pad nitride layer 408 can be formed by low pressure chemical vapor deposition or plasma assisted chemical vapor deposition.

The method of patterning the mask layer may employ a photolithography technique. Generally, photolithography deposits, irradiates (exposes), and develops a photoresist material (not shown) to remove a portion of the photoresist material. The remaining photoresist material can protect the underlying material (such as the mask layer in this example) from subsequent processing steps, such as etching. For example, a photoresist material is used to pattern the pad oxide layer 406 and the pad nitride layer 408 to form a patterned mask 410, as shown in fig. 4.

The patterned mask 410 may then be used to pattern the exposed portions of the substrate 302 to form trenches (or openings) 411, thereby defining active fins 404A-404D between adjacent trenches 411, as shown in fig. 4. In forming a plurality of fins, such a trench may be referred to as between any adjacent fins. In some embodiments, the active fins 404A-404D may be formed by etching a trench in the substrate 302, and the etching may be reactive ion etching, neutral beam etching, the like, or a combination thereof. The etching may be anisotropic. In some embodiments, the grooves 411 may be strips that are parallel to each other (in top view) and closely arranged to each other. In some embodiments, trench 411 may continuously surround active fins 404A-404D.

The method of patterning the active fins 404A-404D may be any suitable method. For example, the active fins 404A-404D may be patterned using one or more photolithography processes, including double patterning or multiple patterning processes. In general, double patterning or multiple patterning processes combine photolithography and self-aligned processes that produce a pattern pitch that is smaller than that obtained using a single direct lithography process. For example, one embodiment may form a sacrificial layer on a substrate and pattern the sacrificial layer using a photolithography process. A self-aligned process may be employed to form spacers along the sides of the patterned sacrificial layer. The sacrificial layer is then removed and the remaining spacers or cores may then be used to pattern the fins.

As shown in fig. 4, active fins 404A and 404B in i/o region 302A may be separated from each other by a first spacing 417, and active fins 404C and 404D in core region 302B may be separated from each other by a second spacing 419. In various embodiments, the first spacing 417 may be substantially greater than the second spacing 419. For example, for a particular process node (e.g., 5nm), the first spacing 417 may be about 5nm to about 500nm, and the second spacing 419 may be about 5nm to about 500 nm.

Fig. 3 and 4 illustrate one embodiment of forming active fins 404A-404D, but the active fins may be formed by a variety of different processes. For example, the top of the substrate 302 may be replaced with a suitable material, such as an epitaxial material suitable for a predetermined type (e.g., n-type or p-type) of semiconductor device to be formed. The substrate 302 with epitaxial material on top may then be patterned to form active fins 404A-404D comprising epitaxial material.

In another example, a dielectric layer may be formed on the upper surface of the substrate, trenches etched through the dielectric layer, homoepitaxial structures epitaxially grown in the trenches, and the dielectric layer recessed to allow the homoepitaxial structures to protrude from the dielectric layer to form one or more fins.

In yet another example, a dielectric layer may be formed on a top surface of a substrate, trenches etched through the dielectric layer, heteroepitaxial structures (using a different material than the substrate) epitaxially grown in the trenches, and the dielectric layer recessed to allow the heteroepitaxial structures to protrude from the dielectric layer to form one or more fins.

In embodiments where epitaxial materials or epitaxial structures (such as heteroepitaxial structures or homoepitaxial structures) are grown, the grown materials or structures may be doped in situ during growth to eliminate prior or subsequent implantation processes. Although in-situ doping and implant doping may be used in combination. Furthermore, it may be advantageous for the material epitaxially grown in the n-type metal oxide semiconductor region to be different from the material in the p-type metal oxide semiconductor region. In various embodiments, the active fins 404A-404D may comprise silicon germanium (e.g., Si)_xGe_1-xWhere x may be between 0 and 1), silicon carbide, pure or substantially pure germanium, a group III-V semiconductor compound, a group II-VI semiconductor compound, or the like. For example, possible materials for the III-V semiconductor compound include, but are not limited to, indium arsenide, aluminum arsenide, gallium arsenide, indium phosphide, gallium nitride, indium gallium arsenide, indium aluminum arsenide, gallium antimonide, aluminum phosphide, gallium phosphide, or the like.

Fig. 5, which corresponds to step 206 of fig. 2, is a cross-sectional view of finfet device 300 at one of various stages of fabrication, including dummy channel layer 500. Fig. 6 is a cross-sectional view of finfet device 300 at one of various stages of fabrication, including dummy fins 600A and 600B. Fig. 5 and 6 are cross-sectional views (such as section B-B in fig. 1) taken along the length direction of the active gate structure and the dummy gate structure of the finfet device 300, respectively.

Although the dummy via layer 500 is shown as being deposited entirely in the I/O region 302A and the core region 302B, it is understood that similar dummy via layers may be deposited over the I/O region 302A and the core region 302B, respectively.

In some embodiments, dummy channel layer 500 may include a dielectric material for forming dummy fins 600A and 600B. For example, the dielectric material may comprise silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon oxynitride, silicon oxycarbide, or combinations thereof. In another example, the dielectric material may comprise a group IV oxide or a group IV nitride, such as tantalum nitride, tantalum oxide, hafnium oxide, or combinations thereof.

For example, the dummy channel layer 500 may be formed by low pressure chemical vapor deposition or plasma assisted chemical vapor deposition.

Once dummy channel layer 500 is deposited to cover active fins 404A-404D, and one or more dummy fins 600A and 600B may be formed between active fins 404A-404D. For example, dummy fin 600A may be formed between active fins 404A and 404B, and dummy fin 600B may be formed between active fins 404C and 404D. For example, dummy fins 600A and 600B may be formed by patterning a dummy channel layer, and the patterning may be performed by photolithography and etching. For example, a patterned mask (not shown) may be formed on dummy channel layer 500 to mask portions of dummy channel layer 500 to form dummy fins 600A and 600B. The unmasked portions of dummy channel layer 500 may then be etched to define dummy fins 600A and 600B between adjacent active fins 404A-404D (or in trenches 411), and the etching process may be a reactive ion etch, a neutral etch, the like, or combinations thereof, as shown in fig. 6. In some embodiments, the etching may be anisotropic. In some other embodiments, dummy fins 600A and 600B may be formed after or simultaneously with the formation of isolation regions between adjacent fins (e.g., isolation region 700 of fig. 7), as described below.

As shown in fig. 6, dummy fins 600A formed in i/o region 302A have a width 601A (in a direction perpendicular to the length direction of the fins) and dummy fins 600B formed in core region 302B have a width 601B (in the same direction). In various embodiments, width 601A is substantially greater than width 601B. For example, at a particular process node (e.g., 5nm), width 601A may be about 2nm to about 200nm, and width 601B may be about 2nm to about 200 nm.

Fig. 7, which corresponds to step 208 of fig. 2, is a cross-sectional view of finfet device 300 at one of various stages of fabrication, including isolation region 700. Fig. 7 is a cross-sectional view along the length direction of the active gate structure and the dummy gate structure of the finfet device 300 (e.g., the cross-section B-B shown in fig. 1).

Isolation region 700 is comprised of an insulating material that electrically isolates adjacent fins from each other. The insulating material may be an oxide such as silicon nitride, the like, or combinations thereof, and may be formed by high density plasma chemical vapor deposition, flowable chemical vapor deposition (such as depositing a chemical vapor deposition-based material in a remote pad system followed by curing the material to convert it to another material such as an oxide), the like, or combinations thereof. Other insulating materials and/or other formation processes may also be employed. In one example, the insulative material is silicon oxide formed by a flowable chemical vapor deposition process. Once the insulating material is formed, an annealing process may be performed. A planarization process, such as chemical mechanical polishing, may be performed to remove any excess insulating material and to make the upper surfaces of isolation region 700, active fins 404A-404D, and dummy fins 600A and 600B coplanar (not shown). The planarization process may also remove the patterned mask 410 (fig. 4).

In some embodiments, isolation regions 700 include a liner layer, such as a liner oxide (not shown), at the interface between each isolation region 700 and substrate 302 (or active fins 404A-404D). In some embodiments, the pad oxide may reduce crystalline defects at the interface between the substrate 302 and the isolation region 700. Similarly, the liner oxide may also be used to reduce crystalline defects at the interface between active fins 404A-404D and isolation region 700. The pad oxide (e.g., silicon oxide) may be a thermal oxide formed by thermally oxidizing a surface layer of the substrate 302, but other suitable methods may be used to form the pad oxide.

The isolation region 700 is then recessed to form a shallow trench isolation region 700, as shown in fig. 7. Isolation region 700 is recessed such that upper portions of active fins 404A-404D and dummy fins 600A and 600B protrude from between adjacent sti regions 700. The respective upper surfaces of the sti regions 700 may have a flat surface (as shown), a convex surface, a concave surface (as dishing), or a combination thereof. By appropriate etching, the upper surface of the shallow trench isolation region 700 may be flat, convex and/or concave. The method of recessing the isolation regions 700 may employ an acceptable etch process, such as an etch process that is selective to the material of the isolation regions 700. For example, the isolation region 700 may be recessed by dry etching or wet etching with dilute hydrofluoric acid.

Dummy fins 600A and 600B may be formed after isolation region 700 is formed, or isolation region 700 and dummy fins 600A and 600B may be formed simultaneously, as described above. For example, in forming active fins 404A-404D (fig. 4), one may form one or more other active fins in trench 411. The insulating material of isolation region 700 may be deposited over the active fins, followed by a cmp process to planarize isolation region 700 and the upper surface of the active fins (which may include active fins 404A-404D and the active fins formed in trench 411), after which the upper portion of the active fins in trench 411 may be partially removed to form voids. The dielectric material of dummy channel layer 500 may then be filled into the voids and another cmp process may be performed to form dummy fins 600A and 600B. The isolation region 700 is recessed to form a shallow trench isolation region 700, as shown in fig. 8. Dummy fins 600A and 600B formed by this method may be formed on substrate 302 with the lower surfaces of dummy fins 600A and 600B below the upper surfaces of isolation regions 700, as shown in fig. 8. The lower surfaces of dummy fins 600A and 600B may be higher than the upper surface of isolation region 700 depending on the degree of recess of isolation region 700, which is within the scope of embodiments of the present invention.

As another example, after forming active fins 404A-404D (fig. 4), the insulating material of isolation region 700 may be deposited on active fins 404A-404D at a controlled deposition rate, thereby spontaneously forming a void in trench 411. The void is filled with the dielectric material of the dummy channel layer 500, followed by a chemical mechanical polishing process to form dummy fins 600A and 600B. The isolation region 700 is recessed to form a shallow trench isolation region 700, as shown in fig. 9. By forming dummy fins 600A and 600B in this manner, dummy fins 600A and 600B may be formed on corresponding isolation regions 700 with the lower surfaces of dummy fins 600A and 600B buried in corresponding isolation regions 700, as shown in fig. 9. As another example, after forming active fins 404A-404D and depositing the insulating material of isolation region 700 on active fins 404A-404D, a patterned mask may be formed over isolation region 700 to expose portions of isolation region 700 to form dummy fins 600A and 600B (in trench 411). For example, the exposed portions of the isolation region 700 may then be etched using reactive ion etching, neutral beam etching, the like, or a combination thereof to define the voids. The dielectric material of dummy channel layer 500 is then filled into the voids, and then a chemical mechanical polishing process is performed to form dummy fins 600A and 600B, which are similar to the embodiment shown in fig. 9.

Fig. 10, which corresponds to step 210 of fig. 2, is a cross-sectional view of finfet device 300 at one of several stages of fabrication, including dummy gate structure 1000 in i/o region 302A and dummy gate structure 1020 in core region 302B. Fig. 10 is a cross-sectional view along the length of the dummy gate structures 1000 and 1020 of the finfet device 300 (e.g., the cross-section B-B shown in fig. 1).

Dummy gate structure 1000 is formed to cover respective portions of each fin in core region 302B, such as active fins 404A and 404B and dummy fin 600A. Dummy gate structure 1020 may be formed in core region 302B to cover each of active fins 404C and 404D and a portion of dummy fin 600B before, simultaneously with, or after forming dummy gate structure 1000 in i/o region 302A. The dummy gate structure 1020 is similar to the dummy gate structure 1000 except that the dimensions of the dummy gate structure are different, and the dummy gate structure 1020 is briefly described as follows.

In some embodiments, dummy gate structure 1000 includes a dummy gate dielectric layer 1002 and a dummy gate 1004. A mask 1006 may be formed over the dummy gate structure 1000. To form dummy gate structure 1000, a dielectric layer may be formed on active fins 404A and 404B and dummy fin 600A. For example, the dielectric layer may be silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, multiple layers thereof, or the like, and may be deposited or thermally grown. Similarly, dummy gate structure 1020 may include a dummy gate dielectric layer 1022 and a dummy gate 1024 having a mask 1026 formed thereon.

A gate layer may be formed on the dielectric layer and a mask layer may be formed on the gate layer. A gate layer may be deposited on the dielectric layer followed by planarization of the gate layer, which may be chemical mechanical polishing. A mask layer may be deposited on the gate layer. For example, the gate layer may be comprised of polysilicon, although other materials may be used. For example, the composition of the mask layer may be silicon nitride or the like.

After forming layers such as dielectric layers, gate layers, and mask layers, the mask layer may be patterned using suitable photolithography and etching techniques to form mask 1006. The patterns of masks 1006 and 1026 may then be transferred to the gate and dielectric layers by suitable etching techniques to form dummy gates 1004 and 1024 and underlying dummy gate dielectric layers 1002 and 1022, respectively. Dummy gate 1004 and dummy gate dielectric layer 1002 cover respective portions (e.g., channel regions) of each active fin 404A and 404B and dummy fin 600A, while dummy gate 1024 and dummy gate dielectric layer 1022 cover a portion (e.g., channel regions) of active fins 404C and 404D and dummy fin 600B. The length of dummy gate 1004 (or 1024) (e.g., the direction of cross-section B-B in figure 1) may also be perpendicular to the length of the fin (e.g., the direction of cross-section a-a in figure 1).

In the example of fig. 10, dummy gate dielectric layer 1002 is formed on active fins 404A and 404B and dummy fin 600A (e.g., on respective top surfaces and sidewalls of the fins), and on shallow trench isolation region 700. Similarly, dummy gate dielectric layer 1022 may be formed to cover active fins 404C and dummy fin 600B, such as the respective top surfaces and sidewalls of the fins. In other embodiments, the dummy gate dielectric layer 1002 or 1022 may be formed by thermally oxidizing the material of the fin so that it is formed on the fin and not on the sti region 700. It is to be understood that these and other variations are intended to be included within the scope of embodiments of the present invention.

Fig. 13 illustrates a cross-sectional view of finfet device 300 in subsequent processing (or fabrication), along section a-a of one of active fins 404A-404D (shown in fig. 1). For example, one dummy gate structure 1000 of fig. 11-13 is located on active fin 404A. It is understood that multiple dummy gate structures may be formed on fin 404A (as well as on other fins such as each of active fins 404B-404D and dummy fins 600A and 600B) while remaining within the scope of embodiments of the present invention.

Fig. 11, which corresponds to step 212 of fig. 2, is a cross-sectional view of finfet device 300 at one of several stages of fabrication, including gate spacers 1100 formed around dummy gate structure 1000 (e.g., along sidewalls of dummy gate structure 1000 and contacting sidewalls of dummy gate structure 1000). For example, gate spacers 1100 are formed on both sidewalls of the dummy gate structure 1000. It is understood that any number of gate spacers may be formed around the dummy gate structure 1000 and remain within the scope of the embodiments of the present invention.

The gate spacers 1100 may be low-k spacers composed of a suitable dielectric material such as silicon oxide, silicon oxycarbonitride, or the like. Any suitable deposition method, such as thermal oxidation, chemical vapor deposition, or the like, may be employed to form the gate spacers 1100. The formation method and shape of the gate spacers 1100 shown in fig. 11 are merely non-limiting examples, and other formation methods and shapes are possible. These and other variations are fully included within the scope of embodiments of the present invention.

Figure 12 is a cross-sectional view of finfet device 300, including a plurality of source/drain regions, such as epitaxial source/drain and structure 1200, at one of a plurality of stages of fabrication, corresponding to step 214 of figure 2. Source/drain regions, such as epitaxial source/drain structures 1200, are formed in recesses of active fin 404A adjacent to dummy gate structures 1000, such as between adjacent dummy gate structures 1000 and/or adjacent to dummy gate structures 1000. In some embodiments, the recess may be formed by an anisotropic etching process using the dummy gate structure 1000 as an etching mask, although other suitable etching processes may be used.

The epitaxial source/drain structure 1200 may be formed by epitaxially growing a semiconductor material in the recess by a suitable method such as organic chemical vapor deposition, molecular beam epitaxy, liquid phase epitaxy, vapor phase epitaxy, selective epitaxial growth, the like, or combinations thereof.

As shown in fig. 12, epitaxial source/drain structure 1200 may have surfaces that are raised from respective surfaces of active fin 404A (raised above non-recessed portions of active fin 404A), and may have crystallographic planes. In some embodiments, the epitaxial source/drain structures 1200 of adjacent fins may merge to form a continuous epitaxial source/drain structure (not shown). In some embodiments, the epitaxial source/drain structures 1200 of adjacent fins may not merge together and separate epitaxial source/drain structures 1200 may be maintained (not shown). In some embodiments, when the final finfet device is an n-type finfet, the epitaxial source/drain structure 1200 may comprise silicon carbide, silicon phosphide, silicon carbophosphide, or the like. In some embodiments, when the final finfet device is a p-type finfet, the epitaxial source/drain structure 1200 may comprise silicon germanium with a p-type impurity such as boron or indium.

The epitaxial source/drain structure 1200 may be annealed after dopant implantation. The implantation process may include forming and patterning a mask, such as a photoresist, to cover and protect regions of the finfet device 300 from the implantation process. The impurity (e.g., dopant) concentration of the epitaxial source/drain structure 1200 may be about 1x10¹⁹cm^-3To about 1x10²¹cm^-3. P-type dopants such as boron or indium may be implanted into the p-type crystalIn the epitaxial source/drain structure 1200 of the transistor. An n-type impurity such as phosphorous or arsenic may be implanted into the epitaxial source/drain structure 1200 of the n-type transistor. In some embodiments, in-situ doping may be performed while growing the epitaxial source/drain structure 1200.

Fig. 13, which corresponds to step 216 of fig. 2, is a cross-sectional view of the finfet device 300 in one of various stages of fabrication, including an interlayer dielectric layer 1300. In some embodiments, a contact etch stop layer 1302 may be formed on the structure during the formation of the interlayer dielectric 1300, as shown in FIG. 13. The contact etch stop layer 1302 may serve as an etch stop layer in a subsequent etching process and may comprise a suitable material such as silicon oxide, silicon nitride, silicon oxynitride, combinations thereof or the like, and may be formed by a suitable method such as chemical vapor deposition, physical vapor deposition, combinations thereof or the like.

An interlayer dielectric 1300 is then formed over the contact etch stop layer 1302 and the dummy gate structure 1000. In some embodiments, the composition of the interlayer dielectric layer 1300 is a dielectric material such as silicon oxide, phosphosilicate glass, borosilicate glass, borophosphosilicate glass, undoped silicate glass, or the like, and the deposition method thereof may be any suitable method such as chemical vapor deposition, plasma-assisted chemical vapor deposition, or flowable chemical vapor deposition. After the formation of the interlayer dielectric layer 1300, a dielectric layer 1304 may optionally be formed on the interlayer dielectric layer 1300. The dielectric layer 1304 may serve as a protection layer to prevent or reduce the loss of the ild 1300 in subsequent etching processes. The dielectric layer 1304 may be formed of a suitable material, such as silicon nitride, silicon carbonitride, or the like, and may be formed by a suitable method, such as chemical vapor deposition, plasma-assisted chemical vapor deposition, or flowable chemical vapor deposition. After the dielectric layer 1304 is formed, a planarization process, such as a chemical mechanical polishing process, may be performed to achieve a flush upper surface for the dielectric layer 1304. The chemical mechanical polishing may also remove portions of the mask 1006 and contact etch stop layer 1302 over the dummy gate 1004 (fig. 12). Some embodiments have the upper surface of the dielectric layer 1304 flush with the upper surface of the dummy gate 1004 after the planarization process.

Fig. 14A, corresponding to step 218 of fig. 2, is a cross-sectional view of finfet device 300 at one of a plurality of stages of fabrication, in which dummy gate structures 1000 and 1020 are respectively cut, truncated, or otherwise separated to form gate cut trench 1400 in i/o region 302A and gate cut trench 1450 in core region 302B. Fig. 14B, 14C and 14D correspond to the same steps, each showing a cross-sectional view of the finfet device 300 in which the gate cut trenches 1400 and/or 1450 have a different profile than that shown in fig. 14A. The cross-sectional views of fig. 14A-14D are along the length direction of the dummy gate structures 1000 and 1020 of the finfet device 300, such as the cross-sectional view B-B shown in fig. 1.

To form gate cut trench 1400, an etch process (which may contain one or more stages) may be performed to remove a portion of dummy gate 1004 and a portion of dummy gate dielectric layer 1002 on dummy fin 600A. The same etch process may be performed to remove a portion of dummy gate 1024 and a portion of dummy gate dielectric layer 1022 on dummy fin 600B while forming gate cut trench 1400. In a first stage of the etching process, a mask 1403 may be formed over dummy gate structures 1000 and 1020 to expose respective portions of dummy gates 1004 and 1024 to be removed, such as the portions on dummy fins 600A and 600B, followed by the etching process. Mask 1403 may continue to be employed at a later stage of the etch process, if present.

In various embodiments of the I/O region 302A, the width W of the gate cut trench 1400₁The width 601A of dummy fin 600A (along the length of dummy gate structure 1000) is approximately equal to the width 601A of dummy fin 600A (as shown in fig. 14A and 14B) or less than the width 601A of dummy fin 600A (as shown in fig. 14C and 14D). In the core region, the gate cut trench 1450 has a width W₂Approximately equal to the width 601B of dummy fin 600B (along the length of dummy gate structure 1020) (as shown in fig. 14A-14D). Width W of gate cut trench 1400 in i/o region 302A₁Whether width 601A is equal to or less than width 601A of dummy fin 600A depends on whether width 601A is greater than a predetermined threshold. By way of example toIn other words, if the width 601A is greater than the threshold value, the width of the gate cutting trench 1400 may be smaller than the width 601A (see fig. 14C and 14D). If the width 601A is less than or equal to a critical value, the width of the gate cutting trench 1400 may be equal to the width 601A (see fig. 14A and 14B). In a particular process node (e.g., 5nm), the threshold may be about 50 nm. It should be understood, however, that the threshold may vary depending on the process node.

In some embodiments, each gate cut trench 1400 and 1450 may have a non-tapered profile. As an example in fig. 14A and 14C, the sidewalls of gate cut trenches 1400 and 1450 are perpendicular to their lower surfaces (e.g., the exposed upper surfaces of dummy fins 600A and 600B). As such, the width W of the gate cut trench 1400₁May be defined as the distance separating the sidewalls of the gate cut trench 1400 entirely and the width W of the gate cut trench 1450₂May be defined as the distance that completely separates the sidewalls of the gate cut trench 1450. In some other embodiments, each gate cut trench 1400 and 1450 may have a tapered profile. As shown in fig. 14B and 14D, each of the gate cut trenches 1400 and 1450 has sidewalls to connect to the bottom surface, and the bottom surface has a predominantly arcuate or predominantly edge profile. As such, the width W of the gate cut trench 1400₁Defined by the distance separating the sidewalls (without the bottom surface) of gate cut trench 1400, and gate cut trench 1450 has a width W₂Defined by the distance separating the sidewalls (without the lower surface) of the gate cut trench 1450.

Fig. 15A, corresponding to step 220 of fig. 2, is a cross-sectional view of finfet device 300 at one of several stages of fabrication, including a gate isolation structure 1500 in i/o region 302A and a gate isolation structure 1550 in core region 302B. The method of forming the gate isolation structures 1500 and 1550 shown in fig. 15A is based on the gate cutting trenches 1400 and 1450 shown in fig. 14A. In the cross-sectional views of the finfet device 300 shown in fig. 15B, 15C, and 15D, the gate isolation structures 1500 and 1550 are formed according to the gate cutting trenches 1400 and 1450 shown in fig. 14B, 14C, and 14D, respectively. The cross-sectional views of fig. 15A-15D are along the length direction of the dummy gate structures 1000 and 1020, respectively, of the finfet device 300 (as shown in section B-B of fig. 1).

The gate isolation structures 1500 and 1550 may be formed by filling dielectric material into the gate cut trenches 1400 and 1450 (fig. 14A-14D), respectively. As such, the gate isolation structures 1500 and 1550 inherit the profile (or size) of the gate cut trenches 1400 and 1450, respectively. Taking fig. 15A as an example, the gate isolation structure 1500 may have a non-tapered profile with a width W₁Approximately equal to width 601A of dummy fin 600A. The gate isolation structure 1550 may have a non-tapered profile with a width W₂Approximately equal to width 601B of dummy fin 600B. Taking fig. 15B as an example, the gate isolation structure 1500 may have a tapered profile with a width W₁Approximately equal to width 601A of dummy fin 600A. The gate isolation structure 1550 may have a tapered profile with a width W₂Approximately equal to width 601B of dummy fin 600B. Taking fig. 15C as an example, the gate isolation structure 1500 may have a non-tapered profile with a width W₁Less than width 601A of dummy fin 600A. The gate isolation structure 1550 may have a non-tapered profile with a width W₂Approximately equal to width 601B of dummy fin 600B. Taking fig. 15D as an example, the gate isolation structure 1500 may have a tapered profile with a width W₁Less than width 601A of dummy fin 600A. The gate isolation structure 1550 may have a tapered profile with a width W₂Approximately equal to width 601B of dummy fin 600B.

For example, the dielectric material used to form the gate isolation structures 1500 and 1550 may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon oxycarbide, or combinations thereof. The gate isolation structures 1500 and 1550 may be formed by depositing dielectric materials in the gate cutting trenches 1400 and 1450, respectively, and the deposition method may employ any suitable method such as chemical vapor deposition, plasma-assisted chemical vapor deposition, or flowable chemical vapor deposition. A chemical mechanical polish may be performed after deposition to remove any excess dielectric material from the remaining dummy gate structures 1000 and 1020.

Although the examples of fig. 15A-15D show the gate isolation structures 1500 and 1550 filling the gate cut trenches 1400 and 1450, respectively, with a single dielectric portion (which may include one or more of the dielectric materials described above), it is understood that the gate isolation structures 1500 and 1550 may each include multiple portions. For example, each portion may comprise silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon oxycarbide, or combinations thereof. For example, the gate isolation structures 1500 and 1550 may each include a first portion (which is a compliant layer to line respective gate cut trenches) and a second portion (which may fill the gate cut trenches, and the first portion may be coupled between the second portion and the gate cut trenches). In another example, the gate isolation structures 1500 and 1550 may each include a first portion filling a lower portion of a respective gate cut trench and a second portion filling an upper portion of the gate cut trench.

Fig. 16A, which corresponds to step 222 of fig. 2, is a cross-sectional view of finfet device 300 at one of several stages of fabrication, including active gate structure 1600 in i/o region 302A and active gate structure 1620 in core region 302B. The active gate structures 1600 and 1620 of fig. 16A are formed according to the cross-sectional view of the finfet device 300 of fig. 15A. The cross-sectional views of the finfet device 300 shown in fig. 16B, 16C, and 16D are respectively according to the cross-sectional views shown in fig. 15B, 15C, and 15D. The cross-sectional views of fig. 16A-16D are each along the length of the active gate structures 1600 and 1620 of the finfet device 300 (as shown in cross-section B-B of fig. 1).

The method for forming the active gate structure 1600 may be replacing the dummy gate structure 1000 (fig. 15A-15D), and the method for forming the active gate structure 1620 may be replacing the dummy gate structure 1020 (fig. 15A-15D). As shown, the active gate structure 1600 may include two portions 1600A and 1600B, which are separated by a gate isolation structure 1500 and a dummy fin 600A. Active gate structure 1620 may comprise two portions 1620A and 1620B separated by gate isolation structure 1550 and dummy fin 600B. Portion 1600A may cover active fin 404A, portion 1600B may cover active fin 404B, portion 1620A may cover active fin 404C, and portion 1620B may cover active fin 404D.

After forming the active gate structures 1600 and 1620, the finfet device 300 may include a plurality of transistors. For example, a first active transistor employing active fin 404A as a conductive channel and portion 1600A as an active gate structure, a second active transistor employing active fin 404B as a conductive channel and portion 1600B as an active gate structure, a third active transistor employing active fin 404C as a conductive channel and portion 1620A as an active gate structure, and a fourth active transistor employing active fin 404D as a conductive channel and portion 1620B as an active gate structure may be formed. In addition, the first transistor and the second transistor formed in the input/output region 302A may be respectively configured as an input/output transistor. The third transistor and the fourth transistor formed in the core region 302B may be respectively configured as core transistors.

The active gate structures 1600 and 1620 may each include a gate dielectric layer (e.g., gate dielectric layers 1602 and 1622), a metal gate layer (e.g., metal gate layers 1604 and 1624), and/or one or more other layers (not shown for clarity). For example, each active gate structure 1600 and 1620 may further comprise a cap layer and an adhesion layer. The capping layer may protect the underlying work function layer from oxidation. In some embodiments, the cap layer may be a silicon-containing layer, such as a silicon layer, a silicon oxide layer, or a silicon nitride layer. The adhesion layer may serve as an adhesion layer between an underlying layer and a gate material (e.g., tungsten) subsequently formed on the adhesion layer. The adhesion layer may be composed of a suitable material such as titanium nitride.

Gate dielectric layers 1602 and 1622 may each be deposited (e.g., conformally deposited) in corresponding gate trenches to surround (e.g., straddle) one or more fins. Taking fig. 16A-16D as an example, a portion 1600A of gate dielectric layer (sometimes referred to as gate dielectric layer 1602A) is deposited in the gate trench, which may be formed by removing a portion of dummy gate structure 1000 (e.g., remaining dummy gate dielectric layer 1002 and dummy gate 1004) on the left side of dummy fin 600A. Gate dielectric layer 1602A may cover the top surface and sidewalls of active fin 404A, one of the sidewalls of dummy fin 600A, and one of the sidewalls of gate isolation structure 1500. The gate dielectric layer (sometimes referred to as gate dielectric layer 1602B) of portion 1600B is deposited in the gate trench, and the gate trench may be formed by removing a portion of dummy gate structure 1000 (e.g., remaining dummy gate dielectric layer 1002 and dummy gate 1004) on the right side of dummy fin 600A. Gate dielectric layer 1602B may cover the top surface and sidewalls of active fin 404B, the other sidewalls of dummy fin 600A, and the other sidewalls of gate isolation structure 1500. A gate dielectric layer (sometimes referred to as gate dielectric layer 1622A) of portion 1620A is deposited in the gate trench, which may be formed by removing a portion of dummy gate structure 1020 on the left side of dummy fin 600B (e.g., remaining dummy gate dielectric layer 1022 and dummy gate 1024). Gate dielectric 1622 may cover the top surface and sidewalls of active fin 404C, one of the sidewalls of dummy fin 600B, and one of the sidewalls of gate isolation structure 1550. The gate dielectric layer of portion 1620B (sometimes referred to as gate dielectric layer 1622B) is deposited in the gate trench, and the gate trench may be formed by removing a portion of dummy gate structure 1020 on the right side of dummy fin 600B (e.g., remaining dummy gate dielectric layer 1022 and dummy gate 1024). Gate dielectric 1622B may cover the top surface and sidewalls of active fin 404D, the other sidewalls of dummy fin 600B, and the other sidewalls of gate isolation structure 1550.

Each of the gate dielectric layers 1602 and 1622 includes silicon oxide, silicon nitride, or multiple layers thereof. In an embodiment, the gate dielectric layers 1602 and 1622 each comprise a high-k dielectric material. In these embodiments, the dielectric constants of the gate dielectric layers 1602 and 1622 may each be greater than about 7.0 and may comprise metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, magnesium, barium, titanium, lead, or combinations thereof. The formation method of the gate dielectric layers 1602 and 1622 may include molecular beam deposition, atomic layer deposition, plasma-assisted chemical vapor deposition, or the like. For example, the thickness of each gate dielectric layer 1602 and 1622 may be between aboutTo aboutIn the meantime.

Metal gate layers 1604 and 1624 may each be formed on a respective gate dielectric layer. The metal gate layer of portion 1600A (sometimes referred to as metal gate layer 1604A) is deposited in a gate trench on gate dielectric layer 1602A, the metal gate layer of portion 1600B (sometimes referred to as metal gate layer 1604B) is deposited in a gate trench on gate dielectric layer 1602B, the metal gate layer of portion 1620A (sometimes referred to as metal gate layer 1624A) is deposited in a gate trench on gate dielectric layer 1622A, and the metal gate layer of portion 1620B (sometimes referred to as metal gate layer 1624B) is deposited in a gate trench on gate dielectric layer 1622B.

In some embodiments, the metal gate layers 1604 and 1624 may each be a p-type work function layer, an n-type work function layer, multiple layers thereof, or combinations thereof. In summary, the metal gate layers 1604 and 1624 in some embodiments may each be considered a work function layer. In the context described herein, the work function layer may also be considered a work function metal. Examples of p-type workfunction metals that may be included in gate structures for p-type devices include titanium nitride, tantalum nitride, ruthenium, molybdenum, aluminum, tungsten nitride, zirconium silicide, molybdenum silicide, tantalum silicide, nickel silicide, other suitable p-type workfunction materials, or combinations thereof. Examples of n-type workfunction metals that may be included in the gate structure for n-type devices include titanium, silver, tantalum aluminum carbide, titanium aluminum nitride, tantalum carbide, tantalum carbonitride, tantalum silicon nitride, manganese, zirconium, other suitable n-type workfunction materials, or combinations thereof.

The work function value is related to the material composition of the work function layer, and the material of the work function layer may be adjusted to adjust the work function value to achieve a target threshold voltage in the desired device to be formed. The deposition method of the work function layer may be chemical vapor deposition, physical vapor deposition, atomic layer deposition, and/or other suitable processes. For example, the thickness of the p-type work function layer may be between aboutTo aboutAnd the thickness of the n-type work function layer may be between aboutTo aboutIn the meantime.

Fig. 17A, 17B, and 17C are each top views of a portion of finfet device 300 after formation of active gate structures 1600 and/or 1620, in various embodiments. For example, fig. 17A shows a partial top view of finfet device 300 in core region 302B. As shown, gate isolation structure 1550 divides active gate structure 1620 into two portions that cover active fins 404C and 404D, respectively. In top view, the width W of the gate isolation structure 1550₂Approximately equal to width 601B of dummy fin 600B between active fins 404C and 404D (along the length of active gate structure 1620). Fig. 17B shows a top view of a portion of finfet device 300 in i/o area 302A, where width 601A of dummy fin 600A is less than or equal to a predetermined threshold. As shown, gate isolation structure 1500 divides active gate structure 1600 into two portions that cover active fins 404A and 404B, respectively. In top view, the width W of the gate isolation structure 1500₁Approximately equal to width 601A of dummy fin 600A between active fins 404A and 404B (along the length of active gate structure 1600). Fig. 17C shows a top view of a portion of finfet device 300 in i/o area 302A, where width 601A of dummy fin 600A is greater than a predetermined threshold. As shown, gate isolation structure 1500 divides active gate structure 1600 into two portions that cover active fins 404A and 404B, respectively. In top view, the width W of the gate isolation structure 1500₁Is smaller (along the length of active gate structure 1600) than width 601A of dummy fin 600A between active fins 404A and 404B. As shown in fig. 17A-17C, each dummy fin (e.g., dummy fin)Fins 600A and 600B) may be separated from adjacent active fins (e.g., active fins 404A,404B,404C, and 404D) by a distance D of aboutTo about

An embodiment of the invention discloses a semiconductor device. The semiconductor device includes: the substrate comprises a first area and a second area. A first density of transistors formed in the first region is greater than a second density of transistors formed in the second region. The semiconductor device in the first region includes: first and second semiconductor fins extending along a first direction; a first dielectric fin extending along a first direction and located between the first semiconductor fin and the second semiconductor fin, wherein sidewalls of the first dielectric fin are separated by a first distance along a second direction, and the second direction is perpendicular to the first direction; and a first gate isolation structure vertically on the first dielectric fin, wherein sidewalls of the first gate isolation structure are spaced apart a second distance along a second direction, and the first distance is equal to the second distance. The semiconductor device in the second region includes: a third semiconductor fin and a fourth semiconductor fin extending along a first direction; a second dielectric fin extending along the first direction and located between the third semiconductor fin and the fourth semiconductor fin, wherein sidewalls of the second dielectric fin are spaced apart a third distance along the second direction; and a second gate isolation structure vertically on the second dielectric fin, wherein sidewalls of the second gate isolation structure are spaced apart a fourth distance along the second direction, and the fourth distance is less than the third distance.

In some embodiments, the first region further includes a first metal gate layer extending along the second direction, wherein the first metal gate layer includes a first portion that spans the first semiconductor fin and a second portion that spans the second semiconductor fin.

In some embodiments, the second region further includes a second metal gate layer extending along the second direction, wherein the second metal gate layer includes a first portion crossing the third semiconductor layer and a second portion crossing the fourth semiconductor layer.

In some embodiments, the third distance is greater than the first distance.

In some embodiments, the first and second semiconductor fins are disposed as respective active channels of the first and second transistors in the first region, and the first dielectric fin is disposed as a dummy channel in the first region.

In some embodiments, the third and fourth semiconductor fins are provided as respective active channels for the third and fourth transistors in the second region, and the second dielectric fin is provided as a dummy channel in the second region.

In some embodiments, the first and second transistors are configured to operate at a first gate voltage, the third and fourth transistors are configured to operate at a second gate voltage, and the second gate voltage is greater than the first gate voltage.

Another embodiment of the invention discloses a semiconductor device. The semiconductor device includes: a first group of a plurality of transistors and a second group of a plurality of transistors. The gate voltage of the plurality of transistors operating the first group is set to be lower than the gate voltage of the plurality of transistors operating the second group. The first group of the plurality of transistors includes a first transistor having a first active gate structure and a second transistor having a second active gate structure. The first and second active gate structures are spaced apart from each other along a first direction by a first dielectric fin having a first width along the first direction and a first gate isolation structure having a second width along the first direction, the first width being equal to the second width. The second group of the plurality of transistors includes a third transistor having a third active gate structure and a fourth transistor having a fourth active gate structure. The third and fourth active gate structures are spaced apart from each other along the first direction by a second dielectric fin having a third width along the first direction and a second gate isolation structure having a fourth width along the first direction, the third width being greater than the fourth width.

In some embodiments, the second plurality of transistors includes a fifth transistor having a fifth active gate structure and a sixth transistor having a sixth active gate structure, and wherein the fifth and sixth active gate structures are spaced apart from each other along the first direction by a third dielectric fin and a third gate isolation structure, the third dielectric fin having a fifth width along the first direction, the third gate isolation structure having a sixth width along the first direction, and the fifth width is equal to the sixth width.

In some embodiments, the first transistor includes a first semiconductor fin extending along a second direction, the second transistor includes a second semiconductor fin extending along the second direction, and the second direction is perpendicular to the first direction, wherein the first dielectric fin also extends along the second direction and is located between the first semiconductor fin and the second semiconductor fin.

In some embodiments, the first active gate structure crosses over the first semiconductor fin, the second active gate structure crosses over the second semiconductor fin, and the first active gate structure and the second active gate structure extend along a first direction.

In some embodiments, the third transistor includes a third semiconductor fin extending along the second direction, the fourth transistor includes a fourth semiconductor fin extending along the second direction, and the second direction is perpendicular to the first direction, wherein the second dielectric fin also extends along the second direction and is located between the third semiconductor fin and the fourth semiconductor fin.

In some embodiments, the third active gate structure crosses the third semiconductor fin, the fourth active gate structure crosses the fourth semiconductor fin, and the third active gate structure and the fourth active gate structure extend along the first direction.

In some embodiments, the first and second pluralities of transistors are located in first and second regions of the substrate, respectively, and wherein a first density of transistors in the first region is greater than a second density of transistors in the second region.

In some embodiments, the third distance is greater than the first distance.

In another embodiment of the invention, a method of forming a semiconductor device is disclosed. The method includes forming a first semiconductor fin and a second semiconductor fin on a substrate extending along a first direction. The method includes forming a dielectric fin extending along a first direction and between a first semiconductor fin and a second semiconductor fin. The dielectric fin has a first width along a second direction, and the second direction is perpendicular to the first direction. The method includes forming a dummy gate structure extending along a second direction and across the first semiconductor fin, the second semiconductor fin, and the dielectric fin. The method includes confirming that the first width is greater than a predetermined threshold. The method includes removing a portion of the dummy gate structure on the dielectric fin to form a trench, and the trench has a second width along a second direction. The second width is less than the first width. The method includes filling the trench with a dielectric material.

In some embodiments, the method further includes confirming that the first width is less than or equal to a predetermined threshold to form the trench, and the trench has a third width along the second direction, wherein the third width is equal to the first width.

In some embodiments, the predetermined threshold is about 50 nm.

In some embodiments, the method further comprises replacing the dummy gate structure with an active gate structure comprising portions covering the first and second semiconductor fins, respectively, to form the first and second transistors.

In some embodiments, the first transistor and the second transistor are located in an input/output region on the substrate.

The features of the above-described embodiments are helpful to those skilled in the art in understanding the present invention. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced above. It should also be understood by those skilled in the art that these equivalent substitutions and alterations can be made without departing from the spirit and scope of the present invention, and that these changes, substitutions and alterations can be made without departing from the spirit and scope of the present invention.