阅读说明：本技术 逻辑闸及数字电路 (Logic gate and digital circuit ) 是由 王振志 何立玮 于 2021-03-01 设计创作，主要内容包括：本发明是一种逻辑闸及数字电路。所述逻辑闸包括第一至第五子层与贯穿硅通孔。第一子层包括第一导电性连接元件。第二子层位于第一子层上,且包括垂直连接至第一导电性连接元件的第一通孔。第三子层位于第二子层上,且包括电晶体区域及水平地连接至电晶体区域的第二导电性连接元件。第一通孔垂直连接至电晶体区域。电晶体区域包括多个电晶体。第四子层包括垂直连接至第三子层的第二通孔。第五子层位于第四子层上,且包括第三导电性连接元件。第二通孔垂直连接至第三导电性连接元件。贯穿硅通孔垂直连接至第三导电性连接元件。通过上述的结构,可达到增加密度的效果。(The invention relates to a logic gate and a digital circuit. The logic gate comprises a first sublayer, a second sublayer, a third sublayer, a fourth sublayer and a through silicon via. The first sub-layer includes a first electrically conductive connecting element. The second sub-layer is located on the first sub-layer and includes a first via vertically connected to the first conductive connection element. The third sub-layer is located on the second sub-layer and includes a transistor region and a second conductive connection element horizontally connected to the transistor region. The first via is vertically connected to the transistor region. The transistor region includes a plurality of transistors. The fourth sublayer includes a second via vertically connected to the third sublayer. The fifth sublayer is located on the fourth sublayer and includes a third electrically conductive connecting element. The second via is vertically connected to the third conductive connecting element. The through-silicon via is vertically connected to the third conductive connection element. By the structure, the effect of increasing the density can be achieved.)

1. A logic gate, comprising:

a first sublayer comprising a first electrically conductive connecting element;

a second sublayer overlying the first sublayer, wherein the second sublayer comprises a first via vertically connected to the first conductive connection element;

a third sub-layer located on the second sub-layer, the third sub-layer comprising a transistor region and a second conductive connection element horizontally connected to the transistor region, wherein the first via is vertically connected to the transistor region, and the transistor region comprises a plurality of transistors;

a fourth sublayer including a second via vertically connected to the third sublayer;

a fifth sublayer located over the fourth sublayer and comprising a third conductive connecting element, wherein the second via is vertically connected to the third conductive connecting element; and

a through silicon via vertically connected to the third conductive connection element.

2. The logic gate of claim 1, wherein the first sub-layer, the second sub-layer, the third sub-layer, the fourth sub-layer, the fifth sub-layer and the through silicon via are stacked in sequence.

3. The logic gate of claim 1, wherein the third sub-layer further comprises an input terminal horizontally connected to the second conductive connecting element, and the second conductive connecting element vertically connects the first via and the second via.

4. The logic gate of claim 3, wherein the transistors comprise a PMOS transistor and an NMOS transistor, a gate of the PMOS transistor being electrically connected to a gate of the NMOS transistor through the second conductive connection, wherein the gate of the PMOS transistor and the gate of the NMOS transistor are used as inputs.

5. The logic gate of claim 4, wherein the first sub-layer includes an output terminal horizontally connected to the first conductive connection element, wherein a drain region of the PMOS transistor and a drain region of the NMOS transistor are used as outputs.

6. The logic gate of claim 3, wherein the transistors comprise at least two PMOS transistors and at least two NMOS transistors, and wherein the PMOS transistors are electrically connected in parallel and the NMOS transistors are electrically connected in series.

7. The logic gate of claim 6, wherein the first sub-layer includes an output terminal horizontally connected to the first conductive connecting element.

8. The logic gate of claim 3, wherein the transistors comprise at least two PMOS transistors and at least two NMOS transistors, and wherein the PMOS transistors are electrically connected in series and the NMOS transistors are electrically connected in parallel.

9. The logic gate of claim 8, wherein said fifth sublayer comprises an output terminal horizontally connected to said third conductive connecting element.

10. The logic gate of claim 1, wherein said transistors of said third sub-layer include a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor and a sixth transistor,

wherein the first transistor and the second transistor define a first anti-gate, the third transistor and the fourth transistor define a second anti-gate, and the first anti-gate is electrically cross-coupled to the second anti-gate,

wherein the first and second inversion gates are electrically connected to the sixth and fifth transistors through the first and second sub-layers, respectively.

11. A digital circuit, comprising:

a plurality of logic gates as in claim 1, wherein said logic gates are in a coplanar structure, a stacked structure or a combination thereof.

Technical Field

The present disclosure relates to a logic gate and a digital circuit, and more particularly, to a logic gate and a digital circuit implemented by a fan-shaped field effect transistor (FanFET).

Background

The semiconductor transistor can be applied to electronic circuit devices and memory devices. Memory devices can be divided into volatile memory devices and non-volatile memory devices. The electronic circuit element can be widely applied to analog circuit design and digital circuit design, in particular to digital circuit design for processing digital signals. Generally, a digital circuit design is a switch circuit, which is a control unit and an operation unit composed of various gate circuits, flip-flops, various combinational logic circuits, and sequential logic circuits. Under the drive of the clock, the control unit controls the operation unit to complete the operation to be executed. For example, various Microcontrollers (MCUs), controllers (controllers), Digital Signal Processors (DSPs), Central Processing Units (CPUs), and Graphic Processing Units (GPUs), are all chips for digital logic applications. The digital circuit design and the analog circuit signal can also be connected with each other by an analog-to-digital converter and a digital-to-analog converter. In order to further improve the scaling capability of the digital circuit node technology and the performance of the chip electrical performance, a new transistor structure is needed.

Disclosure of Invention

According to some embodiments of the present disclosure, a logic gate includes a first sub-layer, a second sub-layer, a third sub-layer, a fourth sub-layer, a fifth sub-layer, and a through silicon via. The first sub-layer includes a first electrically conductive connecting element. The second sublayer via is located over the first sublayer. The second sub-layer includes a first via vertically connected to the first electrically conductive connection element. The third sub-layer is located on the second sub-layer and includes a transistor region and a second conductive connection element horizontally connected to the transistor region. The first via is vertically connected to the transistor region. The transistor region includes a plurality of the transistors. The fourth sublayer includes a second via vertically connected to the third sublayer. The fifth sublayer is located over the fourth sublayer and includes a third conductive connecting element. The second via is vertically connected to the third conductive connecting element. The through-silicon via is vertically connected to the third conductive connection element.

In some embodiments, the first sublayer, the second sublayer, the third sublayer, the fourth sublayer, the fifth sublayer and the through-silicon via are stacked in sequence.

In some embodiments, the third sublayer further comprises an input terminal horizontally connected to the second electrically conductive connection element. The second conductive connecting element vertically connects the first via and the second via.

In some embodiments, the transistors include PMOS transistors and NMOS transistors, the gates of the PMOS transistors are connected to the gates of the NMOS transistors through second conductive connection elements. The gate of the PMOS transistor and the gate of the NMOS transistor are used as input.

In some embodiments, the first sub-layer includes an output terminal horizontally connected to the first electrically conductive connecting element. The drain region of the PMOS transistor and the drain region of the NMOS transistor are used as outputs.

In some embodiments, the transistors include at least two PMOS transistors and at least two NMOS transistors. The PMOS transistors are electrically connected in parallel, and the NMOS transistors are electrically connected in series.

In some embodiments, the first sub-layer includes an output terminal horizontally connected to the first electrically conductive connecting element.

In some embodiments, the transistors include at least two PMOS transistors and at least two NMOS transistors. The PMOS transistors are electrically connected in series, and the NMOS transistors are electrically connected in parallel.

In some embodiments, the fifth sublayer comprises an output terminal horizontally connected to the third electrically conductive connecting element.

In some embodiments, the transistors of the third sub-layer include a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor. The first and second transistors define a first inversion gate, and the third and fourth transistors define a second inversion gate. The first and second back gates are cross-coupled. The first and second inversion gates are electrically connected to the sixth and fifth transistors through the first and second sub-layers, respectively.

According to some embodiments of the present disclosure, the digital circuit includes a plurality of logic gates as described above. The logic gate is a coplanar structure, a stacked structure or a combination thereof.

By the technical scheme, the logic gate and the digital circuit can achieve the effect of increasing the density, and further achieve the effect of improving the efficiency.

Embodiments of the present disclosure provide several advantages. It is to be understood, however, that other embodiments may provide different advantages, that not all advantages need be disclosed herein, and that no one particular advantage is a requirement of all embodiments.

It is to be understood that both the foregoing general description and the following detailed description are examples, and are intended to provide further explanation of the disclosure.

Drawings

Embodiments of the present disclosure may be more completely understood in consideration of the following detailed description of the embodiments in connection with the accompanying drawings, which are described below.

Fig. 1A is a side view of a fan field effect transistor (FanFET), fig. 1B is a top view of the FanFET as shown in fig. 1A, and fig. 1C is a cross-sectional view of the FanFET as shown in fig. 1A, in accordance with some embodiments of the present disclosure.

Fig. 2A is a side view of another FanFET, fig. 2B is a top view of the FanFET as shown in fig. 2A, and fig. 2C is a cross-sectional view of the FanFET as shown in fig. 2A, in accordance with some embodiments of the present disclosure.

Fig. 3A is a side view of another FanFET, fig. 3B is a top view of the FanFET as shown in fig. 3A, and fig. 3C is a cross-sectional view of the FanFET as shown in fig. 3A, in accordance with some embodiments of the present disclosure.

Fig. 4A, 4B, 4C, 5A, 5B, 6A, 6B, and 6C are cross-sectional views of a FanFET according to some embodiments of the present disclosure.

Fig. 7 is a top view of a FanFET according to some embodiments of the present disclosure.

Fig. 8 is a schematic diagram of a layer-by-layer fabricated digital circuit stack assembly according to some embodiments of the present disclosure.

FIG. 9A is a schematic diagram of a back gate.

FIG. 9B is a schematic diagram of a NAND gate.

FIG. 9C is a schematic diagram of a NOR gate.

Fig. 9D and 9E are schematic diagrams of an SRAM.

[ description of main element symbols ]

1：FanFET 2：FanFET

3：FanFET 4a：FanFET

4b：FanFET 4c：FanFET

5a：FanFET 5b：FanFET

6a：FanFET 6b：FanFET

6c：FanFET 7：FanFET

10: substrate 20: dielectric layer

40: substrate 50: thin oxide layer

60: gate dielectric layer BL: bit line

A reverse bit line C: channel region

G: a gate GN: NMOS gate

GND: and a ground wire GP: PMOS gate

I1: first back-gate I2: second back-gate

L0: formation L1: first layer

L11: first sublayer L11O: output terminal

L11V: conductive connection via L11X: conductive connecting wire

L11 XN: conductive connection line L11 XP: conductive connecting wire

L11Y: conductive connection line Q: conductive connecting wire

Conductive connecting line L12: second sub-layer

L13: third sublayer L13I: input terminal

L13 IA: input terminal L13 IB: input terminal

L13N: NMOS transistor L13P: PMOS transistor

L13R: transistor region L13X: conductive connecting wire

L13Y: conductive connecting line L14: the fourth sublayer

L15: fifth sublayer L15V: conductive connecting through hole

L15X: conductive connection line L15 XN: conductive connecting wire

L15 XP: conductive connection line L15Y: conductive connecting wire

L15O: output terminal L2: second layer

L21: first sublayer L22: second sub-layer

L23: third sublayer L24: the fourth sublayer

L25: fifth sublayer M1: transistor with a metal gate electrode

M2: transistor M3: transistor with a metal gate electrode

M4: transistor M5: transistor with a metal gate electrode

M6: transistor S/D: source/drain region

TSV 1: through-silicon via TSV 2: through silicon via

WL: word line Vdd: positive supply voltage

X: axis Y: shaft

Z: shaft

Detailed Description

Reference will now be made in detail to the embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. The present disclosure contemplates that, to the extent possible, the same reference numbers will be used in the drawings and the description to refer to the same or like parts.

Furthermore, spatially relative terms, such as "below" …, "below" lower "upper" and "upper," and similar terms, are used for convenience in describing the relative relationship of one element or feature to another element or feature in the drawings. These spatially relative terms may be used to facilitate understanding of various orientations of the elements in use or operation in addition to the orientation depicted in the figures. The spatially relative descriptors used in this disclosure may also be used to facilitate understanding when the elements are rotated to other orientations, such as 90 degrees or other orientations.

FIGS. 1A to 1C, 2A to 2C, and 3A to 3C illustrate various types of fan-shaped field effect transistors (FAnFETs). The FanFET is suitable for integrated circuits of transistors and memory cells. Fig. 1A, 2A, and 3A are side views of various types of a FanFET according to some embodiments of the present disclosure. Fig. 1B, 2B, and 3B are top views of various types of fanfets, respectively, according to some embodiments of the present disclosure. Fig. 1C, 2C, and 3C are cross-sectional views of various types of a FanFET according to some embodiments of the present disclosure.

Referring to fig. 1A to 1C, the FanFET 1 includes a substrate 10, source/drain regions S/D and a channel region C in the substrate 10, a gate G, and a dielectric layer 20 (which may be referred to herein as a gate dielectric layer) between the gate G and the substrate 10. The substrate 10 tapers (taper) in a direction away from the dielectric layer 20. In some embodiments, the substrate 10 may taper to a point. For example, in the embodiment as depicted in fig. 1B, the shape of the substrate 10 may be an equilateral triangle, an acute triangle, and an obtuse triangle in top view in some embodiments. The channel region C is between the source/drain regions S/D and is doped with a different type of dopant than the source/drain regions S/D. Alternatively, the regions of the substrate 10 remote from the channel region C and the source/drain regions S/D may be doped with an appropriate dopant. The dielectric layer 20 contacts the sidewalls closest to the source/drain regions S/D and the channel region C in the substrate 10. The gate G is in contact with the dielectric layer 20.

In some embodiments, the substrate 10 may be made of, for example, polysilicon. The source/drain regions S/D are doped with either an n-type dopant (e.g., phosphorous or arsenic) or a p-type dopant (e.g., boron). The channel region C is doped with a dopant having a conductivity different from that of the source/drain regions S/D. The region of the substrate 10 away from the channel region C and the source/drain regions S/D may be selectively doped with the same dopant as the channel region C.

In some embodiments, the dielectric layer 20 may be a single layer of film or a multi-layer film. For example, in some embodiments, the dielectric layer 20 is a single oxide layer, while in other embodiments, the dielectric layer 20 is a two-layer film made of an oxide layer (referred to as a tunnel oxide in some embodiments) and a nitride layer between the oxide layer and the gate electrode G. In some embodiments, the dielectric layer 20 is a high dielectric constant dielectric layer or a combination with multiple thin films. For example, the dielectric layer 20 may include one layer of a metal oxide or a silicate of Hf, Al, Zr, combinations thereof. Other suitable materials include La, Mg, Ba, Ti, Pb, Zr in the form of metal oxides, metal alloy oxides, and combinations thereof. Exemplary materials include MgO_x、BaTi_xO_y、BaSr_xTi_yO_z、PbTi_xO_y、PbZr_xTi_yO_z、SiCN、SiON、SiN、Al₂O₃、La₂O₃、Ta₂O₅、Y₂O₃、HfO₂、ZrO₂、HfSiON、YGe_xO_y、YSi_xO_yAnd LaAlO₃And other suitable materials.

In some embodiments, the gate electrode G is made of a conductive material, such as doped polysilicon, tantalum nitride (TaN), other conductive nitrides, tungsten, other metals, or combinations thereof. For example, the gate G is made of TaN.

Fig. 2A-2C illustrate another FanFET (FanFET 2) that is similar in many features to the FanFET 1, except for the shape of the substrate 10. In some embodiments as depicted in fig. 2A-2C, the shape of the substrate 10 is trapezoidal in top view in some embodiments. In detail, the substrate 10 includes a long base in contact with the dielectric layer 20, and a short base shorter than the long base and distant from the dielectric layer 20. Due to the trapezoidal shape, as illustrated in fig. 2B, the substrate 10 is also tapered in a direction away from the dielectric layer 20.

Fig. 3A-3C illustrate another FanFET (FanFET 3) that is similar in many features to the FanFET 1, except for the shape of the substrate 10. In some embodiments as depicted in fig. 3A-3C, the shape of the substrate 10 is hemispherical, semi-elliptical, semi-cylindrical, semi-elliptical cylinder-like (SECL), and other suitable shapes in some embodiments. Due to the hemispherical shape, as shown in fig. 3B, the substrate 10 is also tapered in a direction away from the dielectric layer 20.

Fig. 4A-4C, 5A-5B, 6A-6C, and 7 are various types of fanfets according to some embodiments of the present disclosure. Fig. 4A depicts another FanFET (FanFET 4A) that is similar to many of the features of the FanFET 1, the FanFET 2, and/or the FanFET 3 as depicted in fig. 1A-1C, 2A-2C, and 3A-3C, except for the shape of the substrate 10 in cross-section. In some embodiments as illustrated in fig. 4A, the substrate 10 is triangular in shape in cross-section. In detail, the triangular substrate 10 has two inclined sides which meet at a tip end away from the dielectric layer 20 in a cross-sectional view. Fig. 4B depicts another FanFET (FanFET 4B) that is similar in many features to the FanFET 4a, except for the shape of the substrate 10 in cross-section. In detail, the triangular substrate 10 has a substantially straight side and a slanted side meeting at a tip away from the dielectric layer 20, and the substantially straight side is located higher than the slanted side in the cross-sectional view. Fig. 4C depicts another FanFET (FanFET 4C) that is similar in many features to the FanFET 4b, except for the shape of the substrate 10 in cross-section. In detail, the triangular substrate 10 has a substantially straight side and a slanted side that meets away from the tip of the dielectric layer 20 in a cross-sectional view, and the substantially straight side is located lower than the slanted side in the cross-sectional view.

Fig. 5A depicts another FanFET (FanFET 5A) that is similar to many of the features of the FanFET 1, the FanFET 2, and/or the FanFET 3 as depicted in fig. 1A-1C, 2A-2C, and 3A-3C, except for the shape of the substrate 10 in cross-section. In some embodiments as illustrated in fig. 5A, the substrate 10 is trapezoidal in shape in cross-section. In detail, in the cross-sectional view, the trapezoid substrate 10 has a long base contacting the dielectric layer 20 and a short base far from the dielectric layer 20. It should be appreciated that if the FanFET 5a has a top view profile as illustrated in fig. 1B or fig. 3B, the short base of the trapezoidal substrate 10 would resemble a line in a perspective view in cross-section. In contrast, if the FanFET 5a has a top view profile as illustrated in fig. 2B, the short base of the trapezoidal substrate 10 would resemble a surface in a perspective view in a cross-sectional view.

Fig. 5B depicts another FanFET (FanFET 5B) that is similar in many features to the FanFET 5a, except for the shape of the substrate 10 in cross-section. In detail, the trapezoid substrate 10 as illustrated in fig. 5B has a short base contacting the dielectric layer 20 and a long base far from the dielectric layer 20. It should be appreciated that if the FanFET 5B has a top view profile as illustrated in fig. 1B or fig. 3B, the long base of the trapezoidal substrate 10 would resemble a line in a perspective view in cross-section. In contrast, if the FanFET 5B has a top view profile as illustrated in fig. 2B, the long base of the trapezoidal substrate 10 would be similar to a surface in a perspective view in a cross-sectional view.

Fig. 6A depicts another FanFET (FanFET 6A) that is similar to many of the features of the FanFET 1, the FanFET 2, and/or the FanFET 3 as depicted in fig. 1A-1C, 2A-2C, and 3A-3C, except for the shape of the substrate 10 in cross-section. In some embodiments as depicted in fig. 6A, the substrate 10 has a curved end away from the dielectric layer 20 in cross-section. Fig. 6B depicts another FanFET (FanFET 6B) that is similar in many features to the FanFET 6a, except for the shape of the substrate 10 in cross-section. In detail, the substrate 10 is tapered in a direction away from the dielectric layer 20, and also has a curved end away from the dielectric layer 20 in a cross-sectional view. Fig. 6C depicts another FanFET (FanFET 6C) that is similar in many features to the FanFET 6a, except for the shape of the substrate 10 in cross-section. In detail, the substrate 10 is tapered in a direction toward the dielectric layer 20, and also has a curved end away from the dielectric layer 20 in a cross-sectional view.

Fig. 7 depicts another FanFET (FanFET 7) that is similar to many of the features of the FanFET 1, the FanFET 2, the FanFET 3, the FanFET 4A-the FanFET 4C, the FanFET 5A-the FanFET 5B, and/or the FanFET 6A-the FanFET 6C as depicted in fig. 1A-1C, fig. 2A-2C, fig. 3A-3C, fig. 4A-4C, fig. 5A-5B, and fig. 6A-6C, except for the shape of the substrate 10 in top view. In some embodiments as depicted in fig. 7, the substrate 10 is tapered in a direction away from the dielectric layer 20, and also has a curved end in a top view.

It should be understood that all of the geometries depicted in fig. 1A-1C, 2A-2C, 3A-3C, 4A-4C, 5A-5B, 6A-6C, and 7 are merely examples of a FanFET and are not intended to limit the scope of the present disclosure. Any other variations or aspects of the FanFET are intended to be included within the scope of the present disclosure.

Fig. 8 is a schematic diagram of a layer by layer (layer) digital circuit stack set according to some embodiments of the present disclosure. Referring to fig. 8, the digital circuit stack set may include a ground layer L0, a first layer L1, and a second layer L2. The digital circuit stack set may include more than three layers. The formation L0 may include a ground line (GND). The first layer L1 includes a first sublayer L11, a second sublayer L12, a third sublayer L13, a fourth sublayer L14, a fifth sublayer L15, and a through-silicon via (TSV) TSV 1. In detail, the logic gate may include a ground layer L0 and a first layer L1. The first sublayer L11 may include first conductive connection elements. In some embodiments, the formation L0 is vertically connected to the first sublayer L11. The second sublayer L12 is disposed over the first sublayer L11. The third sublayer L13 is disposed over the second sublayer L12. The fourth sublayer L14 is disposed over the third sublayer L13. The fifth sublayer L15 is disposed over the fourth sublayer L14. Through-silicon via TSV1 is disposed above fifth sublayer L15. The first sublayer L11, the second sublayer L12, the third sublayer L13, the fourth sublayer L14, the fifth sublayer L15 and the through-silicon via TSV1 are stacked in sequence.

The first sublayer L11 may include electrically conductive connection elements and output terminals. In detail, the conductive connection elements of the first sub-layer L11 may include conductive connection lines and conductive connection vias. The electrically conductive connection lines may include longitudinal electrically conductive connection lines and transverse electrically conductive connection lines. For example, the longitudinal conductive connection lines may be along the X-axis, the transverse conductive connection lines may be along the Y-axis, and the conductive connection vias may be along the Z-axis.

The second sublayer L12 may include vias. The vias of the second sublayer L12 are vertically connected to the electrically conductive connecting elements of the first sublayer L11. In detail, the via of the second sub-layer L12 may be along the Z-axis, and the via may be vertically connected to the conductive connection line and the conductive connection via of the first sub-layer L11.

The third sub-layer L13 may include transistor regions, conductive connection elements, and input terminals. The vias of the second sublayer L12 may be vertically connected to the transistor regions of the third sublayer L13. The transistor region of the third sublayer L13 may include a transistor (FanFET) and may have a geometry corresponding to the FanFET 1, FanFET 2, FanFET 3, FanFET 4A-FanFET 4C, FanFET 5A, FanFET 5B, FanFET 6A-FanFET 6C, and FanFET 7, respectively illustrated in fig. 1A-1C, 2A-2C, 3A-3C, 4A-4C, 5A-5B, 6A-6C, and 7. The transistors of the transistor region of the third sublayer L13 may include the substrate 10, the source region S, the drain region D, and the gate G illustrated in fig. 1A to 1C, fig. 2A to 2C, fig. 3A to 3C, fig. 4A to 4C, fig. 5A to 5B, fig. 6A to 6C, and fig. 7.

Similarly, the conductive connecting elements of the third sub-layer L13 may include conductive connecting lines and conductive connecting vias. The electrically conductive connection lines may include longitudinal electrically conductive connection lines and transverse electrically conductive connection lines. For example, the longitudinal conductive connection lines may be along the X-axis, the transverse conductive connection lines may be along the Y-axis, and the conductive connection vias may be along the Z-axis.

The fourth sublayer L14 may include vias. The via of the fourth sublayer L14 may be vertically connected to the third sublayer L13. For example, the vias of the fourth sublayer L14 may be vertically connected to the transistor regions of the third sublayer L13.

The fifth sublayer L15 may include electrically conductive connection elements and output terminals. In detail, the conductive connection elements of the fifth sublayer L15 may include conductive connection lines and conductive connection vias. The electrically conductive connection lines may include longitudinal electrically conductive connection lines and transverse electrically conductive connection lines. For example, the longitudinal conductive connection lines may be along the X-axis, the transverse conductive connection lines may be along the Y-axis, and the conductive connection vias may be along the Z-axis. In some embodiments, the fifth sublayer L15 may include an output terminal horizontally connected to the electrically conductive connecting element of the fifth sublayer L15. The conductive connecting element of the third sub-layer L13 may also be connected to the conductive connecting element of the first sub-layer L11 and the conductive connecting element of the fifth sub-layer L15 through the through hole of the second sub-layer L12 and the through hole of the fourth sub-layer L14, respectively. That is, in this embodiment, the connection manner of the endpoints is not limited to the connection between the upper layer and the lower layer (e.g., the first sublayer L11 to the second sublayer L12), but may also be connected across layers (e.g., the third sublayer L13 is connected to the first sublayer L11 via the second sublayer L12).

The through-silicon vias TSV1 may be vertically connected to the conductive connection elements of the fifth sublayer L15. In some embodiments, through-silicon via TSV1 may be considered a biasing element (bias). For example, the TSV1 may include a positive supply voltage (Vdd), a voltage level, a Ground (GND), a word line, a bit line, or a bit line bar. From an electrical perspective, through-silicon via TSV1 may be used as a bias. From a process perspective, through-silicon via TSV1 may serve as a conductive connection element connecting the upper and lower layers.

In some embodiments, the electrically conductive connecting elements of the first, third and fifth sublayers L11, L13, L15 may be made of a polysilicon material. The gate of the transistor region of the third sublayer L13 may be made of polysilicon material. The second sublayer L12 and the fourth sublayer L14 may include an isolation layer and conductive vias in this isolation layer. Through-silicon via TSV1 may include an isolation layer and a conductive via in such an isolation layer. The transistors in the transistor region of the third sublayer L13 may include polysilicon, oxide layers, dielectric layers, and conductive layers.

The second layer L2 includes a first sublayer L21, a second sublayer L22, a third sublayer L23, a fourth sublayer L24, a fifth sublayer L25, and a through-silicon via TSV 2. Similarly, the second sublayer L22 is disposed over the first sublayer L21, the third sublayer L23 is disposed over the second sublayer L22, the fourth sublayer L24 is disposed over the third sublayer L23, the fifth sublayer L25 is disposed over the fourth sublayer L24, and the through-silicon via TSV2 is disposed over the fifth sublayer L25.

In some embodiments, the first layer L1 and the second layer L2 may constitute digital circuits. That is, the plurality of logic gates (e.g., the first layer L1 and the second layer L2) can be in a coplanar structure, a stacked structure, or a combination of a coplanar structure and a stacked structure.

It should be understood that the configurations of the first sublayer L21, the second sublayer L22, the third sublayer L23, the fourth sublayer L24, the fifth sublayer L25 and the through silicon via TSV2 are similar to the first sublayer L11, the second sublayer L12, the third sublayer L13, the fourth sublayer L14, the fifth sublayer L15 and the through silicon via TSV1, respectively, and the description will not be repeated.

The layer-by-layer digital circuit stack set shown in fig. 8 can be applied to logic gates, such as inversion gates, OR gates, exclusive-OR gates (XOR gates), NOR gates, exclusive-NOR gates (XNOR gates), AND gates (AND gates), NAND gates (NAND gates), Static Random Access Memories (SRAMs), AND so on. Furthermore, the FanFET described above may be applied to analog circuits.

FIG. 9A is a schematic diagram of a back gate. In other words, the structure of fig. 9A can be regarded as an equivalent circuit of the inverter. As shown in fig. 9A, the back gate includes a first sub-layer L11, a second sub-layer L12, a third sub-layer L13, a fourth sub-layer L14, a fifth sub-layer L15, and a TSV 1. The first sublayer L11 may include an output terminal L11O and an electrically conductive connecting element. The output terminal L11O is horizontally connected to the conductive connecting element. The conductive connection element may include a transverse conductive connection line L11Y along the Y-axis. For example, the output terminal L11O is horizontally connected to the transverse conductive connecting line L11Y.

The second sublayer L12 is disposed over the first sublayer L11. The second sublayer L12 includes vias. The third sublayer L13 is disposed over the second sublayer L12. The third sub-layer L13 may include a transistor region L13R and conductive connecting elements. The electrically conductive connecting element of the third sublayer L13 is horizontally connected to the transistor region L13R of the third sublayer L13. The conductive connection element may include a transverse conductive connection line L13Y along the Y-axis. In some embodiments, the third sublayer L13 further includes an input terminal L13I. The input terminal L13I is horizontally connected to the transverse electrically conductive connection line L13Y of the electrically conductive connection element of the third sublayer L13. The transistors in the transistor region of the third sublayer L13 may include an NMOS transistor L13N and a PMOS transistor L13P. The NMOS transistor L13N includes a substrate 40, a thin oxide layer 50, a gate dielectric layer 60 and a gate GN. It should be appreciated that NMOS transistor L13N may comprise a transistor (FanFET) and have the geometries illustrated in fig. 1A-1C, 2A-2C, 3A-3C, 4A-4C, 5A-5B, 6A-6C, and 7 corresponding to FanFET 1, FanFET 2, FanFET 3, FanFET 4A-4C, FanFET 5A, FanFET 5B, FanFET 6A-FanFET 6C, and FanFET 7, respectively. The gate GN of the NMOS transistor L13N in the transistor region of the third sublayer L13 may have the geometry of the gate G illustrated in FIGS. 1A-1C, 2A-2C, 3A-3C, 4A-4C, 5A-5B, 6A-6C, and 7. Similarly, the PMOS transistor L13P has a similar configuration to the NMOS transistor L13N, such as a substrate, a thin oxide layer, a gate dielectric layer, and a gate GP, and will not be described again. In some embodiments, the gate GP of the PMOS transistor L13P is connected to the gate GN of the NMOS transistor L13N and is considered as an input (e.g., the input terminal L13I). The drain region of the PMOS transistor L13P is connected to the drain region of the NMOS transistor L13N and is considered as an output (e.g., output terminal L11O).

The fourth sublayer L14 includes vias vertically connected to the third sublayer L13. The fifth sublayer L15 may be disposed over the fourth sublayer L14. The fifth sublayer L15 may include conductive connection elements that vertically connect to the vias of the fourth sublayer L14. For example, such a conductive connection element may comprise a conductive connection via along the Z-axis.

The through-silicon vias TSV1 are vertically connected to the conductive connecting elements of the fifth sublayer L15. Through-silicon via TSV1 may be considered a biasing element. For example, through-silicon via TSV1 may include a positive power supply voltage (Vdd) and Ground (GND). For example, as shown in fig. 9A, the through-silicon via TSV1 on the left may be considered a positive power supply voltage (Vdd). The positive power voltage (Vdd) may be set above the PMOS transistor L13P and electrically connected to the PMOS transistor L13P. Through-silicon via TSV1 on the right side may be considered Ground (GND). The Ground (GND) may be disposed above the NMOS transistor L13N and electrically connected to the NMOS transistor L13N. In detail, the source region of the PMOS transistor L13P and the source region of the NMOS transistor L13N may be connected to a positive power supply voltage (through-silicon via TSV1 on the left side) and a ground line (through-silicon via TSV1 on the right side), respectively. In some embodiments, the positive power supply voltage (through-silicon via TSV1 on the left) is aligned to the fourth sublayer L14 and the fifth sublayer L15. In some embodiments, the ground line (through-silicon via TSV1 on the right) is aligned with the fourth sublayer L14 and the fifth sublayer L15. In some embodiments, through-silicon via TSV1 may serve as a biasing or conductive connecting element to upper and lower layers.

FIG. 9B is a schematic diagram of a NAND gate. In other words, the structure of FIG. 9B can be considered as an equivalent circuit of a NAND gate. As shown in fig. 9B, the NAND gate includes a ground layer L0, a first sub-layer L11, a second sub-layer L12, a third sub-layer L13, a fourth sub-layer L14, a fifth sub-layer L15, and a through-silicon via TSV 1. The first sublayer L11 is vertically connected to the formation L0. The formation L0 may include Ground (GND). The first sublayer L11 may include electrically conductive connecting elements and output terminals L11O. The output terminal L11O is horizontally connected to the conductive connecting element of the first sublayer L11. The conductive connecting element may include a longitudinal conductive connecting line L11XP and a longitudinal conductive connecting line L11XN along the X-axis, a transverse conductive connecting line L11Y along the Y-axis, and a conductive connecting via L11V along the Z-axis. For example, the output terminal L11O, the longitudinal conductive connecting line L11XP, the longitudinal conductive connecting line L11XN, and the transverse conductive connecting line L11Y are horizontally connected.

The second sublayer L12 may include a via that may be vertically connected to the electrically conductive connection element of the first sublayer L11 (e.g., the longitudinal electrically conductive connection line L11X) or the output terminal L11O of the first sublayer L11. The third sublayer L13 may be disposed over the second sublayer L12. The third sublayer L13 may include a transistor region L13R vertically connected to the via of the second sublayer L12. Further, the third sublayer L13 includes a conductive connecting element and two input terminals L13I horizontally connected to the conductive connecting element. The input terminal L13I may include an input terminal L13IA and an input terminal L13 IB. The conductive connection element may include a transverse conductive connection line L13Y along the Y-axis and a longitudinal conductive connection line L13X along the X-axis. The transistors of the transistor region of the third sublayer L13 may include at least two PMOS transistors L13P and at least two NMOS transistors L13N. The PMOS transistor L13P is electrically connected in parallel, and the NMOS transistor L13N is electrically connected in series. In detail, the PMOS transistor L13P is electrically connected in parallel and connected to the TSV 1. The NMOS transistor L13N is electrically connected in series and connected to the ground L0. The gate GP of one of the PMOS transistors L13P and the gate GN of one of the NMOS transistors L13N are connected via a lateral conductive connection line L13Y and can be considered as two inputs (input terminal L13IA and input terminal L13 IB). The two PMOS transistors L13P in parallel and the two NMOS transistors L13N in series are electrically connected and can be connected to the output (output terminal L11O).

The fourth sublayer L14 may include vias vertically connected to the third sublayer L13. The fifth sublayer L15 may include conductive connection elements that vertically connect to the vias of the fourth sublayer L14. For example, such an electrically conductive connection element may comprise a longitudinal electrically conductive connection line L15XP and a longitudinal electrically conductive connection line L15XN along the X-axis.

Through-silicon via TSV1 is vertically connected to fifth sublayer L15. Through-silicon via TSV1 may be considered a biasing element. For example, through-silicon via TSV1 may include a positive supply voltage (Vdd). In some embodiments, through-silicon via TSV1 may serve as a biasing or conductive connecting element to upper and lower layers.

FIG. 9C is a schematic diagram of a NOR gate. In other words, the structure of FIG. 9C can be regarded as an equivalent circuit of a NOR gate. As shown in fig. 9C, the NOR gate includes a ground layer L0, a first sub-layer L11, a second sub-layer L12, a third sub-layer L13, a fourth sub-layer L14, a fifth sub-layer L15, and a through-silicon via TSV 1. The formation L0 may include Ground (GND). The first sublayer L11 may include electrically conductive connection elements that connect vertically to the formation L0. The conductive connecting element may include a longitudinal conductive connecting line L11XP and a longitudinal conductive connecting line L11XN along the X-axis.

The second sublayer L12 may include vias that connect vertically to the conductive connecting elements of the first sublayer L11. The third sublayer L13 is disposed over the second sublayer L12. The third sub-layer L13 may include a transistor region L13R vertically connected to the second sub-layer L12. The third sublayer L13 may include a conductive connecting element and two input terminals L13I horizontally connected to the conductive connecting element. The input terminal L13I may include an input terminal L13IA and an input terminal L13 IB. The conductive connection elements may include conductive connection lines and/or conductive connection vias. For example, the third sublayer L13 may include a longitudinal electrically conductive connection line L13X along the X-axis and a transverse electrically conductive connection line L13Y along the Y-axis. The transistors of the transistor region of the third sublayer L13 may include at least two PMOS transistors L13P and at least two NMOS transistors L13N. The PMOS transistor L13P is electrically connected in series, and the NMOS transistor L13N is electrically connected in parallel. In detail, the PMOS transistor L13P is electrically connected in series and connected to the through-silicon via TSV 1. The NMOS transistor L13N is electrically connected in parallel and connected to ground L0 (ground). The gate of one of the PMOS transistors L13P and the gate GN of one of the NMOS transistors L13N are electrically connected via a lateral conductive connection line L13Y and may be considered as two inputs (e.g., input terminal L13IA and input terminal L13 IB). The series PMOS transistor L13P and the parallel NMOS transistor L13N are electrically connected and can be connected to the output (e.g., output terminal L15O).

The fourth sublayer L14 may include vias vertically connected to the third sublayer L13. The fifth sublayer L15 may include electrically conductive connection elements that are vertically connected to the fourth sublayer L14. Further, the fifth sublayer L15 may include an output terminal L15O horizontally connected to the electrically conductive connecting element of the fifth sublayer L15. The conductive connecting element may include a longitudinal conductive connecting line L15XP and a longitudinal conductive connecting line L15XN along the X-axis, a transverse conductive connecting line L15Y along the Y-axis, and a conductive connecting via L15V along the Z-axis. For example, the output terminal L15O, the longitudinal conductive connecting line L15XP, the longitudinal conductive connecting line L15XN, and the transverse conductive connecting line L15Y are horizontally connected.

The through-silicon vias TSV1 are vertically connected to the conductive connecting elements of the fifth sublayer L15. For example, through-silicon via TSV1 is vertically connected to conductive connecting via L15V. Through-silicon via TSV1 may be considered a biasing element. For example, through-silicon via TSV1 may include a positive supply voltage (Vdd). In some embodiments, through-silicon via TSV1 may serve as a biasing or conductive connecting element to upper and lower layers.

The circuit design and transistor arrangement of the current SRAM are of various types, such as four transistors and two resistors (4T +2R), six transistors (6T), eight transistors (8T), etc. Some embodiments of the present disclosure describe six transistor SRAM (6T SRAM). Fig. 9D and 9E are schematic diagrams of an SRAM. In other words, the structures of fig. 9D and 9E can be regarded as equivalent circuits of SRAM. As shown in fig. 9D and 9E, the SRAM includes a first sublayer L11, a second sublayer L12, a third sublayer L13, a fourth sublayer L14, a fifth sublayer L15, and a through-silicon via TSV 1. The first sublayer L11 may include electrically conductive connection elements. The conductive connection elements may include a longitudinal conductive connection line L11X along the X-axis and a transverse conductive connection line L11Y along the Y-axis. One transverse electrically conductive link line L11Y may be considered Q and the other transverse electrically conductive link line L11Y may be considered an inverted Q (qbar;)。

the second sublayer L12 may include vias that connect vertically to the conductive connecting elements of the first sublayer L11. The third sublayer L13 may be disposed over the second sublayer L12. The third sub-layer L13 may include a transistor region L13R vertically connected to the second sub-layer L12. The transistors of the transistor region L13R of the third sublayer L13 may include a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5 and a sixth transistor M6. In detail, the first transistor M1 and the second transistor M2 define a first counter gate I1, the third transistor M3 and the fourth transistor M4 define a second counter gate I2, and the first counter gate I1 is electrically cross-coupled to the second counter gate I2. The transverse conductive connection line L11Y (e.g., Q and reverse Q) of the first sub-layer L11 is electrically connected to the fifth transistor M5 and the sixth transistor M6 for controlling the switch. In other words, the first and second gates I1 and I2 are electrically connected to the sixth and fifth transistors M6 and M5 through the first and second sub-layers L11 and L12, respectively. In some embodiments, Q may be referred to as the gates of transistor M1 and transistor M2, electrically connected to the drain region of transistor M3, the drain region of transistor M4, and the source region of transistor M6. In some embodiments, the aforementioned inverse Q (Q bar) can be used as the gates of the transistor M3 and the transistor M4, which are electrically connected to the drain region of the transistor M1, the drain region of the transistor M2, and the source region of the transistor M5.

In some embodiments, the first transistor M1, the third transistor M3, the fifth transistor M5, and the sixth transistor M6 can be regarded as NMOS transistors, and the second transistor M2 and the fourth transistor M4 can be regarded as PMOS transistors. In some embodiments, the third sublayer L13 may include electrically conductive connecting elements. The conductive connection elements may include conductive connection lines and/or conductive connection vias. For example, the third sublayer L13 may include a longitudinal conductive connection line L13X along the X-axis and a transverse conductive connection line L13Y along the Y-axis. For example, the transverse conductive connection L13Y is connected to the gates of the fifth transistor M5 and the sixth transistor M6.

The fourth sublayer L14 may include vias vertically connected to the third sublayer L13. The fifth sublayer L15 may include electrically conductive connection elements that are vertically connected to the fourth sublayer L14. The conductive connection elements may include conductive connection lines and/or conductive connection vias.

Through-silicon via TSV1 is vertically connected to fifth sublayer L15. Through-silicon via TSV1 may be considered a biasing element. In detail, the TSV1 may include a power voltage Vdd electrically connected to the source regions of the second and fourth transistors M2 and M4, and a ground GND electrically connected to the source regions of the first and third transistors M1 and M3. In some embodiments, through the tubeThe TSV1 may include word lines WL, bit lines BL and inversion bit linesIn detail, the word line WL is electrically connected to the gates of the transistor M5 and the transistor M6. The bit line BL is electrically connected to the drain region of the transistor M6. Inversion bit lineElectrically connected to the drain region of the transistor M5. Two NMOS transistors (transistor M5 and transistor M6) of the SRAM are used to control the reading and writing of data. The word line WL is used to determine the switching of the NMOS transistors (transistor M5 and transistor M6). Bit line (bit line BL and reverse bit line)) For reading and writing data. In some embodiments, through-silicon via TSV1 may serve as a biasing or conductive connecting element to upper and lower layers.

In the above embodiments, the logic gates and the plurality of logic gates are formed in a coplanar structure, a stacked structure or a combination thereof to achieve the effect of increasing the density and further achieve the effect of improving the performance.

Although the present invention has been described with reference to a preferred embodiment, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.