阅读说明：本技术 半导体器件及其制造方法 (Semiconductor device and method for manufacturing the same ) 是由 刘志拯 于 2021-01-14 设计创作，主要内容包括：本发明提供一种半导体器件及其制造方法,半导体器件包括：半导体衬底,所述半导体衬底内具有浅沟槽及所述浅沟槽限定的有源区,在沿预设方向上,所述浅沟槽具有交替排布的第一区域及第二区域,所述第一区域的宽度大于所述第二区域的宽度；浅沟槽隔离结构,填充在所述浅沟槽内,在所述第一区域,所述浅沟槽隔离结构至少包括依次设置的第一填充层及第二填充层,其中,所述第二填充层为低K介质层,在所述第二区域,所述浅沟槽隔离结构至少包括所述第一填充层。本发明优点是,利用第二填充层(低K介质材料)的隔离作用而阻挡电子的流通,从而避免了寄生电容的产生,从而避免了漏电流的产生,大大提高了半导体器件的电学性能,提高半导体器件的良率。(The invention provides a semiconductor device and a method of manufacturing the same, the semiconductor device including: the semiconductor device comprises a semiconductor substrate, wherein a shallow trench and an active region defined by the shallow trench are arranged in the semiconductor substrate, the shallow trench is provided with a first region and a second region which are alternately arranged along a preset direction, and the width of the first region is greater than that of the second region; the shallow trench isolation structure is filled in the shallow trench and at least comprises a first filling layer and a second filling layer which are sequentially arranged in the first area, wherein the second filling layer is a low-K dielectric layer, and the shallow trench isolation structure at least comprises the first filling layer in the second area. The invention has the advantages that the isolation effect of the second filling layer (low-K dielectric material) is utilized to block the circulation of electrons, thereby avoiding the generation of parasitic capacitance, avoiding the generation of leakage current, greatly improving the electrical performance of a semiconductor device and improving the yield of the semiconductor device.)

1. A semiconductor device, comprising:

the semiconductor device comprises a semiconductor substrate, wherein a shallow trench and an active region defined by the shallow trench are arranged in the semiconductor substrate, the shallow trench is provided with a first region and a second region which are alternately arranged along a preset direction, and the width of the first region is greater than that of the second region;

the shallow trench isolation structure is filled in the shallow trench and at least comprises a first filling layer and a second filling layer which are sequentially arranged in the first area, wherein the second filling layer is a low-K dielectric layer, and the shallow trench isolation structure at least comprises the first filling layer in the second area.

2. The semiconductor device of claim 1, wherein in the first region, the first fill layer covers sidewalls of the shallow trench, and the second fill layer covers the first fill layer sidewalls and fills the shallow trench.

3. The semiconductor device according to claim 1, wherein the first filling layer fills the shallow trench in the second region.

4. The semiconductor device according to claim 1, wherein the first filling layer is an oxide layer.

5. The semiconductor device according to claim 1, wherein a dielectric constant of the second filling layer is less than or equal to 4.

6. The semiconductor device according to claim 1, wherein a width of the second filling layer is smaller than a width of the first region and is greater than or equal to one third of the width of the first region in a predetermined direction.

7. The semiconductor device according to any one of claims 1 to 6, wherein the shallow trench further comprises a third region, the width of the third region is greater than that of the first region, and in the third region, the shallow trench isolation structure comprises at least the first filling layer, the second filling layer and a third filling layer which are sequentially arranged.

8. The semiconductor device of claim 7, wherein in the third region, the shallow trench isolation structure further comprises a fourth filling layer covering the third filling layer and filling up the shallow trench.

9. The semiconductor device according to claim 8, wherein the third filling layer is a nitride layer, and wherein the fourth filling layer is an oxide layer.

10. The semiconductor device according to claim 7, wherein the semiconductor device comprises an array region and a peripheral circuit region, the first region and the second region are located in the array region, and the third region is located in the peripheral circuit region.

11. The semiconductor device of claim 1, further comprising a plurality of word lines sequentially passing through the active region and the shallow trench isolation structure along the predetermined direction.

12. A method for manufacturing a semiconductor device according to any one of claims 1 to 11, comprising the steps of:

providing a semiconductor substrate, wherein a shallow trench and an active region defined by the shallow trench are arranged in the semiconductor substrate, the shallow trench is provided with a first region and a second region which are alternately arranged along a preset direction, and the width of the first region is greater than that of the second region;

and forming a shallow trench isolation structure in the shallow trench, wherein the shallow trench isolation structure at least comprises a first filling layer and a second filling layer which are sequentially arranged in the first area, the second filling layer is a low-K dielectric layer, and the shallow trench isolation structure at least comprises the first filling layer in the second area.

13. The method of manufacturing a semiconductor device according to claim 12, wherein the step of forming the shallow trench isolation structure within the shallow trench further comprises:

forming a first filling layer in the shallow trench, wherein the first filling layer covers the side wall of the shallow trench in the first region, and the first filling layer fills the shallow trench in the second region;

and forming a second filling layer in the shallow trench, wherein in the first area, the second filling layer covers the first filling layer and fills the shallow trench.

14. The method for manufacturing a semiconductor device according to claim 13, wherein the shallow trench further comprises a third region, a width of the third region being larger than a width of the first region;

the step of forming a first fill layer within the shallow trench further comprises, in the third region, the first fill layer covering sidewalls of the shallow trench;

the step of forming a second filling layer in the shallow trench further comprises: in the third area, the second filling layer covers the side wall of the first filling layer;

and forming a third filling layer in the shallow trench, wherein the third filling layer covers the second filling layer in the third area.

15. The method for manufacturing a semiconductor device according to claim 14, further comprising, after the step of forming a third filling layer in the shallow trench:

and forming a fourth filling layer in the shallow trench, wherein in the third area, the fourth filling layer covers the third filling layer and fills the shallow trench.

16. The method of manufacturing a semiconductor device according to claim 12, further comprising, after the step of forming a shallow trench isolation structure in the shallow trench:

and forming a plurality of word lines, wherein the word lines sequentially penetrate through the active region and the shallow trench isolation structure along the preset direction.

Technical Field

The present invention relates to the field of semiconductor manufacturing, and more particularly, to a semiconductor device and a method for manufacturing the same.

Background

With the high integration of semiconductors, more and more advanced processes are applied to the semiconductor manufacturing process. As moore's law evolves to the level of 1Xnm, it is required that the arrangement of the active regions is more dense. The novel 3 x 2 structure enables the layout of the memory cell to be closer to the closest packing through the staggered arrangement of the active regions. However, it is the layout of the active regions that are staggered so that the Word Lines (WL) periodically pass through the region between two active regions in a given direction. Fig. 1 is a schematic diagram of the distribution of active regions and word lines of a conventional semiconductor device, and referring to fig. 1, in a direction D (i.e., an extending direction of the word lines 10), the word lines 10 periodically pass through a region a between two active regions 11. The word lines Passing through region a are referred to as pass word lines (paging WL). With the increase of the arrangement density, the distance between the word lines is smaller and smaller, when one word line is turned on, besides the influence on the passing active region, a PN junction is induced between the position passing through the word line (i.e., the region a) and the word line which is not turned on the adjacent active region, and a parasitic capacitance is generated, thereby causing junction leakage (junction leakage) and further reducing the product yield.

Therefore, a new semiconductor device is needed to reduce or eliminate junction leakage and improve the yield of the semiconductor device.

Disclosure of Invention

The invention aims to provide a semiconductor device and a manufacturing method thereof.

In order to solve the above technical problem, the present invention provides a semiconductor device including: the semiconductor device comprises a semiconductor substrate, wherein a shallow trench and an active region defined by the shallow trench are arranged in the semiconductor substrate, the shallow trench is provided with a first region and a second region which are alternately arranged along a preset direction, and the width of the first region is greater than that of the second region; the shallow trench isolation structure is filled in the shallow trench and at least comprises a first filling layer and a second filling layer which are sequentially arranged in the first area, wherein the second filling layer is a low-K dielectric layer, and the shallow trench isolation structure at least comprises the first filling layer in the second area.

Further, in the first region, the first filling layer covers the side wall of the shallow trench, and the second filling layer covers the side wall of the first filling layer and fills the shallow trench.

Further, in the second region, the shallow trench is filled with the first filling layer.

Further, the first filling layer is an oxide layer.

Further, the dielectric constant of the second filling layer is less than or equal to 4.

Further, in a preset direction, the width of the second filling layer is smaller than the width of the first area and is greater than or equal to one third of the width of the first area.

Further, the shallow trench further comprises a third region, the width of the third region is greater than that of the first region, and in the third region, the shallow trench isolation structure at least comprises the first filling layer, the second filling layer and a third filling layer which are sequentially arranged.

Further, in the third region, the shallow trench isolation structure further includes a fourth filling layer, and the fourth filling layer covers the third filling layer and fills the shallow trench.

Further, the third filling layer is a nitride layer, and the fourth filling layer is an oxide layer.

Further, the semiconductor device includes an array region and a peripheral circuit region, the first region and the second region are located in the array region, and the third region is located in the peripheral circuit region.

Furthermore, the semiconductor device further comprises a plurality of word lines, and the word lines sequentially penetrate through the active region and the shallow trench isolation structure along the preset direction.

The present invention also provides a method for manufacturing the semiconductor device as described above, comprising the steps of: providing a semiconductor substrate, wherein a shallow trench and an active region defined by the shallow trench are arranged in the semiconductor substrate, the shallow trench is provided with a first region and a second region which are alternately arranged along a preset direction, and the width of the first region is greater than that of the second region; and forming a shallow trench isolation structure in the shallow trench, wherein the shallow trench isolation structure at least comprises a first filling layer and a second filling layer which are sequentially arranged in the first area, the second filling layer is a low-K dielectric layer, and the shallow trench isolation structure at least comprises the first filling layer in the second area.

Further, the step of forming the shallow trench isolation structure in the shallow trench further comprises: forming a first filling layer in the shallow trench, wherein the first filling layer covers the side wall of the shallow trench in the first region, and the first filling layer fills the shallow trench in the second region; and forming a second filling layer in the shallow trench, wherein in the first area, the second filling layer covers the first filling layer and fills the shallow trench.

Further, the shallow trench also comprises a third area, and the width of the third area is greater than that of the first area; the step of forming a first fill layer within the shallow trench further comprises, in the third region, the first fill layer covering sidewalls of the shallow trench; the step of forming a second filling layer in the shallow trench further comprises: in the third area, the second filling layer covers the side wall of the first filling layer; and forming a third filling layer in the shallow trench, wherein the third filling layer covers the second filling layer in the third area.

Further, after the step of forming the third filling layer in the shallow trench, the method further includes: and forming a fourth filling layer in the shallow trench, wherein in the third area, the fourth filling layer covers the third filling layer and fills the shallow trench.

Further, after the step of forming the shallow trench isolation structure in the shallow trench, the method further includes: and forming a plurality of word lines, wherein the word lines sequentially penetrate through the active region and the shallow trench isolation structure along the preset direction.

The invention has the advantages that the isolation effect of the second filling layer (low-K dielectric material) is utilized to block the circulation of electrons, thereby avoiding the generation of parasitic capacitance, avoiding the generation of leakage current, greatly improving the electrical performance of a semiconductor device and improving the yield of the semiconductor device.

Drawings

FIG. 1 is a schematic diagram of an active region and word lines of a conventional semiconductor device;

fig. 2 is a schematic top view of a semiconductor device of a first embodiment of the present invention;

FIG. 3 is a schematic cross-sectional view taken along line B-B of FIG. 2;

fig. 4 is a schematic top view of a semiconductor device provided with word lines;

fig. 5 is a schematic cross-sectional view of a semiconductor device of a second embodiment of the present invention;

fig. 6 is a schematic step view of a method for manufacturing a semiconductor device according to an embodiment of the present invention;

fig. 7A to 7H are process flow diagrams of a method of manufacturing a semiconductor device according to an embodiment of the present invention.

Detailed Description

Embodiments of a semiconductor device and a method for manufacturing the same according to the present invention will be described in detail below with reference to the accompanying drawings.

Fig. 2 is a schematic top view of a semiconductor device according to a first embodiment of the present invention, and fig. 3 is a schematic cross-sectional view taken along line B-B in fig. 2. Referring to fig. 2 and 3, the semiconductor device includes a semiconductor substrate 200 and a shallow trench isolation structure 210.

The semiconductor substrate 200 may be a single crystal silicon substrate, a Ge substrate, a SiGe substrate, an SOI, a GOI, or the like, and an appropriate semiconductor material may be selected as the semiconductor substrate 200 according to actual requirements of devices, which is not limited herein. In this embodiment, the semiconductor substrate 200 is a single crystalline silicon substrate.

The semiconductor substrate 200 has a shallow trench 201 and an active region 202 defined by the shallow trench 201. In this embodiment, the shallow trenches 201 are formed in the semiconductor substrate 200 by using photolithography and etching processes, and the regions between the shallow trenches 201 are the active regions 202. The active region 202 extends along a set direction C, i.e. the active region 202 runs along the direction C.

In a predetermined direction, the shallow trench 201 has first regions 201A and second regions 201B alternately arranged, and a width of the first region 201A is greater than a width of the second region 201B. In fig. 2, the first region 201A and the second region 201B are schematically enclosed by dashed boxes.

The preset direction is shown as direction D in fig. 2. In the direction D, between two active regions 202 arranged at an interval, the width of the shallow trench 201 is larger, which is the first region 201A, and between two active regions 202 arranged adjacently, the width of the shallow trench 201 is smaller, which is the second region 201B. Wherein the predetermined direction is an extension of a subsequently formed word line that periodically passes through the first region 201A, the active region 202, the second region 201B, and the active region 202. The word line Passing through the first region 201A is a Passing word line (paging WL). The predetermined direction (D direction) and the extending direction (C direction) of the active region 202 have an angle, which depends on the manufacturing process of the active region 202.

The shallow trench isolation structure 210 is filled in the shallow trench 201 to isolate the active region 202. In the first region 201A, the shallow trench isolation structure 210 at least includes a first filling layer 210A and a second filling layer 210B, which are sequentially disposed, where the second filling layer 210B is a low-K dielectric layer, and in the second region 201B, the shallow trench isolation structure at least includes the first filling layer 210A.

In this embodiment, in the first region 201A, the shallow trench isolation structure 210 has two layers, wherein a first filling layer 210A covers a sidewall of the shallow trench 201, and a second filling layer 210B covers a sidewall of the first filling layer 210A and fills the shallow trench; in the second region 201B, the shallow trench isolation structure 210 is a layer, and the first filling layer 210A covers the sidewall of the shallow trench 201 and fills the shallow trench.

Since the width of the first region 201A is greater than the width of the second region 201B, after the first filling layer 210A is formed in the shallow trench, the shallow trench 201 in the first region 201A is not filled, and therefore, the second filling layer 210B is continuously filled in the first region 201A.

The second filling layer 210B is a low-K dielectric layer, which can reduce parasitic capacitance caused by word lines, thereby reducing leakage current. Specifically, referring to fig. 4, which is a schematic top view of a semiconductor device provided with word lines, a plurality of word lines 220 sequentially pass through the active region 202 and the shallow trench isolation structure 210 along the predetermined direction (D direction), that is, the word lines 220 periodically sequentially pass through the first region 201A, the active region 202, the second region 201B and the active region 202. In the first region 201A, due to the existence of the second filling layer 210B, when the word line passing through the first region 201A is turned on, the second filling layer 210B can play a good role in isolation, and can prevent the word line 220 from being turned on to cause electrons to flow to the active region 202, so that the generation of parasitic capacitance between the word line 220 located in the first region 201A and the word line which passes through the active region 202 and is not turned on beside the word line is avoided, the generation of leakage current is avoided, and the electrical performance of the semiconductor device is greatly improved.

For example, referring to fig. 4, taking the word line 220-1, the word line 220-2, and the word line 220-3 as an example, the word line 220-1 extends along the direction D and periodically sequentially passes through the first region 201A, the active region 202, the second region 201B, and the active region 202, the word line 220-2 extends along the direction D and periodically sequentially passes through the first region 201A, the active region 202, the second region 201B, and the active region 202, the word line 220-3 extends along the direction D and periodically sequentially passes through the first region 201A, the active region 202, the second region 201B, and the active region 202, when the word line 220-1 is activated and the word line 220-2 and the word line 220-3 are not activated, the second filling layer 210B can perform a good isolation function in the first region 201A, the word line 220-1 is prevented from being turned on to cause electrons to flow (in the direction C) to the adjacent active regions 202, such as the active regions 202-1 and 202-2 shown in fig. 4, thereby preventing the generation of parasitic capacitance between the word line 220-1 in the first region 201A and the word lines 220-2 and 220-3 passing through the active regions 202-1 and 2020-2 and not turned on, thereby preventing the generation of leakage current and greatly improving the electrical performance of the semiconductor device.

Further, the dielectric constant of the second filling layer 201B is less than or equal to 4, for example, about 3, and the second filling layer 201B can play a good role in isolation with respect to materials with higher dielectric constants such as silicon nitride and silicon oxide, thereby avoiding the generation of parasitic capacitance and thus avoiding the generation of leakage current. The material of the second filling layer 201B may be a low-K dielectric material such as phospho-Silicate-Glass (PSG), boro-phospho-Silicate-Glass (BPSG), Fluorine-Doped Silicate Glass (fluoride-Doped Silicate Glass FSG), and the like.

Further, in the predetermined direction (D direction), the width of the second filling layer 210B is smaller than the width of the first region 201A and is greater than or equal to one third of the width of the first region 201A, so as to reduce parasitic capacitance caused by word lines to the maximum extent on the basis of maintaining the electrical isolation performance of the shallow trench isolation structure, thereby reducing leakage current.

Further, the first filling-up layer 210A is an oxide layer, which may depend on the material of the semiconductor substrate 200, for example, in the present embodiment, the semiconductor substrate 200 is a monocrystalline silicon substrate, and then the first filling-up layer 210A is a silicon oxide layer. In other embodiments of the present invention, the semiconductor substrate is a Ge substrate, and the first filling layer 210A is a nitride layer.

The semiconductor device can block the circulation of electrons by utilizing the isolation effect of the second filling layer 210B (low-K dielectric material), thereby avoiding the generation of parasitic capacitance, avoiding the generation of leakage current, greatly improving the electrical performance of the semiconductor device and improving the yield of the semiconductor device.

A second embodiment of a semiconductor device is provided in the present invention, please refer to fig. 5, which is a schematic cross-sectional view of the semiconductor device according to the second embodiment of the present invention, and the difference between the embodiment and the first embodiment is that in this embodiment, the shallow trench 201 of the semiconductor device further includes a third region 201C. The width of the third region 201C is greater than the width of the first region 201A, and in the third region 201C, the shallow trench isolation structure 210 at least includes the first filling layer 210A, the second filling layer 210B, and the third filling layer 210C, which are sequentially disposed. That is, in the third region 201C, the shallow trench isolation structure 210 includes at least three filling layers.

Since the width of the third region 201C is greater than the width of the first region 201B, after the first and second filling layers 210A and 210B are formed in the shallow trench 201, the shallow trench 201 in the third region 201C is not filled, and therefore, the shallow trench 201 needs to be refilled with the third filling layer 210C.

Further, the third filling-up layer 210C may be a nitride layer, for example, a silicon nitride layer. The thermal expansion coefficient of the nitride is close to that of the semiconductor substrate, so that the stress can be reduced in the high-temperature processes of other subsequent processes, and the performance of the semiconductor device is improved.

Further, in this embodiment, since the difference between the width of the shallow trench 201 located in the third region 201C and the width of the shallow trench 201 located in the first region 201A is too large, after the third filling layer 210C is formed, the shallow trench isolation structure 210 further includes a fourth filling layer 210D in the third region 201C, and the fourth filling layer 210D covers the third filling layer 210C and fills the shallow trench 201. The fourth filling-up layer 210D may be an oxide layer, for example, a silicon oxide layer.

Further, according to different functions, the semiconductor device includes an array region 500 and a peripheral circuit region 510, the first region 201A and the second region 201B are located in the array region 500, and the third region 201C is located in the peripheral circuit region 510.

The invention also provides a manufacturing method of the semiconductor device. Fig. 6 is a schematic step diagram of a method for manufacturing a semiconductor device according to an embodiment of the present invention. Referring to fig. 6, the manufacturing method includes the following steps: step S60, providing a semiconductor substrate, where the semiconductor substrate has a shallow trench and an active region defined by the shallow trench, and the shallow trench has a first region and a second region alternately arranged along a predetermined direction, and the width of the first region is greater than that of the second region; step S61, forming a shallow trench isolation structure in the shallow trench, where in the first region, the shallow trench isolation structure at least includes a first filling layer and a second filling layer that are sequentially arranged, where the second filling layer is a low-K dielectric layer, and in the second region, the shallow trench isolation structure at least includes the first filling layer.

Fig. 7A to 7H are process flow diagrams of a method of manufacturing a semiconductor device according to an embodiment of the present invention.

Referring to step S60, fig. 7A and fig. 7B, wherein fig. 7A is a top view, fig. 7B is a schematic cross-sectional view taken along line B-B in fig. 7A, a semiconductor substrate 200 is provided, the semiconductor substrate 200 has shallow trenches 201 and active regions 202 defined by the shallow trenches 201, the shallow trenches 201 have first regions 201A and second regions 201B alternately arranged along a predetermined direction, and a width of the first regions 201A is greater than a width of the second regions 201B.

In this embodiment, the shallow trenches 201 are formed in the semiconductor substrate 200 by using photolithography and etching processes, and the regions between the shallow trenches 201 are the active regions 202. The active region 202 extends along a set direction C, i.e. the active region 202 runs along the direction C.

In a predetermined direction (e.g., the direction D shown in fig. 7A), the first regions 201A and the second regions 201B are alternately arranged, and the width of the first regions 201A is greater than that of the second regions 201B. In fig. 7A, the first region 201A and the second region 201B are schematically enclosed by dashed boxes.

Further, in this embodiment, the shallow trench 201 further includes a third region 201C, and a width of the third region 201C is greater than a width of the first region 201A.

Further, in the present embodiment, the semiconductor device of the present invention includes an array region 500 and a peripheral circuit region 510 according to different functions. The first region 201A and the second region 201B are located in the array region 500, and the third region 201C is located in the peripheral circuit region 510. Wherein the peripheral circuit region 510 is not shown in fig. 7A.

Referring to step S61 and fig. 7C to 7F, a shallow trench isolation structure 210 is formed in the shallow trench 201, where in the first region 201A, the shallow trench isolation structure 210 at least includes a first filling layer 210A and a second filling layer 210B that are sequentially disposed, where the second filling layer 210B is a low-K dielectric layer, and in the second region 201B, the shallow trench isolation structure 210 at least includes the first filling layer 210A.

Further, in the third region 201C of the shallow trench 201, the shallow trench isolation structure 210 at least includes the first filling layer 210A, the second filling layer 210B and the third filling layer 210C.

In the present embodiment, in the first region 201A, the first filling layer 210A covers the sidewall of the shallow trench 201, and the second filling layer 210B covers the sidewall of the first filling layer 210A and fills the shallow trench; in the second region 201B, the shallow trench isolation structure 210 is a layer, and the first filling layer 210A covers the sidewall of the shallow trench 201 and fills the shallow trench; in the third region 201C, the first filling layer 210A covers the sidewall of the shallow trench 201, the second filling layer 210B covers the sidewall of the first filling layer 210A, and the third filling layer 210C covers the sidewall of the second filling layer 210B.

In this embodiment, since the width of the shallow trench 201 in the third region 201C is too different from the width of the shallow trench 201 in the first region 201A, after the third filling layer 210C is formed, a fourth filling layer 210D is formed in the shallow trench, and the fourth filling layer 210D covers the third filling layer 210C and fills the shallow trench 201.

The material of the first filling-up layer 210A may be an oxide, such as silicon oxide; the second filling layer 210B is made of a low-K dielectric material, such as phosphosilicate glass, borophosphosilicate glass, fluorine-doped silicate glass, or the like; the material of the third filling-up layer 210C may be nitride, such as silicon nitride; the material of the fourth filling-up layer 210D may be an oxide, such as silicon oxide.

The steps for forming the shallow trench isolation structure in this embodiment are specifically described below.

Referring to fig. 7C, a first filling layer 210A is formed in the shallow trench 201. In the first region 201A, the first filling layer 210A covers the sidewall of the shallow trench 201, and in the second region 201B, the first filling layer 210A fills the shallow trench; in the third region 201C, the first filling layer 210A covers the sidewall of the shallow trench 201.

Referring to fig. 7D, a second filling layer 210B is formed in the shallow trench 201. In the first region 201A, the second filling layer 210B covers the first filling layer 210A and fills the shallow trench 201; the second filling-up layer 210B is not formed in the second region 201B; in the third region 201C, the second filling-up layer 210B covers the first filling-up layer 210A.

Referring to fig. 7E, a third filling layer 210C is formed in the shallow trench 201. In the first region 201A, the third filling-up layer 210C is not formed; the third filling-up layer 210C is not formed in the second region 201B; in the third region 201C, the third filling-up layer 210C covers the second filling-up layer 210B.

Referring to fig. 7F, a fourth filling layer 210D is formed in the shallow trench 201. The fourth filling-up layer 210D is not formed in the first region 201A; the fourth filling-up layer 210D is not formed in the second region 201B; in the third region 201C, the fourth filling layer 210D covers the third filling layer 210C and fills the shallow trench 201.

In other embodiments of the present invention, if the fourth filling-up layer 210D is not formed, in the step shown in fig. 7E, the shallow trench 201 is filled up with the third filling-up layer 210C in the third region 201C.

Further, after step S61, the method further includes the following steps: referring to fig. 7G and 7H, fig. 7G is a top view, and fig. 7H is a schematic cross-sectional view taken along line B-B in fig. 7G, forming a plurality of word lines 220, wherein the word lines 220 sequentially pass through the active region 202 and the shallow trench isolation structure 210 along the predetermined direction (direction D).

The method for forming the word line 220 may be conventional in the art, and is not described in detail.

In the manufacturing method of the invention, the second filling layer 210B (namely, the low-K dielectric layer) is arranged in the first area 201B (namely, the area through which the word line passes), so that the parasitic capacitance caused by the word line is greatly reduced, and the leakage current is further reduced.

The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.