阅读说明：本技术 三维半导体存储器件 (Three-dimensional semiconductor memory device ) 是由 韩太钟 高在康 金汶濬 金须钟 李承宪 于 2020-11-26 设计创作，主要内容包括：公开了一种三维半导体存储器件。该器件可以包括：基板,包括单元阵列区域以及提供在单元阵列区域的端部处的连接区域；电极结构,从单元阵列区域延伸到连接区域,该电极结构包括顺序地堆叠在基板上的电极；提供在电极结构上的上绝缘层；提供在上绝缘层中并沿着电极延伸的第一水平绝缘层；以及提供在连接区域上以穿透上绝缘层和第一水平绝缘层的第一接触插塞。第一水平绝缘层可以包括具有比上绝缘层更好的耐蚀刻性能的材料。(A three-dimensional semiconductor memory device is disclosed. The device may include: a substrate including a cell array region and a connection region provided at an end of the cell array region; an electrode structure extending from the cell array region to the connection region, the electrode structure including electrodes sequentially stacked on the substrate; an upper insulating layer provided on the electrode structure; a first horizontal insulating layer provided in the upper insulating layer and extending along the electrodes; and a first contact plug provided on the connection region to penetrate the upper insulating layer and the first horizontal insulating layer. The first horizontal insulating layer may include a material having better etch resistance than the upper insulating layer.)

1. A three-dimensional semiconductor memory device comprising:

a substrate including a cell array region and a connection region at an end of the cell array region;

an electrode structure extending from the cell array region to the connection region, the electrode structure including electrodes sequentially stacked on the substrate;

an upper insulating layer on the electrode structure;

a first horizontal insulating layer in the upper insulating layer and extending along the electrode; and

a first contact plug in the connection region, penetrating the upper insulation layer and the first horizontal insulation layer,

wherein the first horizontal insulating layer includes a material having higher etching resistance than the upper insulating layer.

2. The device of claim 1, wherein the first horizontal insulating layer comprises a plurality of first horizontal insulating layers provided in the upper insulating layer and vertically spaced apart from each other with a portion of the upper insulating layer interposed therebetween.

3. The device of claim 1, further comprising:

an interlayer insulating layer between the electrodes; and

a second horizontal insulating layer in an uppermost one of the interlayer insulating layers, extending along the electrode,

wherein the second horizontal insulating layer is between an uppermost one of the electrodes and the first horizontal insulating layer.

4. The device of claim 3, wherein the second horizontal insulating layer extends from the uppermost one of the interlayer insulating layers toward the connection region, and

the first contact plug penetrates the second horizontal insulating layer.

5. The device of claim 3, further comprising a vertical structure penetrating the electrode structure,

wherein the vertical structure penetrates the second horizontal insulating layer.

6. The device of claim 5, wherein each of the vertical structures comprises a data storage pattern, a vertical semiconductor pattern surrounded by the data storage pattern, and a conductive pad connected to a top of the vertical semiconductor pattern, and

the top surface of the second horizontal insulating layer is located at a height lower than or equal to the bottom surface of the conductive pad.

7. The device of claim 5, wherein each of the vertical structures has a width that increases from a top surface of the uppermost one of the interlayer insulating layers to the second horizontal insulating layer and decreases from the second horizontal insulating layer to the substrate.

8. The device of claim 1, wherein the substrate further comprises a peripheral circuit region including peripheral circuitry thereon,

the device further includes a second contact plug penetrating the upper insulating layer and the first horizontal insulating layer in the peripheral circuit region, and wherein the second contact plug is connected to the peripheral circuit.

9. The device of claim 8, wherein each of the first and second contact plugs has a width that increases from a top surface of the upper insulating layer to the first horizontal insulating layer and decreases from the first horizontal insulating layer to the substrate.

10. The device of claim 1, wherein a distance from a top surface of the upper insulating layer to the first horizontal insulating layer is atAndin the meantime.

11. The device of claim 1, wherein the first horizontal insulating layer comprises a material containing at least one of nitrogen (N), carbon (C), boron (B), phosphorus (P), helium (He), and argon (Ar).

12. The device of claim 1, further comprising:

a peripheral circuit structure under the substrate, the peripheral circuit structure including a peripheral circuit and a peripheral line connected to the peripheral circuit; and

at least one third contact plug adjacent to the connection region, penetrating the upper insulating layer, the first horizontal insulating layer, and a portion of the substrate,

wherein one of the peripheral lines is connected to the at least one third contact plug.

13. A three-dimensional semiconductor memory device comprising:

a substrate including a cell array region and a connection region at an end of the cell array region;

an electrode structure extending from the cell array region to the connection region, the electrode structure including electrodes sequentially stacked on the substrate and an interlayer insulating layer between the electrodes;

an upper insulating layer on the electrode structure;

a first horizontal insulating layer in an uppermost one of the interlayer insulating layers, extending along the electrode;

a second horizontal insulating layer in the upper insulating layer, extending along the electrode;

a vertical structure penetrating the electrode structure and the first horizontal insulating layer; and

a first contact plug penetrating the upper insulating layer and the first and second horizontal insulating layers,

wherein the first horizontal insulating layer and the second horizontal insulating layer are vertically spaced apart from each other, and

wherein a concentration of a non-metal element other than oxygen is higher in the second horizontal insulating layer than in the upper insulating layer.

14. The device according to claim 13, wherein the non-metallic element is one selected from nitrogen (N), carbon (C), boron (B), phosphorus (P), helium (He), and argon (Ar).

15. The device of claim 13, wherein each of a first distance from a top surface of the uppermost one of the interlayer insulating layers to a top surface of the first horizontal insulating layer and a second distance from a top surface of the upper insulating layer to a top surface of the second horizontal insulating layer is atAndin the meantime.

16. The device of claim 13, wherein the substrate further comprises a peripheral circuit region including peripheral circuitry thereon,

the device further includes a second contact plug in the peripheral circuit region, the second contact plug penetrating the upper insulating layer and the first and second horizontal insulating layers, and wherein the second contact plug is connected to the peripheral circuit.

17. The device according to claim 13, wherein a concentration of the non-metal element other than oxygen is higher in the first horizontal insulating layer than in the uppermost one of the interlayer insulating layers.

18. The device of claim 13, further comprising:

a peripheral circuit structure under the substrate, the peripheral circuit structure including a peripheral circuit and a peripheral line connected to the peripheral circuit; and

at least one third contact plug adjacent to the connection region, penetrating the upper insulating layer, the first and second horizontal insulating layers, and a portion of the substrate,

wherein one of the peripheral lines is connected to the at least one third contact plug.

19. A three-dimensional semiconductor memory device comprising:

a substrate including a cell array region, a peripheral circuit region including a peripheral circuit, and a connection region between the cell array region and the peripheral circuit region;

an electrode structure extending from the cell array region to the connection region, the electrode structure including electrodes vertically stacked on the substrate and an interlayer insulating layer interposed between the electrodes;

an upper insulating layer on the electrode structure;

a horizontal insulating layer in the upper insulating layer, extending along the electrode;

a vertical structure penetrating the electrode structure, the vertical structure including a data storage pattern, a vertical semiconductor pattern surrounded by the data storage pattern, and a conductive pad connected to a top of the vertical semiconductor pattern;

a bit line on the upper insulating layer and electrically connected to the conductive pad of the vertical structure;

a plurality of first contact plugs, wherein each first contact plug is on the connection region and penetrates one of the upper insulating layer, the horizontal insulating layer, and the interlayer insulating layer, and is connected to a corresponding one of the electrodes;

a plurality of second contact plugs on the peripheral circuit region, penetrating the upper insulating layer and the horizontal insulating layer and connected to the peripheral circuit; and

conductive lines connected to the first contact plugs and the second contact plugs, respectively,

wherein a concentration of a non-metallic element other than oxygen is higher in the horizontal insulating layer than in the upper insulating layer.

20. The device of claim 19, wherein the horizontal insulating layer comprises a plurality of horizontal insulating layers provided in the upper insulating layer and vertically spaced apart from each other with a portion of the upper insulating layer interposed therebetween.

Technical Field

The present disclosure relates to a three-dimensional semiconductor memory device, and more particularly, to a three-dimensional semiconductor memory device having improved electrical characteristics.

Background

Higher integration of semiconductor devices may be required to meet consumer demands for superior performance and low price. In the case of semiconductor devices, since their integration degree is an important factor determining the price of products, an increased integration degree may be required. In the case of two-dimensional or planar semiconductor devices, since their degree of integration is mainly determined by the area occupied by a unit memory cell, the degree of integration is greatly influenced by the level of fine pattern formation technology. However, the extremely expensive processing equipment required to improve the fineness of the pattern may place practical limits on improving the integration of two-dimensional or planar semiconductor devices. Accordingly, three-dimensional semiconductor memory devices including memory cells arranged three-dimensionally have been recently proposed.

Disclosure of Invention

Embodiments of the inventive concept provide a three-dimensional semiconductor memory device having improved electrical characteristics.

According to an embodiment of the inventive concept, a three-dimensional semiconductor memory device may include: a substrate including a cell array region and a connection region provided at an end of the cell array region; an electrode structure extending from the cell array region to the connection region, the electrode structure including electrodes sequentially stacked on the substrate; an upper insulating layer on the electrode structure; a first horizontal insulating layer in the upper insulating layer and extending along the electrodes; and a first contact plug in the connection region penetrating the upper insulating layer and the first horizontal insulating layer. The first horizontal insulating layer may include a material having higher etch resistance than the upper insulating layer.

According to an embodiment of the inventive concept, a three-dimensional semiconductor memory device may include: a substrate including a cell array region and a connection region at an end of the cell array region; an electrode structure extending from the cell array region to the connection region, the electrode structure including electrodes sequentially stacked on the substrate; an interlayer insulating layer between the electrodes; an upper insulating layer on the electrode structure; a first horizontal insulating layer in an uppermost one of the interlayer insulating layers and extending along the electrode; a second horizontal insulating layer in the upper insulating layer and extending along the electrodes; a vertical structure penetrating the electrode structure and the first horizontal insulating layer; and a first contact plug penetrating the upper insulating layer and the first and second horizontal insulating layers. The first horizontal insulating layer and the second horizontal insulating layer may be vertically spaced apart from each other. The concentration of the non-metal element other than oxygen may be higher in the second horizontal insulating layer than in the upper insulating layer.

According to an embodiment of the inventive concept, a three-dimensional semiconductor memory device may include: a substrate including a cell array region, a peripheral circuit region including a peripheral circuit, and a connection region between the cell array region and the peripheral circuit region; an electrode structure extending from the cell array region to the connection region, the electrode structure including electrodes vertically stacked on the substrate; an interlayer insulating layer interposed between the electrodes; an upper insulating layer on the electrode structure; a horizontal insulating layer in the upper insulating layer and extending along the electrodes; a vertical structure penetrating the electrode structure, the vertical structure including a data storage pattern, a vertical semiconductor pattern surrounded by the data storage pattern, a conductive pad connected to a top of the vertical semiconductor pattern; a bit line provided on the upper insulating layer and electrically connected to the conductive pad of the vertical structure; first contact plugs each penetrating one of the upper insulating layer, the horizontal insulating layer, and the interlayer insulating layer on the connection region and connected to a corresponding one of the electrodes; a second contact plug on the peripheral circuit region to penetrate the upper insulating layer and the horizontal insulating layer and connected to the peripheral circuit; and conductive lines connected to the first and second contact plugs, respectively. The concentration of the non-metal element other than oxygen may be higher in the horizontal insulating layer than in the upper insulating layer.

Drawings

Example embodiments will be more clearly understood from the following brief description taken in conjunction with the accompanying drawings. The drawings depict non-limiting example embodiments as described herein.

Fig. 1 is a circuit diagram schematically illustrating a cell array of a three-dimensional semiconductor memory device according to an embodiment of the inventive concept.

Fig. 2A is a plan view illustrating a three-dimensional semiconductor memory device according to an embodiment of the inventive concept.

Fig. 2B, 8A and 9A are sectional views taken along line I-I' of fig. 2A illustrating a three-dimensional semiconductor memory device according to an embodiment of the inventive concept.

Fig. 2C, 8B and 9B are sectional views taken along line II-II' of fig. 2A illustrating a three-dimensional semiconductor memory device according to an embodiment of the inventive concept.

Fig. 3A and 3B are enlarged cross-sectional views illustrating a portion (e.g., a of fig. 2B) of a three-dimensional semiconductor memory device according to an embodiment of the inventive concept.

Fig. 4A and 4B are enlarged cross-sectional views illustrating a portion (e.g., B of fig. 2B) of a three-dimensional semiconductor memory device according to an embodiment of the inventive concept.

Fig. 5 is an enlarged cross-sectional view illustrating a portion (e.g., C of fig. 2B) of a three-dimensional semiconductor memory device according to an embodiment of the inventive concept.

Fig. 6A is a plan view illustrating a three-dimensional semiconductor memory device according to an embodiment of the inventive concept.

Fig. 6B and 6C are cross-sectional views taken along lines I-I 'and II-II' of fig. 6A illustrating a three-dimensional semiconductor memory device according to an embodiment of the inventive concept.

Fig. 7 is a cross-sectional view taken along line I-I' of fig. 6A illustrating a three-dimensional semiconductor memory device according to an embodiment of the inventive concept.

It should be noted that these drawings are intended to illustrate the general nature of methods, structures, and/or materials used in certain example embodiments, and to supplement the written description provided below. However, the drawings are not to scale and may not accurately reflect the precise structural or performance characteristics of any given embodiment, and should not be construed as limiting or restricting the scope of values or properties encompassed by example embodiments. For example, the relative thicknesses and positions of molecules, layers, regions and/or structural elements may be reduced or exaggerated for clarity. The use of like or identical reference numbers in the various figures is intended to indicate the presence of like or identical elements or features.

Detailed Description

Example embodiments of the present inventive concept will now be described more fully with reference to the accompanying drawings, in which example embodiments are shown.

Fig. 1 is a circuit diagram schematically illustrating a cell array of a three-dimensional semiconductor memory device according to an embodiment of the inventive concept.

Referring to fig. 1, a cell array of a three-dimensional semiconductor memory device may include a common source line CSL, a plurality of bit lines BL0-BL2, and a plurality of cell strings CSTR provided between the common source line CSL and the bit lines BL0-BL 2.

The cell strings CSTR may be two-dimensionally arranged in the first direction D1 and the second direction D2 that are not parallel to each other. In an embodiment, the second direction D2 may be perpendicular to the first direction D1. Each cell string CSTR may extend in a third direction D3. In an embodiment, the third direction D3 may be perpendicular to both the first direction D1 and the second direction D2. The bit lines BL0-BL2 may be spaced apart from each other in the first direction D1. Each of the bit lines BL0-BL2 may extend in the second direction D2.

A plurality of cell strings CSTRs may be connected in parallel to each of the bit lines BL0-BL 2. The cell strings CSTR may be commonly connected to a common source line CSL. That is, a plurality of cell strings CSTR may be provided between the bit lines BL0-BL2 and a single common source line CSL. In one embodiment, the common source line CSL may be provided in a plurality of pieces. The common source lines CSL may be two-dimensionally arranged. The common source line CSL may be applied with the same voltage or may have an independently controlled electrical state.

In an embodiment, each cell string CSTR may include a first string selection transistor SST1 and a second string selection transistor SST2 connected in series to each other, a memory cell transistor MCT connected in series to each other, a ground selection transistor GST, and an erase control transistor ECT. Each memory cell transistor MCT may include a data storage element.

As an example, each cell string CSTR may include a first string selection transistor SST1 and a second string selection transistor SST2 connected in series, and the second string selection transistor SST2 may be coupled to one of the bit lines BL0-BL 2. As another example, each cell string CSTR may include one string selection transistor. As another example, in each cell string CSTR, the ground selection transistor GST may be composed of a plurality of Metal Oxide Semiconductor (MOS) transistors connected in series, similar to the first string selection transistor SST1 and the second string selection transistor SST 2.

Each cell string CSTR may include a plurality of memory cell transistors MCT located at a different height from the common source line CSL. The memory cell transistors MCT may be connected in series between the first string selection transistor SST1 and the ground selection transistor GST. The erase control transistor ECT may be provided between and connected to the ground selection transistor GST and the common source line CSL. In addition, each cell string CSTR may include a dummy cell transistor DMC provided between and connected to the first string selection transistor SST1 and an uppermost one of the memory cell transistors MCT, and provided between and connected to a ground selection transistor GST and a lowermost one of the memory cell transistors MCT.

In an embodiment, the first string selection transistor SST1 may be controlled by one of first string selection lines SSL1-1, SSL1-2, and SSL1-3, and the second string selection transistor SST2 may be controlled by one of second string selection lines SSL2-1, SSL2-2, and SSL 2-3. The memory cell transistors MCT may be controlled by a plurality of word lines WL0-WLn, respectively, and the dummy cell transistors DMC may be controlled by a dummy word line DWL. The ground selection transistor GST may be controlled by one of the ground selection lines GSL0, GSL1, and GSL2, and the erase control transistor ECT may be controlled by the erase control line ECL. In one embodiment, the erase control transistor ECT may be provided in plurality. The common source line CSL may be commonly connected to the source of the erase control transistor ECT.

The gate electrodes of the memory cell transistors MCT located at substantially the same height from the common source line CSL may be commonly connected to one of the word lines WL0-WLn and may be in an equipotential state. Alternatively, even when the gate electrodes of the memory cell transistors MCT are located at substantially the same height from the common source line CSL, the gate electrodes constituting different rows or columns can be independently controlled.

The ground select lines GSL0-GSL2, the first string select lines SSL1-1, SSL1-2, and SSL1-3, and the second string select lines SSL2-1, SSL2-2, and SSL2-3 may extend in the first direction D1 and be spaced apart from each other in the second direction D2. The ground select lines GSL0-GSL2, the first string select lines SSL1-1, SSL1-2, and SSL1-3, and the second string select lines SSL2-1, SSL2-2, and SSL2-3, which are located at substantially the same height from the common source line CSL, may be electrically separated from each other. In addition, the erase control transistors ECT included in different cell strings among the cell strings CSTR may be commonly controlled by the erase control line ECL. During an erase operation of the memory cell array, the erase control transistor ECT may cause Gate Induced Drain Leakage (GIDL). In an embodiment, an erase voltage may be applied to the bit lines BL0-BL2 and/or the common source line CSL during an erase operation of the memory cell array, and in this case, a gate-induced leakage current may be generated at the string selection transistors SST1 and SST2 and/or the erase control transistor ECT.

Fig. 2A is a plan view illustrating a three-dimensional semiconductor memory device according to an embodiment of the inventive concept. Fig. 2B and 2C are sectional views taken along lines I-I 'and II-II' of fig. 2A, respectively, illustrating a three-dimensional semiconductor memory device according to an embodiment of the inventive concept.

Referring to fig. 2A, 2B, and 2C, the substrate 10 may include a cell array region CAR, a connection region CNR, a dummy region DMY, and a peripheral circuit region PCR. The connection region CNR may be located between the cell array region CAR and the peripheral circuit region PCR. The dummy region DMY may be adjacent to the cell array region CAR in a first direction D1 parallel to the top surface of the substrate 10. The dummy region DMY may be located between the cell array region CAR and the connection region CNR. The peripheral circuit region PCR may be adjacent to the connection region CNR in the first direction D1. The peripheral circuit region PCR may include a first peripheral circuit region PCR1 and a second peripheral circuit region PCR2, and in an embodiment, the first peripheral circuit region PCR1 may be closer to the cell array region CAR than the second peripheral circuit region PCR 2. However, the inventive concept is not limited to this example, and in an embodiment, the substrate 10 may further include a boundary region between the peripheral circuit region PCR and the connection region CNR.

The substrate 10 may be a silicon substrate, a silicon germanium substrate, a germanium substrate, or a single crystal epitaxial layer grown on a single crystal silicon substrate. A device isolation layer 13 may be provided in the peripheral circuit region PCR of the substrate 10 to define a peripheral active region PACT. Peripheral logic circuits for writing data in and reading data from the memory cells may be provided on the peripheral circuit region PCR of the substrate 10. The peripheral logic circuit may include row and column decoders, a page buffer, and a control circuit. The peripheral logic circuit may include, for example, high or low voltage transistors, resistors, and capacitors. In an embodiment, a high voltage transistor may be provided on the first peripheral circuit region PCR1 of the substrate 10, and a low voltage transistor may be provided on the second peripheral circuit region PCR2 of the substrate 10. The high voltage transistor may be closer to the cell array region CAR than the low voltage transistor.

The first peripheral gate stack PGS1 may be provided on the first peripheral circuit region PCR1, and the second peripheral gate stack PGS2 may be provided on the second peripheral circuit region PCR 2. Each of the first and second peripheral gate stacks PGS1 and PGS2 may be provided to cross a corresponding one of the peripheral active areas PACT. Each of the first and second peripheral gate stacks PGS1 and PGS2 may include a gate conductive pattern PCP, a gate metal pattern PMP, and a peripheral hard mask pattern HMP sequentially stacked on the substrate 10, as shown in fig. 2B. In addition, each of the first and second peripheral gate stacks PGS1 and PGS2 may further include a gate spacer PSP covering both side surfaces of the gate conductive pattern PCP, both side surfaces of the gate metal pattern PMP, and both side surfaces of the peripheral hard mask pattern HMP, as shown in fig. 2B. A gate insulating layer 15 may be provided between the substrate 10 of the peripheral circuit region PCR and the first and second peripheral gate stacks PGS1 and PGS2, as shown in fig. 2B. In addition, source/drain impurity regions may be provided in the peripheral active region PACT and at both sides of the first peripheral gate stack PGS1 and both sides of the second peripheral gate stack PGS 2. A peripheral circuit insulating layer 110 may be provided on the peripheral circuit region PCR to cover the top surface of the substrate 10, as shown in fig. 2B. The peripheral circuit insulating layer 110 may be formed of or include at least one of silicon oxide and silicon oxynitride. The peripheral circuit insulating layer 110 may have a substantially flat top surface.

The electrode structure ST may be disposed on the cell array region CAR, the dummy region DMY, and the connection region CNR of the substrate 10, as shown in fig. 2A to 2C. The electrode structure ST may extend from the cell array region CAR to the connection region CNR or in the first direction D1. The electrode structures ST may be spaced apart from each other in the second direction D2. The electrode structure ST may include electrodes EL and ELt and interlayer insulating layers ILDa and ILDb alternately stacked in a third direction D3 perpendicular to the top surface of the substrate 10, as shown in fig. 2B and 2C. Each electrode structure ST may have a substantially flat top surface on the cell array region CAR and the dummy region DMY. That is, in each electrode structure ST, the top surface ILDbt of the uppermost interlayer insulating layer ILDb may be parallel to the top surface of the substrate 10, as shown in fig. 2C. The electrode structure ST may be provided to have a stepped structure on the connection region CNR as shown in fig. 2B and 2C. The length of the electrodes EL and ELt of the electrode structure ST in the first direction D1 may decrease as the distance from the substrate 10 increases, and the height of the electrode structure ST may decrease as the distance from the cell array region CAR increases.

The electrodes EL and ELt may have side surfaces that are uniformly spaced apart from each other by a certain distance in the first direction D1 when viewed in a plan view. Among the electrodes EL and ELt, the uppermost electrode ELt may have the shortest length in the first direction D1 and the largest distance from the substrate 10 in the third direction D3, as shown in fig. 2B and 2C. In an embodiment, the electrodes EL and ELt may have substantially the same thickness in the third direction D3. The electrodes EL and ELt may be formed of or include, for example, at least one of a doped semiconductor material (e.g., doped silicon, etc.), a metal (e.g., tungsten, copper, aluminum, etc.), a conductive metal nitride (e.g., titanium nitride, tantalum nitride, etc.), and a transition metal (e.g., titanium, tantalum, etc.), or include, for example, at least one of a doped semiconductor material (e.g., doped silicon, etc.), a metal (e.g., tungsten, copper, aluminum, etc.), a conductive metal nitride (e.g., titanium nitride, tantalum nitride, etc.), and a transition metal (e.g., titanium, tantalum, etc.). Referring back to fig. 1, the electrodes EL and ELt may be used as ground selection lines GSL0-GSL2, word lines WL0-WLn and DWL, first string selection lines SSL1-1, SSL1-2 and SSL1-3, and second string selection lines SSL2-1, SSL2-2 and SSL 2-3.

The interlayer insulating layers ILDa and ILDb may extend from the cell array region CAR to the peripheral circuit region PCR, and may cover the electrodes EL and ELt, respectively, as shown in fig. 2B. An uppermost interlayer insulating layer ILDb may be provided on the uppermost electrode ELt. The uppermost interlayer insulating layer ILDb may be thicker than each interlayer insulating layer ILDa as measured in the third direction D3. The interlayer insulating layers ILDa and ILDb may be formed of or include substantially the same insulating material as each other or different insulating materials from each other. For example, the interlayer insulating layers ILDa and ILDb may be formed of or include a High Density Plasma (HDP) oxide or tetraethyl orthosilicate (TEOS).

The common source plugs CSP may be provided between the electrode structures ST when viewed in a plan view, and each of the common source plugs CSP may be surrounded by an insulating spacer SP. Each of the common source plugs CSP may have a plate-shaped structure extending in the first direction D1 and the third direction D3. The common source plugs CSP may extend from the cell array region CAR to the connection region CNR in the first direction D1. The common source plugs CSPs may be spaced apart from each other in the second direction D2. The common source plug CSP may be connected to a common source region formed in the substrate 10. The common source region may be used as the common source line CSL of fig. 1.

The source structure SC may be interposed between the electrode structure ST and the substrate 10. The source structure SC may be parallel to the electrode structure ST and extend in the first direction D1. The source structure SC may include a first source conductive pattern SCP1 and a second source conductive pattern SCP2 sequentially stacked on the substrate 10. The thickness of the first source conductive pattern SCP1 in the third direction D3 may be greater than the thickness of the second source conductive pattern SCP2 in the third direction D3. The first source conductive pattern SCP1 may be in contact with the substrate 10, and the second source conductive pattern SCP2 may be in direct contact with the first source conductive pattern SCP 1. The second source conductive pattern SCP2 may be provided between the first source conductive pattern SCP1 and the lowermost one of the interlayer insulating layers ILDa and ILDb of the electrode structure ST. The first and second source conductive patterns SCP1 and SCP2 may be formed of or include a doped semiconductor material. In an embodiment, the doping concentration may be higher in the first source conductive pattern SCP1 than in the second source conductive pattern SCP 2.

A planarization insulating layer 130 may be provided on the substrate 10 to cover the electrode structure ST and the peripheral circuit insulating layer 110. The top surface 130t (fig. 2C) of the planarizing insulating layer 130 can be substantially planar. A top surface 130t of the planarization insulating layer 130 may be substantially coplanar with a top surface ILDbt of the uppermost interlayer insulating layer ILDb. On the connection region CNR, the thickness of the planarization insulating layer 130 measured in the third direction D3 may increase in the first direction D1. The thickness of the planarized insulating layer 130 measured in the third direction D3 may have a maximum value on the peripheral circuit region PCR. The planarization insulating layer 130 may be formed of an insulating material different from the interlayer insulating layers ILDa and ILDb or include an insulating material different from the interlayer insulating layers ILDa and ILDb. In one embodiment, the interlayer insulating layers ILDa and ILDb may be formed of or include a high density plasma oxide, and the planarization insulating layer 130 may be formed of or include TEOS.

The first horizontal insulating layer IMP1 may be provided in the uppermost interlayer insulating layer ILDb and may extend in the first direction D1 along the electrodes EL and ELt. The first horizontal insulating layer IMP1 may extend into the planarization insulating layer 130. Referring to fig. 4A and 4B, the top surface IMP1t of the first horizontal insulating layer IMP1 may be located more than the top surface IL of the uppermost interlayer insulating layer ILDbAt a level where Dbt is low. The bottom surface of the first horizontal insulating layer IMP1 may be located at a higher level than the top surface of the uppermost electrode ELt. In other words, the first horizontal insulating layer IMP1 may be provided between the top surface of the uppermost electrode ELt and the top surface ILDbt of the uppermost interlayer insulating layer ILDb. For example, the distance from the top surface ILDbt of the uppermost interlayer insulating layer ILDb to the top surface IMP1t of the first horizontal insulating layer IMP1 may beAndin the meantime. The first horizontal insulating layer IMP1 may be formed of or include a material whose etching resistance is better than those of the uppermost interlayer insulating layer ILDb and the planarization insulating layer 130 (that is, the material of the first horizontal insulating layer IMP1 has a higher etching resistance than those of the uppermost interlayer insulating layer ILDb and the planarization insulating layer 130). Here, the etch resistance may mean resistance to an etchant used in a wet etching process or a dry etching process. In an embodiment, the first horizontal insulating layer IMP1 may have a higher density than the uppermost interlayer insulating layer ILDb and the planarization insulating layer 130. In one embodiment, the concentration of the non-metal element other than oxygen may be higher in the first horizontal insulating layer IMP1 than in the uppermost interlayer insulating layer ILDb and the planarization insulating layer 130. In an embodiment, the concentration of the non-metal element may be continuously varied at the boundary between the first horizontal insulating layer IMP1 and the uppermost interlayer insulating layer ILDb and at the boundary between the first horizontal insulating layer IMP1 and the planarization insulating layer 130. For example, the first horizontal insulating layer IMP1 may include at least one non-metal element selected from nitrogen (N), carbon (C), boron (B), phosphorus (P), helium (He), and argon (Ar). An ion implantation process may be performed on the uppermost interlayer insulating layer ILDb and the planarization insulating layer 130 to form a first horizontal insulating layer IMP 1. In one embodiment, a heat treatment process may be further performed after the ion implantation process. In one embodiment, the heat treatment process maySo as to be a rapid thermal annealing (RTP) process. The first horizontal insulating layer IMP1 may have improved etch resistance if the ion implantation process is performed under the condition of a large ion implantation amount.

In an embodiment, a plurality of first horizontal insulating layers IMP1 may be provided. Referring to fig. 4B, at least two first horizontal insulating layers IMP1a may be provided between the top surface of the uppermost electrode ELt and the top surface ILDbt of the uppermost interlayer insulating layer ILDb. The first horizontal insulating layers IMP1a may be spaced apart from each other in the third direction D3. In an embodiment, the first horizontal insulating layers IMP1a may be formed of or include different materials from each other. The first horizontal insulating layer IMP1a may be formed by performing an ion implantation process at least twice on the uppermost interlayer insulating layer ILDb and the planarization insulating layer 130. The ion implantation process may be performed using ions of different elements. In addition, the ion implantation process may be performed under process conditions in which ion implantation energies or ion implantation amounts are different from each other. In one embodiment, after the ion implantation process, a heat treatment process may be further performed. The position of the first horizontal insulating layer IMP1a may be changed by adjusting the ion implantation energy in the ion implantation process and the heating method in the heat treatment process.

A plurality of first vertical structures VS1 may be provided on the cell array region CAR and the dummy region DMY to penetrate the electrode structure ST, the source structure SC, and portions of the substrate 10. The first vertical structure VS1 may penetrate the uppermost interlayer insulating layer ILDb and the first horizontal insulating layer IMP1 provided in the uppermost interlayer insulating layer ILDb. Referring back to fig. 1, the first vertical structure VS1 may function as a channel region of the erase control transistor ECT, channel regions of the first and second string selection transistors SST1 and SST2, a channel region of the ground selection transistor GST, and a channel region of the memory cell transistor MCT.

Each of the first vertical structures VS1 may include a data storage pattern DSP, a first vertical semiconductor pattern VSP1, and a first conductive PAD 1. Referring to fig. 4A, 4B and 5, the data storage pattern DSP may include a blocking insulating layer BLK, a charge storage layer CIL and a tunnel insulating layer TIL, which are sequentially stacked. Each of the first vertical structures VS1 may further include a buried insulating pattern VI surrounded by the first vertical semiconductor pattern VSP1 and the first conductive PAD 1. The top surface IMP1t of the first horizontal insulating layer IMP1 may be located at a lower height than the bottom surface PAD1b of the first conductive PAD1, as shown in fig. 4A. However, in an embodiment, unlike that shown in fig. 4A, the top surface IMP1t of the first horizontal insulating layer IMP1 may be substantially coplanar with the bottom surface PAD1b of the first conductive PAD 1.

The first vertical semiconductor pattern VSP1 may be surrounded by the data storage pattern DSP. A portion of the side surface of the first vertical semiconductor pattern VSP1 may be in contact with the source structure SC. For example, the first vertical semiconductor pattern VSP1 may be in contact with the first source conductive pattern SCP1 of the source structure SC and may be spaced apart from the second source conductive pattern SCP 2. Each of the first vertical structures VS1 may further include a lower data storage pattern DSPr. The lower data storage pattern DSPr may have a substantially "U" -shaped cross-section. The lower data storage pattern DSPr may be spaced apart from the data storage pattern DSP, and the first source conductive pattern SCP1 contacting the first vertical semiconductor pattern VSP1 may be interposed between the lower data storage pattern DSPr and the data storage pattern DSP. The lower data storage pattern DSPr may be provided under the top surface of the substrate 10. The first conductive PAD1 may be connected to the top of the first vertical semiconductor pattern VSP 1. The top surface of the first conductive PAD1 may be substantially coplanar with the top surface of the data storage pattern DSP and the top surface of the first vertical semiconductor pattern VSP1, as shown in fig. 4A. The first conductive PAD1 may be formed of or include a doped semiconductor material or a conductive material.

The data storage pattern DSP and the first vertical semiconductor pattern VSP1 may be formed by etching the electrode structure ST, depositing an insulating material or a semiconductor material using a Chemical Vapor Deposition (CVD) or Atomic Layer Deposition (ALD) method, and performing a planarization process to expose a top surface of the electrode structure ST.

A plurality of second vertical structures VS2 may be provided on the connection region CNR to penetrate the planarization insulating layer 130, the electrode structure ST, the source structure SC, and portions of the substrate 10. The second vertical structure VS2 may penetrate the stair structure of the electrode structure ST, as shown in fig. 2C. The second vertical structure VS2 may penetrate the first horizontal insulating layer IMP1 provided in the planarization insulating layer 130, as shown in fig. 2C. Each of the second vertical structures VS2 may include a data storage pattern DSP, a second vertical semiconductor pattern VSP2, and a second conductive PAD 2. Each of the second vertical structures VS2 may have substantially the same structure as the first vertical structure VS1 and may be formed by substantially the same method as that used for the first vertical structure VS 1.

The first and second vertical structures VS1 and VS2 may be arranged in a zigzag shape when viewed in a plan view. In each of the first and second vertical structures VS1 and VS2, the data storage pattern DSP may have a hollow tube shape or a macaroni shape. The first and second vertical semiconductor patterns VSP1 and VSP2 of the first and second vertical structures VS1 and VS2 may have a tube shape or a macaroni shape with a closed bottom. The first and second vertical semiconductor patterns VSP1 and VSP2 may be formed of or include at least one of semiconductor materials, such as silicon (Si) and germanium (Ge). In an embodiment, the first and second vertical semiconductor patterns VSP1 and VSP2 may be formed of or include a doped semiconductor material, an intrinsic semiconductor material, or a polycrystalline semiconductor material. For example, the top surface of the first vertical structure VS1 and the top surface of the second vertical structure VS2 may have a circular, oval, or bar shape. In an embodiment, the width of the second vertical structure VS2 may be greater than the width of the first vertical structure VS 1. In an embodiment, the first vertical structure VS1 and the second vertical structure VS2 may have substantially the same length in the third direction D3. The bottom surface of the first vertical structure VS1 and the bottom surface of the second vertical structure VS2 may be located at a lower height than the top surface of the substrate 10. For example, the first and second vertical structures VS1 and VS2 may be connected to the substrate 10. At least one of the first vertical structure VS1 and the second vertical structure VS2 may be a dummy vertical structure including dummy data storage patterns DSPd.

As shown in fig. 2B and 2C, an upper insulating layer 150 may be provided on the electrode structure ST and the planarization insulating layer 130. The upper insulating layer 150 may cover the top surface ILDbt of the uppermost interlayer insulating layer ILDb and the top surface 130t of the planarization insulating layer 130. The upper insulating layer 150 may be provided to have substantially the same thickness in the third direction D3 on the cell array region CAR, the connection region CNR, and the peripheral circuit region PCR. In an embodiment, the upper insulating layer 150 may be formed of substantially the same insulating material as the planarization insulating layer 130 or include substantially the same insulating material as the planarization insulating layer 130. As an example, the upper insulating layer 150 may be formed of an insulating material different from or include an insulating material different from the uppermost interlayer insulating layer ILDb.

The second horizontal insulating layer IMP2 may be provided in the upper insulating layer 150 and may extend along the electrodes EL and ELt in the first direction D1. Referring to fig. 3A and 3B, the top surface IMP2t of the second horizontal insulating layer IMP2 may be located at a lower height than the top surface 150t of the upper insulating layer 150. The bottom surface of the second horizontal insulating layer IMP2 may be located at a higher height than the top surface 130t of the planarization insulating layer 130. In other words, the second horizontal insulating layer IMP2 may be provided between the top surface 130t of the planarization insulating layer 130 and the top surface 150t of the upper insulating layer 150. For example, the distance from the top surface 150t of the upper insulating layer 150 to the top surface IMP2t of the second horizontal insulating layer IMP2 may be atAndin the meantime. The second horizontal insulating layer IMP2 may be formed of a material having better etch resistance than that of the upper insulating layer 150 or include a material having better etch resistance than that of the upper insulating layer 150. The etch resistance may represent resistance to an etchant used in a dry etching process. In one embodiment, the firstThe two-level insulating layer IMP2 may have a higher density than the upper insulating layer 150. In an embodiment, the concentration of the non-metal elements other than oxygen may be higher in the second horizontal insulating layer IMP2 than in the upper insulating layer 150. In an embodiment, the concentration of the non-metallic element may be continuously varied at the boundary between the second horizontal insulating layer IMP2 and the upper insulating layer 150. For example, the second horizontal insulating layer IMP2 may include at least one non-metal element selected from nitrogen (N), carbon (C), boron (B), phosphorus (P), helium (He), and argon (Ar). In an embodiment, the second horizontal insulating layer IMP2 may have substantially the same chemical composition as the first horizontal insulating layer IMP 1. In some embodiments, the second horizontal insulating layer IMP2 may include a non-metal element that is not included in the first horizontal insulating layer IMP 1. The second horizontal insulating layer IMP2 may be formed by performing an ion implantation process on the upper insulating layer 150. In one embodiment, a heat treatment process may be further performed after the ion implantation process. A method of forming the second horizontal insulating layer IMP2 may be substantially the same as that for the first horizontal insulating layer IMP 1.

In an embodiment, a plurality of second horizontal insulating layers IMP2 may be provided. Referring to fig. 3B, at least two second horizontal insulating layers IMP2a may be provided between the top surface 130t of the planarization insulating layer 130 and the top surface 150t of the upper insulating layer 150. The second horizontal insulating layers IMP2a may be spaced apart from each other in the third direction D3. In an embodiment, the second horizontal insulating layers IMP2a may be formed of or include different materials from each other. The second horizontal insulating layer IMP2a may be formed by performing an ion implantation process twice on the upper insulating layer 150. The position of the second horizontal insulating layer IMP2a may be changed by adjusting the ion implantation energy in the ion implantation process and the heating method in the heat treatment process. A method of forming the second horizontal insulating layer IMP2a may be substantially the same as the method of forming the first horizontal insulating layer IMP1a described with reference to fig. 4B.

The plurality of bit lines BL may be provided on the cell array region CAR, may extend in the second direction D2, and may be spaced apart from each other in the first direction D1. Referring back to FIG. 1, the bit line BL of FIGS. 2A-2C may be used as the bit line BL0-BL2 of FIG. 1. The bit line BL may be provided on the upper insulating layer 150. The bit lines BL may be respectively connected to the first vertical structures VS1 through bit line contact plugs BPLG. The bit line contact plug BPLG may be provided to penetrate the upper insulating layer 150 and the second horizontal insulating layer IMP 2. The bit line BL and the bit line contact plug BPLG may be formed of or include at least one of conductive materials.

A plurality of conductive lines CL may be provided on the connection region CNR and the peripheral circuit region PCR, and in an embodiment, the conductive lines CL may extend in the second direction D2 and may be spaced apart from each other in the first direction D1. The conductive line CL may be provided on the upper insulating layer 150. The conductive lines CL on the connection region CNR may be respectively connected to the electrodes EL of the electrode structure ST through the cell contact plugs CPLG. The cell contact plug CPLG may be provided to penetrate the upper insulating layer 150, the second horizontal insulating layer IMP2, the planarization insulating layer 130, the first horizontal insulating layer IMP1, and the interlayer insulating layer ILDa of the electrode structure ST. The conductive lines CL on the peripheral circuit region PCR may be connected to the first and second peripheral gate stacks PGS1 and PGS2, respectively, through peripheral contact plugs PPLG. Specifically, each of the peripheral contact plugs PPLG may be in contact with the gate metal pattern PMP. The peripheral contact plug PPLG may be provided to penetrate the upper insulating layer 150, the second horizontal insulating layer IMP2, the planarization insulating layer 130, the first horizontal insulating layer IMP1, the peripheral circuit insulating layer 110, and the peripheral hard mask pattern HMP.

Fig. 3A and 3B are enlarged cross-sectional views illustrating a portion (e.g., a of fig. 2B) of a three-dimensional semiconductor memory device according to an embodiment of the inventive concept.

One of the cell contact plugs CPLG will be described with reference to fig. 3A, but the remaining cell contact plugs CPLG and the peripheral contact plug PPLG on the peripheral circuit region PCR may also have substantially the same features as the cell contact plugs CPLG to be described here. As described above, each cell contact plug CPLG may be provided to penetrate the upper insulating layer 150, the second horizontal insulating layer IMP2, and the planarization insulating layer 130.

Cell contact plug CPL measured in first direction D1The width of G may increase from the top surface 150t of the upper insulating layer 150 to the top surface IMP2t of the second horizontal insulating layer IMP2 and may decrease from the bottom surface of the second horizontal insulating layer IMP2 to the substrate 10 (see, for example, fig. 2B). Specifically, the cell contact plug CPLG may have a maximum width W1m that is greater than the width W1 of the cell contact plug CPLG at the top surface CPLGt thereof. Further, the maximum width W1m of the cell contact plug CPLG may be greater than the widths W1t and W1b of the cell contact plug CPLG at the top and bottom heights of the second horizontal insulating layer IMP 2. Maximum width W1m of cell contact plug CPLG may be from aboutTo aboutWithin the range of (1). In an embodiment, the cell contact plug CPLG may have a maximum width W1m at an intermediate height of the second horizontal insulating layer IMP2 in the third direction D3. The first distance L1 from the top surface CPLGt of the unit contact plug CPLG to the portion having the maximum width W1m may be from aboutTo aboutWithin the range of (1).

Since the second horizontal insulating layer IMP2 is provided in the upper insulating layer 150, the maximum width W1m of the cell contact plug CPLG may be reduced. The reduction in the maximum width W1m of the cell contact plug CPLG may be due to the fact that the etch resistance of the second horizontal insulating layer IMP2 is better than that of the upper insulating layer 150. Due to the reduction in maximum width W1m of cell contact plug CPLG, it is possible to prevent a short circuit from being formed between adjacent ones of cell contact plugs in cell contact plug CPLG. Further, by controlling the process conditions (e.g., ion implantation energy and ion implantation amount) in the ion implantation process, the maximum width W1m of the cell contact plug CPLG and the first distance L1 from the top surface CPLGt of the cell contact plug CPLG to the portion having the maximum width W1m can be controlled.

Table 1 below shows the maximum width W1m of cell contact plug CPLG formed under different conditions with respect to the ion implantation energy and the ion implantation amount.

[ Table 1]

Referring to table 1, in the case (Ref) where the second horizontal insulating layer IMP2 is not provided (i.e., the ion implantation process is not performed), the maximum width W1m of the cell contact plug CPLG is aboutIn addition, in the case where the second horizontal insulating layer IMP2 is formed through the ion implantation process, the maximum width W1m of the cell contact plug CPLG is reduced. The maximum width W1m of the cell contact plug CPLG is reduced by about 5-6% as compared with the case (Ref) in which the ion implantation process is not performed. In this case, a short circuit is prevented from being formed between adjacent ones of the cell contact plugs CPLG. Referring to fig. 3B, a plurality of second horizontal insulating layers IMP2a may be provided in the upper insulating layer 150. In an embodiment, the second horizontal insulating layer IMP2a may have a different thickness T1a when measured in the third direction D3. Specifically, the difference in the thickness T1a between the second horizontal insulating layers IMP2a may be achieved by adjusting process conditions (e.g., ion implantation energy and ion implantation amount) in at least two ion implantation processes. Since the second horizontal insulating layer IMP2a is provided in the upper insulating layer 150, the maximum width W1m of the cell contact plug CPLG may be smaller than that in fig. 3A.

Fig. 4A and 4B are enlarged cross-sectional views illustrating a portion (e.g., B of fig. 2B) of a three-dimensional semiconductor memory device according to an embodiment of the inventive concept.

One of the first vertical structures VS1 will be described with reference to fig. 4A, but the remaining first vertical structures VS1 and the second vertical structure VS2 on the connection region CNR may also have substantially the same features as the first vertical structure VS1 to be described herein. As described above, the first vertical structure VS1 may be provided to penetrate the uppermost interlayer insulating layer ILDb, the first horizontal insulating layer IMP1, and the uppermost electrode ELt.

The width of the first vertical structure VS1 measured in the first direction D1 may increase from the top surface ILDbt of the uppermost interlayer insulating layer ILDb to the top surface IMP1t of the first horizontal insulating layer IMP1 and may decrease from the bottom surface of the first horizontal insulating layer IMP1 to the substrate 10 (see, e.g., fig. 2B). In particular, the first vertical structure VS1 may have a maximum width W2m that is greater than the width W2 of the first vertical structure VS1 at its top surface VS1 t. Further, the maximum width W2m of the first vertical structure VS1 may be greater than the widths W2t and W2b of the first vertical structure VS1 at the top and bottom levels of the first horizontal insulating layer IMP 1. The maximum width W2m of the first vertical structure VS1 may be from aboutTo aboutWithin the range of (1). In an embodiment, the first vertical structure VS1 may have a maximum width W2m at a middle height of the first horizontal insulating layer IMP1 in the third direction D3. The second distance L2 from the top surface VS1t of the first vertical structure VS1 to the portion having the maximum width W2m may be from aboutTo aboutWithin the range of (1).

Since the first horizontal insulating layer IMP1 is provided in the uppermost interlayer insulating layer ILDb, the maximum width W2m of the first vertical structure VS1 may be reduced. The reduction in the maximum width W2m of the first vertical structure VS1 may be due to the fact that the etch resistance of the first horizontal insulating layer IMP1 is better than that of the uppermost interlayer insulating layer ILDb. Due to the reduction of the maximum width W2m of the first vertical structure VS1, it is possible to prevent short circuits from being formed between adjacent ones of the first vertical structures VS 1. Further, by controlling the ion implantation energy and the ion implantation amount in the ion implantation process, the maximum width W2m of the first vertical structure VS1 and the second distance L2 from the top surface VS1t of the first vertical structure VS1 to the portion having the maximum width W2m may be controlled.

Referring to fig. 4B, a plurality of first horizontal insulating layers IMP1a may be provided in the uppermost interlayer insulating layer ILDb. The first horizontal insulating layer IMP1a may have a different thickness T2a when measured in the third direction D3. Specifically, the difference in the thickness T2a between the first horizontal insulating layers IMP1a may be achieved by adjusting process conditions (e.g., ion implantation energy and ion implantation amount) in at least two ion implantation processes. Since the plurality of first horizontal insulating layers IMP1a are provided, the maximum width W2m of the first vertical structure VS1 may be smaller than that in fig. 4A.

Fig. 5 is an enlarged cross-sectional view illustrating a portion (e.g., C of fig. 2B) of a three-dimensional semiconductor memory device according to an embodiment of the inventive concept.

One of the source structure SC and the first vertical structure VS1 will be described with reference to fig. 5, but the remaining first vertical structure VS1 may also have substantially the same features as those to be described herein. As described above, the source structure SC may include the first source conductive pattern SCP1 and the second source conductive pattern SCP2, and each of the first vertical structures VS1 may include the data storage pattern DSP, the first vertical semiconductor pattern VSP1, the buried insulating pattern VI, and the lower data storage pattern DSPr.

The first source conductive pattern SCP1 of the source structure SC may be in contact with the first vertical semiconductor pattern VSP1, and the second source conductive pattern SCP2 may be spaced apart from the first vertical semiconductor pattern VSP1 with the data storage pattern DSP interposed therebetween. The first source conductive pattern SCP1 may be spaced apart from the buried insulating pattern VI with the first vertical semiconductor pattern VSP1 interposed therebetween.

Specifically, the first source conductive pattern SCP1 may include a protruding portion SCP1bt, the protruding portion SCP1bt being located at a height higher than the bottom surface SCP2b of the second source conductive pattern SCP2 or at a height lower than the bottom surface SCP1b of the first source conductive pattern SCP 1. However, the protruding portion SCP1bt may be located at a lower height than the top surface SCP2a of the second source conductive pattern SCP 2. The surface of the protruding portion SCP1bt, which is in contact with the data storage pattern DSP or the lower data storage pattern DSPr, for example, may have a curved shape.

Fig. 6A is a plan view illustrating a three-dimensional semiconductor memory device according to an embodiment of the inventive concept. Fig. 6B and 6C are cross-sectional views taken along lines I-I 'and II-II' of fig. 6A illustrating a three-dimensional semiconductor memory device according to an embodiment of the inventive concept. For the sake of concise description, elements previously described with reference to fig. 2A to 5 may be identified by the same reference numerals without repeating repeated descriptions thereof.

Referring to fig. 6A, 6B, and 6C, the three-dimensional semiconductor memory device may include a peripheral circuit structure PS and a cell array structure CS on the peripheral circuit structure PS.

The peripheral circuit structure PS may include a first substrate 10, a peripheral circuit PTR integrated on a top surface of the first substrate 10, and a peripheral insulating layer 30 covering the peripheral circuit PTR. The first substrate 10 may be a silicon substrate, a silicon germanium substrate, a germanium substrate, or a single crystal epitaxial layer grown on a single crystal silicon substrate. The first substrate 10 may have an active region defined by a device isolation layer 11.

The peripheral circuits PTR may include, for example, row and column decoders, page buffers, control circuits, and the like. Specifically, each peripheral circuit PTR may include a peripheral gate electrode 21, a peripheral gate insulating layer 23, a peripheral capping pattern 25, a peripheral gate spacer 27, and a peripheral source/drain region 29. A peripheral gate insulating layer 23 may be provided between the peripheral gate electrode 21 and the first substrate 10. A peripheral overlay pattern 25 may be provided on the peripheral gate electrode 21. The peripheral gate spacer 27 may cover a side surface of the peripheral gate electrode 21, a side surface of the peripheral gate insulating layer 23, and a side surface of the peripheral cover pattern 25. Peripheral source/drain regions 29 may be provided in portions of the substrate 10 on both sides of the peripheral gate electrode 21. The peripheral circuit line 33 may be electrically connected to the peripheral circuit PTR through the peripheral contact plug 31. As an example, the peripheral contact plugs 31 and the peripheral circuit lines 33 may be connected to transistors on the first substrate 10. For example, the transistors on the first substrate 10 may include NMOS, PMOS, or surrounding gate transistors. The peripheral insulating layer 30 may be provided on the top surface of the first substrate 10. In an embodiment, a peripheral insulating layer 30 may be provided on the first substrate 10 to cover the peripheral circuit PTR, the peripheral contact plugs 31, and the peripheral circuit lines 33. The peripheral insulating layer 30 may include a plurality of insulating layers stacked on the substrate 10. For example, the peripheral insulating layer 30 may be formed of or include at least one of silicon oxide, silicon nitride, silicon oxynitride, and a low-k dielectric material.

The cell array structure CS may be provided on the peripheral insulating layer 30, and in an embodiment, the cell array structure CS may include a second substrate 100, an electrode structure ST on the second substrate 100, a planarization insulating layer 130 provided on the second substrate 100 to cover the electrode structure ST, and an upper insulating layer 150 covering the electrode structure ST and the planarization insulating layer 130. The cell array structure CS may further include: a first horizontal insulating layer IMP1 provided in the uppermost interlayer insulating layer ILDb of the electrode structure ST and extending along the electrodes EL and ELt; and a second horizontal insulating layer IMP2 provided in the upper insulating layer 150 and extending along the electrodes EL and ELt.

The connection structure ICS may be provided to connect the cell array structure CS to the peripheral circuit structure PS. The connection structure ICS may include one of the conductive lines CL, the cell contact plug CPLG, and the through plug TPLG on the upper insulating layer 150. The through plug TPLG may be provided to penetrate the upper insulating layer 150, the planarization insulating layer 130, the first and second horizontal insulating layers IMP1 and IMP2, the second substrate 100, and a portion of the peripheral insulating layer 30. The through plug TPLG may be connected to at least one of the peripheral circuit lines 33. Although not shown, a plurality of through plugs TPLG may be provided and may be respectively connected to the peripheral circuit lines 33.

Fig. 7 is a cross-sectional view taken along line I-I' of fig. 6A illustrating a three-dimensional semiconductor memory device according to an embodiment of the inventive concept. For the sake of brevity, elements previously described with reference to fig. 2A to 6C may be identified by the same reference numerals without repeating repeated descriptions thereof.

Referring to fig. 7, each electrode structure ST may include a first electrode structure ST1 and a second electrode structure ST 2. The first electrode structure ST1 may include first electrodes EL1 sequentially stacked on the substrate 10 and a first interlayer insulating layer ILD1a provided between the first electrodes EL 1. The second electrode structure ST2 may include second electrodes EL2 sequentially stacked on the substrate 10 and second interlayer insulating layers ILD2a and ILD2b provided between the second electrodes EL 2. The first electrode structure ST1 may be provided on the source structure SC, and the second electrode structure ST2 may be provided on the first electrode structure ST 1. Specifically, the second electrode structure ST2 may be provided on the top surface of the uppermost one of the first interlayer insulating layers ILD1a of the first electrode structure ST 1. Accordingly, the lowermost one of the second interlayer insulating layers ILD2a and ILD2b of the second electrode structure ST2 may contact the uppermost one of the first interlayer insulating layers ILD1a of the first electrode structure ST 1.

The first vertical channel CH1 may be provided to penetrate the first electrode structure ST1 and expose a portion of the second substrate 100. The second vertical channel CH2 may be provided to penetrate the second electrode structure ST2 and expose the first vertical channel CH 1. The first vertical channel CH1 and the second vertical channel CH2 may be connected to each other. The lower diameter of the second vertical channel CH2 may be smaller than the upper diameter of the first vertical channel CH 1. A first vertical structure VS1 may be provided in the first vertical channel CH1 and the second vertical channel CH 2. Each of the first vertical structures VS1 may include a data storage pattern DSP, a first vertical semiconductor pattern VSP1, and a first conductive PAD 1. The data storage pattern DSP may be provided to conformally cover the side surface of the first vertical channel CH1 and the side surface of the second vertical channel CH 2.

Fig. 8A and 9A are cross-sectional views taken along line I-I' of fig. 2A illustrating a three-dimensional semiconductor memory device according to an embodiment of the inventive concept. Fig. 8B and 9B are sectional views taken along line II-II' of fig. 2A illustrating a three-dimensional semiconductor memory device according to an embodiment of the inventive concept. For the sake of concise description, elements previously described with reference to fig. 2A to 5 may be identified by the same reference numerals without repeating repeated descriptions thereof.

Referring to fig. 8A and 8B, the three-dimensional semiconductor memory device may include an upper insulating layer 150, the upper insulating layer 150 including a second horizontal insulating layer IMP2 without a first horizontal insulating layer IMP 1. Referring to fig. 9A and 9B, the three-dimensional semiconductor memory device may include an uppermost interlayer insulating layer ILDb including a first horizontal insulating layer IMP1 without a second horizontal insulating layer IMP 2. The first horizontal insulating layer IMP1 may extend from the uppermost interlayer insulating layer ILDb into the planarization insulating layer 130. In other words, one of the first and second horizontal insulating layers IMP1 and IMP2 of fig. 2B and 2C may be omitted, and the other may be provided.

According to an embodiment of the inventive concept, a three-dimensional semiconductor memory device may include an insulating layer formed to have a portion whose etch resistance is improved through an ion implantation process, which makes it possible to reduce a maximum width of a contact having a high aspect ratio. Accordingly, it is possible to prevent a short circuit from being formed between the contacts and improve electrical characteristics of the three-dimensional semiconductor memory device.

While example embodiments of the inventive concept have been particularly shown and described, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the scope of the appended claims.

This patent application claims priority from korean patent application No. 10-2019-0155598 filed in the korean intellectual property office at 28.11.2019, the entire contents of which are incorporated herein by reference.