阅读说明：本技术 用于多个数据存储体的共享错误校验及校正逻辑 (Shared error checking and correction logic for multiple data banks ) 是由 高橋進 藤澤宏樹 于 2019-06-20 设计创作，主要内容包括：本发明揭示与可执行错误校验及校正ECC功能的存储器装置相关的系统及方法。所述系统及方法可采用可在两个或更多个存储体(0到7)之间共享的ECC逻辑(162A到162D、164A到164D、166A到166D、168A到168D)。所述ECC逻辑可用于执行例如读取、写入及屏蔽写入操作等存储器操作,且可提高存储数据的可靠性。(Systems and methods related to memory devices that can perform error checking and correcting ECC functions are disclosed. The systems and methods may employ ECC logic (162A-162D, 164A-164D, 166A-166D, 168A-168D) that may be shared between two or more banks (0-7). The ECC logic may be used to perform memory operations such as read, write, and mask write operations, and may improve the reliability of stored data.)

1. An apparatus, comprising:

a first memory block of a first data bank, the first memory block comprising a first plurality of memory cells;

a second memory block of a second data bank, the second memory block comprising a second plurality of memory cells, wherein the second data bank is different from the first data bank; and

an error checking and correcting ECC block configured to perform ECC operations associated with memory operations that address the first memory block or the second memory block or both.

2. The apparatus of claim 1, wherein the ECC block comprises: an input circuitry and an output circuitry; first block selection circuitry configured to couple the input circuitry to the first memory block or the second memory block based on a bank selection command; and second block selection circuitry configured to couple the output circuitry to the first memory block or the second memory block based on the bank selection command.

3. The apparatus of claim 2, wherein the first block selection circuitry comprises a multiplexer controlled by the bank select command.

4. The apparatus of claim 2, wherein the second block selection circuitry comprises a first latch coupled to the first memory block and a second latch coupled to the second memory block, wherein the first latch and the second latch are controlled by the bank selection command.

5. The apparatus of claim 1, wherein the ECC block comprises:

a bit correction block configured to receive read data from the first memory block or the second memory block; and

a multiplexer comprising a first input, a second input, and a third input, wherein the first input is configured to receive the read data from the first memory block or the second memory block, the second input is configured to receive write data from a read/write bus, and the third input is configured to receive correction data from the bit correction block.

6. The apparatus of claim 5, comprising input/output circuitry coupled to the read/write bus, wherein the input/output circuitry is configured to receive data from outside the apparatus and to provide data to outside the apparatus.

7. The apparatus of claim 5, wherein the multiplexer is configured to perform a masked write operation by:

receiving a data masking signal;

selecting the write data from the second input when the data mask signal indicates a mask; and

selecting the correction data from the third input when the data mask signal indicates no mask.

8. The apparatus of claim 1, wherein the memory operation comprises a read operation, a write operation, or a masked write operation.

9. The apparatus of claim 1, comprising a Dynamic Random Access Memory (DRAM) device.

10. A memory device, comprising

Control circuitry comprising a command decoder, an address decoder, and a write latency counter; and

a dynamic random access memory DRAM array, comprising:

a plurality of data banks, wherein each data bank includes a set of memory blocks;

a plurality of error checking and correcting ECC blocks, wherein each respective ECC block comprises a respective ECC decoder and a respective ECC syndrome decoder, and wherein each respective ECC block is configured to be coupled to a first memory block of a first bank of data and a second memory block of a second bank of data, wherein the second bank of data is different from the first bank of data; and

ECC control logic configured to receive a start signal from the write latency counter and provide a trigger signal and a bank select command to the plurality of ECC blocks.

11. The memory device of claim 10, wherein the command decoder is configured to receive a read command, a write command, and a mask write command.

12. The memory device of claim 10, comprising an I/O circuit, a read/write bus configured to transfer data between the I/O circuit and the plurality of ECC blocks, and a data mask bus configured to provide data masking to the plurality of ECC blocks.

13. The memory device of claim 12, wherein each respective ECC block comprises a respective 3-input multiplexer, the 3-input multiplexer configured to receive read data from the first memory block or the second memory block via a first input, write data from the read/write bus via a second input, and correction data from a respective bit correction block via a third input of the respective ECC block.

14. The memory device of claim 13, wherein each respective ECC syndrome decoder is configured to provide an error information vector to the respective bit correction block.

15. The memory device of claim 13, wherein each respective 3-input multiplexer is configured to perform data masking by selecting the write data via the second input when the data mask indicates unshielded and selecting the correction data via the third input when the data mask indicates masked.

16. The memory device of claim 10, wherein the memory device comprises a Double Data Rate (DDR) memory device, a graphics DDR (GDDR) memory device, or a low power DDR (DDR) LPDDR memory device.

17. A method of performing a masked write operation using a shared Error Checking and Correcting (ECC) block coupled to a first memory block and a second memory block of a memory device, the method comprising:

retrieving first read data from the first memory block using first bank selection circuitry;

correcting the first read data using an ECC decoder, an ECC syndrome decoder, and bit correction circuitry of the ECC block to generate first correction data;

receiving first write data from a read/write (RW) bus coupled to the ECC block;

receiving a first data mask from a Data Mask (DM) bus coupled to the ECC block;

generating first mask write data based on the first correction data, the first write data, and the first data mask; and

providing the first masked write data to the first memory block using a second bank selection circuit; and is

Wherein the memory device includes inter-column tCCD cycles and the generating of the first mask write data is performed within 1 tCCD cycle.

18. The method of claim 17, comprising:

retrieving second read data from the second memory block using the first bank select circuitry;

correcting the second read data using the ECC decoder, the ECC syndrome decoder, and the bit correction circuitry of the ECC block to generate second corrected data;

receiving second write data from the RW bus;

receiving a second data mask from the DM bus;

generating second masked-write data based on the second corrected data, the second write data and the second data mask; and

providing the second masked write data to the second memory block using the second bank selection circuitry.

19. The method of claim 17, wherein generating the first masked write data comprises selecting the first write data when the first data mask indicates unmasking and selecting the first correction data when the first data mask indicates masking.

20. The method of claim 17, wherein correcting the first read data comprises generating parity bits using the ECC decoder, determining an error information vector using the ECC syndrome decoder, and selectively inverting bits using the bit correction circuitry based on the error information vector.

21. A memory device, comprising:

a first memory block belonging to a first memory bank, the first memory block comprising a first plurality of memory cells;

a second memory block belonging to a second memory bank, the second memory block comprising a second plurality of memory cells, wherein the second memory bank is different from the first memory bank; and

an error checking and correcting ECC block comprising ECC circuitry, wherein the first memory block and the second memory block share the ECC circuitry.

22. The memory device of claim 21, wherein the ECC circuit comprises an input node and an output node and wherein the ECC block comprises:

first control circuitry configured to selectively couple the input node of the ECC circuit to the first memory block or the second memory block; and

a second control circuit configured to selectively couple the output node of the ECC circuit to the first memory block or the second memory block.

23. The memory device of claim 21, wherein the ECC block comprises a multiplexer having a first input, a second input, and a third input, wherein the first input is configured to receive an output from the first memory block or the second memory block, and the second input is configured to receive a data signal from a read/write RW bus, and wherein the ECC circuit comprises an error corrector configured to receive the output from the first memory block or the second memory block and provide its output to the third input of the multiplexer.

24. The memory device of claim 23, comprising data input/output circuitry coupled to the RW bus, the data input/output circuitry configured to receive data from and provide data external to the memory device.

Technical Field

The present disclosure relates to memory systems and devices, and more specifically, the present disclosure relates to Error Checking and Correction (ECC) circuitry.

Background

This section is intended to introduce the reader to various aspects of art, which may be related to various aspects of the present invention, as described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate an understanding of the various aspects of the present invention. Accordingly, it should be understood that these statements are to be read in this light, and not as admissions of prior art.

Memory devices, such as Random Access Memory (RAM) devices, dynamic RAM Devices (DRAM), static RAM devices (SRAM), or flash memory, are important components of electronic systems and devices, such as computers, servers, network devices, mobile phones, smart phones, wearable devices, media players, internet of things (IoT) devices, and the like. Memory devices may be used to provide memory functions for processing circuitry (e.g., processors, microcontrollers, systems on a chip) and to facilitate data processing operations and/or to provide data storage during data processing operations. To this end, a memory device may have addressable memory elements arranged in a memory array and/or bank. These memory devices may also include a control interface that allows the memory device to receive commands and addresses and/or an input/output (I/O) interface that provides data access between the memory elements and the processing circuitry.

Certain memory devices may provide Error Checking and Correction (ECC) functions that may be used to improve the reliability of data storage. In such systems, data stored in a memory element, array, or bank may be associated with (e.g., stored with) an error bit or parity bit. The parity bits may provide data redundancy that allows verification of data integrity. For example, during a write operation, ECC circuitry may be used to determine parity bits that may be stored with the write data. During a read operation, ECC circuitry may retrieve read data and parity bits and check for errors in the read data. During a masked write operation, ECC circuitry may retrieve old data, correct errors using parity bits, perform a masked write operation, and generate new parity bits using a new mask word. In general, ECC codes may allow verification and/or correction of data, and ECC circuitry may perform error correction accordingly.

The ECC circuitry may be associated with a data bank or a segment of the data bank. An example of a memory device having ECC circuitry is the Dynamic Random Access Memory (DRAM) array 10 illustrated in FIGS. 1A, 1B, and 1C. The DRAM array 10 may have 8 data banks and each data bank may have 4 memory blocks. In the example, the DRAM array 10 has a data bank 0 containing memory blocks 12A, 12B, 12C, and 12D, a data bank 1 containing memory blocks 14A, 14B, 14C, and 14D, a data bank 2 containing memory blocks 16A, 16B, 16C, and 16D, a data bank 3 containing memory blocks 18A, 18B, 18C, and 18D, a data bank 4 containing memory blocks 22A, 22B, 22C, and 22D, a data bank 5 containing memory blocks 24A, 24B, 24C, and 24D, a data bank 6 containing memory blocks 26A, 26B, 26C, and 26D, and a data bank 7 containing memory blocks 28A, 28B, 28C, and 28D.

The blocks may be controlled by bank logic circuitry. In the example of DRAM array 10, data bank 0 is associated with bank logic 32A and 32B, data bank 1 is associated with bank logic 34A and 34B, data bank 2 is associated with bank logic 36A and 36B, data bank 3 is associated with bank logic 38A and 38B, data bank 4 is associated with bank logic 42A and 42B, data bank 5 is associated with bank logic 44A and 44B, data bank 6 is associated with bank logic 46A and 46B, and data bank 7 is associated with bank logic 48A and 48B. The illustrated DRAM array 10 may also include peripheral circuitry blocks 50. Each memory block may be associated with a dedicated column decoder 52 and row decoder 54, as illustrated.

As discussed above, memory devices typically have ECC circuitry dedicated to each data bank. This may provide a dedicated ECC function to each data bank. In the illustrated DRAM array 10, each bank of data is illustrated as being served by two dedicated ECC blocks. For example, ECC blocks 62A and 62B may be dedicated to data bank 0. As illustrated, ECC block 62A services memory blocks 12A and 12B and ECC block 62B services memory blocks 12C and 12D. Similarly, ECC block 64A services memory blocks 14A and 14B and ECC block 64B services memory blocks 14C and 14D of data bank 1, ECC block 66A services memory blocks 16A and 16B and ECC block 66B services memory blocks 16C and 16D of data bank 2, ECC block 68A services memory blocks 18A and 18B and ECC block 68B services memory blocks 18C and 18D of data bank 3, ECC block 72A services memory blocks 22A and 22B and ECC block 72B services memory blocks 22C and 22D of data bank 4, ECC block 74A services memory blocks 24A and 24B and ECC block 74B services memory blocks 24C and 24D of data bank 5, ECC block 76A services memory blocks 26A and 26B and ECC block 76B services memory blocks 26C and 26D of data bank 6, ECC block 78A services memory blocks 28A and 28B and ECC block 78B services memory blocks 28C and 28D of data bank 7. The DRAM array 10 may have a length 82 and a height 84 as dimensions.

An arrangement such as the above-described arrangement, in which each data bank may have dedicated ECC circuitry, facilitates the design of a memory device to conform to particular user specifications and/or standard specifications. For example, a particular standard, such as the Joint Electron Device Engineering Council (JEDEC) standard, may have different latency specifications between two commands (i.e., a minimum period between two consecutive commands) when issuing two commands to addresses in the same data bank or different data banks. That is, commands issued to two addresses in two different data banks may have a smaller latency specification, while commands issued to two addresses in a common bank may have a larger latency specification. As an example, in the JEDEC specification for a Mask Write (MWR) command in a low power double data rate 4(LPDDR4) memory, the minimum delay between two adjacent mask read commands when issued to the same data bank is 4 × tCCD, and the minimum delay between two adjacent mask read commands when issued to different data banks is 1 × tCCD. In other words, the time interval of adjacent MWR commands for the same data bank may be relatively long, while the time interval of two adjacent MWR commands for different data banks may be very short. Because the ECC operation may be performed during a masked write operation, the presence of ECC circuitry dedicated to each data bank may facilitate MWR commands in different data blocks to meet short time intervals.

The presence of dedicated ECC circuitry per data bank can occupy a significant amount of floor plan resources. As memory devices become denser (e.g., more memory per device) and/or the size of memory devices decreases, the available floor plan for memory logic (which includes ECC logic) may become more limited.

Drawings

Various aspects of the invention may be better understood upon reading the following detailed description and upon reference to the drawings in which:

FIGS. 1A, 1B and 1C illustrate a conventional Dynamic Random Access Memory (DRAM) array with dedicated Error Checking and Correction (ECC) blocks;

FIGS. 2A, 2B and 2C illustrate a DRAM array with shared ECC blocks according to an embodiment of the present invention;

FIG. 3 is a schematic block diagram of a memory device that may employ shared ECC blocks, according to an embodiment of the present invention;

FIG. 4A is a schematic block diagram of a shared ECC block coupled to different data banks, according to an embodiment of the present invention;

FIG. 4B is a schematic block diagram of a DRAM array having a shared ECC block controlled by ECC control logic in accordance with an embodiment of the present invention;

FIG. 5 is a flow diagram of a method of performing a memory read operation using a shared ECC block, according to an embodiment of the present invention;

FIG. 6 is a flow diagram of a method of performing a memory write operation using a shared ECC block, according to an embodiment of the present invention;

FIG. 7 is a flow diagram of a method of performing a masked-write operation using shared ECC blocks, according to an embodiment of the invention;

FIG. 8 is a timing diagram illustrating an adjacent mask write operation according to an embodiment of the present invention;

FIG. 9 is a timing diagram illustrating trigger and data signals that may be exchanged during a neighbor mask write operation, according to an embodiment of the invention;

FIG. 10 includes a first data flow and timing diagram illustrating execution of a masked-write operation according to an embodiment of the present invention;

FIG. 11 includes a second dataflow and timing diagram illustrating a masked write operation execution and may occur after the diagram of FIG. 10;

FIG. 12 includes a third dataflow and timing diagram illustrating a masked write operation execution and may occur after the diagram of FIG. 11;

FIG. 13 includes a fourth dataflow and timing diagram illustrating a masked write operation execution and may occur after the diagram of FIG. 12;

FIG. 14 includes a fifth dataflow and timing diagram illustrating a masked write operation execution, which may occur after the diagram of FIG. 13;

FIG. 15 includes a sixth dataflow and timing diagram illustrating execution of a masked write operation, and may occur after the diagram of FIG. 14; and

FIG. 16 includes a seventh dataflow and timing diagram illustrating execution of a masked write operation, and may occur after the diagram of FIG. 15.

Detailed Description

One or more specific embodiments will be described below. In an effort to provide a concise description of these embodiments, not all features of an actual implementation are described in the specification. It should be appreciated that in the development of any such actual implementation, as in any engineering or design project, numerous implementation-specific decisions must be made to achieve the developers' specific goals, such as compliance with system-related and enterprise-related constraints, which may vary from one implementation to another. Moreover, it should be appreciated that such a development effort might be complex and time consuming, but would nevertheless be a routine undertaking of design, fabrication, and manufacture for those of ordinary skill having the benefit of this disclosure.

Many electronic systems and devices, such as computers, mobile phones, wearable devices, internet of things (IoT) devices, servers, data center processing and storage devices, and the like, may employ memory devices to provide data storage functions and/or facilitate performance of data processing operations. To this end, these electronic systems may include processing circuitry that may be coupled to a memory device. A number of memory devices may store data using addressable memory elements (e.g., memory rows or columns) that may be disposed in a data bank. Examples of addressable memory devices include Random Access Memory (RAM) devices, dynamic RAM (dram) devices (e.g., Synchronous Dram (SDRAM) devices), double data rate SDRAM devices (e.g., DDR SDRAM, DDR2 SDRAM, DDR3 SDRAM, DDR4 SDRAM), low power DDR devices (e.g., LPDDR3 SDRAM, LPDDR4 SDRAM, and graphics DDR SDRAM devices (e.g., GDDR3 SDRAM, GDDR4 SDRAM), and static RAM (sram) devices and/or flash memory devices, among others.

To interact with a memory device, processing circuitry in an electronic system may access (e.g., read or write) a memory element by interacting with an input/output (I/O) interface and a command interface. As an example, a processor may store information by providing a write command and/or address to a memory element and a series of words to be stored, and read storage information from a particular memory element from a memory device by providing a read command and/or address and receiving a storage word. Commands and/or addresses may be provided via a command interface, and request information (e.g., words) may be retrieved via an I/O interface. A particular memory device is capable of performing a masked write operation. In a masking operation, the processor may provide a masked write command and/or address and a series of words to be stored and a data mask indicating which portions of the old data should be retained to the memory element containing the old data.

Many devices also include Error Checking and Correction (ECC) circuitry that may be used to improve data integrity. ECC circuitry may be used to generate parity bits (e.g., error check bits, ECC bits, error bits) that may be stored with the data during a write operation. ECC circuitry may also use previously stored error bits to verify and/or correct stored data during a read operation. In some implementations, ECC circuitry can mark (e.g., label) words identified as corrupted or not repairable. In a masked write operation, ECC logic may retrieve old data, identify any errors to generate corrected old data, perform corrections based on incoming data and the data mask to generate new data, generate new parity bits, and store the new data containing new parity bits. In this way, the ECC circuitry may provide redundancy to the stored data, which may improve the reliability of the storage operation.

As discussed above, the ECC operation may be performed for each operation that may access, store, or modify data in the data bank, including read, write, and/or mask write operations. Thus, to meet certain latency specifications (e.g., read, write, and mask write specifications), proper allocation of ECC resources (e.g., number and distribution of ECC circuitry) affects the design of the memory device. For example, as discussed above, the latency period between commands issued to the same data bank (i.e., addresses associated with a common data bank) may be relatively long, while the latency period between commands to different data banks (i.e., addresses in different data banks) may be very short. Thus, ECC execution resources may be allocated based on the arrangement of the data banks.

In a conventional system, such as the DRAM array 10 illustrated in fig. 1A-1C, each bank of data may have one or more dedicated ECC blocks for servicing its memory blocks, as described above. Embodiments of the present description include memory devices that may have ECC blocks that may be shared by memory blocks of different data banks. Such sharing may allow for a reduction in the number and/or size of ECC blocks employed, which may result in reduced planar programming die, faster memory device operation, and/or increased memory density. Because an ECC block may be shared by data banks of different ECC blocks, an ECC block may include input circuitry, output circuitry, block selection circuitry, latch circuitry, and/or multiplexing circuitry that may facilitate access to different data banks. Such implementations may facilitate compliance with standards having relatively short latency periods for commands issued to different data banks of a sharable ECC block. The improvements described herein may also reduce latency of commands issued to a common memory block, and may increase the operating speed of the memory device.

In view of the above, FIGS. 2A, 2B, and 2C illustrate a DRAM array 110 that may employ ECC blocks that service different banks of data. The DRAM array 110 may have 8 data banks and 4 memory blocks per data bank. In an example, the DRAM array 110 has data bank 0 with memory blocks 112A, 112B, 112C, and 112D, data bank 1 with memory blocks 114A, 114B, 114C, and 114D, data bank 2 with memory blocks 116A, 116B, 116C, and 116D, data bank 3 with memory blocks 118A, 118B, 118C, and 118D, data bank 4 with memory blocks 122A, 122B, 122C, and 122D, data bank 5 with memory blocks 124A, 124B, 124C, and 124D, data bank 6 with memory blocks 126A, 126B, 126C, and 126D, and data bank 7 with memory blocks 128A, 128B, 128C, and 128D. Thus, the capacity (i.e., memory capacity) of the DRAM array 110 may be similar to the capacity of the DRAM array 10 illustrated in FIGS. 1A, 1B, and 1C.

The memory blocks may be controlled by bank logic circuitry. In the DRAM array 110, the memory blocks of each data bank may be contiguous. Thus, the number of bank logical blocks can be reduced, each data bank having a single bank logical block. As illustrated in DRAM array 110, data bank 0 may be associated with a single bank logic 132, data bank 1 with bank logic 134, data bank 2 with bank logic 136, data bank 3 with bank logic 138, data bank 4 with bank logic 142, data bank 5 with bank logic 144, data bank 6 with bank logic 146, and data bank 7 with bank logic 148. Thus, the number of bank logic blocks can be reduced from 32 for DRAM array 10 to 16 in DRAM array 110 without any reduction in memory capacity.

The illustrated DRAM array 110 may include a peripheral circuitry block 150. A memory block may also be associated with a column decoder block 152 and a row decoder block 154, as illustrated in the example. As discussed above, in the DRAM array 110, the memory blocks of each data bank may be adjacent. Thus, it should be noted that the number of row decoder blocks 154 may be reduced from 32 in the DRAM array 10 to 16 in the DRAM array 110. This may be due to the sharing of the row decoder block 154. For example, in data bank 0, memory blocks 112A and 112C may share a first row decoder 154 and memory blocks 112B and 112D may share a second row decoder 154, as illustrated. Memory blocks 112A and 112C may share row decoder 154 because they are activated by a common address that shares up to the most significant bit (i.e., RA ═ 0), and memory blocks 112B and 112D may share row decoder 154 because they are activated by a common address that is up to the most significant bit (i.e., RA ═ 1). As illustrated, data banks 1, 2, 3, 4, 5, 6, and 7 may also have a similar arrangement of row decoder blocks 154, with two memory blocks activated by a common row address being served by each row decoder block 154.

The arrangement of the DRAM array 110 may also include the presence of shared ECC logic blocks. For example, ECC blocks 162A, 162B, 162C, and 162D may be shared by memory blocks of data banks 0 and 1. Shared ECC block 162A may serve memory block 112A of data bank 0 and memory block 114A of data bank 1, shared ECC block 162B may serve memory block 112C of data bank 0 and memory block 114C of data bank 1, shared ECC block 162C may serve memory block 112B of data bank 0 and memory block 114B of data bank 1, and shared ECC block 162D may serve memory bank 112D of data bank 0 and memory block 114D of data bank 1.

Similarly, ECC blocks 164A, 164B, 164C, and 164D may be shared by memory blocks of data banks 2 and 3. Shared ECC block 164A may serve memory block 116A of data bank 2 and memory block 118A of data bank 3, shared ECC block 164B may serve memory block 116C of data bank 2 and memory block 118C of data bank 3, shared ECC block 164C may serve memory block 116B of data bank 2 and memory block 118B of data bank 3, and shared ECC block 164D may serve data bank 116D of data bank 2 and data bank 118D of data bank 3.

A shared arrangement of ECC blocks may also be found between data banks 4 and 5. The ECC blocks 166A, 166B, 166C, and 166D may be shared by the memory blocks of the data banks 4 and 5. Shared ECC block 166A may serve memory block 122A of data bank 4 and memory block 124A of data bank 5, shared ECC block 166B may serve memory block 122C of data bank 4 and memory block 124C of data bank 5, shared ECC block 166C may serve memory block 122B of data bank 4 and memory block 124B of data bank 5, and shared ECC block 166D may serve memory block 122D of data bank 4 and memory block 124D of data bank 5. Similar arrangements of ECC blocks 168A, 168B, 168C, and 168D shared by the memory blocks of data banks 6 and 7 are also illustrated. Shared ECC block 168A may serve memory block 126A of data bank 6 and memory block 128A of data bank 7, shared ECC block 168B may serve memory block 126C of data bank 6 and memory block 128C of data bank 7, shared ECC block 168C may serve memory block 126B of data bank 6 and memory block 128B of data bank 7, and shared ECC block 168D may serve memory block 126D of data bank 6 and memory block 128D of data bank 7. Due to the arrangement, the DRAM array 110 may have a length 182 and a height 184 that may be less than the length 82 and the height 84 of the DRAM array 10 to result in a smaller device with the same capacity. That is, if the DRAM array 110 has the same length and height as the DRAM 10, the memory capacity of the DRAM array 110 becomes larger than the DRAM array 10.

In view of the above, FIG. 3 illustrates a block diagram of the memory device 202. The memory device 202 may include control circuitry that may be configured to control and access the DRAM array 110. The control circuitry of the memory device 202 may include a command decoder 204 and an address decoder 206. The command decoder 204 and the address decoder 206 may receive command and address signals 210 from an input buffer 208, which may be provided by processing circuitry coupled to the memory device 202. The command decoder 204 may use the command signals 212 to generate a set of instructions to the access control circuitry 211. The command signals 212 may include an ECC command (ECC _ CMD) signal 214 that may be used to control ECC control logic (ECC _ CTRL) 216. The ECC control logic 216 may control the ECC blocks 162A, 162B, 162C, 162D, 164A, 164B, 64C, 164D, 166A, 166B, 166C, 166D, 168A, 168B, 168C, and 168D (only ECC blocks 162A and 168D are illustrated in FIG. 3). The ECC command signal 214 may indicate a command decoded by the command decoder 204 from the command and address signals 210. Thus, the ECC command signal 214 may contain information describing the requested memory device operation (e.g., a mask write command, a read command, a write command, or any other operation that may employ ECC functionality). The address decoder 206 may generate address signals 218 that may be used by the access control circuitry 211. The access control circuitry 211 may use the command signals 212 and the address signals 218 to generate appropriate activation signals 220 that may be used to activate a bank and/or block of data in the DRAM array 110.

The control circuitry of memory device 202 may also include clocked circuitry. To this end, the clock signal 226 may be provided by an input buffer 228, and the input buffer 228 may receive a clock signal 230 from external processing circuitry accessing the memory. Clock signal 226 may be provided to an internal clock generator 229 that generates a series of internal clock signals 231. The control circuitry of the memory device 202 may also include circuitry that may be used to generate a synchronization signal from the clock signal 226 to assist in the operation of the ECC control logic 216. For example, a write latency counter 224 receiving the clock signal 226 may be used to generate the start signal (MWRR _ clk0)232 and the start signal (MWRW _ clk0) 234. The start signals 232 and 234 may be used to coordinate the operation of the ECC blocks, as will be described in detail below. The start signals 232 and 234 may be generated in response to signals generated by the command decoder 204. For example, if the command decoder 204 identifies that the command and address signals 210 are associated with a masked-write command, a masked-write signal (DMWR)222 may be generated to trigger the start signals 232 and 234 to be generated.

The DRAM array 110 may be coupled to a read/write (RW) bus 242 and a Data Mask (DM) bus 244. The RW bus 242 may be used to carry words to and from memory blocks of the DRAM array 110. The DM bus 244 may be used to carry a data mask that may be associated with a masked-write operation, as will be described in detail below. Both the RW bus 242 and the DM bus 244 may be coupled to the ECC blocks 162A-D, 164A-D, 166A-D, 168A-D, and the ECC control logic 216. In some embodiments, the RW bus 242 may be 128 bits wide and the DM bus 244 may be 16 bits wide, as illustrated. The RW bus 242 and the DM bus 244 may be coupled to input/output (I/O) circuitry 246 in the memory device.

The I/O circuitry 246 may exchange data with the processing circuitry using a Data (DQ) signal 248 and a data strobe Signal (DQs) signal 249. In this example, I/O circuit 246 may receive DQ signal 248 over 16 pins that may support 8 bits for the low byte (e.g., DQ <7:0>) and 8 bits for the high byte (e.g., DQ <8: 15). The I/O circuitry 246 may also receive a data mask signal 250 to perform a masked write operation. The DQ signal 248 may be provided at double the data rate of the DQS signal 249. The I/O circuitry 246 may receive the data mask signal 250 via two pins, which may correspond to a low byte and a high byte of data. The burst length (i.e., the number of bits sequentially provided by the processor to each pin) of the memory device 202 may be 16 or 32. During a masked-write operation, the burst length may be 16. Thus, during a masked write operation, the I/O circuit 246 may receive 256 bits (i.e., a 16-bit sequence in each of the 16 pins) over the DQ signals 248 and provide 256 bits to the RW bus 242 in two cycles. Further, the I/O circuitry 246 may receive 32 bits (i.e., a 16-bit sequence in each of the 2 pins) through the DM signal 250 and provide 32 bits to the DM bus 244 in two cycles. Thus, during the masked-write operation, the data provided via the RW bus 242 and the data mask provided via the DM bus 244 are provided in parallel in two cycles.

FIG. 4A illustrates a schematic block diagram 270 of a portion of a DRAM array 110 including a shared ECC block 162A coupled to a memory block 112A of data bank 0 and a memory block 114A of data bank 1. The block diagram illustrates a portion of an ECC block 162A that may facilitate shared operations of the ECC block and may reduce minimum latency between successive commands of the memory device 202. It should be noted that the shared ECC blocks 162B, 162C, 162D, 164A, 164B, 164C, 164D, 166A, 166B, 166C, and 166D may be arranged in a manner similar to that described above.

As discussed above, the shared ECC block 162A may be coupled to the memory blocks 112A and 114A. The memory block 112A may be coupled to the ECC block 162A using 128 data lines 272A and 272B and 8 parity lines 274A and 274B. Similarly, the memory block 114A may be coupled to the ECC block 162A using 128 data lines 276A and 276B and 8 parity lines 278A and 278B. In the illustrative figure, data lines 272A, 272B, 276A, and 276B are coupled to ECC memory blocks 284A and 284B. Similarly, parity lines 274A, 274B, 278A, and 278B are coupled to ECC parity blocks 286A and 286B. Block diagram 270 details the ECC memory block 284A and ECC parity block 286A interacting with data lines associated with the lowest data bits (e.g., data lines 272A and 276A) and the ECC parity block 286A interacting with parity lines associated with the lowest parity bits (e.g., parity lines 274A and 278A). Details of the ECC memory block 284B and the ECC parity block 286B are omitted from the block diagram 270 for clarity. The ECC memory block 284B may include 127 instances of the circuitry illustrated in the ECC memory block 284A, and the ECC parity block 286B may include 7 instances of the circuitry illustrated in the ECC parity block 286B. 128 data bits from data lines 272A and 272B and 8 parity bits from parity lines 274A and 274B may be provided in parallel by memory block 112A. Similarly, 128 data bits from data lines 276A and 276B and 8 parity bits from parity lines 278A and 278B may be provided in parallel by memory block 114A.

ECC block 162A may also include an ECC decoder 288, an ECC syndrome decoder 290, and a bit correction block 292, which may facilitate ECC operations. ECC decoder 288 may be used to generate parity bits (PoutP)341 (which includes parity bits 340A) from 128 of data bits 321 (which includes data bits 320A). ECC syndrome decoder 290 may be used to generate an error information vector (SC)315 (which includes error bits 314A) from generated parity bits 341 and retrieved parity bits (ECC _ Bit)339 (which includes parity bits 338A). For example, during a read operation or during a masked write operation, the ECC syndrome decoder 290 may use the generated parity bits 341 and the parity bits 339 stored with the data bits 321 to determine the error information vector 315. The error information vector 315 may have the same dimensions as the number of bits of data (e.g., 128 bits in the example) and may indicate whether a particular bit of the data bits 321 is incorrect. The bit correction block 292 in the ECC memory block 282A may correct the corresponding data bit stored in the latch 312 based on receiving the error bit 314A of the error information vector 315. In some embodiments, the correction in the bit correction block 292 may occur using an inverter. As discussed above, ECC memory blocks 282B may each have a respective bit correction block similar to bit correction block 292, which receives corresponding erroneous bits from error information vector 315.

ECC memory block 284A may also include a 3-input multiplexer 316 that may configure ECC operations based on control instruction (R/W/M _ sel) 318. When write mode W (e.g., input W) is selected, multiplexer 316 may provide the signal from latch 322 as data bit 320A, latch 322 may be clocked by toggle signal (MWRW _ clk1) 313. The latch 322 may store the data bit 323 received from the RW bus 242. When correction bit mode M is selected, multiplexer 316 may provide the correction data bits from bit correction block 292 as data bits 320A. The correction of the bits is performed as described above. Correction of the data bit may be performed based on triggering latch 312 by trigger signal (MWRR _ clk1) 311.

When read mode R is selected in multiplexer 316, the output bit from bank select multiplexer 304 is provided as data bit 320A. The bank select multiplexer 304 may be configured by a bank select command (BK _ sel) 308. The bank select multiplexer 304 may be used to receive the bit 306A from the data line 272A via the buffer 302A or the bit 306B from the data line 276A via the buffer 302A. The output data bits 320A of the multiplexer 316 may be provided to the ECC decoder 288 during a read operation to identify errors, the output data bits 320A of the multiplexer 316 may be provided to the ECC decoder 288 during a write operation to generate parity bits, and/or the output data bits 320A of the multiplexer 316 may be provided to the ECC decoder 288 during a masked write operation to identify errors in the old data and generate parity bits associated with the new data, as discussed above. The output data bit 320A of the multiplexer 316 may also be provided to a latch 324, the latch 324 being clocked by the toggle signal (MWRW _ clk2) 317. The output 397 of latch 324 may be coupled to latch 326A, latch 326A providing data to memory block 112A via buffer 302B. The output 397 of latch 324 may also be coupled to a latch 326B, latch 326B providing data to memory block 114A via buffer 302B. Latches 326A and 326B may be controlled by a trigger signal (CWCCLK + BK _ sel)309, which trigger signal 309 may be gated by a bank select command 308 to select a data bank that receives data generated by ECC memory block 248A.

In some scenarios (e.g., during read and/or mask write operations), the ECC parity block 286A may receive parity bits from the memory blocks 112A and 114A via the buffer 332A. A bank select multiplexer 334, controllable by the bank select command 308, may be used to select the data applied to and stored in the latch 336. Latch 336 may be clocked by trigger signal 311, and trigger signal 311 may also clock latch 312, as described above. The parity bits 338A provided by the latches 336 may be provided to an ECC syndrome decoder 290 to identify errors in the read data, as described above. Parity bit 340A generated by ECC decoder 288 may be stored in latch 346, latch 346 may be clocked by trigger signal (CWCCLK) 309. The bank select demultiplexer 342, controlled by the bank select command 308, may determine whether the parity bit 344A should be received by the memory block 112A via the buffer 332B or the parity bit 344B should be received by the memory block 114A via the buffer 332B.

The ECC block 162A may also include circuitry to retrieve and store the data mask 382 from the DM bus 244. To this end, a data mask latch 386, which may be clocked by a toggle signal (MWRW _ clk1)313 that also toggles latch 322, may be used to store the data mask 382 and provide a latched data mask signal (LDM)390 to indicate that the data mask 382 is ready for masked write operations. In some embodiments, the multiplexer 316 in the ECC memory block 248A may also be used to perform the data masking step of the masked-write operation. Because multiplexer 316 may receive new data through its W input and old data through its M input, data masking may be performed by adjusting control instructions 318. For example, when masking should be performed, multiplexer 316 may select the old data from the M input, and when masking should not be performed, multiplexer 316 may select the new data through its W input. To this end, the ECC logic may generate the control instructions 318 based on the received data mask 382, which may be locked in the data mask latch 386.

FIG. 4B illustrates a schematic block diagram 400 including the DRAM array 110 and the RW bus 242 and the DM bus 244 (as illustrated in FIG. 4A). It should be noted that in FIG. 4B, data lines 272A and 272B of FIG. 4A are indicated as data line 404A, data lines 276A and 276B are indicated as data line 404B, parity lines 274A and 274B are indicated as parity line 406A, and parity lines 278A and 278B are indicated as parity line 406B. Further, ECC parity blocks 286A and 286B are referred to herein as ECC parity block 414, and ECC memory blocks 284A and 284B are referred to herein as ECC memory block 416. Block diagram 400 also illustrates ECC control logic 216. ECC control logic 216 may provide block select command 308, control instructions 318, and trigger signals 309, 311, 313, and 370, indicated in fig. 4A. The ECC control logic 216 may generate signals based on the ECC command signal (ECC _ CMD)214, the start signals (MWRW _ clk0 and MWRR _ clk0)232 and 324, and the latched data mask signal (LDM) 390. In fig. 4A and 4B, a shared ECC block may serve two memory blocks in different data banks. It should be noted that the block select command 308 may be used to select which memory block should be coupled to the shared ECC block associated with the ECC operation.

In view of the above, fig. 5, 6, and 7 illustrate methods of a memory device performing ECC operations during memory operations using shared ECC blocks, such as the shared ECC blocks illustrated above. Fig. 5 illustrates a method 420 of reading data using the shared ECC block described above. For clarity, the description of a particular process includes reference to the circuits in fig. 4A and 4B as examples. It should be noted that the method 420 may be used with any memory device that may employ shared ECC circuitry, such as the shared ECC circuitry described above. In process block 422, the memory device may receive command and address instructions containing a read operation command and address. Based on the read operation, the memory device can access the appropriate memory cells by activating the row and column of the memory block associated with the request address.

In response to this activation, the activated memory block (e.g., memory block 112A and/or 114A) may provide read data to the shared ECC block (e.g., ECC block 162A) during process block 424. This may be performed by using data lines, such as data lines 404A and/or 404B. In process block 426, the activated memory block may also provide parity bits associated with storing data to the corresponding shared ECC block. This may be performed by using parity lines, such as parity lines 406A and/or 406B.

In process block 428, the memory device may provide a command to the ECC block for selecting a data bank that provides data. This operation may be performed using, for example, bank select command 308. In process block 430, verification and correction of the data in the ECC block (e.g., ECC block 162A) may be performed based on a comparison between retrieving the parity bits and calculating the parity bits, as discussed above. The process blocks 424, 426, and 428 may be performed in parallel or in any other order, and the trigger signals discussed above may be used to adjust the scheduling of the process. Process block 430 may occur after process blocks 426 and 428.

When two banks coupled to an ECC block have requested data (e.g., two memory blocks 112A and 114A provide data to ECC block 162A), the bank select command 308 in process block 428 may be used with a trigger signal and a latch to service the two data in sequence. For example, process blocks 424, 426, and 428 may be performed to service memory block 112A, and process blocks 424, 426, and 428 may be performed sequentially to service memory block 114A, while process block 430 is performed to service memory block 112A. This type of pipelining may be used to reduce latency of memory operations during active sharing of ECC blocks. At the end of process block 430, the read data is ready to be provided to the I/O interface (e.g., via RW bus 242) in process block 432, which may return the data to the requesting processing circuitry.

Fig. 6 illustrates a method 440 of writing data using the shared ECC block described above. The description of some processes may refer to the elements of fig. 4A and 4B as examples. It should be noted that the method 440 may be used with any memory device that may employ shared ECC circuitry. In process block 442, the memory device may receive command and address instructions containing a write operation command and address. In process block 444, I/O circuitry of the memory device, such as I/O circuitry 246, may receive incoming data, which may be transferred to the data bank via, for example, the RW bus 242. The data bank receiving the data may be determined based on the request address. ECC blocks associated with the data banks and/or blocks may receive write data. For example, the ECC block 162A may receive data directed to the memory blocks 112A and/or 114A.

As discussed above, the parity bits may be calculated in process block 446 using the ECC block. For example, the ECC block 162A may calculate parity bits 341 from incoming data (e.g., data bits 323). After the parity bits are computed, the received data and the computed parity bits may be directed to the appropriate memory block in process block 448. The selection of the memory block may be performed using a bank select command, such as bank select command 308. For example, ECC block 162A may use latch 326A or 326B and bank select command 308 to direct the reception of data, and may use latch 346 and bank select demultiplexer 342 and bank select command 308 to direct the calculation of parity bits. The transfer of the received data may be performed in process block 450 using data lines, such as data lines 404A and/or 404B, and the transfer of the parity bits may be performed in process block 452 by using parity lines, such as parity lines 406A and/or 406B.

The process blocks 448, 450, and 452 may be performed in parallel or in any other order, and the trigger signals discussed above may be used to adjust the scheduling of the process. When two banks coupled to an ECC block have addresses for writing data (e.g., the two memory blocks 112A and 114A are to receive data from the ECC block 162A), the two memory blocks may be serviced sequentially using the bank select command 308 in process block 448 and the trigger signals and latches in process blocks 444, 446, 448, 450, and 452. For example, process blocks 444, 446, and 448 may be performed to service memory block 112A, and process blocks 444, 446, and 448 may be performed sequentially to service memory block 114A while process blocks 450 and 452 are performed to service memory block 112A. This type of pipelining may be used to reduce latency of memory operations during active sharing of ECC blocks. At the end of process blocks 450 and/or 452, the data may be stored in a data bank.

FIG. 7 illustrates a method 460 of performing a masked-write operation using the shared ECC block described above. Some process descriptions refer to fig. 4A and 4B. It should be noted that method 460 may be used with any memory device that may employ shared ECC circuitry. In process block 462, the memory device may receive a command and address instruction containing a masked write operation command and address. In process block 464, I/O circuitry of the memory device (e.g., I/O circuitry 246) may receive incoming data, which may be transferred to the data bank via, for example, the RW bus 242. In process block 466, I/O circuitry of the memory device (e.g., I/O circuitry 246) may receive the data mask 382 via, for example, the DM bus 244.

The masked write data operation may also cause the memory device to access the appropriate memory cells by activating the row and column of the memory block associated with the request address. In response to this activation, the activated memory block (e.g., memory block 112A and/or 114A) may provide storage data to the shared ECC block (e.g., ECC block 162A) in process block 468. This may be performed by using data lines, such as data lines 404A and/or 404B in fig. 4A. The activated memory block may also provide parity bits associated with storing data to the corresponding shared ECC block in process block 470. This may be performed by using parity lines, such as parity lines 406A and/or 406B. The memory device may also provide commands for selecting a data bank (e.g., bank select command 308) to the ECC block. Verification and correction of the read data in the ECC block (e.g., ECC block 162A) may be performed in process block 472 based on a comparison between the retrieved parity bits and the calculated parity bits, as discussed above.

In process block 474, new mask data may be generated. This process may be performed based on the correction data generated in process block 472, the received data received in process block 464, and the received data mask 382 received in process block 466. The new masking of data may be performed by selectively changing bytes of correction data using the received data mask 382 as a guide. The generated new mask data may then be stored in a data bank. As discussed above, the ECC block may be used to calculate parity bits associated with the newly masked data. For example, ECC block 162A may calculate parity bits 341 from the received data (e.g., data bits 321).

After the parity bits are computed, the received data and the computed parity bits may be directed to the appropriate memory block. The transfer of new mask data may be performed in process block 476 using data lines, such as data lines 404A and/or 404B in fig. 4A, and the transfer of parity bits may be performed in process block 478 by using parity lines, such as parity lines 406A and/or 406B. The process blocks of method 460 may be performed in parallel or in any other order, and the trigger signals discussed above may be used to adjust the scheduling of the process. At the end of process blocks 476 and/or 478, the mask data may be stored in a data bank.

When two banks of a shared ECC block are involved in a masked-write operation (e.g., the two memory blocks 112A and 114A perform a masked-write operation using the shared ECC block 162A), pipelining may be used to facilitate sharing. An example of this is illustrated in timing diagram 800 of FIG. 8. The timing diagram 800 may include a command diagram 802, an ECC sequence diagram 804 associated with a first mask write command, and an ECC sequence diagram 806 associated with a second mask write command. The command map 802 includes a first masked-write command 808 that may result in a series of masked-write ECC operations 810. The command map 802 includes a second masked-write command 812 that may result in a series of masked-write ECC operations 814.

Masked write commands 808 and 812 may be associated with different data stores (e.g., addresses associated with different data stores) and may be separated by a delay 816. As discussed above, the minimum latency of operations occurring in different data banks may be relatively less than the latency of operations occurring in a common data bank. This may be related to the time to perform the masked-write ECC operations 810 and 814. Thus, overlapping period 818 may occur. If the masked-write ECC operations 810 and 814 are performed using different ECC blocks, the overlap period 818 does not necessarily interfere with the operations. However, if the shared ECC block serves two different data banks (e.g., data banks 0 and 1 in this example), the overlap period 818 may result in congestion of the shared ECC block. To prevent such congestion, a pipeline operation strategy may be used, such as the pipeline operation strategy that will be described in detail in fig. 9-16 below.

In view of the above, the timing diagram 820 of FIG. 9 illustrates the trigger signals and data flow associated with the above-described pipeline operation. The timing diagram 820 includes a command diagram 802, a clock diagram 822, a data diagram 824, a data mask diagram 826, an ECC I/O diagram 828 associated with a first data bank, an ECC I/O diagram 830 associated with a second data bank, start signal diagrams 832 and 834, ECC signal diagrams 836 and 838, and an ECC sequence diagram 840. The following description refers to tCCD periods 842 (i.e., inter-column periods, which may be the minimum delay period between two masked write commands to different banks) and tCK periods 844 (which may be the periods of the clock signal). Timing diagram 820 also includes references to write latency, represented by WL, and burst length, represented by BL.

In timing diagram 820, the command and address signals 210 may include a first masked write command 846 that may be directed to data bank 0, as illustrated in command diagram 802. After a write latency associated with the first masked-write command, the processor may provide new data 862 and data mask 864 associated with the first masked-write command 846, as represented in data map 824 and data mask 826. After the tCCD period 842 after the first masked write command 846, the command and address signals 210 may receive a second masked write command 852 that may be directed to data bank 1. After a write latency associated with the second masked-write command equal to the period 850(WL + BL), the processor may provide new data 884 and a data mask 886 associated with the second masked-write command 852, as represented in data map 824 and data mask 826.

As timed by the first masked write command 846 (dashed arrow 858), data bank 0 may provide the old data and corresponding parity bits from the requested address to the ECC block via data lines 404A and parity lines 406A (operation 860). The write latency counter 224 illustrated in fig. 3 may use the start signal 232 to provide the start pulse 868. As illustrated, the start pulse 868 may be provided within (WL + BL-1/2 × tCCD) period 848 from the issuance of the first mask write command 846. 1/2 tCCD corresponds to 4 tCK (or 4 cycles of the clock signal CLK). In response, the ECC control logic 216 may provide a pulse 870 via the trigger signal 311, the pulse 870 may cause an ECC operation 872 related to the old data (e.g., verify and correct the old data). For example, pulse 870 may trigger latches 312 and 336 illustrated in FIG. 4A.

After half of the tCCD period 842, the write latency counter 224 may use the start signal 234 to provide a start pulse 874. That is, the start pulse 874 may be provided within the (WL + BL) period 850 from the issuance of the first mask write command 846. In response, the ECC control logic 216 may provide a pulse 876 via the trigger signal 313 that may result in an ECC operation 878 related to the masked data (e.g., generating parity bits for the newly masked data). For example, pulse 876 may trigger latches 322 and 386 illustrated in FIG. 4A. The ECC operations 872 and 878 may each occupy up to half of the tCCD period 843 to result in a total time of 1 tCCD period 842. Following ECC operation 878, data line 404A may be used to provide data back to data bank 0 during operation 866 represented in ECC I/O map 828.

As timed by the second masked write command 852 (dashed arrow 880), data bank 1 may provide the old data and corresponding parity bits from the request address to the ECC block via the data lines 404B and parity lines 406B (operation 882). It should be noted that operations 860 and 882 may have some timing overlap. The ECC block may use bank select multiplexers 304 and 334 controlled by bank select command 308 to prevent data collisions. The write latency counter 224 illustrated in fig. 3 may use the start signal 232 to provide a start pulse 890. As illustrated, the start pulse 890 may be provided within (WL + BL-1/2 tCCD period 854 from the issuance of the second mask write command 852 in response, ECC control logic 216 may provide a pulse 892 via trigger signal 311 that may cause ECC operation 894 related to the old data (e.g., verify and correct the old data). for example, pulse 892 may trigger latches 312 and 336 illustrated in FIG. 4A.

After half of tCCD period 842, write delay counter 224 may use start signal 234 to provide start pulse 896. That is, the start pulse 896 may be provided within a (WL + BL) period 856 from the issuance of the second mask write command 852. In response, the ECC control logic 216 may provide a pulse 898 via the trigger signal 313 that may cause the ECC operation 900 associated with the masked data (e.g., generate the parity bits of the newly masked data). For example, pulse 898 may trigger latches 322 and 386 illustrated in FIG. 4A. ECC operations 894 and 900 may each occupy up to half a tCCD period 843 to result in a total time of 1 tCCD period 842. Following the ECC operation 900, the data line 404B may be used to provide data back to data bank 1 during operation 888, represented in the ECC I/O map 830. It should be noted that operations 866 and 888 may have some timing overlap. The ECC block may use the bank select command 308 and latches 326A and 326B and bank select demultiplexer 342 to prevent mask data misleading.

The data operation of an ECC block in response to the above commands during a sequence of masked write operations is detailed in fig. 10, 11, 12, 13, 14, 15 and 16, which include schematic data flow and timing diagrams. Fig. 10 includes an illustrative data flow diagram 910 and timing diagram 914. As illustrated, the trigger signal 311 generated in response to the start signal 232 may cause the ECC memory block 414 and the ECC parity block 416 to latch the old data and parity bits, respectively. The old data and parity bits are associated with bank 0 and latching may be performed using latches 312 and 336, bank select multiplexers 304 and 334 controlled by bank select command 308. Further, the multiplexer 316 coordinating the data transferred to the ECC decoder 288 may be adjusted by setting the control instructions 318 to a read mode R (e.g., input R) that provides the data from the data lines 404A as data bits 321 to the ECC decoder 288.

Fig. 11 includes an illustrative data flow diagram 920 and a timing diagram 924. As illustrated, ECC decoder 288 may generate parity bits 341. ECC syndrome decoder 290 may receive generated parity bits 341 and retrieved parity bits 339. Fig. 12 includes an illustrative data flow diagram 930 and a timing diagram 934. As illustrated, the ECC syndrome decoder 290 may generate an error information vector 315. The error information vector 315 may indicate whether the bits have errors and may be used to cause the bit correction block 292 of the ECC memory block 414 to generate corrected old data. The multiplexer 316 may receive corrected old data from the bit correction block 292 by setting the control instructions 318 to the correction bit pattern M (e.g., input M).

Fig. 13 includes an illustrative data flow diagram 940 and timing diagram 944. As illustrated, the trigger signal 313 generated in response to the start signal 234 may cause the latch 322 to latch incoming data (e.g., the data bit 323) and cause the data mask latch 386 to latch the data mask 382. The incoming data may be selected by the multiplexer 316 setting the control instructions 318 to the write mode W. In some embodiments, the control instructions 318 may be adjusted based on the data mask 382. For example, when the mask bits of the data mask 382 specify "no mask" (i.e., the incoming data should replace the corrected old data), the multiplexer 316 may be adjusted by setting the control instruction 318 to the write mode W. When the mask bits of the data mask 382 specify "mask" (i.e., the corrected old data should be retained), the multiplexer 316 may be adjusted by setting the control instructions 318 to the correction bit pattern M. Thus, ECC memory block 414 provides the new mask data as data bits 321 to ECC decoder 288. The new mask data may also be stored by the latch 324 in response to the trigger signal 317. The output 397 of latch 324 may be provided to the data store for storage.

Fig. 14 includes a dataflow diagram 946 and a timing diagram 948. In this figure, ECC decoder 288 generates parity bits 341 from the newly masked data provided via data bits 321. Parity bits may be provided to the ECC parity block 416. Fig. 15 illustrates an embodiment including a dataflow diagram 950 and a timing diagram 952. In this figure, the assertable trigger signal 309 triggers the latch 326A to store the output 397 of the latch 324 containing the new mask data. Data lines 404A and parity lines 406A may be used to transfer the newly masked new data and its parity information to data bank 0. Fig. 16 illustrates a data flow diagram 960 and a timing diagram 962. In this figure, the bank select command 308 may be adjusted to configure the process to operate data bank 1. The process described above for data bank 0 in fig. 10-16 may be performed using data bank 1.

While the embodiments set forth in this disclosure are susceptible to various modifications and alternative forms, specific embodiments have been shown by way of example in the drawings and have been described in detail herein. It should be understood, however, that the invention is not intended to be limited to the particular forms disclosed. The intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims.