阅读说明：本技术 混合信号电路的数字化建模方法和装置 (Digital modeling method and device for mixed signal circuit ) 是由 叶佐昌 王燕 冷洋洋 于 2021-03-05 设计创作，主要内容包括：本申请提出一种混合信号电路的数字化建模方法和装置。其中,方法包括：获取电路的网表文件,文件用于描述需要仿真的电路的拓扑结构、外部激励信号以及仿真参数；为电路的网表文件生成激励信号,并基于激励信号对网表文件进行仿真,将所有激励产生的数据进行组合,得到关于电路的全覆盖输入输出数据和电路的输入输出的完备关系；根据电路系统的特点,采用动态模态分解的方法从全覆盖输入输出数据中提取电路特征；根据提取得到的电路特征和电路的输入输出的完备关系,基于机器学习方法构建电路的数字化模型；通过硬件描述语言将数学模型转换为Verilog/Verilog-AMS电路模型,该电路模型能够通用于其他的数字电路。(The application provides a digital modeling method and device of a mixed signal circuit. The method comprises the following steps: obtaining a netlist file of the circuit, wherein the file is used for describing a topological structure, an external excitation signal and simulation parameters of the circuit to be simulated; generating an excitation signal for a netlist file of the circuit, simulating the netlist file based on the excitation signal, and combining data generated by excitation to obtain a complete relation between full-coverage input and output data of the circuit and input and output of the circuit; according to the characteristics of a circuit system, extracting circuit characteristics from full-coverage input and output data by adopting a dynamic modal decomposition method; according to the extracted circuit characteristics and the complete relation between the input and the output of the circuit, a digital model of the circuit is constructed based on a machine learning method; the mathematical model is converted into a Verilog/Verilog-AMS circuit model through a hardware description language, and the circuit model can be universally used for other digital circuits.)

1. A method for digitally modeling a mixed-signal circuit, comprising:

obtaining a netlist file of a circuit, wherein the file is used for describing a topological structure, an external excitation signal and simulation parameters of the circuit to be simulated;

generating an excitation signal for a netlist file of the circuit, simulating the netlist file based on the excitation signal, and combining data generated by all excitation to obtain a complete relation between full-coverage input and output data of the circuit and input and output of the circuit;

according to the characteristics of a circuit system, extracting circuit characteristics from the full-coverage input and output data by adopting a dynamic modal decomposition method;

according to the extracted complete relation between the circuit characteristics and the input and output of the circuit, a digital model of the circuit is constructed based on a machine learning method;

and converting the digital model of the circuit into a Verilog description language to obtain a corresponding digital circuit model.

2. The method of claim 1, wherein constructing the digitized model of the circuit based on a machine learning method according to the extracted complete relationship between the circuit features and the input and output of the circuit comprises:

and taking the extracted circuit characteristics as input, taking the complete relation of input and output of the circuit as output, and constructing a digital model of the circuit by using a machine learning method.

3. The method of claim 1 or 2, wherein the machine learning method comprises: any one of a decision tree method, a random forest method, and an artificial neural network method.

4. An apparatus for digitally modeling mixed-signal circuits, comprising:

the simulation system comprises a first acquisition module, a second acquisition module and a simulation module, wherein the first acquisition module is used for acquiring a netlist file of a circuit, and the file is used for describing a topological structure, an external excitation signal and simulation parameters of the circuit to be simulated;

the second acquisition module is used for generating an excitation signal for the netlist file of the circuit, simulating the netlist file based on the excitation signal, and combining data generated by excitation to obtain a complete relation between full-coverage input and output data of the circuit and input and output of the circuit;

the extraction module is used for extracting circuit characteristics from the full-coverage input and output data by adopting a dynamic modal decomposition method according to the characteristics of a circuit system;

the modeling module is used for constructing a digital model of the circuit based on a machine learning method according to the extracted complete relation between the circuit characteristics and the input and output of the circuit;

and the conversion module is used for converting the digital model of the circuit into a Verilog description language to obtain a corresponding digital circuit model.

5. The apparatus of claim 4, wherein the modeling module is specifically configured to:

and taking the extracted circuit characteristics as input, taking the complete relation of input and output of the circuit as output, and constructing a digital model of the circuit by using a machine learning method.

6. The apparatus of claim 4 or 5, wherein the machine learning method comprises: any one of a decision tree method, a random forest method, and an artificial neural network method.

Technical Field

The application belongs to the technical field of integrated circuit design, and particularly relates to a digital modeling method and device for a mixed signal circuit.

Background

Electronic Design Automation (EDA) is a method for analyzing and predicting the performance of an integrated circuit at the design stage by using software as a carrier. The simulators aiming at circuit simulation are HSPICE, Spectre, Verilog-AMS, Verilog and the like, wherein the HSPICE simulator needs to solve a circuit equation of a circuit node, and the required simulation quantity is exponentially increased along with the number of the circuit nodes. Analog Mixed Signal (AMS) simulators are based on the parallel operation of a spice-type simulator and an event-driven simulator, which interact only at the analog-to-digital signal boundaries of the circuit and perform well when most systems are described in the Hardware Description Language (HDL), but if the model cannot be abstracted to a level where an analog solver is no longer needed, the model still exhibits all of the limitations of an analog solver when simulating complex circuits. A pure event-driven simulator does not need to solve a circuit equation, overcomes the limit caused by the inherent slow speed of an analog solver, and is an optimal tool for realizing a fast strategy.

With the progress and development of integrated circuit technology, mixed signal systems are widely used. In chip design, a large number of test vectors are usually required for full-chip functional verification simulation, however, the simulation speed of the HSPICE transistor-level analog circuit is slow, and a large amount of overhead is required in circuit verification. In order to shorten the period of the whole chip design and shorten the time to market, the verification time, i.e. the simulation time of the circuit, needs to be shortened. The simulation time can be shortened to the maximum extent by converting the mixed signal circuit into a digital circuit. Therefore, how to convert the mixed signal circuit into a digital circuit has become an urgent problem to be solved.

Disclosure of Invention

The present application is directed to solving, at least to some extent, one of the technical problems in the related art.

Therefore, a first objective of the present application is to provide a digital modeling method for a mixed signal circuit, which converts the mixed signal circuit into a digital circuit and converts mixed signal simulation into pure digital simulation, thereby shortening the time of circuit verification process and shortening the time of circuit product on the market.

A second object of the present application is to provide a digital modeling apparatus for mixed signal circuits.

In order to achieve the above object, an embodiment of the first aspect of the present application provides a method for digitally modeling a mixed-signal circuit, including:

obtaining a netlist file of a circuit, wherein the file is used for describing a topological structure, an external excitation signal and simulation parameters of the circuit to be simulated;

generating an excitation signal for a netlist file of the circuit, simulating the netlist file based on the excitation signal, and combining data generated by all excitation to obtain a complete relation between full-coverage input and output data of the circuit and input and output of the circuit;

according to the characteristics of a circuit system, extracting circuit characteristics from the full-coverage input and output data by adopting a dynamic modal decomposition method;

according to the extracted complete relation between the circuit characteristics and the input and output of the circuit, a digital model of the circuit is constructed based on a machine learning method;

and converting the digital model of the circuit into a Verilog description language to obtain a corresponding digital circuit model.

In order to achieve the above object, a second embodiment of the present application provides a digital modeling apparatus for a mixed signal circuit, including:

the simulation system comprises a first acquisition module, a second acquisition module and a simulation module, wherein the first acquisition module is used for acquiring a netlist file of a circuit, and the file is used for describing a topological structure, an external excitation signal and simulation parameters of the circuit to be simulated;

the second acquisition module is used for generating an excitation signal for the netlist file of the circuit, simulating the netlist file based on the excitation signal, and combining data generated by excitation to obtain a complete relation between full-coverage input and output data of the circuit and input and output of the circuit;

the extraction module is used for extracting circuit characteristics from the full-coverage input and output data by adopting a dynamic modal decomposition method according to the characteristics of a circuit system;

the modeling module is used for constructing a digital model of the circuit based on a machine learning method according to the extracted complete relation between the circuit characteristics and the input and output of the circuit;

and the conversion module is used for converting the digital model of the circuit into a Verilog description language to obtain a corresponding digital circuit model.

According to the technical scheme of the embodiment of the application, a netlist file of a circuit is given, full-coverage input is given according to specific circuit requirements, a circuit simulation file is obtained by combining the netlist file, the file comprises a circuit topological structure, an excitation signal and simulation parameters, and a HSPICE simulator is used for simulation to obtain data of each node of the circuit; obtaining an input and output data set by combining an input data track and an output data track from simulation data by using a dynamic modal decomposition method; utilizing a machine learning method to deal with the nonlinearity of the circuit to obtain the relation of circuit input and output, namely obtaining the system; the system is converted into a digital circuit by using a Verilog description language, and the conversion of a hybrid circuit into a pure digital circuit is realized. Therefore, the method and the device can realize the automation of converting the digital-analog hybrid circuit into the digital circuit, and can improve the digitization efficiency, thereby greatly shortening the simulation time in the chip testing process and accelerating the marketing speed of chip products.

Additional aspects and advantages of the present application will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the present application.

Drawings

The foregoing and/or additional aspects and advantages of the present application will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:

fig. 1 is a schematic flowchart of a digital modeling method for a mixed signal circuit according to an embodiment of the present disclosure;

FIG. 2 is an exemplary diagram of an analog-to-digital converter topology according to an embodiment of the present application;

FIG. 3 is an exemplary diagram of a process for constructing a qualified new data set from an original data set according to an embodiment of the present application;

FIG. 4 is an exemplary diagram of a Verilog behavioral model circuit file generated for an XOR circuit according to an embodiment of the present application;

FIG. 5(a) is a diagram illustrating a comparison between an overall modeling result and an actual result of a Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC);

FIG. 5(b) is a graph comparing the modeled results of some of the sub-modules with the actual results;

FIG. 5(c) is a graph comparing the results of a larger circuit formed by the connections of sub-module digital circuits generated by modeling with actual results;

fig. 6 is a block diagram of a digital modeling apparatus for a mixed signal circuit according to an embodiment of the present disclosure.

Detailed Description

Reference will now be made in detail to embodiments of the present application, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the drawings are exemplary and intended to be used for explaining the present application and should not be construed as limiting the present application.

The following describes a method and apparatus for digital modeling of a mixed-signal circuit according to an embodiment of the present application with reference to the drawings.

Fig. 1 is a schematic flowchart of a digital modeling method for a mixed signal circuit according to an embodiment of the present disclosure. It should be noted that the digital modeling method of the mixed signal circuit according to the embodiment of the present application is applicable to the digital modeling apparatus of the mixed signal circuit according to the embodiment of the present application. As shown in fig. 1, the digital modeling method of the mixed signal circuit of the embodiment of the present application may include the following steps.

In step 101, a netlist file of a circuit is obtained, and the file is used for describing a topology structure, an external excitation signal and simulation parameters of the circuit to be simulated.

In step 102, an excitation signal is generated for the netlist file of the circuit, the netlist file is simulated based on the excitation signal, and all data generated by excitation are combined to obtain a complete relationship between full-coverage input and output data of the circuit and input and output of the circuit.

In step 103, according to the characteristics of the circuit system, a dynamic modal decomposition method is used to extract circuit characteristics from the full coverage input/output data.

In step 104, a digitized model of the circuit is constructed based on a machine learning method according to the extracted circuit characteristics and the complete relationship between the input and the output of the circuit.

Optionally, in this embodiment of the present application, the digital model of the circuit may be constructed by using the extracted circuit features as inputs, using the complete relationship between the inputs and the outputs of the circuit as outputs, and using a machine learning method.

In step 105, the digitized model of the circuit is converted to a Verilog/Verilog-AMS circuit model via a hardware description language.

For example, a netlist file of a circuit may be given, which is used to describe the topology, external stimulus signals and simulation parameters of the circuit to be simulated (usually, such a file is in the form of a circuit netlist, but is not limited to this form); the topological structure of the circuit is the circuit to be analyzed, the external excitation signal is an excitation waveform for simulating the response of the circuit under a specific input, and the simulation parameters are parameters in calculation, such as initial time, termination time, simulation precision and the like. This document describes information about the topology, power supply and external excitation signals and simulation parameters of an example analog-to-digital converter circuit. As shown in fig. 2, which is an exemplary diagram of the topology of an analog-to-digital converter, the diagram describes a successive approximation register analog-to-digital converter, SAR adc is a very typical digital-to-analog hybrid circuit, and SAR adc circuit is mainly composed of three parts, DAC, comparator and SAR logic.

In the present application, when obtaining a netlist file of a circuit, an excitation signal can be generated for the netlist of the circuit, the excitation signal being fully-coveredThe circuit netlist file of the given excitation is simulated, and data generated by all the excitations are combined to obtain full-coverage input and output data of the circuit, so that the complete relation of the input and the output of the circuit is obtained. For example, as shown in FIG. 3, a satisfactory data set X, Y is extracted from the original data set using a dynamic modal decomposition method according to specific data of the circuit, and the current output y is calculated_tCorresponding input [ x ]_t-k,x_t-k+1,…,x_t-1,x_t,y_t-k,y_t-k+1,…,y_t-1]I.e. the output of the present circuit is related to the input of the present circuit and the input-output of the previous circuit.

It should be noted that Dynamic Mode Decomposition (DMD) is originally a data-driven unsteady flow field modal analysis method for reconstructing or predicting flow field dynamics, and is currently applied to various fields except fluid dynamics. The circuitry comprises an input data stream and an output data stream, which is clearly a field to which the method can be applied. The premise of dynamic modal decomposition is that linear systems, if the system is nonlinear, it is necessary to construct a sufficiently rich set of mappings, such as kernel and polynomial methods, to ensure that the current system satisfies the basic assumptions of the dynamic modal decomposition method. The selection of the mapping method is to select a proper function dictionary or kernel function according to the prior knowledge of the system and the dynamic characteristics of the target. The multi-layer perceptron and the cost function can be used, so that the manual selection of a mapping method can be avoided, and manual operation is reduced. In the embodiment of the application, various methods of machine learning including a multilayer perceptron can be selected, the method mainly comprises decision trees, random forests, artificial neural networks, Bayesian learning research and the like, and different methods can be adopted for regression modeling of different circuits. The regression method is based on simulation data, each input data set and corresponding output are combined into a training data set, then the training data set is used as input of the modeling method, and a circuit input and output model is obtained according to the training data set. The goal of this application is to create an accurate model that can quickly estimate the output of any given new input.

That is, the relationship between the input and output of the circuit can be learned by a method of machine learning. The inputs and outputs of the digital circuit can be represented by truth tables, and the logical relationship of the inputs and outputs thereof is very consistent with the decision tree method, so that the digital circuit selects the decision tree method. The input-output relationship of the analog circuit is generally simple linear and nonlinear, a linear model can generally meet the fitting requirement, and a more complex circuit can also use methods such as a neural network and the like. When the machine learning model is obtained, the machine learning model can be converted into a hardware description language Verilog behavioral model, that is, the digitized model of the circuit can be converted into a Verilog/Verilog-AMS circuit model through the hardware description language, the circuit model can be commonly used for other digital circuits, as shown in fig. 4, the circuit model is an exemplary diagram of a Verilog behavioral model circuit file generated for an exclusive or circuit, so as to ensure that the model can be commonly used in the circuit, and the obtained Verilog model can be tested in a test bench or can be used as a submodule to form a new and more complex circuit with other submodules.

In the embodiment of the present application, when the digital model circuit of the mixed signal circuit is obtained, the whole sar adc circuit and its sub-circuits are tested, as shown in fig. 5(a), the digital modeling result of the whole sar adc circuit is shown, as shown in fig. 5(b), the digital modeling result of the SC _ GEN module in sar adc is shown, as shown in fig. 5(c), the result after the generated digital sub-modules are connected is shown, and the model circuit result is substantially consistent with the actual result as can be seen from fig. 5(a) -5 (c), which indicates that the digital model circuit obtained by the present application can better simulate the function of the actual circuit.

In summary, the embodiment of the present application is characterized in that the automation of the digital modeling is realized, and only the netlist file of the target circuit needs to be known, the corresponding digital circuit under a certain parameter setting can be obtained, and the digital circuit can better realize the function of the target circuit without deep circuit knowledge. The method has the advantages that the simulation speed of the circuit can be greatly improved by digitalizing the digital-analog hybrid circuit, the digitalization efficiency can be improved by an automatic digital modeling method, the modeling method is universal, and a digital circuit model can be automatically obtained by only modifying parameters for different circuits.

In order to realize the embodiment, the application also provides a digital modeling device of the mixed signal circuit.

Fig. 6 is a block diagram of a digital modeling apparatus for a mixed signal circuit according to an embodiment of the present disclosure. As shown in fig. 6, the digital modeling apparatus 600 of the mixed signal circuit may include: a first obtaining module 601, a second obtaining module 602, an extracting module 603, a modeling module 604, and a converting module 605.

Specifically, the first obtaining module 601 is configured to obtain a netlist file of a circuit, where the netlist file is used to describe a topology structure, an external excitation signal, and simulation parameters of the circuit to be simulated.

The second obtaining module 602 is configured to generate an excitation signal for the netlist file of the circuit, simulate the netlist file based on the excitation signal, and combine data generated by all excitations to obtain a complete relationship between full-coverage input and output data of the circuit and input and output of the circuit.

The extracting module 603 is configured to extract circuit features from the full-coverage input/output data by using a dynamic modal decomposition method according to characteristics of the circuit system.

The modeling module 604 is configured to construct a digital model of the circuit based on a machine learning method according to the extracted circuit characteristics and the complete relationship between the input and the output of the circuit. Optionally, the modeling module 604 takes the extracted circuit features as input, takes the complete relationship between the input and the output of the circuit as output, and constructs a digital model of the circuit by using a machine learning method. As one example, a machine learning method may include, but is not limited to: a decision tree method, a random forest method, an artificial neural network method, and the like.

The conversion module 605 is configured to convert the digitized model of the circuit into Verilog description language, and obtain a corresponding digital circuit model.

According to the digital modeling device of the mixed signal circuit, a netlist file of the circuit is given, full-coverage input is given according to specific circuit requirements, a circuit simulation file is obtained by combining the netlist file, the file comprises a circuit topological structure, an excitation signal and simulation parameters, and simulation is carried out by using an HSPICE simulator to obtain data of each node of the circuit; obtaining an input and output data set by combining an input data track and an output data track from simulation data by using a dynamic modal decomposition method; utilizing a machine learning method to deal with the nonlinearity of the circuit to obtain the relation of circuit input and output, namely obtaining the system; the system is converted into a digital circuit by using a Verilog description language, and the conversion of a hybrid circuit into a pure digital circuit is realized. Therefore, the method and the device can realize the automation of converting the digital-analog hybrid circuit into the digital circuit, and can improve the digitization efficiency, thereby greatly shortening the simulation time in the chip testing process and accelerating the marketing speed of chip products.

In the description herein, reference to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the application. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.

Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present application, "plurality" means at least two, e.g., two, three, etc., unless specifically limited otherwise.

Any process or method descriptions in flow charts or otherwise described herein may be understood as representing modules, segments, or portions of code which include one or more executable instructions for implementing steps of a custom logic function or process, and alternate implementations are included within the scope of the preferred embodiment of the present application in which functions may be executed out of order from that shown or discussed, including substantially concurrently or in reverse order, depending on the functionality involved, as would be understood by those reasonably skilled in the art of the present application.

Although embodiments of the present application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present application, and that variations, modifications, substitutions and alterations may be made to the above embodiments by those of ordinary skill in the art within the scope of the present application.