阅读说明：本技术 用于存储器装置的行锤击保护 (Row hammer protection for memory devices ) 是由 S·E·谢弗 A·P·贝姆 于 2019-08-22 设计创作，主要内容包括：本发明描述用于存储器装置的行锤击保护的方法、系统和装置。存储器装置可识别用于存储器阵列的相关行存取的阈值(例如,对同一行地址或行地址空间的存取命令或激活)。在第一操作模式中,所述存储器装置可在所述存储器阵列上执行从主机装置接收的命令。所述存储器装置可确定所述所接收的行存取命令的度量满足相关行存取的所述阈值。所述存储器装置可基于满足所述阈值,使所述存储器阵列从所述第一操作模式切换到第二操作模式。所述第二操作模式可约束对所述存储器的至少一行的存取,而所述第一模式可具有较低约束性。另外或替代地,所述存储器装置可向所述主机装置通知所述度量已满足所述阈值。(Methods, systems, and devices for row hammer protection of a memory device are described. The memory device may identify a threshold for an associated row access of the memory array (e.g., an access command or activation to the same row address or row address space). In a first mode of operation, the memory device can execute commands received from a host device on the memory array. The memory device can determine that a metric of the received row access command satisfies the threshold of a related row access. The memory device may switch the memory array from the first mode of operation to a second mode of operation based on the threshold being met. The second mode of operation may restrict access to at least one row of the memory, while the first mode may have a lower restriction. Additionally or alternatively, the memory device may notify the host device that the metric has met the threshold.)

1. A method, comprising:

identifying a threshold for a row access of a memory array, the memory array comprising a plurality of rows;

in a first mode of operation, receiving a row access command for the memory array from a host;

determining, for a row of the plurality of rows, that a metric of the row access command satisfies the threshold; and

based at least in part on determining that the metric of the row access command satisfies the threshold, causing the memory array to switch from the first mode of operation to a second mode of operation, wherein the second mode of operation is associated with restricting access to at least one of the plurality of rows of the memory array.

2. The method of claim 1, further comprising:

receiving, from the host operating in the second mode, a command sequence to reset the memory array to the first mode; and

causing the memory array to switch from the second mode to the first mode based at least in part on receiving the command sequence.

3. The method of claim 1, further comprising:

initiating a timer upon switching the memory array from the first mode to the second mode; and

causing the memory array to switch from the second mode to the first mode based at least in part on the timer expiring.

4. The method of claim 1, further comprising:

receiving signaling from the host indicating a second threshold for row access, wherein identifying the threshold is based at least in part on the second threshold.

5. The method of claim 4, wherein identifying the threshold for a row access comprises:

determining the threshold by comparing the second threshold to a third threshold stored in non-volatile memory.

6. The method of claim 1, further comprising:

the second operating mode is selected from a plurality of operating modes according to a configured setting.

7. The method of claim 1, further comprising, when operating the memory array in the second mode:

operating a first bank of the memory array associated with the row in a self-refresh mode; and

a second bank of the memory array is operated in the first mode.

8. The method of claim 1, further comprising, when operating the memory array in the second mode:

a plurality of banks of the memory array are operated in a self-refresh mode.

9. The method of claim 1, further comprising, when operating the memory array in the second mode:

a row access command to a bank of the memory array associated with the row is suppressed.

10. The method of claim 1, further comprising, when operating the memory array in the second mode:

receiving a row access command for a second row of the memory array; and

refraining from accessing the second row of the memory array based at least in part on receiving the row access command for the second row.

11. The method of claim 10, wherein the second row and the row are the same row.

12. A method, comprising:

identifying a threshold for a row access of a memory array, the memory array comprising a plurality of rows;

receiving a plurality of row access commands for the memory array from a host;

determining, for a row of the plurality of rows, that a pattern of the plurality of row access commands satisfies the threshold; and

transmitting an indication to the host based at least in part on determining that the pattern of the plurality of row access commands satisfies the threshold.

13. The method of claim 12, further comprising:

determining the threshold based at least in part on a minimum of a second threshold received from the host and a third threshold stored in non-volatile memory.

14. The method of claim 12, further comprising:

receiving a command sequence from the host indicating a mode of operation based at least in part on transmitting the indication to the host.

15. An apparatus, comprising:

a memory array having a plurality of rows;

a memory interface coupled with the memory array and a host, the memory interface operable to receive row access commands from the host; and

circuitry coupled with the memory array and the memory interface, the circuitry operable to:

identifying a threshold for a row access of the memory array;

in a first mode of operation, executing the row access command on the memory array;

determining, for a row of the plurality of rows, that a metric of the row access command satisfies the threshold; and

based at least in part on determining that the metric of the row access command satisfies the threshold, causing the memory array to switch from the first mode of operation to a second mode of operation, wherein the second mode of operation is associated with restricting access to at least one of the plurality of rows of the memory array.

16. The device of claim 15, the circuitry further operable to:

while operating the memory array in the second mode, receiving a command sequence from the host via the memory interface for resetting the memory array to the first mode; and

causing the memory array to switch to the first mode based at least in part on receiving the command sequence.

17. The device of claim 15, the circuitry further operable to:

initiating a timer upon switching the memory array from the first mode to the second mode; and

causing the memory array to switch from the second mode to the first mode based at least in part on the timer expiring.

18. The device of claim 15, the circuitry further operable to:

identifying the threshold based at least in part on comparing a second threshold received from the host to a third threshold stored in non-volatile memory.

19. The device of claim 15, the circuitry further operable to:

the second operating mode is selected from a plurality of operating modes according to a configured setting.

20. The device of claim 15, the circuitry further operable to, when operating the memory array in the second mode:

operating a first bank of the memory array associated with the row in a self-refresh mode; and

operating a second bank of the memory array in a mode other than the self-refresh mode.

21. The device of claim 15, the circuitry further operable to, when operating the memory array in the second mode:

a plurality of banks of the memory array are operated in a self-refresh mode.

22. The device of claim 15, the circuitry further operable to, when operating the memory array in the second mode:

determining whether to execute the row access command for at least some of a plurality of banks of the memory array.

23. The device of claim 15, the circuitry further operable to, when operating the memory array in the second mode:

receiving a row access command for a second row of the memory array; and

inhibiting access for the second row of the memory array after receiving the row access command.

24. The device of claim 23, wherein the second row and the row are the same row.

25. An apparatus, comprising:

a memory array having a plurality of rows;

a memory interface coupled with the memory array and a host, the memory interface operable to receive row access commands from the host; and

circuitry coupled with the memory array and the memory interface, the circuitry operable to:

identifying a threshold for a row access of the memory array;

executing the row access command on the memory array;

determining, for a row of the plurality of rows, that executing the row access command satisfies the threshold; and

transmitting, via the memory interface, an indication to the host that execution of the row access command satisfies the threshold.

Background

The following generally relates to systems including at least one memory device, and more specifically relates to row hammer protection for a memory device.

Memory devices are widely used to store information in various electronic devices such as computers, wireless communication devices, cameras, digital displays, and the like. Information is stored by programming different states of the memory device. For example, binary devices most often store one of two states, often represented by a logical 1 or a logical 0. In other devices, more than two states may be stored. To access the stored information, components of the device may read or sense at least one stored state in the memory device. To store information, components of the device may write or program states in the memory device.

There are various types of memory devices, including magnetic hard disks, Random Access Memories (RAMs), Read Only Memories (ROMs), dynamic RAMs (drams), static RAMs (srams), synchronous dynamic RAMs (sdrams), ferroelectric RAMs (ferams), magnetic RAMs (mrams), resistive RAMs (rrams), flash memories, Phase Change Memories (PCMs), and the like. The memory device may be volatile or non-volatile. Non-volatile memory, such as FeRAM, can maintain its stored logic state for long periods of time, even if no external power source is present. Volatile memory devices, such as DRAM and SRAM, can lose their stored state over time unless connected to an external power source. Dynamic memory devices, such as DRAMs, may also use periodic refreshing to maintain memory cell states.

In some cases, the memory state of some types of memory, such as Dynamic Random Access Memory (DRAM), may be affected with frequent row activations, which may be referred to as row hammering. For example, if a row is repeatedly accessed (e.g., a row is hammered) over a time interval, leakage, parasitic current, or charge pumping caused by repeatedly accessing one or more rows may cause data in physically adjacent (e.g., neighboring) rows that are not accessed to be corrupted. As the size of the memory decreases, the number of physically adjacent rows (e.g., the number of victim rows) that may experience data corruption during row hammering may increase. In general, improving a memory device may include increasing memory cell density, increasing read/write speed, increasing reliability, increasing data retention, reducing power consumption, or reducing manufacturing costs, among other metrics. Moreover, it may be desirable to improve memory device performance (e.g., increase reliability, increase data retention) in the case of row hammering.

Drawings

FIG. 1 illustrates an example of a system that supports row hammer protection for a memory device as disclosed herein.

FIG. 2 illustrates an example of memory dies that support row hammer protection for a memory device as disclosed herein.

FIG. 3 illustrates an example of a system that supports row hammer protection for a memory device as disclosed herein.

Fig. 4-6 illustrate process flows to support row hammer protection for a memory device as disclosed herein.

FIG. 7 shows a block diagram of circuitry to support row hammer protection for a memory device as disclosed herein.

Fig. 8 and 9 show flow diagrams illustrating one or more methods of supporting row hammer protection for a memory device as disclosed herein.

Detailed Description

The memory device may operate under various conditions as part of an electronic device, such as a personal computer, a wireless communication device, a server, an internet of things (IoT) device, an electronic component of a motor vehicle, and so forth. In some cases, memory devices supporting applications for certain implementations (e.g., motor vehicles, in some cases motor vehicles with autonomous or semi-autonomous driving capabilities) may be limited by increased reliability constraints. As such, memory devices (e.g., DRAMs) for some applications may be expected to operate with reliability that is limited by relatively high industry specifications (e.g., high reliability constraints).

Some memory types may lose or change a stored state to a different state with frequent row activations or row hammering. That is, if a single row, group of rows, or pattern of rows (pattern) is accessed with a relatively high frequency, the memory state of the victim row (e.g., adjacent or neighboring rows) may be affected. In some cases (e.g., automotive applications), increased reliability of the memory unit may be desirable (e.g., for critical safety functions). That is, it may be desirable to prevent dynamic memory cells from changing the stored state due to row hammering. For example, dynamic memory cells (e.g., DRAM cells) of a memory device may lose their stored data without periodically refreshing the data, and row hammering may cause the dynamic memory cells to lose the stored state or change the stored state to a different state in less time (e.g., more quickly for a refresh cycle). Additionally, some applications may have different memory access patterns during normal or predicted usage.

Techniques to improve row hammer protection for memory devices are described. For example, a memory device may utilize a threshold value corresponding to a maximum metric of relative access (e.g., access command or activation to the same row address or the same row address space) of a memory array. In the event that the memory device detects a metric (e.g., a number or pattern) of the row access commands that satisfies (e.g., is equal to or greater than) the threshold (e.g., the memory device detects row hammering), the memory device may take action based on detecting row hammering. In one example, the memory device may activate a secure mode of the memory array associated with the detected row hammer. The secure mode may prevent row accesses to at least one row of the memory array, thus reducing the chance of further data corruption resulting from frequent row accesses. Additionally or alternatively, the memory device may transmit a notification to the host device indicating the detected row hammer associated with the memory array. Based on the notification, the host device may take evasive action to prevent the application from performing additional row accesses related to row hammering at the memory array.

The features of the present disclosure are first described in the context of the memory system and apparatus described with reference to fig. 1, 2 and 3. Features of the present disclosure are described in the context of a process flow as described with reference to fig. 4, 5 and 6. These and other features of the present disclosure are further illustrated by and described with reference to the apparatus diagrams and flow diagrams in fig. 7-9 relating to row hammer protection for memory devices.

Fig. 1 illustrates an example of a system 100 utilizing one or more memory devices in accordance with aspects disclosed herein. System 100 may include an external memory controller 105, a memory device 110, and a plurality of channels 115 coupling external memory controller 105 and memory device 110. The system 100 may include one or more memory devices, but for ease of description, the one or more memory devices may be described as a single memory device 110.

The system 100 may include aspects of an electronic device, such as a computing device, a mobile computing device, a wireless device, or a graphics processing device. In some cases, the system 100 is an automotive system, such as a vehicle control system, fleet management system, position tracking system, navigation system, infotainment system, or the like. In other cases, the system 100 may be an example of a portable electronic device. System 100 may be an example of a computer, handheld computer, tablet computer, smart phone, cellular phone, wearable device, internet connected device, and so forth. Memory device 110 may be a component of a system configured to store data for one or more other components of system 100. In some examples, system 100 is configured for two-way wireless communication with other systems or devices using a base station or access point. In some examples, the system 100 is capable of Machine Type Communication (MTC), machine-to-machine (M2M) communication, or device-to-device (D2D) communication.

At least part of the system 100 may be an instance of a host device. Such a host device may be an example of a device that performs a process using memory, such as a computing device, a mobile computing device, a wireless device, a graphics processing device (e.g., a Graphics Processing Unit (GPU)), a computer, a handheld computer, a tablet computer, a smartphone, a cellular phone, a wearable device, an internet-connected device, some other fixed or portable electronic device, and so forth. In some cases, a host device may refer to hardware, firmware, software, or a combination thereof, that implements the functionality of external memory controller 105. In some cases, external memory controller 105 may be referred to as a host or a host device.

In some cases, memory device 110 may be a stand-alone device or component configured to communicate with other components of system 100 and provide physical memory addresses/space that may potentially be used or referenced by system 100. In some examples, memory device 110 may be configured to cooperate with at least one or more different types of systems 100. Signaling between components of the system 100 and the memory device 110 may be used to support modulation schemes for modulating signals, different pin designs for transferring signals, different packaging of the system 100 and the memory device 110, clock signaling and synchronization between the system 100 and the memory device 110, timing conventions, and/or other factors.

The memory device 110 may be configured to store data for the components of the system 100. In some cases, memory device 110 may act as a slave to system 100 (e.g., respond to and execute commands provided by system 100 through external memory controller 105). Such commands may include access commands for access operations, such as write commands for write operations, read commands for read operations, refresh commands for refresh operations, or other commands. The memory device 110 may include two or more memory dies 160 (e.g., memory chips) that support a desired or specified capacity for data storage. A memory device 110 including two or more memory dies may be referred to as a multi-die memory or package (also referred to as a multi-chip memory or package).

The system 100 may additionally include a processor 120, a basic input/output system (BIOS) component 125, one or more peripheral components 130, and an input/output (I/O) controller 135. The components of system 100 may be in electronic communication with each other using a bus 140.

The processor 120 may be configured to control at least a portion of the system 100. The processor 120 may be a general purpose processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or it may be a combination of these types of components. In such cases, processor 120 may be an instance of a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), a general purpose GPU (gpgpu), or a system on a chip (SoC), among other instances.

The BIOS component 125 may be a software component containing a BIOS operating as firmware that may initialize and run various hardware components of the system 100. The BIOS component 125 may also manage data flow between the processor 120 and various components of the system 100, such as peripheral components 130, I/O controllers 135, and the like. The BIOS component 125 may include programs or software stored in Read Only Memory (ROM), flash memory, or any other non-volatile memory.

Peripheral component 130 may be any input device or output device, or interface to such a device, which may be integrated into system 100 or integrated with system 100. Examples may include disk controllers, voice controllers, graphics controllers, ethernet controllers, modems, Universal Serial Bus (USB) controllers, serial or parallel ports, or peripheral card slots such as Peripheral Component Interconnect (PCI) or Accelerated Graphics Port (AGP) slots. The peripheral components 130 may be other components understood by those skilled in the art as peripheral devices.

The I/O controller 135 may manage data communications between the processor 120 and peripheral components 130, inputs 145, or outputs 150. I/O controller 135 may manage peripheral devices that are not integrated into system 100 or integrated with system 100. In some cases, I/O controller 135 may represent a physical connection or port to an external peripheral component.

Input 145 may represent a device or signal external to system 100 that provides information, signals, or data to system 100 or a component thereof. This may include a user interface or an interface with or between other devices. In some cases, input 145 may be a peripheral device that interfaces with system 100 via one or more peripheral components 130, or may be managed by I/O controller 135.

Output 150 may represent a device or signal external to system 100 that is configured to receive an output from system 100 or any component thereof. Examples of output 150 may include a display, an audio speaker, a printed device, or another processor on a printed circuit board, and so forth. In some cases, output 150 may be a peripheral device that interfaces with system 100 via one or more peripheral components 130, or may be managed by I/O controller 135.

The components of system 100 may be comprised of general purpose or special purpose circuits designed to perform their functions. This may include various circuit elements, such as wires, transistors, capacitors, inductors, resistors, amplifiers, or other active or passive elements, configured to perform the functions described herein.

Memory device 110 may include a device memory controller 155 and one or more memory dies 160. Each memory die 160 may include a local memory controller 165 (e.g., local memory controller 165-a, local memory controller 165-b, and/or local memory controller 165-N) and a memory array 170 (e.g., memory array 170-a, memory array 170-b, and/or memory array 170-N). The memory array 170 may be a collection (e.g., a grid) of memory cells, where each memory cell is configured to store at least one bit of digital data. Features of the memory array 170 and/or memory cells are described in more detail with reference to FIG. 2.

The memory device 110 may be an example of a two-dimensional (2D) array of memory cells or may be an example of a three-dimensional (3D) array of memory cells. For example, a 2D memory device may include a single memory die 160. The 3D memory device can include two or more memory dies 160 (e.g., memory die 160-a, memory die 160-b, and/or any number of memory dies 160-N). In a 3D memory device, multiple memory dies 160-N may be stacked on top of each other. In some cases, the memory dies 160-N in a 3D memory device may be referred to as a deck, level, layer, or die. The 3D memory device may include any number of stacked memory dies 160-N (e.g., two tall stacked memory dies, three tall stacked memory dies, four tall stacked memory dies, five tall stacked memory dies, six tall stacked memory dies, seven tall stacked memory dies, eight tall stacked memory dies). This may increase the number of memory cells that may be positioned on the substrate compared to a single 2D memory device, which in turn may reduce production costs or increase performance of the memory array, or both. In some 3D memory devices, different decks may share at least one common access line, such that some decks may share at least one of a word line, a digit line, and/or a plate line.

Device memory controller 155 may include circuitry or components configured to control the operation of memory device 110. As such, device memory controller 155 may include hardware, firmware, and software that enable memory device 110 to execute commands, and may be configured to receive, transmit, or execute commands, data, or control information related to memory device 110. Device memory controller 155 may be configured to communicate with external memory controller 105, one or more memory dies 160, or processor 120. In some cases, memory device 110 may receive data and/or commands from external memory controller 105. For example, memory device 110 may receive a write command instructing memory device 110 to store certain data representative of a component of system 100 (e.g., processor 120) or a read command instructing memory device 110 to provide certain data stored in memory die 160 to a component of system 100 (e.g., processor 120). In some cases, device memory controller 155 can control the operation of memory device 110 described herein in conjunction with local memory controller 165 of memory die 160. Examples of components included in device memory controller 155 and/or local memory controller 165 may include a receiver for demodulating signals received from external memory controller 105, a decoder, logic, decoder, amplifier, filter, etc. for modulating and transmitting signals to external memory controller 105.

A local memory controller 165 (e.g., local to the memory die 160) may be configured to control the operation of the memory die 160. Also, local memory controller 165 may be configured to communicate (e.g., receive and transmit data and/or commands) with device memory controller 155. Local memory controller 165 may support device memory controller 155 to control the operation of memory device 110 as described herein. In some cases, memory device 110 does not include device memory controller 155, and local memory controller 165 or external memory controller 105 may perform the various functions described herein. Thus, local memory controller 165 may be configured to communicate with device memory controller 155, with other local memory controllers 165, or directly with external memory controller 105 or processor 120.

External memory controller 105 may be configured to enable communication of information, data, and/or commands between components of system 100 (e.g., processor 120) and memory device 110. The external memory controller 105 may act as a liaison between the components of the system 100 and the memory device 110, such that the components of the system 100 may not need to know the operational details of the memory device 110. Components of system 100 may present to external memory controller 105 a request (e.g., a read command or a write command) that external memory controller 105 satisfies. The external memory controller 105 may translate or translate communications exchanged between components of the system 100 and the memory device 110. In some cases, external memory controller 105 may include a system clock that generates a common (source) system clock signal. In some cases, external memory controller 105 may contain a common data clock that generates a common (source) data clock signal.

In some cases, external memory controller 105 or other components of system 100 or their functions described herein may be implemented by processor 120. For example, external memory controller 105 may be hardware, firmware, or software, or some combination thereof, implemented by processor 120 or other components of system 100. Although the external memory controller 105 is depicted as being external to the memory device 110, in some cases, the external memory controller 105 or its functions described herein may be implemented by the memory device 110. For example, external memory controller 105 may be hardware, firmware, or software implemented by device memory controller 155 or one or more local memory controllers 165, or some combination thereof. In some cases, external memory controller 105 may be distributed across processor 120 and memory device 110 such that portions of external memory controller 105 are implemented by processor 120 and other portions are implemented by device memory controller 155 or local memory controller 165. Likewise, in some cases, one or more functions attributed herein to device memory controller 155 or local memory controller 165 may in some cases be performed by external memory controller 105 (separate from processor 120 or included in processor 120).

Components of system 100 may exchange information with memory device 110 using multiple channels 115. In some examples, channel 115 may enable communication between external memory controller 105 and memory device 110. Each channel 115 may include one or more signal paths or transmission media (e.g., conductors) between terminals associated with components of system 100. For example, the channel 115 may include a first terminal that includes one or more pins or pads at the external memory controller 105 and one or more pins or pads at the memory device 110. A pin may be an example of a conductive input or output point of a device of system 100, and a pin may be configured to act as part of a channel. In some cases, a pin or pad of a terminal may be part of the signal path of channel 115. Additional signal paths may be coupled with terminals of the channels for routing signals within components of system 100. For example, memory device 110 may include signal paths (e.g., signal paths internal to memory device 110 or components thereof, such as internal to memory die 160) that route signals from terminals of channel 115 to various components of memory device 110 (e.g., device memory controller 155, memory die 160, local memory controller 165, memory array 170).

The channel 115 (and associated signal paths and terminals) may be dedicated to conveying a particular type of information. In some cases, channel 115 may be an aggregated channel and thus may contain multiple individual channels. For example, the data channel 190 may be x4 (e.g., including four signal paths), x8 (e.g., including eight signal paths), x16 (including sixteen signal paths), and so on.

In some cases, the channels 115 may include one or more Command and Address (CA) channels 186. CA channel 186 may be configured to communicate commands between external memory controller 105 and memory devices 110, including control information (e.g., address information) associated with the commands. For example, the CA channel 186 may include a read command regarding the address of the desired data. In some cases, CA channel 186 may register a rising clock signal edge and/or a falling clock signal edge. In some cases, CA channel 186 may include eight or nine signal paths.

In some cases, the channel 115 may include one or more clock signal (CK) channels 188. The CK channel 188 may be configured to transfer one or more common clock signals between the external memory controller 105 and the memory device 110. Each clock signal may be configured to oscillate between a high state and a low state and coordinate the measures of external memory controller 105 and memory device 110. In some cases, the clock signals may be differential outputs (e.g., CK _ t and CK _ c signals) and the signal paths of the CK channel 188 may be configured accordingly. In some cases, the clock signal may be single ended. In some cases, the clock signal may be a 1.5GHz signal. The CK channel 188 may include any number of signal paths. In some cases, clock signal CK (e.g., the CK _ t signal and the CK _ c signal) may provide a timing reference for command and addressing operations of memory device 110 or operations within other systems of memory device 110. The clock signal CK may thus be variously referred to as a control clock signal CK, a command clock signal CK, or a system clock signal CK. The system clock signal CK may be generated by a system clock, which may include one or more hardware components (e.g., oscillators, crystals, logic gates, transistors, etc.).

In some cases, channel 115 may include one or more Data (DQ) channels 190. Data channel 190 may be configured to transfer data and/or control information between external memory controller 105 and memory device 110. For example, the data channel 190 may transfer information to be written to the memory device 110 (e.g., bi-directional) or read from the memory device 110. The data channel 190 may transmit a signal that may be modulated using a number of different modulation schemes (e.g., NRZ, PAM 4).

In some cases, the channel 115 may include one or more other channels 192 that may be dedicated for other purposes. These other channels 192 may include any number of signal paths.

In some cases, other channels 192 may include one or more write clock signal (WCK) channels. While 'W' in WCK may nominally represent "write," the write clock signal WCK (e.g., the WCK _ t and WCK _ c signals) may provide timing references generally used for access operations of the memory device 110 (e.g., timing references for both read and write operations). Therefore, the write clock signal WCK may also be referred to as a data clock signal WCK. The WCK channels may be configured to communicate a common data clock signal between the external memory controller 105 and the memory devices 110. The data clock signal may be configured to coordinate access operations (e.g., write operations or read operations) of external memory controller 105 and memory device 110. In some cases, the write clock signals may be differential outputs (e.g., the WCK _ t and WCK _ c signals), and the signal paths of the WCK channels may be configured accordingly. The WCK channels may include any number of signal paths. The data clock signal WCK may be generated by a data clock, which may include one or more hardware components (e.g., oscillators, crystals, logic gates, transistors, etc.).

The channel 115 may couple the external memory controller 105 with the memory device 110 using a variety of different architectures. Examples of various architectures may include a bus, a point-to-point connection, a crossbar switch, a high density interposer such as a silicon interposer, or a channel formed in an organic substrate, or some combination thereof. For example, in some cases, the signal path may include, at least in part, a high density interposer, such as a silicon interposer or a glass interposer.

Various different modulation schemes may be used to modulate signals transmitted over channel 115. In some cases, signals communicated between external memory controller 105 and memory device 110 may be modulated using a binary symbol (or binary level) modulation scheme. The binary symbol modulation scheme may be an example of an M-ary modulation scheme, where M is equal to two. Each symbol of the binary symbol modulation scheme may be configured to represent a bit of digital data (e.g., a symbol may represent a logical 1 or a logical 0). Examples of binary symbol modulation schemes include, but are not limited to, non-return-to-zero (NRZ), unipolar coding, bipolar coding, manchester coding, Pulse Amplitude Modulation (PAM) with two symbols (e.g., PAM2), and the like.

In some cases, signals communicated between external memory controller 105 and memory device 110 may be modulated using a multi-symbol (or multi-level) modulation scheme. The multi-symbol modulation scheme may be an example of an M-ary modulation scheme, where M is greater than or equal to three. Each symbol of the multi-symbol modulation scheme may be configured to represent more than one bit of digital data (e.g., a symbol may represent logic 00, logic 01, logic 10, or logic 11). Examples of multi-symbol modulation schemes include, but are not limited to, PAM4, PAM8, and the like, Quadrature Amplitude Modulation (QAM), Quadrature Phase Shift Keying (QPSK), and the like. The multi-symbol signal or PAM4 signal may be a signal modulated using a modulation scheme that includes at least three levels to encode more than one bit of information. Multi-symbol modulation schemes and symbols may alternatively be referred to as non-binary, multi-bit, or higher order modulation schemes and symbols.

System 100 may be configured to employ techniques that improve row hammer protection for memory device 110. The memory device 110 may utilize a threshold value corresponding to a maximum metric of related accesses (e.g., access commands or activations to the same row address or the same row address space) of the memory array 170. In the event memory device 110 detects a metric (e.g., a number or pattern) of row access commands that satisfies the threshold (e.g., memory device 110 detects row hammering), memory device 110 may take action based on detecting row hammering. In one example, memory device 110 may activate a secure mode of memory array 170 associated with the detected row hammer. The secure mode may prevent row accesses to at least one row of the memory array 170, thus reducing the chance of further data corruption resulting from frequent row accesses. Additionally or alternatively, memory device 110 may transmit a notification to a host (e.g., external memory controller 105) indicating the detected row hammer associated with memory array 170. The host may take evasive action to prevent the application from performing additional row accesses related to row hammering at the memory array 170.

Fig. 2 illustrates an example of a memory device 200 according to various examples of the present disclosure. Memory die 200 may be an example of memory die 160 described with reference to FIG. 1. In some cases, the memory die 200 may be referred to as a memory chip, a memory device, or an electronic memory apparatus. The memory die 200 may include one or more memory cells 205 that are programmable to store different logic states. Each memory cell 205 may be programmable to store two or more states. For example, memory cell 205 may be configured to store digital logic (e.g., logic 0 and logic 1) one bit at a time. In some cases, a single memory cell 205 (e.g., a multi-level memory cell) may be configured to store more than one bit of digital logic (e.g., logic 00, logic 01, logic 10, or logic 11) at a time.

The memory cell 205 may store a charge representing a programmable state in the capacitor 230. The DRAM architecture may include a capacitor 230 comprising a dielectric material to store a charge representing a programmable state. Other storage devices and components are possible in other memory architectures. For example, a nonlinear dielectric material may be used.

Operations such as reads and writes may be performed on memory cells 205 by activating or selecting access lines such as word lines 210 and/or digit lines 215. In some cases, digit lines 215 may also be referred to as bit lines. References to access lines, word lines, and digit lines or the like are interchangeable and do not affect understanding or operation. Activating or selecting a word line 210 or digit line 215 may include applying a voltage to the respective line.

The memory die 200 may arrange the access lines (e.g., word lines 210 and digit lines 215) in a grid-like pattern. Memory cell 205 may be located at the intersection of word line 210 and digit line 215. By biasing the word line 210 and digit line 215 (e.g., applying a voltage to the word line 210 or digit line 215), a single memory cell 205 can be accessed at its intersection.

Access to the memory cells 205 may be controlled by a row decoder 220 or a column decoder 225. For example, the row decoder 220 may receive a row address from the local memory controller 260 and activate the wordline 210 based on the received row address. Column decoder 225 may receive a column address from local memory controller 260 and may activate digit lines 215 based on the received column address. For example, the memory die 200 may include a plurality of word lines 210 labeled WL _1 to WL _ M and a plurality of digit lines 215 labeled DL _1 to DL _ N, where M and N depend on the size of the memory array. Thus, by activating wordline 210 and digit lines 215, e.g., WL _1 and DL _3, memory cell 205 at its intersection can be accessed. The intersection of word line 210 and digit line 215 in a two-dimensional or three-dimensional configuration may be referred to as an address of memory cell 205.

Memory cell 205 may include logic storage components such as capacitor 230 and switching component 235. The capacitor 230 may be an example of a dielectric capacitor or a ferroelectric capacitor. A first node of capacitor 230 may be coupled with switching element 235 and a second node of capacitor 230 may be coupled with voltage source 240. In some cases, voltage source 240 may be a cell plate reference voltage, such as Vpl, or may be ground, such as Vss. In some cases, voltage source 240 may be an example of a plate line coupled to a plate line driver. The switching component 235 may be an example of a transistor or any other type of switching device that selectively establishes or de-establishes electronic communication between the two components.

Selecting or deselecting memory cell 205 may be accomplished by activating or deactivating switch component 235. Capacitor 230 may be in electronic communication with digit line 215 using a switching component 235. For example, capacitor 230 may be isolated from digit line 215 when switch component 235 is deactivated, and capacitor 230 may be coupled with digit line 215 when switch component 235 is activated. In some cases, the switch component 235 is a transistor, and its operation may be controlled by applying a voltage to the transistor gate, where the voltage difference between the transistor gate and the transistor source may be greater than or less than the threshold voltage of the transistor. In some cases, the switching component 235 may be a p-type transistor or an n-type transistor. The word line 210 may be in electronic communication with a gate of the switch component 235, and the switch component 235 may be activated/deactivated based on a voltage applied to the word line 210.

The word line 210 may be a conductive line in electronic communication with the memory cell 205 that is used to perform an access operation on the memory cell 205. In some architectures, the word line 210 may be in electronic communication with the gate of the switch component 235 of the memory cell 205 and may be configured to control the switch component 235 of the memory cell. In some architectures, the word line 210 may be in electronic communication with a node of a capacitor of the memory cell 205, and the memory cell 205 may not include the switch component 235.

Digit line 215 may be a conductive line connecting memory cell 205 and sense component 245. In some architectures, memory cells 205 may be selectively coupled with digit lines 215 during portions of an access operation. For example, the word line 210 and the switching component 235 of the memory cell 205 may be configured to couple and/or isolate the capacitor 230 and the word line 215 of the memory cell 205. In some architectures, memory unit 205 may be in electronic communication (e.g., constant) with digit line 215.

The sensing component 245 may be configured to detect a state (e.g., charge) stored on the capacitor 230 of the memory cell 205 and determine a logic state of the memory cell 205 based on the stored state. In some cases, the charge stored by memory cell 205 may be extremely small. Thus, the sensing component 245 may include one or more sense amplifiers to amplify the signals output by the memory cells 205. The sense amplifier may detect small changes in the charge of the digit line 215 during a read operation and may generate a signal corresponding to logic state 0 or logic state 1 based on the detected charge. During a read operation, the capacitor 230 of the memory cell 205 may output a signal (e.g., discharge charge) to its corresponding digit line 215. The signal may cause the voltage of digit line 215 to change. The sensing component 245 may be configured to compare a signal received from the memory cell 205 across the digit line 215 to a reference signal 250 (e.g., a reference voltage). The sensing component 245 may determine the storage state of the memory cell 205 based on the comparison. For example, in binary signaling, if digit line 215 has a higher voltage than reference signal 250, sensing component 245 may determine that the storage state of memory cell 205 is a logic 1, and if digit line 215 has a lower voltage than reference signal 250, sensing component 245 may determine that the storage state of memory cell 205 is a logic 0. The sensing component 245 may include various transistors or amplifiers to detect and amplify the difference in signals. The detected logic state of memory cell 205 may be output as output 255 via column decoder 225. In some cases, sensing component 245 may be part of another component (e.g., column decoder 225, row decoder 220). In some cases, the sensing component 245 may be in electronic communication with the row decoder 220 or the column decoder 225.

The local memory controller 260 may control the operation of the memory cells 205 via various components, such as the row decoder 220, the column decoder 225, and the sensing component 245. Local memory controller 260 may be an example of local memory controller 165 described with reference to fig. 1. In some cases, one or more of row decoder 220, column decoder 225, and sensing component 245 may be co-located with local memory controller 260. Local memory controller 260 may be configured to receive commands and/or data from external memory controller 105 (or device memory controller 155 described with reference to fig. 1), translate the commands and/or data into information usable by memory die 200, perform one or more operations on memory die 200, and communicate data from memory die 200 to external memory controller 105 (or device memory controller 155) in response to performing the one or more operations. The local memory controller 260 may generate row and column address signals to activate the target word line 210 and the target digit line 215. The local memory controller 260 may also generate and control various voltages or currents used during operation of the memory die 200. In general, the amplitude, shape, or duration of the applied voltages or currents discussed herein can be adjusted or varied, and can be different for the various operations discussed in operating the memory die 200.

In some cases, the local memory controller 260 may be configured to perform a write operation (e.g., a programming operation) on one or more memory cells 205 of the memory die 200. During a write operation, the memory cells 205 of the memory die 200 can be programmed to store a desired logic state. In some cases, multiple memory cells 205 may be programmed during a single write operation. The local memory controller 260 may identify the target memory cell 205 that is to perform the write operation. The local memory controller 260 may identify a target wordline 210 and a target digit line 215 (e.g., an address of the target memory cell 205) in electronic communication with the target memory cell 205. The local memory controller 260 may activate the target wordline 210 and the target digit line 215 (e.g., apply a voltage to the wordline 210 or the digit line 215) to access the target memory cell 205. The local memory controller 260 may apply a particular signal (e.g., voltage) to the digit lines 215 during a write operation to store a particular state (e.g., charge) in the capacitor 230 of the memory cell 205, which may indicate a desired logic state.

In some cases, the local memory controller 260 may be configured to perform read operations (e.g., sense operations) on one or more memory cells 205 of the memory die 200. During a read operation, the logic state stored in memory cells 205 of memory die 200 can be determined. In some cases, multiple memory cells 205 may be sensed during a single read operation. The local memory controller 260 may identify the target memory cell 205 that is to perform the read operation. The local memory controller 260 may identify a target wordline 210 and a target digit line 215 (e.g., an address of the target memory cell 205) in electronic communication with the target memory cell 205. The local memory controller 260 may activate the target word line 210 and the target digit line 215 (e.g., apply a voltage to the word line 210 or the digit line 215) to access the target memory cell 205. The target memory cell 205 may pass a signal to the sense component 245 in response to the biased access line. The sensing component 245 may amplify the signal. The local memory controller 260 may trigger the sensing component 245 (e.g., latch the sensing component 245) and thereby compare the signal received from the memory cell 205 to the reference signal 250. Based on the comparison, the sensing component 245 can determine the logic state stored on the memory cell 205. As part of a read operation, local memory controller 260 may communicate the logic state stored on memory cells 205 to external memory controller 105 (or device memory controller 155).

In some memory architectures, accessing the memory cell 205 may degrade or destroy the logic state stored in the memory cell 205. For example, a read operation performed in a DRAM architecture may partially or completely discharge the capacitor 230 of the target memory cell 205. The local memory controller 260 may perform a rewrite operation or a refresh operation to restore the memory cells 205 to their original logical states. The local memory controller 260 may rewrite the logic state to the target memory cell 205 after the read operation. In some cases, the rewrite operation may be considered part of a read operation. In addition, activating a single access line (e.g., word line 210) may disturb the state stored in some memory cells in electronic communication with the access line. Thus, a rewrite operation or a refresh operation may be performed on one or more memory cells that may not have been accessed.

FIG. 3 illustrates an example of a system 300 that supports a row hammer protection technique for a memory device. The system 300 may include one or more components described herein with reference to fig. 1 and 2. For example, the system 300 may include a host device 305, which may be an example of the external memory controller 105 described with reference to FIG. 1; memory device 310, which may be an example of memory device 110, memory die 160, or memory die 200 described with reference to FIGS. 1 and 2; a controller 320, which may be an example of the device memory controller 155, the one or more local memory controllers 165, or the local memory controller 260 described with reference to fig. 1 and 2, or any combination thereof; a memory array 325, which may be an example of the memory array 170 described with reference to fig. 1. The memory device 310 may also include a threshold storage 330 and a redundant row access detection circuit 335.

Host device 305 can send commands to memory device 310, which can be received via memory interface 315. The commands may include individual row access commands, such as individual read or write commands, or burst commands (multiple sequential row or column access commands). The controller 320 may receive commands from the memory interface 315, process the commands, and execute the commands on the memory array 325. The controller 320 may operate the memory array 325 according to an operating mode. An access mode as used herein may include the controller 320 executing a command (e.g., all commands received) issued from the host device 305 to an indicated portion of the memory array 325. The memory array 325 may include one or more memory banks, each of which may include one or more rows and/or one or more columns. Each command may include an access command, which may include an activation (e.g., read, write, etc.) for a row address within the memory array 325. The controller 320 may execute a plurality of access commands (e.g., access command patterns) on the memory array 325, thus accessing the pattern of banks, rows, and/or columns within the memory array 325.

Threshold storage 330 may store a threshold associated with an access command or access for memory device 310. The threshold may define a relative number of accesses that, when exceeded, may cause data corruption from row hammering. In some cases, a related access may correspond to a maximum number of accesses to the same row address or the same row address space (e.g., a row group, bank, etc.). Additionally or alternatively, the associated access may correspond to an access composite of one or more access patterns for the row address space. The maximum number of related accesses may occur sequentially or may occur within a particular time window (e.g., a refresh cycle, a portion of a refresh cycle), a particular number of access operations, or some other criteria.

In some cases, memory device 310 may have an associated preconfigured threshold. For example, threshold storage 330 may store a preconfigured threshold fixed by a vendor (e.g., a DRAM vendor). Threshold storage 330 may include a value of a preconfigured threshold, such as hardwired (e.g., stored in one or more fuses, antifuses, or otherwise stored in one or more memory elements that are non-volatile and that may be preconfigured (e.g., Read Only Memory (ROM) or One Time Programmable (OTP) memory)).

Memory device 310 may be used to support a variety of applications. In some cases, each application may access the memory array 325 of the memory device 310 according to a known access pattern. That is, the intended purpose of the application may result in a particular set of access patterns. For example, a general purpose application (e.g., having various intended purposes) may access the memory array 325 according to an unpredictable access pattern. Alternatively, a dedicated application (e.g., having a narrower intended purpose) may access the memory array 325 according to a more predictable access pattern, and may have a discernible boundary on access commands to related or adjacent addresses (e.g., a single row or group of rows). For dedicated applications (e.g., applications within an autonomous vehicle), certain access patterns may be determined to be less likely than other access patterns. For example, a dedicated application may not likely exhibit an access pattern similar to row hammer in its normal operation. Memory device 310 may be required to utilize a lower threshold of memory device 310 associated with some applications (e.g., special-purpose applications) when compared to other applications (e.g., general-purpose applications). Alternatively, it may be possible for a dedicated application to exhibit an access pattern similar to row hammer in its normal operation. Here, the memory device 310 may need to utilize a higher threshold.

In some cases, different portions (e.g., rows, banks, etc.) of the memory array 325 may be associated with different thresholds. For example, some portions of the memory array 325 may be protected areas where a lower number of accesses are allowed. In one example, some protected regions may have a threshold for a single row access, where any additional row access (e.g., within a refresh cycle) would exceed the threshold and cause detection of a redundant row access condition. Thus, the host device 305 may utilize different portions of the memory array 325 for different applications or purposes. For example, portions of the memory array 325 associated with lower threshold values may be used for applications associated with critical functions that rarely, if ever, generate access patterns consistent with row hammering, while other portions of the memory array 325 associated with higher threshold values may be used for general or less critical functions.

In some cases, the preconfigured threshold in threshold storage 330 may be adjustable or rewritable (e.g., as a trimming parameter). For example, threshold storage 330 may include OTP memory (e.g., fuse or antifuse) for storing a preconfigured threshold, and host device 305 may program the preconfigured threshold upon initial memory device 310 power-up or configuration (e.g., the first time host device 305 accesses memory device 310). After programming, the preconfigured threshold may then be fixed for a subsequent power cycle.

Threshold storage 330 according to various aspects may include the ability to store programmed (e.g., not preconfigured) thresholds. In some cases, threshold storage 330 may include non-volatile memory (e.g., one-time programmable (OTP) memory, Electrically Erasable Programmable Read Only Memory (EEPROM), Ferroelectric Random Access Memory (FRAM), magnetoresistive Random Access Memory (RAM)) for storing programmed thresholds. Alternatively, threshold storage 330 may include volatile memory (e.g., DRAM, Static Random Access Memory (SRAM), registers) for storing programmed thresholds host device 305 may program threshold storage 330 to store programmed thresholds (e.g., upon initialization or configuration). The programmed threshold may be based on the application of the memory device 310. That is, while the preconfigured threshold may represent a number of related accesses associated with reduced data retention, certain applications (e.g., dedicated applications) may utilize a different (e.g., lower) threshold. For example, the preconfigured threshold for memory device 310 may be 10,000. However, memory device 310 may be associated with an autonomous vehicle application that may not likely exhibit row hammer-like access. Thus, the host device 305 programmable threshold storage 330 (via the controller 320 or memory interface 315) stores programmed thresholds of less than 10,000. In some cases, host device 305 can program threshold storage device 330 to store programmable thresholds by programming a mode register within memory device 310. In some cases, host device 305 may program threshold storage 330 to store a programmable threshold that is greater than a preconfigured threshold, but spare row access detection circuit 335 may be configured to consider the lower of the two thresholds as operational.

Threshold storage 330 may store programmed thresholds and subsequently protect the storage of programmed thresholds. For example, the threshold storage 330 may include a fuse that can be blown to prevent a programmed threshold from changing (e.g., the threshold storage 330 may be OTP memory). In another example, threshold storage 330 may not adjust the programmed threshold until a known command sequence is received from host device 305. That is, host device 305 may transmit a sequence of commands to memory device 310. The memory device 310 (e.g., via the controller 320 or the spare row access detection circuitry 335) may then determine to store the updated programmed threshold at the threshold storage 330 based on receiving the command sequence.

The spare row access detection circuit 335 may determine which of the preconfigured threshold or the programmed threshold to use based on the minimum threshold (e.g., select the minimum of the preconfigured threshold or the programmed threshold). In some other cases, the spare row access detection circuit 335 may determine which of the preconfigured threshold or the programmed threshold to use based on a flag register. The flag register may indicate that the redundant row access detection circuitry 335 uses a programmed threshold. For example, if the flag register stores a logic '0', the extra row access detection circuit 335 may use a preconfigured threshold. Alternatively, the redundant row access detection circuit 335 may use a programmed threshold if the flag register stores a logic '1'. In some cases, the host device 305 may set a flag register. In some cases, one or more (e.g., some or all) of the herein attributed redundant row access detection circuitry 335 may be integrated into the controller 320.

The redundant row access detection circuitry 335 may include circuit components configured to determine row access metrics. The redundant row access detection circuit 335 may be or include a counter, a timer, and the like. The row access metric may indicate a relative number of accesses (e.g., a number or pattern of accesses to the same or similar rows, banks, etc.). The redundant row access detection circuit 335 may receive an access indication (e.g., an access command received from the host device 305) from the memory interface 315 or the controller 320. That is, during the access mode, the controller 320 may execute an access command received from the host device 305 on the memory array 325. The controller 320 may further provide an access indication to the redundant row access detection circuitry 335. Based on the accesses, the redundant row access detection circuit 335 may determine a relative number of accesses and compare the row access metric to a threshold value (e.g., a preconfigured threshold value or a programmed threshold value) from the threshold storage 330. If the redundant row access detection circuit 335 determines that the row access metric satisfies the threshold, the redundant row access detection circuit 335 may provide an indication to the controller 320. The indication may include information indicating one or more rows (e.g., row groups, banks) for which the row access metric satisfies a threshold. Upon receiving an indication that the row access metric satisfies the threshold, the controller 320 may transition one or more portions of the memory array 325 from an access mode to a secure mode. The secure mode may prevent additional row accesses to the memory array 325 that increase the probability that bits of the memory array 325 change memory states (e.g., due to a row hammer access pattern). As used herein, a secure mode includes an access constraint to at least one row of the memory array 325.

In addition to entering secure mode, or alternatively, controller 320 may transmit an indication that the row access metric satisfies a threshold to host device 305. In some cases, the indication may include information related to a line or line pattern for which the access metric satisfies a threshold (e.g., a trigger condition). Additionally or alternatively, information related to the row or row pattern of the trigger condition may be stored (e.g., in the controller 320 or the redundant row access detection circuit 335) for access by the host device 305. Thus, upon receiving the indication, host device 305 may read one or more registers of the memory device that include information related to the row or row pattern for which the access metric satisfies the threshold.

The secure mode may include the controller 320 blocking access commands directed to the memory array 325. In one example, the secure mode may include the controller 320 blocking access commands to each of the banks of the memory array 325. In another example, the secure mode may include the controller 320 blocking access commands to a single bank (e.g., a victim bank of access commands). Here, the controller 320 may block access commands to a single bank while the remaining banks within the memory array 325 may continue to operate in the access mode (e.g., the controller 320 may propagate access commands to the remaining banks). During the secure mode, the controller 320 may initiate a refresh operation of one or more banks associated with the secure mode.

The controller 320 may maintain the secure mode for a predetermined period of time (e.g., a period of time or a number of clocks), or until a command is received from the host device 305 to return to the access mode. The reset procedure may transition the memory array 325 from the secure mode to the access mode. The command to reset to access mode may comprise a single command, a sequence of commands that may be known to the host device 305 and the controller 320. The sequence may serve as a guard key. Here, host device 305 may transmit a command sequence (e.g., a guard key) to memory device 310. The controller 320 can recognize the command sequence and transition one or more banks or rows from a secure mode to an access mode. Due to the time to transition into secure mode and receive the sequence to re-enter access mode, any victim cells of the memory array 325 may be fully refreshed upon resuming access mode. Thus, any attempted row hammer may cause cycling into and out of the safe mode, but the state of the memory cell may not be compromised.

In addition to entering the safe mode, or in the case where the safe mode is not entered, controller 320 may perform other evasive measures for the detected row hammer condition. For example, where controller 320 does not place the entire bank or multiple banks in self-refresh mode, controller 320 may perform additional background refresh operations on victim rows (e.g., those rows that may be affected by the detected row hammer).

FIG. 4 illustrates an example diagram of a process flow 400 to support a row hammer protection technique for a memory device. The features of process flow 400 may be implemented or performed by a memory device described with reference to fig. 1-3 (e.g., memory device 110, memory die 160, memory die 200, or memory device 310 described with reference to fig. 1-3) or a component of a memory device (e.g., device memory controller 155, local memory controller 165, local memory controller 260, controller 320, or spare row access detection circuitry 335).

At block 405, circuitry associated with the memory device may receive a command from a host device. The command may be a row access command for the memory array. The circuitry can operate according to an access mode, which includes the circuitry executing commands from a host device on a memory array. For example, the circuitry may correspond to portions of the memory interface 315, the controller 320, the redundant row access detection circuitry 335, or the threshold storage 330 of fig. 3.

At block 410, the circuitry may determine whether a threshold associated with an access command of the memory array has been exceeded. The threshold may define a relative number of accesses (e.g., portions of a pattern) that, when exceeded, may create a risk of row hammering causing data corruption. In some cases, the row access command received at block 405 may be associated with one or more rows that experience multiple related accesses. The circuitry may generate a metric related to the access and compare the metric to a threshold. When the circuitry determines that the metric of memory access satisfies the threshold, the circuitry may pass to block 415. Alternatively, when the circuitry determines that the metric does not satisfy the threshold, the circuitry may continue to operate in the access mode, such as at block 430.

At block 415, the circuitry can optionally transmit a notification to the host device indicating that the threshold has been met.

At block 420, the circuitry may transition the memory array from an access mode to a secure mode of operation. The secure mode may prevent additional row accesses to the memory array that increase the probability that bits of the memory array change memory states (e.g., due to a row hammer access pattern). The secure mode may additionally include circuitry completing refresh operations of portions of the memory array operating within the secure mode. In some cases, the circuitry may determine to transition from one secure mode operation to a plurality of different secure mode operations. Each different secure mode operation may include at least a portion of the memory array transitioning into a secure mode. For example, a first secure mode operation may include circuitry to block access commands to a row or group of rows. In a second secure mode of operation, the circuitry may block commands to an entire row address space or bank. In a third secure mode of operation, the circuitry may block commands to the entire memory array. In some examples, (e.g., in the first or second secure modes), portions within the memory array that are not operating within the secure mode may continue normal operation (e.g., according to the access mode). That is, the circuitry may transition a portion of the memory array to a secure mode (e.g., thus blocking access commands to that portion) while executing access commands for the host device to access other portions of the memory array.

At block 425, the controller may identify whether a reset procedure has been performed at the portion of the memory array that has transitioned to secure mode operation. The reset procedure may transition the memory array from the secure mode to the access mode. When the circuitry determines that a reset procedure has been performed, the circuitry may proceed to block 430, where the circuitry may transition one or more portions of the memory array that have been operated in the secure mode into the access mode. Alternatively, when the circuitry determines that a reset procedure has not been performed, the controller may proceed to block 420 (e.g., the circuitry may continue to block access commands to one or more portions of the memory array operating within the secure mode).

FIG. 5 shows an example diagram of a process flow 500 that supports a row hammer protection technique for a memory device. The features of process flow 500 may be implemented or performed by a memory device described with reference to fig. 1-3 (e.g., memory device 110, memory die 160, memory die 200, or memory device 310 described with reference to fig. 1-3) or a component of a memory device (e.g., device memory controller 155, local memory controller 165, local memory controller 260, controller 320, or spare row access detection circuitry 335).

At block 505, circuitry associated with the memory device may receive a command from a host device. The command may be a row access command for the memory array. The circuitry can operate according to an access mode, which includes the circuitry executing commands from a host device on a memory array. For example, the circuitry may correspond to portions of the memory interface 315, the controller 320, the redundant row access detection circuitry 335, or the threshold storage 330 of fig. 3.

At block 510, the circuitry may determine whether a threshold associated with an access command of the memory array has been met. The threshold may define a relative number of accesses (e.g., portions of a pattern) that, when exceeded, may create a risk of row hammering causing data corruption. In some cases, the row access command received at block 505 may be associated with a row that has undergone multiple dependent accesses. The circuitry may generate a metric related to the access and compare the metric to a threshold. When the circuitry determines that the threshold of the memory device has been met, the circuitry may proceed to block 515. Alternatively, when the circuitry determines that the threshold of the memory device is not met, the circuitry may continue to operate in the access mode, such as at block 525.

At block 515, the circuitry may transmit a notification to the host device indicating that the threshold has been met. The transmission of the notification may include, for example, changing a state on a pin (e.g., a multi-function or dedicated pin) coupled with the host device. In some other examples, the notification may be transmitted via sideband port communication, e.g., via an inter-integrated circuit (I2C) bus or a Joint Test Action Group (JTAG) bus. The notification may be transmitted via one or more bits within the data packet. Additionally or alternatively, the notification may be stored in one or more bits of a register, and the host may poll circuitry to determine the value stored in the register (e.g., communicate via a pin or sideband port). The host device may take any number of responsive measures based on the notification. For example, in some cases, the host device may receive the notification and may block commands that may correspond to one or more portions of the memory array indicated by the threshold being met (e.g., not send commands to the memory device), may allow the memory device to continue normal operation (e.g., may determine that the access that generated the notification is legitimate or valid, or determine that continued operation of the memory device is task critical), or may block one or more applications from sending subsequent access commands to the memory device. Additionally or alternatively, the circuitry may continue to block 520.

At block 520, the circuitry may optionally block access commands corresponding to a portion of the memory array. The controller may block the access command for a predetermined amount of time before proceeding to block 525. That is, the controller may transition a portion of the memory array into a secure mode. In some cases, the controller may allow access commands from the host device to portions of the memory array that are not operating in secure mode. That is, the circuitry may operate a portion of the memory array according to the secure mode while operating some other portion of the memory array according to the access mode.

At block 525, the circuitry may transition the entire memory array to an access mode of operation. That is, the controller can resume execution of access commands (e.g., all access commands) issued from the host device to the memory array.

FIG. 6 illustrates an example of a process flow 600 to support a row hammer protection technique for a memory device. In some examples, the process flow 600 may implement aspects of the systems 100 and 300, the memory die 200, and the process flows 400 and 500. The process flow 600 may include operations performed by an application 605, which application 605 may be an example of software running on a processor. The host 610 may be an example of the host device described with reference to fig. 1, 3, 4, and 5. Application 605 may run on a processor separate from host 610. Alternatively, application 605 may run on a processor that is a component of host 610. Memory device 615 may be an example of a memory device described with reference to fig. 1-5 (e.g., memory device 110, memory die 160, memory die 200, or memory device 310).

Application 605 may issue access command 620, which may be a logical or virtual memory access command. Host 610 may execute access command 620, which may cause host 610 to perform a memory function on memory device 615. The host 610 may transmit an access command 625 to the memory device 615. Memory device 615 may operate according to an access mode, which may include executing all access commands received from host 610.

At 630, memory device 615 can detect a redundant row access (e.g., row hammer) condition. In some cases, the memory device 615 may detect a redundant row access condition by determining that a metric (e.g., a number or pattern) associated with an access command including the access command 625 satisfies a threshold associated with the access command for the memory device 615.

The memory device 615 can transmit an indication 635 of the detected redundant row access condition to the host 610. The indication 635 may include an indication of a row, group of rows, or bank associated with the detected redundant row access condition. At 645, memory device 615 can optionally enter a secure mode. The security mode can restrict access to at least one row (e.g., row, group of rows, bank, multiple banks) of a memory array of the memory device 615.

At 640, the host 610 may perform an avoidance measure for the extra row access condition detected by the memory device 615. In some cases, the avoidance measures may include causing memory device 615 to enter a secure mode (e.g., a self-refresh mode). Alternatively, the host 610 may prevent commands executed by the application 605 from generating memory access commands to at least a portion of the memory device 615. That is, the host 610 may not transmit access commands to the memory devices that access the row, group of rows, or bank or banks associated with the detected redundant row access condition. For example, rather than executing an access command to memory device 615, host 610 may process access command 650 that requires access to memory device 615. In some other case, the host 610 may account for a spare row access condition by, for example, temporarily switching to a redundant memory device. That is, any command executed based on application 605 may be transmitted to and/or executed by a memory device other than memory device 615. In some other case, the host 610 may circumvent the extra row access condition by shutting down the application 605 (e.g., pausing execution of commands from the application 605). The shutdown may be temporary (e.g., the host 610 may shut down the application 605 for a predetermined amount of time in reaction to the extra row access condition indication). Additionally or alternatively, the shutdown may occur based on the time of the refresh operation (e.g., the host 610 may shutdown the application 605 within an amount of time necessary to refresh one or more banks within the memory device 615 associated with the detected redundant row access condition).

Host 610 can optionally cause a reset command 655 to be transmitted to memory device 615 to transition memory device 615 from secure mode to access mode. That is, where memory device 615 has entered a secure mode, host 610 may transmit reset command 655 to memory device 615. For example, if a command received from the host 610 is associated with one or more banks corresponding to a detected extra row access condition, a controller associated with the memory device 615 may not execute the command. At 655, the host 610 can transmit a reset command, triggering the memory device 615 to transition from a secure mode to an access mode. The command to reset to the access mode may comprise a single command, or a sequence of commands that may be known to the host 610 and the memory device 615. Memory device 615 may recognize the command sequence and transition from secure mode to access mode (not shown).

Fig. 7 shows a block diagram 700 of circuitry 705 that supports row hammer protection for a memory device as disclosed herein. The circuitry 705 may be examples of aspects of a controller, a memory interface, a spare row access detection circuit, or a threshold storage device as described herein. Circuitry 705 may include a threshold identifier 710, an access command receiver 715, a threshold determination component 720, a mode switch component 725, a command sequence component 730, a refresh mode component 735, a command suppression component 740, and an indication component 745. Each of these modules may communicate with each other directly or indirectly (e.g., via one or more buses).

The threshold identifier 710 may identify thresholds for row accesses of a memory array, the memory array including a set of rows. In some examples, threshold identifier 710 may identify a threshold for a row access of a memory array that includes a set of rows. In some examples, threshold identifier 710 may receive signaling from the host indicating a second threshold for row access, where identifying the threshold is based on the second threshold. In some examples, the threshold identifier 710 may determine the threshold by comparing the second threshold to a third threshold (e.g., a preconfigured threshold) stored in the non-volatile memory. In some examples, the threshold identifier 710 may determine the threshold based on a minimum of the second threshold received from the host and a third threshold stored in the non-volatile memory.

The access command receiver 715 may receive a row access command for the memory array from the host in a first mode of operation. For example, the first mode of operation may be an access mode as described herein. In some examples, the access command receiver 715 may receive a set of row access commands for the memory array from a host. In some examples, the access command receiver 715 may receive a row access command for a second row of the memory array. In some examples, the access command receiver 715 may receive a command sequence from the host indicating a mode of operation based on transmitting an indication to the host.

The threshold determination component 720 may determine, for a row in the set of rows, that a metric for the row access command satisfies a threshold. In some examples, the threshold determination component 720 may determine, for a row in the set of rows, that a pattern or metric of the set of row access commands satisfies a threshold.

The mode switching component 725 may switch the memory array from a first mode of operation to a second mode of operation based on determining that a metric of the row access command satisfies a threshold, wherein the second mode of operation is associated with restricting access to at least one row of a set of rows of the memory array. For example, the second mode of operation may be a secure mode as described herein.

In some examples, the mode switching component 725 may switch the memory array from the second mode to the first mode based on receiving a command sequence. In some examples, the mode switching component 725 may start a timer upon switching the memory array from the first mode to the second mode. In some examples, the mode switching component 725 may cause the memory array to switch from the second mode to the first mode based on expiration of a timer. In some examples, mode switching component 725 may select the second operating mode from the set of operating modes according to a configured setting. In some examples, the mode switching component 725 may cause a second bank of the memory array to operate in the first mode.

The command sequence component 730 can receive a command sequence from a host operating in the second mode to reset the memory array to the first mode.

The refresh mode component 735 can cause a first bank of the memory array associated with the row to operate in a self-refresh mode. In some examples, refresh mode component 735 may cause a bank set of a memory array to operate in a self-refresh mode.

The command suppression component 740 may suppress row access commands to the memory array bank associated with the row. In some examples, command suppression component 740 may suppress access for a second row of the memory array based on receiving a row access command for the second row. In some cases, the second row and the row are the same row.

The indicating component 745 may transmit an indication to the host based on determining that the pattern of the row access command set satisfies the threshold.

FIG. 8 shows a flow diagram illustrating a method 800 of supporting row hammer protection for a memory device as disclosed herein. The operations of method 800 may be implemented by an apparatus as described herein or components thereof. For example, the operations of method 800 may be performed by circuitry as described herein. In some examples, a device may execute a set of instructions to control the functional elements of the device to perform the functions described below. Additionally or alternatively, the device may perform aspects of the functions described below using dedicated hardware.

At 805, the device may identify thresholds for row access of a memory array, the memory array including a set of rows. The operations of 805 may be performed according to methods described herein. In some examples, aspects of the operations of 805 may be performed by the threshold identifier described with reference to fig. 7.

At 810, the device may receive a row access command for the memory array from a host in a first mode of operation. For example, the first mode of operation may be an access mode as described herein. The operations of 810 may be performed according to methods described herein. In some examples, aspects of the operations of 810 may be performed by the access command receiver described with reference to fig. 7.

At 815, the device may determine, for a row in the set of rows, that a metric for the set of row access commands satisfies a threshold. The operations of 815 may be performed according to methods described herein. In some examples, aspects of the operations of 815 may be performed by the threshold determination component described with reference to fig. 7.

At 820, the device may switch the memory array from the first mode of operation to a second mode of operation based on determining that the metric of the row access command satisfies the threshold, wherein the second mode of operation is associated with restricting access to at least one row of the set of rows of the memory array. For example, the second mode of operation may be a secure mode as described herein. The operations of 820 may be performed according to methods described herein. In some examples, aspects of the operations of 820 may be performed by the mode switching component described with reference to fig. 7.

In some examples, an apparatus as described herein may perform one or more methods, such as method 800. The apparatus may include features, means, or instructions (e.g., non-transitory computer-readable medium storing instructions executable by a processor) for: identifying a threshold for a row access of a memory array, the memory array comprising a plurality of rows; in a first mode of operation, receiving a row access command for the memory array from a host; determining, for a row of the plurality of rows, that a metric of the row access command satisfies the threshold; and based at least in part on determining that the metric of the row access command satisfies the threshold, causing the memory array to switch from the first mode of operation to a second mode of operation, wherein the second mode of operation is associated with restricting access to at least one of the plurality of rows of the memory array.

Some examples of the methods and apparatus described herein may additionally include processes, features, devices, or instructions for: receiving, from the host operating in the second mode, a command sequence to reset the memory array to the first mode; and based on receiving the command sequence, causing the memory array to switch from the second mode to the first mode.

In some examples, the methods and apparatus described herein may additionally include processes, features, devices, or instructions for: initiating a timer upon switching the memory array from the first mode to the second mode; and causing the memory array to switch from the second mode to the first mode based on the timer expiring.

Some examples of the methods and apparatus described herein may additionally include processes, features, devices, or instructions for: signaling is received from the host indicating a second threshold of row accesses, wherein identifying the threshold may be based on the second threshold.

In some examples of the methods and apparatus described herein, the threshold identifying a row access may include a process, feature, device, or instruction for: the threshold is determined by comparing the second threshold to a third threshold that may be stored in non-volatile memory.

Some examples of the methods and apparatus described herein may additionally include processes, features, devices, or instructions for: selecting the second operating mode from a set of operating modes according to configured settings.

Some examples of the methods and apparatus described herein may additionally include processes, features, devices, or instructions for: while operating the memory array in the second mode, operating a first bank of the memory array associated with the row in a self-refresh mode; and operating a second bank of the memory array in the first mode.

Some examples of the methods and apparatus described herein may additionally include processes, features, devices, or instructions for: while operating the memory array in the second mode, operating a bank set of the memory array in a self-refresh mode.

Some examples of the methods and apparatus described herein may additionally include processes, features, devices, or instructions for: while operating the memory array in the second mode, a row access command to a bank of the memory array associated with the row is suppressed.

Some examples of the methods and apparatus described herein may additionally include processes, features, devices, or instructions for: receiving a row access command for a second row of the memory array while operating the memory array in the second mode; and inhibiting access for the second row of the memory array based on receiving the row access command for the second row.

In some examples of the methods and apparatus described herein and the non-transitory computer-readable media described herein, the second row and the row may be the same row.

FIG. 9 shows a flow diagram illustrating a method 900 of supporting row hammer protection for a memory device as disclosed herein. The operations of method 900 may be performed by an apparatus as described herein or components thereof. For example, the operations of method 900 may be performed by circuitry as described herein. In some examples, a device may execute a set of instructions to control the functional elements of the device to perform the functions described below. Additionally or alternatively, the device may perform aspects of the functions described below using dedicated hardware.

At 905, the device may identify thresholds for row access of a memory array, the memory array including a set of rows. The operations of 905 may be performed according to methods described herein. In some examples, aspects of the operations of 905 may be performed by the threshold identifier described with reference to fig. 7.

At 910, the device may receive a set of row access commands for the memory array from a host. The operations of 910 may be performed according to methods described herein. In some examples, aspects of the operations of 910 may be performed by the access command receiver described with reference to fig. 7.

At 915, the device may determine, for a row in the set of rows, that a pattern or metric of the set of row access commands satisfies a threshold. The operations of 915 may be performed according to the methods described herein. In some examples, aspects of the operations of 915 may be performed by the threshold determination component described with reference to fig. 7.

At 920, the device may transmit an indication to the host based on determining that the pattern of the row access command set satisfies the threshold. The operations of 920 may be performed according to methods described herein. In some examples, aspects of the operations of 920 may be performed by the indication component described with reference to fig. 7.

In some examples, an apparatus as described herein may perform one or more methods, such as method 900. The apparatus may include features, means, or instructions (e.g., non-transitory computer-readable medium storing instructions executable by a processor) for: identifying a threshold for a row access of a memory array, the memory array comprising a set of rows; receiving a set of row access commands for the memory array from a host; determining, for a row of the set of rows, that a style of the set of row access commands satisfies the threshold; and based on determining that the pattern of the set of row access commands satisfies the threshold, transmitting an indication to the host.

Some examples of the methods and apparatus described herein may additionally include processes, features, devices, or instructions for: determining the threshold based on a minimum of a second threshold received from the host and a third threshold stored in non-volatile memory.

Some examples of the methods and apparatus described herein may additionally include processes, features, devices, or instructions for: based on transmitting the indication to the host, a command sequence is received from the host indicating a mode of operation.

It should be noted that the methods described herein describe possible implementations, and that the operations and steps may be rearranged or otherwise modified, and that other implementations are possible. Further, aspects from two or more methods may be combined.

In some examples, an apparatus or device may perform aspects of the functions described herein using general or special purpose hardware. The apparatus or device may include a memory array having a set of rows; a memory interface coupled with the memory array and a host, the memory interface operable to receive row access commands from the host; and circuitry coupled with the memory array and the memory interface. The circuitry may be operable to execute the row access command on the memory array in a first mode of operation; determining, for a row in the set of rows, that a metric of the row access command satisfies the threshold; and based on determining that the metric of the row access command satisfies the threshold, causing the memory array to switch from the first mode of operation to a second mode of operation, wherein the second mode of operation is associated with restricting access to at least one row of the set of rows of the memory array.

In some examples, the circuitry may be operable to receive, from the host via the memory interface, a command sequence for resetting the memory array to the first mode when operating the memory array in the second mode; and based on receiving the command sequence, causing the memory array to switch to the first mode.

In some examples, the circuitry may be operable to initiate a timer upon switching the memory array from the first mode to the second mode; and causing the memory array to switch from the second mode to the first mode based on the timer expiring.

In some examples, the circuitry may be operable to identify the threshold based on comparing a second threshold received from the host to a third threshold that may be stored in non-volatile memory.

In some examples, the circuitry may be operable to select the second operating mode from a set of operating modes according to a configured setting.

In some examples, the circuitry may be operable to cause a first bank of the memory array associated with the row to operate in a self-refresh mode; and operating a second bank of the memory array in a mode other than the self-refresh mode.

In some examples, the circuitry may be operable to operate a bank set of the memory array in a self-refresh mode.

In some examples, the circuitry may be operable to determine whether to execute the row access command for at least some of a bank set of the memory array.

In some examples, the circuitry may be operable to receive a row access command for a second row of the memory array; and inhibiting access for the second row of the memory array after receiving the row access command. In some examples, the second row and the row may be the same row.

In some examples, the apparatus or device may include a memory array having a set of rows; a memory interface coupled with the memory array and a host, the memory interface operable to receive row access commands from the host; and circuitry coupled with the memory array and the memory interface. The circuitry may be operable to execute the row access command on the memory array; determining, for a row in the set of rows, that executing the row access command satisfies the threshold; and transmitting, via the memory interface, an indication to the host that execution of the row access command satisfies the threshold.

Information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Some figures may illustrate a signal as a single signal; however, one of ordinary skill in the art will appreciate that the signals may represent a signal bus, where the bus may have a variety of bit widths.

The terms "electronic communication," "conductive contact," "connection," and "coupling" may refer to a relationship between components that supports a flow of electrons between the components. Components are considered to be in electronic communication with each other (or in conductive contact with each other, or connected to each other, or coupled to each other) if there are any conductive paths between the components that can support signals flowing between the components at any time. At any given time, the conductive paths between components that are in electronic communication with each other (or in conductive contact with each other, or connected to each other, or coupled to each other) may be open or closed based on the operation of the device that contains the connected components. The conductive path between connected components may be a direct conductive path between components, or the conductive path between connected components may be an indirect conductive path that may include intermediate components such as switches, transistors, or other components. In some cases, signal flow between connected components may be interrupted for a period of time, for example, using one or more intermediate components such as switches or transistors.

The term "isolation" refers to the relationship between components where signals cannot currently flow between components. The components are isolated from each other if there is an open circuit between the components. For example, the components that are spaced apart by a switch positioned between the two components are isolated from each other when the switch is open. When the controller isolates two components, the controller implements the following changes: signals are prevented from flowing between components using conductive paths that previously permitted signal flow.

The devices discussed herein, including memory arrays, may be formed on a semiconductor substrate such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, and the like. In some cases, the substrate is a semiconductor wafer. In other cases, the substrate may be a silicon-on-insulator (SOI) substrate, such as a silicon-on-glass (SOG) or silicon-on-Sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or sub-regions of the substrate may be controlled by doping using various chemistries including, but not limited to, phosphorous, boron, or arsenic. The doping may be performed during the initial formation or growth of the substrate, by ion implantation or by any other doping method.

The switching components or transistors discussed herein may represent Field Effect Transistors (FETs) and include three terminal devices including a source, a drain, and a gate. The terminals may be connected to other electronic components through conductive materials, such as metals. The source and drain may be conductive and may comprise heavily doped, e.g. degenerate, semiconductor regions. The source and drain may be separated by a lightly doped semiconductor region or channel. If the channel is n-type (e.g., most of the carriers are signals), then the FET may be referred to as an n-type FET. If the channel is p-type (i.e., most of the carriers are holes), the FET may be referred to as a p-type FET. The channel may be terminated by an insulated gate oxide. Channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type FET or a p-type FET, respectively, may cause the channel to become conductive. A transistor may be "on" or "activated" when a voltage greater than or equal to the threshold voltage of the transistor is applied to the transistor gate. A transistor may be "off" or "deactivated" when a voltage less than the threshold voltage of the transistor is applied to the transistor gate.

The description set forth herein in connection with the appended drawings describes example configurations and is not intended to represent all examples that may be practiced or within the scope of the claims. The term "exemplary" as used herein means "serving as an example, instance, or illustration," and is not "preferred" or "advantageous over" other examples. The detailed description includes specific details to provide an understanding of the described technology. However, the techniques may be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form in order to avoid obscuring the concepts of the described examples.

In the drawings, similar components or features may have the same reference numerals. In addition, various components of the same type may be distinguished by following the reference label by a dash and a second label that distinguishes among the similar components. If only the first reference label is used in the specification, the description applies to any one of the similar components having the same first reference label, regardless of the second reference label.

Information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

The various illustrative blocks and modules described in connection with the disclosure herein may be implemented or performed with a general purpose processor, a DSP, an ASIC, an FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Other examples and implementations are within the scope of the disclosure and the following claims. For example, due to the nature of software, the functions described above may be implemented using software executed by a processor, hardware, firmware, hardwiring, or a combination of any of these. Features implementing functions may also be physically located at various locations, including being distributed such that portions of functions are implemented at different physical locations. Also, as used herein, including in the claims, "or" as used in a list of items (e.g., a list of items beginning with a phrase such as "at least one of" or "one or more of") indicates an inclusive list, such that, for example, a list of at least one of A, B or C means a or B or C or AB or AC or BC or ABC (i.e., a and B and C). Additionally, as used herein, the phrase "based on" should not be construed as referring to a closed set of conditions. For example, exemplary steps described as "based on condition a" may be based on both condition a and condition B without departing from the scope of the present disclosure. In other words, the phrase "based on" as used herein should likewise be interpreted as the phrase "based at least in part on".

Computer-readable media includes both non-transitory computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A non-transitory storage medium may be any available medium that can be accessed by a general purpose or special purpose computer. By way of example, and not limitation, a non-transitory computer-readable medium may comprise RAM, ROM, electrically erasable programmable read-only memory (EEPROM), Compact Disc (CD) ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other non-transitory medium that may be used to carry or store desired program code means in the form of instructions or data structures and that may be accessed by a general-purpose or special-purpose computer, or a general-purpose or special-purpose processor. Also, any connection is properly termed a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, Digital Subscriber Line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, Digital Subscriber Line (DSL), or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. Disk and disc, as used herein, includes CD, laser disc, optical disc, Digital Versatile Disc (DVD), floppy disk and blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above are also included within the scope of computer-readable media.

The description herein is provided to enable any person skilled in the art to make or use the present disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other variations without departing from the scope of the disclosure. Thus, the disclosure is not intended to be limited to the examples and designs described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.