阅读说明：本技术 内置自测试电路和相关方法 (Built-in self-test circuit and related method ) 是由 J·范欧维尔 于 2020-02-19 设计创作，主要内容包括：公开了内置自测试(BIST)电路和相关方法。示例BIST电路(302)包括状态机(340),当使能信号(362)为有效时,该状态机(340)生成控制信号(366)以将与晶体管相关联的栅极电压(316)从第一电压降低到第二电压,晶体管(304)在第一电压和第二电压下被启用,并且当栅极电压(316)降低到第二电压时,当与晶体管(304)相关联的栅极到源极电压(328)满足阈值时,该状态机(340)使警报信号(364)为有效。(Built-in self-test (BIST) circuits and related methods are disclosed. The example BIST circuit (302) includes a state machine (340), the state machine (340) generating a control signal (366) to reduce a gate voltage (316) associated with a transistor from a first voltage to a second voltage when an enable signal (362) is active, the transistor (304) being enabled at the first voltage and the second voltage, and the state machine (340) asserting an alarm signal (364) when a gate-to-source voltage (328) associated with the transistor (304) satisfies a threshold when the gate voltage (316) is reduced to the second voltage.)

1. A built-in self-test (BIST) circuit comprising:

a state machine to:

generating a control signal to reduce a gate voltage associated with a transistor from a first voltage to a second voltage when an enable signal is active, the transistor being enabled at the first voltage and the second voltage; and

when the gate voltage is reduced to the second voltage, an alarm signal is asserted when a gate-to-source voltage associated with the transistor satisfies a threshold.

2. The BIST circuit of claim 1, further comprising a variable voltage source coupled to the state machine, and wherein the BIST circuit is included in a gate driver circuit, the gate driver circuit coupled to the transistor, and the gate driver circuit comprising:

an amplifier coupled to the variable voltage source and a gate of the transistor, the amplifier to reduce the gate voltage to the second voltage when the state machine reduces a third voltage at an input of the amplifier by adjusting a fourth voltage associated with the variable voltage source.

3. The BIST circuit of claim 1, further comprising a comparator having an output coupled to the state machine, a first input of the comparator measuring the gate voltage, a second input of the comparator measuring a source voltage associated with the transistor, and the comparator asserting a detect signal when the gate-to-source voltage satisfies the threshold.

4. The BIST circuit of claim 1, wherein the state machine invalidates the control signal to increase the gate voltage to the first voltage when the gate-to-source voltage does not satisfy the threshold value after a BIST timer period has expired.

5. The BIST circuit of claim 1, wherein the threshold is a first voltage and the BIST circuit is included in a gate driver circuit, the gate driver circuit coupled to the transistor, and the gate driver circuit comprising:

a switch coupled to a gate of the transistor, the switch coupling the gate to a ground rail when switching from a first state to a second state;

a gate drive power supply coupled to the transistor;

a first comparator to switch the switch to the second state when a third voltage associated with the gate drive power supply satisfies a second threshold;

a second comparator to switch the switch to the second state when a drain voltage associated with the transistor satisfies a third threshold; and

a third comparator to switch the switch to a second state when a source voltage associated with the transistor satisfies a fourth threshold.

6. The BIST circuit of claim 1, wherein the control signal is a first digital signal, and further comprising:

a first analog-to-digital converter (ADC) that measures a drain voltage associated with the transistor by converting the drain voltage to a second digital signal; and

a second ADC to measure a source voltage associated with the transistor by converting the source voltage to a third digital signal.

7. The BIST circuit of claim 6, wherein the control signal is a first control signal, the threshold is a first threshold, and the state machine is to:

determining a drain-to-source voltage associated with the transistor based on a difference between the second digital signal and the third digital signal;

determining that the transistor has no fault short condition when the difference satisfies a second threshold; and

generating a second control signal to increase the gate voltage to the first voltage.

8. The BIST circuit of claim 6, wherein the threshold is a first threshold and the state machine is to:

determining a drain-to-source voltage associated with the transistor based on a difference between the second digital signal and the third digital signal;

detecting a fault short condition associated with the transistor when the difference does not satisfy a second threshold and a BIST timer period has expired; and

when the fault short condition is detected, the alarm signal is asserted.

9. A power conversion system, comprising:

a power conversion stage;

a transistor coupled to the power conversion stage; and

a built-in self-test (BIST) circuit, the BIST circuit comprising a state machine to:

generating a control signal to reduce a gate voltage associated with the transistor from a first voltage to a second voltage when an enable signal is active, the transistor being enabled at the first voltage and the second voltage; and

when the gate voltage is reduced to the second voltage, an alarm signal is asserted when a gate-to-source voltage associated with the transistor satisfies a threshold.

10. The power conversion system of claim 9, wherein the BIST circuit comprises a variable voltage source coupled to the state machine, and further comprising:

an amplifier coupled to the variable voltage source and a gate of the transistor, the amplifier to reduce the gate voltage to the second voltage when the state machine reduces a third voltage at an input of the amplifier by adjusting a fourth voltage associated with the variable voltage source.

11. The power conversion system of claim 9, further comprising a comparator having an output coupled to the state machine, a first input of the comparator measuring the gate voltage, a second input of the comparator measuring a source voltage associated with the transistor, and the comparator asserting a detection signal when the gate-to-source voltage satisfies the threshold.

12. The power conversion system of claim 9, wherein the state machine invalidates the control signal to increase the gate voltage to the first voltage when the gate-to-source voltage does not meet a threshold value after a BIST timer period has expired.

13. The power conversion system of claim 9, wherein the threshold is a first voltage, and further comprising a gate driver circuit comprising:

a switch coupled to a gate of the transistor, the switch coupling the gate to a ground rail when switching from a first state to a second state, the transistor turning off when the gate is coupled to the ground rail, a load disconnected from the power conversion stage when the transistor turns off;

a gate drive power supply coupled to the transistor;

a first comparator to switch the switch to the second state when a third voltage associated with the gate drive power supply satisfies a second threshold;

a second comparator to switch the switch to the second state when a drain voltage associated with the transistor satisfies a third threshold; and

a third comparator to switch the switch to the second state when a source voltage associated with the transistor satisfies a fourth threshold.

14. The power conversion system of claim 9, wherein the control signal is a first digital signal, and the BIST circuit further comprises:

a first analog-to-digital converter (ADC) that measures a drain voltage associated with the transistor by converting the drain voltage to a second digital signal; and

a second ADC to measure a source voltage associated with the transistor by converting the source voltage to a third digital signal.

15. The power conversion system of claim 14, wherein the control signal is a first control signal, the threshold is a first threshold, and the state machine is to:

determining a drain-to-source voltage associated with the transistor based on a difference between the second digital signal and the third digital signal;

determining that the transistor has no fault short condition when the difference satisfies a second threshold; and

generating a second control signal to increase the gate voltage to the first voltage.

16. The power conversion system of claim 14, wherein the threshold is a first threshold and the state machine is to:

determining a drain-to-source voltage associated with the transistor based on a difference between the second digital signal and the third digital signal;

detecting a fault short condition associated with the transistor when the difference does not satisfy a second threshold and a BIST timer period has expired; and

when the fault short condition is detected, the alarm signal is asserted.

17. A gate driver circuit, comprising:

a state machine;

a variable voltage source coupled to the state machine, a first terminal of the variable voltage source coupled to a first current terminal of a transistor;

an amplifier having a first input coupled to the second terminal of the variable voltage source, an output coupled to the gate of the transistor, and a second input coupled to the second current terminal of the transistor; and

a comparator having an output coupled to the state machine, a first input coupled to the output of the amplifier, the first input of the comparator coupled to a gate of the transistor, a second input coupled to the second current terminal of the transistor.

18. The gate driver circuit of claim 17, further comprising a gate drive power supply, a first terminal of the gate drive power supply coupled to a first terminal of the variable voltage source, a first terminal of the gate drive power supply coupled to the first current terminal of the transistor, and a second terminal of the gate drive power supply coupled to a third input of the amplifier.

19. The gate driver circuit of claim 17, wherein the output of the amplifier is coupled to a switch coupled to the gate of the transistor.

20. The gate driver circuit of claim 17, wherein the second input of the amplifier is coupled to a load, the load being at least one of one or more processors associated with a vehicle, a non-volatile memory, or a volatile memory.

Technical Field

The present disclosure relates generally to power converters, and more particularly to built-in self-test circuits and related methods.

Background

Power converter circuits are used in a variety of devices to convert an input voltage to a desired output voltage. For example, a buck converter converts an input voltage to a lower desired output voltage by controlling transistors and/or switches to charge and/or discharge inductors and/or capacitors to maintain the desired output voltage. The power converter may include one or more power switches that may be used to change a current path in the power converter. When functional safety requirements are met, for example, of an automotive electrical system or electronic device, a power switch, such as a Metal Oxide Semiconductor Field Effect Transistor (MOSFET), may be used to disconnect a voltage supply line to a power converter component in the event of a safety critical fault to bring the power converter into a safe state.

Drawings

Fig. 1 is a schematic diagram of monitoring the output voltage of two typical power conversion stages in series.

Fig. 2 is a schematic diagram of monitoring input and output voltages associated with two exemplary MOSFETs in series with an exemplary power conversion stage.

FIG. 3 is a schematic diagram of a first example built-in self-test circuit for detecting a fault short condition associated with an example MOSFET.

FIG. 4 depicts a first example timing diagram and a second example timing diagram corresponding to the operation of the first example built-in self-test circuit of FIG. 3.

FIG. 5 is a schematic diagram of a second example built-in self-test circuit for detecting a fault short condition associated with the example MOSFET of FIG. 3.

FIG. 6 depicts third and fourth example timing diagrams corresponding to the operation of the second example built-in self-test circuit of FIG. 5.

FIG. 7 is a schematic diagram of a third example built-in self-test circuit for detecting a fault short condition associated with the example MOSFET of FIG. 3.

FIG. 8 depicts fifth and sixth example timing diagrams corresponding to the operation of the third example built-in self-test circuit of FIG. 7.

FIG. 9 depicts an example state diagram of operation of the example BIST state machine corresponding to FIG. 3, FIG. 5, and/or FIG. 7.

FIG. 10 is a flow diagram representative of example machine readable instructions that may be executed to implement the example BIST state machine of FIG. 3, FIG. 5, and/or FIG. 7 to detect a fault short condition associated with the example MOSFET of FIG. 3.

The figures are not drawn to scale. Generally, the same reference numbers will be used throughout the drawings and the following written description to refer to the same or like parts. The connecting lines or connectors shown in the various figures presented are intended to represent example functional relationships and/or physical or logical couplings between the various elements. The term "coupled," as used herein, is defined as connected, directly or indirectly (e.g., through one or more intervening structures and/or layers).

The descriptors "first", "second", "third", etc. are used herein when identifying a plurality of elements or components that may be referred to individually. Unless otherwise specified or understood based on their context of use, such descriptors are not intended to be given any priority or chronological meaning, but merely as labels to refer to a plurality of elements or components, respectively, to facilitate understanding of the disclosed examples. In some examples, the descriptor "first" may be used to refer to an element in a particular embodiment, while different descriptors (such as "second" or "third") may be used in the claims to refer to the same element. In such cases, it should be understood that such descriptors are used only for convenience in referring to a plurality of elements or components.

Detailed Description

A switch-mode power converter (e.g., a boost converter, a buck-boost converter, etc.) or a power conversion stage is used to convert a first voltage (e.g., an input voltage) to a second voltage (e.g., an output voltage). Such power converters include a switching network including one or more switching transistors coupled to a switching node that is switched to form a circuit arrangement to direct current through an energy storage inductor and/or charge/discharge an output capacitor. Such circuit arrangements supply a load current and regulate the output voltage to remain substantially stable at the second voltage.

Some typical power conversion systems include aspects that meet functional safety requirements. Functional safety requirements may be based on international organization for standardization (ISO)26262, International Electrotechnical Commission (IEC)61508, and the like. ISO 26262 is an international standard for the functional safety of electrical and/or electronic systems in mass-produced automobiles. IEC 61508 is an international standard corresponding to application, design, deployment and maintenance of automatic protection or safety related systems.

When supplying voltage for power conversion systems that meet functional safety requirements (e.g., power conversion systems in aircraft, land vehicles, marine vehicles, etc.), power MOSFETs are often used as power switches to turn off voltage supply lines to components of the power conversion system. In case of a safety critical fault, the power MOSFET opens the voltage supply line in order to bring the power conversion system into a safe state. For example, when the power supply input voltage is over-voltage due to a power failure of the ECU, a power MOSFET in an Electronic Control Unit (ECU) in the vehicle may disconnect the voltage supply line to the ECU.

In some typical power conversion systems, the power MOSFET may have a fault short circuit fault (e.g., a fault short fault, a fault short condition, etc.) that prevents the power MOSFET from opening the voltage supply line to the relevant component of the power conversion system to stop power flow. A fault short may correspond to a short between the source and drain of the power MOSFET (e.g., a short circuit fault, a short circuit condition, etc.). For example, the drain-to-source resistance of a damaged or failed power MOSFET may be a resistance in the range of 0-10 ohms. In such examples, even if the power MOSFET is turned off, which should actually decouple the drain and source to prevent current flow, the low drain-to-source resistance still facilitates current flow through the power MOSFET. Thus, a low drain-to-source resistance indicates that there is a short circuit between the source and drain of the power MOSFET. The low drain to source resistance provides a current flow path even when the power MOSFET is off. Such a fault short is a potential defect in the power conversion system that needs to be detected or mitigated to meet functional safety requirements of ISO 26262, IEC 61508, etc.

Some typical power conversion systems may use two power converters in series and monitor the output voltage of each power converter to mitigate a fault short. In such typical systems, the power converter shuts down if either the first output associated with the first power converter or the second output associated with the second power converter is greater than a voltage threshold. However, using two power converters in series does not detect a fault short circuit associated with any transistor of the power converters, but merely determines an error in the output of the power converters. Thus, using two power converters in series increases cost, reduces power efficiency, and reduces the available area in the integrated circuit that can be used for other circuitry, and thus reduces the number of functions that the integrated circuit can provide.

Some typical power conversion systems may include a power converter in series with two power MOSFETs in series to mitigate a fault short. Such typical systems monitor the input voltage of a first one of the power MOSFETs and the output voltage of a second one of the power MOSFETs. When the input voltage or the output voltage is greater than the voltage threshold, the power converter and the power MOSFET are turned off. However, such typical power conversion systems do not detect a fault short in a MOSFET, but rather mitigate the effect after a fault short occurs in one of the two power MOSFETs. Such typical systems assume that there is no common root cause for both power MOSFETs to fail short at the same time.

Examples disclosed herein include a built-in self-test (BIST) circuit and related methods to detect a fault short circuit fault in a power MOSFET. In some disclosed examples, the power MOSFET is in a circuit having one or more power conversion stages. The example BIST circuit detects a fault short circuit fault of a power MOSFET with reduced power loss and improved power efficiency compared to typical power conversion systems. In some disclosed examples, the gate driver circuit includes a BIST circuit. When the BIST circuit is activated, the gate driver circuit controls the voltage of the gate of the power MOSFET to drive the drain-to-source voltage (V) of the power MOSFET_DS) Adjusted to the target voltage.

In some disclosed examplesIn which the BIST circuit includes a comparator to respond to the regulation V_DSTo detect the gate-to-source voltage (V)_GS) Whether or not to cross zero volts (e.g., V)_GSBecomes negative, V_GSZero crossing (zero crossing) is performed). When the comparator detects V_GSThe example BIST circuit detects a fault short fault in the power MOSFET. In other examples, the comparator does not detect V after expiration of a specified time interval (e.g., after the BIST timer expires, after a BIST timer period has elapsed, etc.)_GSThe BIST circuit may determine that there is no fault short fault associated with the power MOSFET. In other examples, V is when after expiration of a specified time interval_DSNot satisfying a threshold (e.g., V)_DSThreshold), the BIST circuit may determine that there is no fault short fault associated with the power MOSFET.

In some disclosed examples, the example gate driver circuit includes a BIST circuit that adjusts V when the BIST circuit is adjusting V_DSWhen the drain voltage (V)_D) Or source voltage (V)_S) The example gate driver circuit detects an overvoltage fault at an output of one of the one or more power conversion stages when at least one of the thresholds is met. In some disclosed examples, the gate driver circuit turns off the power MOSFET upon detection of an overvoltage at the output of the power conversion stage. By turning off the power MOSFET, the example gate driver circuit reduces damage to the power MOSFET and/or improves (e.g., increases, prolongs, etc.) the operating life of the power MOSFET. By turning off the power MOSFETs when one or more faults occur in the power conversion system, the example gate driver circuit may facilitate operation of the functional safety system by providing a supply voltage that is lower than a limited maximum operating voltage of the functional safety system.

Fig. 1 is a schematic diagram of a first exemplary power conversion system 100 including a first exemplary power conversion stage 102 coupled in series to a second exemplary power conversion stage 104. The first power conversion stage 102 converts a first input voltage (Vbat) associated with the power supply 106 to a first output voltage (Vintm). The first power conversion stage 102 includes a first N-channel MOSFET 108, a second N-channel MOSFET 110, a first inductor 112, and a first capacitor 114. In operation, the first N-channel MOSFET is turned on to facilitate current flow from the power supply 106 to the first inductor 112. The first N-channel MOSFET is turned off and the second N-channel MOSFET is turned on to facilitate current flow from the first inductor 112 to the first capacitor 114 to charge the first capacitor 114 to Vintm.

In fig. 1, Vintm is the voltage input to the second power conversion stage 104. The second power conversion stage 104 includes a third N-channel MOSFET 116, a fourth N-channel MOSFET 118, a second inductor 120, and a second capacitor 122. In operation, third N-channel MOSFET 116 is turned on to facilitate current flow from first capacitor 114 to second inductor 120. The third N-channel MOSFET 116 is turned off and the fourth N-channel MOSFET 118 is turned on to facilitate current flow from the second inductor 120 to the second capacitor 122 to charge the second capacitor 122 to Vsys. Therefore, Vsys is supplied to the load 124. In fig. 1, the load 124 has a limited maximum operating voltage to meet functional safety requirements.

In fig. 1, the first power conversion system 100 includes a voltage monitoring circuit 126 to monitor the output voltage of the power conversion stages 102, 104. The voltage monitoring circuit 126 includes a first comparator 128 that monitors Vintm and a second comparator 130 that monitors Vsys. First comparator 128 compares Vintm to a first reference voltage (Vref 1). The second comparator 130 compares Vsys with a second reference voltage (Vref 2). The voltage monitoring circuit 126 turns off the power conversion stages 102, 104 if the first comparator 128 determines that Vintm is greater than Vrefl or the second comparator 130 determines that Vsys is greater than Vref 2.

Disadvantageously, the first power conversion system 100 of fig. 1 does not detect a fault short associated with the N-channel MOSFETs 108, 110, 116, 118 when the voltage monitoring circuit 126 detects a voltage error associated with the output voltages Vintm and Vsys. The first power conversion system 100 of fig. 1 has low power efficiency due to heat losses associated with the second power conversion stage 104. The first power conversion system 100 of fig. 1 increases cost due to the addition of the second power conversion stage 104.

Fig. 2 is a schematic diagram of monitoring a first output voltage (Vsys) and a second output voltage (Vcca) associated with a second exemplary power conversion system 200. The second power conversion system 200 includes the power supply 106, the first power conversion stage 102, and the voltage monitoring circuit 126 of fig. 1. In fig. 2, the first power conversion stage 102 is coupled to a first exemplary gate drive power supply 202 and a fifth exemplary N-channel MOSFET 204. Fifth N-channel MOSFET 204 is coupled in series to second exemplary gate drive power supply 206 and sixth exemplary N-channel MOSFET 208. In fig. 2, a first gate drive power supply 202 provides a first current to a fifth N-channel MOSFET 204 via a first exemplary switch 210. In fig. 2, the second gate drive power supply 206 supplies a second current to the sixth N-channel MOSFET208 via a second exemplary switch 212.

In operation, the first comparator 128 of the voltage monitoring circuit 126 determines whether Vsys is greater than Vrefl. Second comparator 130 of voltage monitoring circuit 126 determines whether Vcca is greater than Vref 2. In fig. 2, Vcca corresponds to the output voltage of the sixth N-channel MOSFET 208. If the first comparator 128 determines that Vsys is greater than Vrefl or the second comparator 130 determines that Vcca is greater than Vref2, the voltage monitoring circuit 126 turns off the first power conversion stage 102 and disconnects the gate drive power supplies 202, 206 from the fifth N-channel MOSFET 204 and the sixth N-channel MOSFET 208. In fig. 2, the voltage monitoring circuit 126 disconnects the gate drive power supplies 202, 206 by turning off the switches 210, 212.

Disadvantageously, the second power conversion system 200 of fig. 2 does not detect a short-circuit fault associated with the first and second N-channel MOSFETs 108 and 110 or the fifth and sixth N-channel MOSFETs 204 and 208 when the voltage monitoring circuit 126 detects voltage errors associated with Vsys and Vcca. The second power conversion system 200 of fig. 2 has low power efficiency due to heat losses associated with the fifth N-channel MOSFET 204 and the sixth N-channel MOSFET 208. The second power conversion system 200 of fig. 2 adds cost due to the addition of the gate drive power supplies 202, 206, the fifth and sixth N-channel MOSFETs 204, 208, and the switches 210, 212. The second power conversion system 200 of fig. 2 includes a fifth N-channel MOSFET 204 and a sixth N-channel MOSFET208 based on the assumption that the voltage error associated with Vcca is not based on a common root cause that causes both the fifth N-channel MOSFET 204 and the sixth N-channel MOSFET208 to fail short at the same time.

FIG. 3 is a schematic diagram of a third example power conversion system 300 including a first example built-in self-test (BIST) circuit 302 for detecting a fault short condition associated with an example transistor 304. In FIG. 3, a first example gate driver circuit 303 includes a first BIST circuit 302. The first gate driver circuit 303 is an integrated circuit (e.g., an integrated circuit chip). Alternatively, the first gate driver circuit 303 may be implemented using hardware logic, machine-readable instructions, a hardware-implemented state machine, and/or any combination thereof.

The third power conversion system 300 includes the power supply 106 and the first power conversion stage 102 of fig. 1. Further depicted as coupled to the third power conversion system 300 is the load 124 of fig. 1. Alternatively, the load 124 may not be coupled to the third power conversion system 300. In fig. 3, the transistor 304 is a power switch device. In fig. 3, transistor 304 is an N-channel enhancement MOSFET or MOSFET 304. In some examples, the first power conversion stage 102, the first gate driver circuit 303, and the MOSFET304 are included in the same integrated circuit. Alternatively, one or more of the first power conversion stage 102, the first gate driver circuit 303 and/or the MOSFET304 may be included in a separate integrated circuit.

The MOSFET304 includes an example gate (e.g., gate terminal) 306, an example drain (e.g., current terminal, drain terminal, etc.) 308, and an example source (e.g., current terminal, source terminal, etc.) 310. In fig. 3, MOSFET304 has an associated example fault short resistance 312 corresponding to the drain-to-source resistance of MOSFET 304. In the illustrated example of fig. 3, the drain 308 of the MOSFET304 is coupled to the first inductor 112 and the first capacitor 114 of the first power conversion stage 102 at the example power conversion stage output node 314. The source 310 of the MOSFET304 is coupled to the load 124.

In some examples, the load 124 is associated with a vehicle (e.g., an air vehicle, a land vehicle (e.g., an automobile), a marine vehicle, etc.). For example, the load 124 may be one or more components included in an ECU, and/or more generally, the load 124 may be an ECU of a vehicle. In such an example, the load 124 may correspond to one or more processors, non-volatile memory, etc., included in and/or otherwise associated with the ECU. In fig. 3, the load 124 has a limited maximum operating voltage. For example, the load 124 may be designed to operate or run to operate to meet and/or otherwise meet functional safety requirements, specifications, standards, and/or the like. Alternatively, the load 124 may not be limited to a limited maximum operating voltage.

In the illustrated example of fig. 3, the first gate driver circuit 303, and/or more generally, the third power conversion system 300, includes a first BIST circuit 302 to perform BIST on a MOSFET304, and the first BIST circuit 302, when activated or enabled, will control a voltage (e.g., gate voltage, V) of a gate 306_G316, etc.) to couple a voltage across the drain 308 and source 310 (e.g., drain-to-source voltage, V_DS318, etc.) to an example target voltage 319 (e.g., target drain-to-source voltage 319, target V_DS319, etc.). For example, the first BIST circuit 302 can execute a fault short BIST or BIST to detect a fault short condition associated with the MOSFET 304. In FIG. 3, target V_DS319 corresponds to the voltage across the variable voltage source 342.

In FIG. 3, V_DS318 corresponds to an example drain voltage (V) at an example drain node 322_D)320 and an example source voltage (V) at an example source node 326_S)324 of the voltage difference. By adjusting V_DS318, the first BIST circuit 302 may determine a voltage across the gate 306 and the source 310 (e.g., a gate-to-source voltage, V)_GS328, etc.) whether to perform a zero-crossing. For example, the first BIST circuit 302 may adjust V in response to the first BIST circuit 302_DS318 to determine V_GS328 from a positive voltage value to a negative voltage value. In FIG. 3, V_GS328 corresponds to V_G316 and V_S324 of the voltage difference.

In the illustrated example of fig. 3, the first gate driver circuit 303 includes a first example comparator 332, a second example comparator 334, a third example comparator 336, an example switch 338, an example gate drive power supply 344, and an example amplifier 346. In FIG. 3, the first BIST circuit 302 includes a first example state machine 340, an example variable voltage source 342, and a fourth example comparator 348.

In some examples, first BIST circuit 302 is an integrated circuit. For example, the first BIST circuit 302 may be included in a first integrated circuit, and the first comparator 332, the second comparator 334, the third comparator 336, the switch 338, the gate drive power supply 344, the amplifier 346, the first example voltage divider 354, the second example voltage divider 358, and the third example voltage divider 360 are included in a second integrated circuit, where the first and second integrated circuits are included in a third integrated circuit corresponding to the first gate driver circuit 303 or the power conversion system 300.

In the illustrated example of fig. 3, the first gate driver circuit 303 facilitates switching operation of the MOSFET304 and, in some examples, triggers BIST of the MOSFET 304. For example, the first gate driver circuit 303 may be implemented by enabling V_GS328 is above the turn-on voltage threshold of MOSFET304 to direct amplifier 346 to increase V_G316 to turn on the MOSFET 304. In other examples, the first gate driver circuit 303 may be implemented by enabling V_GS328 below the off voltage threshold of MOSFET304 to direct amplifier 346 to reduce V_G316 to turn off the MOSFET 304.

In the illustrated example of fig. 3, the first state machine 340 is a hardware-implemented finite state machine. For example, first state machine 340 may correspond to one or more microcontrollers (e.g., one or more analog microcontrollers) that include analog peripherals for sensing and/or measurement functions. In such an example, the first state machine 340 may include one or more Programmable Gain Amplifiers (PGAs), one or more comparators, one or more transimpedance amplifiers, one or more operational amplifiers, and the like, and/or combinations thereof. In some examples, the first state machine 340 may correspond to one or more controllers (e.g., microcontrollers) that execute machine-readable instructions. In some examples, first state machine 340 may be implemented by one or more analog or digital circuits, logic circuits, programmable processor(s), programmable controller(s), graphics processing unit(s) (GPU), digital signal processor(s) (DSP), application specific integrated circuit(s) (ASIC), programmable logic device(s) (PLD), and/or field programmable logic device(s) (FPLD).

In the illustrated example of fig. 3, a variable voltage source 342 is coupled to the first state machine 340. For example, the variable voltage source 342 may be coupled to one or more pins of the first state machine 340. In FIG. 3, variable voltage source 342, when enabled, generates a voltage across variable voltage source 342 corresponding to target V_DS319 (e.g., 50 millivolts (mV), 100mV, 200mV, etc.). For example, when the target V_DS319 is 100mV and Vsys is 5 volts (V), variable voltage source 342, when enabled, may reduce the voltage at the non-inverting input (e.g., non-inverting voltage input) of amplifier 346 from 5V to 4.9V (e.g., 4.9V-Vsys-target V)_DS319 (e.g., 4.9V-5V-0.1V)). In such an example, amplifier 346 may lower V_G316 to attempt to reduce the difference between the inputs of the amplifier 346 to zero.

In some examples, the variable voltage source 342 is a variable resistor and the first state machine 340 may output a fixed amount of current to generate a variable voltage. In some examples, the variable voltage source 342 is a resistor with a fixed resistance and the first state machine 340 may output a variable amount of current to generate a variable voltage. In fig. 3, the gate driving power supply 344 is a fixed voltage source. For example, the gate drive power supply 344 may output a voltage 12V higher than the output voltage (e.g., Vsys) of the first power conversion stage 102. In such an example, when Vsys is 5V, the gate driving power supply 344 may output a voltage of about 17V. Alternatively, the gate driving power supply 344 may output a different voltage. Alternatively, the gate driving power supply 344 may be implemented using any kind of setting converter. For example, the gate drive power supply 344 may be a capacitive charge pump, an inductive boost converter, or the like.

In the illustrated example of fig. 3, amplifier 346 is an operational amplifier. The non-inverting input of amplifier 346 is coupled to the negative terminal of variable voltage source 342, andan inverting input (e.g., an inverting voltage input) of the amplifier 346 is coupled to a fourth comparator 348 at a first example node 350. The inverting input of amplifier 346 has a voltage corresponding to V_S324 of the voltage. The power input terminal of the amplifier 346 is coupled to the positive terminal of the gate drive power supply 344 and the output of the amplifier 346 is coupled to the gate 306 of the MOSFET304 via the switch 338. In operation, the amplifier 346 may output a voltage that is close to the voltage associated with the gate drive power supply 344 when the non-inverting input is greater than the inverting input. When the inverting input is greater than the non-inverting input, the amplifier 346 may output a voltage that approximates the voltage associated with the example ground rail 356. In fig. 3, the fourth comparator 348 is a schmitt trigger. Alternatively, the fourth comparator 348 may be any other type of comparator. A first input of a fourth comparator 348 is coupled to a first node 350 and a second input of the fourth comparator 348 is coupled to the output of the amplifier 346 at a second example node 352.

In the illustrated example of fig. 3, the first comparator 332 and the second comparator 334 are voltage comparators. In fig. 3, the output terminal of the first comparator 332 is coupled to the output terminal of the second comparator 334. The first comparator 332 compares (1) the output voltage of the gate driving power supply 344 scaled by the first voltage divider 354 to generate a first comparison voltage with (2) the first reference voltage (Vref _ Vsys). Vref _ Vsys corresponds to a reference voltage. The voltage based on the product of Vref _ Vsys and the first scaling factor associated with the first voltage divider 354 corresponds to a voltage threshold above which is indicative of a failure of the gate drive power supply. For example, if the gate drive power supply 344 fails and provides a higher than typical gate drive voltage to the power input terminal of the amplifier 346, the first comparator 332 may assert a logic high to switch the switch 338. By switching the switch 338, V_G316 is pulled down to ground rail 356 to turn MOSFET304 off. For example, the first comparator 332 may switch the switch 338 based on the output of the gate drive power supply 344 scaled by the first voltage divider 354 being greater than a voltage threshold (e.g., Vref _ Vsys).

In the illustrated example of fig. 3, the second comparator 334 scales (1) by the second voltage divider 358 to generateThe Vsys of the second comparison voltage is compared with (2) Vref _ Vsys. The voltage based on the product of Vref _ Vsys and the second scaling factor associated with the second voltage divider 358 corresponds to a voltage threshold above which a fault of the first power conversion stage 102 is indicated. When Vsys, scaled by second voltage divider 358, is greater than Vref _ Vsys, second comparator 334 asserts a logic high to toggle switch 338. By switching the switch 338, V_G316 are pulled to the ground rail 356 to turn off the MOSFET 304. For example, if the first power conversion stage 102 fails and generates a higher than typical Vsys, the second comparator 334 may switch the switch 338 based on the Vsys scaled by the second voltage divider 358 being greater than a voltage threshold (e.g., Vref _ Vsys).

In fig. 3, the third comparator 336 compares (1) the source voltage 324 (also denoted Vcca) scaled by the third voltage divider 360 to generate a third comparison voltage with (2) the second reference voltage (Vref _ Vcca). The voltage based on the product of Vref _ Vcca and the third scaling factor associated with the third voltage divider 360 corresponds to a voltage threshold above which a fault of the first power conversion stage 102 is indicated. For example, if the first power conversion stage 102 fails and generates a higher than typical Vsys, and the second comparator 334 fails to detect the failure, then V_S324 will be higher than typical Vcca and the third comparator 336 may assert a logic high to change the state of the switch 338. By changing the state of switch 338, V_G316 are pulled to the ground rail 356 to turn off the MOSFET 304. In fig. 3, the third comparator 336 is a voltage comparator. Alternatively, the third comparator 336 may be any other type of comparator.

In some examples, the first state machine 340 triggers, enables, and/or otherwise activates the BIST in response to the example enable signal 362. For example, the enable signal 362 may be a control signal, a BIST trigger (e.g., a BIST trigger signal), a BIST enable signal, and the like. In some examples, the enable signal 362 is generated by an external controller, state machine, or the like. In other examples, the enable signal 362 may be generated by an engine ignition or powertrain ignition operation when the load 124 is associated with a vehicle. For example, when a driver or user of an automobile turns on an ignition, the ignition may assert a logic high for enabling signal 362.

In fig. 3, the first state machine 340 generates an example alarm signal 364 to indicate that the MOSFET304 has a fault short. For example, when a fault short of the MOSFET304 is detected, the fourth comparator 348 may assert the example fault short detection signal 368 (e.g., assert a signal corresponding to a logic high). In such an example, when V_G316 is less than V_S324, this corresponds to V_GS328 is negative (e.g., MOSFET304 performs a zero-crossing), the fourth comparator 348 may assert the fault short detect signal 368. In response to the fourth comparator 348 asserting the fault short detection signal 368, the first state machine 340 generates an alarm signal 364. In some examples, the alert signal 364 is transmitted to a controller, hardware-implemented state machine, logic circuitry, etc., coupled to the first gate driver circuit 303 and/or otherwise in circuit with the first gate driver circuit 303. For example, the first state machine 340 can assert the alarm signal 364 when a fault short of the MOSFET304 is detected.

In operation, amplifier 346 passes output V_G316 is such that V_GS328 is greater than the turn-on voltage threshold of the MOSFET304 to turn on the MOSFET 304. When MOSFET304 is on and the BIST is not performed, V_DS318 is approximately zero because V_D320 and V_S324 is approximately Vsys. Thus, the non-inverting and inverting inputs of amplifier 346 are approximately Vsys. When the enable signal 362 corresponds to a logic high, the first state machine 340 enables BIST of the MOSFET 304. In response to the enable signal 362 being asserted, the first state machine 340 generates an example control signal 366 to direct the variable voltage source 342 to generate the target V across the variable voltage source 342_DS319 and causes the voltage at the non-inverting input of the amplifier 346 to decrease by the target V_DS 319。

When the non-inverting input of amplifier 346 has a voltage less than the voltage of the inverting input of amplifier 346, amplifier 346 attempts to reduce V by_G316 (e.g., from a first voltage near the voltage of the gate drive power supply 344 to a second voltage near the voltage of the ground rail 356) will be V_DSAdjustment to target V_DS319. If MOSFET304 does not have a fault short, amplifier 346 decreases V_G316, this makes V_GS328 decrease until V_DS318 to the target V_DS319. When V is_DS318 to target V_DS319 amplifier 346 stops decreasing V_G316 and/or otherwise convert V_G316 are maintained at the current voltage level. After the amount of time associated with the BIST timer (e.g., the BIST timer period) has elapsed, the first state machine 340 determines that the MOSFET304 has no fault short and turns off the control signal 366. For example, because V is when the BIST timer has elapsed_G316 is greater than V_S324, the fourth comparator 348 may not assert the fault short detection signal 368. In some examples, the first state machine 340 includes a counter to perform and/or otherwise facilitate operation of the BIST timer and to determine whether a BIST timer period has elapsed.

If MOSFET304 does fail shorted, amplifier 346 decreases V_G316, this makes V_GS328 decrease until V_G316 is close to the voltage associated with the ground rail 356. For example, amplifier 346 may reduce V_G316 until amplifier 346 cannot lower V any further_G316 due to V_DS318 will not increase to the target V_DS319. For example, V_DS318 may not increase to the target V_DS319 since MOSFET 318 has a fault short (e.g., fault short resistance 312 is in the range of 0-10 ohms, 0-20 ohms, etc.) and V_G316 does not result in V_DS318, respectively. At the reduction of V_GAt time V of 316_G316 down to V_SBelow 324, V may occur_GS328. For example, the fourth comparator 348 may detect a zero crossing and assert the fault short detection signal 368 and transmit the asserted fault short detection signal to the first state machine 340. When the first state machine 340 determines that the MOSFET304 has a fault short based on the assertion of the fault short detection signal 368, the first state machine 340 asserts the alarm signal 364.

Although an example manner of implementing the first gate driver circuit 303 is illustrated in fig. 3, one or more of the elements, processes and/or devices illustrated in fig. 3 may be combined, divided, rearranged, omitted, eliminated and/or implemented in any other manner. Further, the first comparator 332, the second comparator 334, the third comparator 336, the switch 338, the first state machine 340, the variable voltage source 342, the gate drive power supply 344, the amplifier 346, the fourth comparator 348, the first voltage divider 354, the second voltage divider 358, the third voltage divider 360, and/or more generally, the first gate driver control circuit 303 of fig. 3 may be implemented by hardware, software, firmware, and/or any combination of hardware, software, and/or firmware. Thus, for example, any of first comparator 332, second comparator 334, third comparator 336, switch 338, first state machine 340, variable voltage source 342, gate drive power supply 344, amplifier 346, fourth comparator 348, first voltage divider 354, second voltage divider 358, third voltage divider 360, and/or more generally, first gate driver circuit 303 may be implemented by one or more analog or digital circuits, logic circuits, programmable processor(s), programmable controller(s), GPU(s), DSP(s), ASIC(s), PLD(s), and/or FPLD(s). When reading any device claims or system claims of this patent to encompass a purely software and/or firmware implementation, at least one of the first comparator 332, the second comparator 334, the third comparator 336, the switch 338, the first state machine 340, the variable voltage source 342, the gate drive power supply 344, the amplifier 346, the fourth comparator 348, the first voltage divider 354, the second voltage divider 358, the third voltage divider 360, and/or more generally, the first gate driver circuit 303 is hereby expressly defined to include a non-transitory computer readable memory device or storage disk containing software and/or firmware, such as non-volatile memory (e.g., Read Only Memory (ROM), Electrically Erasable Programmable Read Only Memory (EEPROM), flash memory, etc.), volatile memory (e.g., Synchronous Dynamic Random Access Memory (SDRAM), Dynamic Random Access Memory (DRAM), etc., and/or any other type of Random Access Memory (RAM) device), etc. Still further, the first gate driver circuit 303 of fig. 3 may include one or more elements, processes and/or devices in addition to or in place of those illustrated in fig. 3, and/or may include more than one of any or all of the illustrated elements, processes and devices. As used herein, the phrase "communication" (including variations thereof) encompasses direct communication and/or indirect communication through one or more intermediate components, and does not require direct physical (e.g., wired) communication and/or continuous communication, but also includes selective communication at periodic intervals, predetermined intervals, aperiodic intervals, and/or one-time events.

FIG. 4 depicts a first example timing diagram 400 and a second example timing diagram 402 corresponding to the operation of the first BIST circuit 302 and/or, more generally, the first gate driver circuit 303 of FIG. 3. In FIG. 4, a first timing diagram 400 corresponds to the operation of the first BIST circuit 302 when the MOSFET304 of FIG. 3 has no fault short. In FIG. 4, the second timing diagram 402 corresponds to the operation of the first BIST circuit 302 when the MOSFET304 has a fault short. Depicted in the timing diagrams 400, 402 of FIG. 4 is the target V of FIG. 3_DS 319、V_GS 328、V_DS318, and a fault short detection signal 368.

In the first timing diagram 400, at a first example time (T)₁) At 404, the enable signal 362 of fig. 3 may be active (e.g., based on car ignition). In response to the assertion, the first state machine 340 of FIG. 3 may trigger the BIST to direct the variable voltage source 342 of FIG. 3 by generating the control signal 366 of FIG. 3 to increase the voltage across the variable voltage source 342 to the target V_DS319. In the first timing diagram 400, at a first time 404, the amplifier 346 of FIG. 3 may decrease V of FIG. 3_G316 to try to get V_DS318 to a target V_DS319. In the first timing diagram 400, V_GS328 corresponds to the voltage of the gate drive power supply 344 of fig. 3.

In the first timing diagram 400, at a second exemplary time (T)₂) At 406, V_DS318 to reach V corresponding to BIST_DS318 target V of voltage level_DS319. In the first timing diagram 400The amplifier 346 decreases V from the first time 404 to the second time 406_G316 so that V_GS328 decreases from a first voltage at a first time 404 to a second voltage at a second time 406. At a second time 406, amplifier 346 stops decreasing V_G316 to convert V_GS328 is maintained at the second voltage. In the first timing diagram 400, V_GS328 is positive at the first time 404 and the second time 406. Therefore, no zero crossing of the MOSFET304 occurs in the first timing diagram.

In the first timing diagram 400, at a third exemplary time (T)₃) At 408, the first state machine 340 may deactivate the control signal 366 so that at a fourth example time (T)₄) Target V of variable voltage source 342 at 410_DS319 to zero. At a third time 408, the amplifier 346 increases V_G316 so that V_GS328 increase back to the voltage level before triggering the BIST (e.g., V at first time 404_GS328). In the first timing diagram 400, an example BIST timer period 409 begins at a first time 404 and ends at a third time 408. For example, the first state machine 340 may start the BIST timer period 409 (e.g., trigger or instantiate the BIST timer period 409 using a counter included in the first state machine 340) in response to asserting the control signal 366 and deassert the control signal 366 when the BIST timer period 409 ends. For example, the first state machine 340 may activate the fault shorts BIST at the first time 404 and terminate the fault shorts at the third time 408. In the first timing diagram 400, the fault short detection signal 368 is not valid because V_GS328 have no zero crossing during the BIST timer period 409.

In the second timing diagram 402, at a first example time (T)₁) At 412, enable signal 362 may be active (e.g., based on car ignition). In response to this assertion, the first state machine 340 may direct the variable voltage source 342 to increase the voltage to the target V by generating a control signal 366_DS319 to trigger a BIST. In the second timing diagram 402, at a first time 412, a BIST timer period 409 begins. In the second timing diagram 402, at a first time 412, the amplifier 346 can lower V_G316 to try to get V_DS318 to a target V_DS 319。

In the second timing diagram 402, at a second example time (T)₂) At 414, V_DS318 does not reach V corresponding to BIST_DS318 target V of voltage level_DS319. In the second timing diagram 402, the amplifier 346 decreases V from the first time 412 to the second time 414_G316 so that V_GS328 decreases from a first voltage at a first time 412 to a second voltage at a second time 414. In the second timing diagram 402, the first voltage corresponds to the voltage of the gate drive power supply 344 and the second voltage is approximately zero. At a second time 414, amplifier 346 continues to decrease V_G316 due to V_DS318 has not yet reached the target V_DS319. When V is_GS328 falls below zero (e.g., at about the second time 414), the fourth comparator 348 asserts the fault short detection signal 368. For example, the first state machine 340 may determine that the MOSFET304 has a fault short fault based on the assertion of the fault short detection signal 368. In such an example, the first state machine 340 may assert the alarm signal 364 of fig. 3 based on assertion of the fault short detection signal 368. In the second timing diagram 402, at a third example time (T)₃) At 416, amplifier 346 will turn V_G316 to about zero and thus makes V_GS328 to-Vsys because of V_G316 is zero and Vs 324 of fig. 3 is Vsys.

In the second timing diagram 402, at a fourth example time (T)₄) At 418, the BIST timer period 409 ends and the first state machine 340 deasserts the fault short detection signal 368. At the fourth time 418, the alarm signal 364 remains active after the BIST timer period 409 expires. When the BIST timer period 409 ends, the first state machine 340 deasserts the control signal 166 and the target V to be associated with the variable voltage source 342_DS319 to zero. When variable voltage source 342 is not enabled, amplifier 346 increases V_G316 so that V_DS318 is decreased. At a fifth exemplary time (T)₅) At 420, amplifier 346 increases V_G 316So that V is_GS328 increase back to the voltage level before triggering the BIST (e.g., V at first time 412_GS328)。

FIG. 5 is a schematic diagram of a fourth example power conversion system 500 including a second example BIST circuit 502 for detecting a fault short condition associated with the MOSFET304 of FIG. 3. In FIG. 5, a second example gate driver circuit 504 includes a second BIST circuit 502. In fig. 5, the second gate driver circuit 504 is an integrated circuit (e.g., an integrated circuit chip). Alternatively, the second gate driver circuit 504 may be implemented using hardware logic, machine-readable instructions, a hardware-implemented state machine, and/or any combination thereof.

The fourth power conversion system 500 includes the power supply 106 and the first power conversion stage 102 of fig. 1. Further depicted as coupled to the fourth power conversion system 500 is the load 124 of fig. 1. Alternatively, the load 124 may not be coupled to the fourth power conversion system 500. The fourth power conversion system 500 includes the MOSFET304 of fig. 3. In some examples, the first power conversion stage 102, the second gate driver circuit 504, and the MOSFET304 are included in the same integrated circuit. Alternatively, one or more of the first power conversion stage 102, the second gate driver circuit 504, and/or the MOSFET304 may be included in a separate integrated circuit.

In the illustrated example of fig. 5, the second gate driver circuit 504, and/or more generally, the fourth power conversion system 500, includes a second BIST circuit 502 to perform BIST on the MOSFETs 304, and the second BIST circuit 502, when activated or enabled, will control V_G316 to convert V_DS318 to a target voltage (e.g., target drain to source voltage, target V)_DSEtc.). In the illustrated example of fig. 5, the second gate driver circuit 504 includes the first, second, third and third comparators 332, 334, 336, switch 338, gate drive power supply 344, first, second and third voltage dividers 354, 358, 360 of fig. 3, and an example digital-to-analog (DAC) converter 512. In fig. 5, DAC512 is a 12-bit voltage output DAC. Alternatively, the DAC512 may have a different resolution and/or have a different type of output (e.g., current output).

In the illustrated example of fig. 5, the second gate driver circuit 504 facilitates switching operation of the MOSFET304 and, in some examples, triggers BIST of the MOSFET 304. For example, the second gate driver circuit 504 may be implemented by enabling V_GS328 is above the turn-on voltage threshold of the MOSFET304 to direct the DAC512 to increase V_G316 to turn on the MOSFET 304. In other examples, the second gate driver circuit 504 may be implemented by enabling V_GS328 below the off voltage threshold of the MOSFET304 to direct the DAC512 to reduce V_G316 to turn off the MOSFET 304.

In the illustrated example of FIG. 5, the second BIST circuit 502 includes a second example state machine 506, a first example analog-to-digital (ADC) converter 508, a second example ADC 510, and the fourth comparator 348 of FIG. 3. In fig. 5, the first ADC 508 and the second ADC 510 are 12-bit 200 kilo-sample per second (ksps) Successive Approximation Register (SAR) ADCs. Alternatively, one or both of the ADCs 508, 510 may have different resolutions, sampling rates, and/or otherwise correspond to different types of ADCs.

In some examples, the second BIST circuit 502 is an integrated circuit. For example, the second BIST circuit 502 may be included in a first integrated circuit, and the first comparator 332, the second comparator 334, the third comparator 336, the switch 338, the gate drive power supply 344, the first voltage divider 354, the second voltage divider 358, the third voltage divider 360, and/or the DAC512 are included in a second integrated circuit, wherein the first and second integrated circuits are included in a third integrated circuit corresponding to the second gate driver circuit 504 or the fourth power conversion system 500.

In the illustrated example of fig. 5, the output of the first ADC 508 is coupled to the second state machine 506, and the input of the first ADC 508 is coupled to the negative terminal of the gate drive power supply 344, the second voltage divider 358, and at the drain node of fig. 3 to the output of the first power conversion stage 102 of fig. 1. In fig. 5, the second state machine 506 is coupled to an input of a DAC 512. In fig. 5, the positive terminal of the gate drive power supply 344 is coupled to the power input of the DAC 512. In fig. 5, the ground or reference input of DAC512 is coupled to ground rail 356. In fig. 5, the output of the DAC512 is coupled to the inverting input of the fourth comparator 348. In fig. 5, the output of DAC512 is coupled to the gate 306 of MOSFET304 via switch 338. In fig. 5, the input of the second ADC 510 is coupled to the non-inverting input of the fourth comparator 348 at the first node 350. In fig. 5, the input of the second ADC 510 is coupled to the third voltage divider 360. In fig. 5, the input of the second ADC 510 is coupled to the source 310 and the load 124 at the source node 326. In fig. 5, the output of the ADC 510 is coupled to the second state machine 506.

In the illustrated example of fig. 5, the second state machine 506 is a hardware-implemented finite state machine. For example, the second state machine 506 may correspond to one or more microcontrollers (e.g., one or more digital microcontrollers) that include analog and/or digital peripherals for sensing and/or measurement functions. In such an example, the second state machine 506 may include one or more ADCs, one or more DACs, one or more Programmable Gain Amplifiers (PGAs), one or more comparators, one or more transimpedance amplifiers, one or more operational amplifiers, and/or the like, and/or combinations thereof. In some examples, the second state machine 506 may correspond to one or more controllers (e.g., microcontrollers) that execute machine-readable instructions. In some examples, second state machine 506 may be implemented by one or more analog or digital circuits, logic circuits, programmable processor(s), programmable controller(s), GPU(s), DSP(s), ASIC(s), PLD(s), and/or FPLD(s).

In operation, in response to assertion of the enable signal 362 of FIG. 3, the second state machine 506 triggers, enables, and/or otherwise activates the BIST of the MOSFET 304. In some examples, the second state machine 506 includes a counter to perform and/or otherwise facilitate operation of the BIST timer and to determine whether a BIST timer period has elapsed. For example, when the enable signal 362 is active, the second state machine 506 may initialize a counter to start the BIST timer period.

In the illustrated example of fig. 5, in response to assertion of the enable signal 362,the second state machine 506 generates a first example digital signal 514 to the DAC 512. In fig. 5, the first digital signal 514 is a control signal. In fig. 5, the first digital signal 514 corresponds to a digital code (digital _ code _ Vgate) that is converted to an output voltage when obtained by the DAC 512. For example, before the second state machine 506 triggers BIST, the second state machine 506 may generate a first digital code that, when obtained by the DAC512, is converted by the DAC512 to output for V_G316, wherein the first voltage is 17V (e.g., 12V above Vsys, wherein Vsys is 5V). When the second state machine 506 triggers BIST, the second state machine 506 may generate a second digital code that is converted by the DAC512 to output the output for V_G316, of 8V. For example, the second state machine 506 may direct the DAC512 to output a second voltage less than the first voltage to adjust V during the BIST_DS 318。

In the illustrated example of fig. 5, the second state machine 506 obtains measurements associated with the MOSFET304 via a second example digital signal (digital _ code _ Vdrain)516 and a third example digital signal (digital _ code _ Vsource) 518. In fig. 5, the first ADC 508 passes V, which will correspond to Vsys_D320 to a digital code (e.g., a binary value, a hexadecimal value, a machine-readable value, etc.) to generate a second digital signal 516. For example, the second state machine 506 may determine V by decoding a digital code associated with the second digital signal 516_D320. In FIG. 5, the second ADC 510 passes V, which will correspond to Vcca_S324 to a digital code to generate a third digital signal 518. For example, the second state machine 506 may determine the Vs 324 by decoding a digital code associated with the third digital signal 518. In such an example, the second state machine 506 may be based on (1) the V indicated by the second digital signal 516_D320 and (2) V indicated by third digital signal 518_S324 to determine V_DS 318。

In some examples, the second state machine 506 performs and/or otherwise facilitates BIST of the MOSFET304 by generating a digital code for the first digital signal 514 that sequentially and/or iteratively reduces V_G316 up to V_DS318 full ofA sufficient threshold (e.g., a predetermined voltage threshold, a value of a voltage threshold stored in a memory of the second state machine 506, etc.). For example, the second state machine 506 may generate a first digital code as the first digital signal 514 to cause the DAC512 to output for V_G316, respectively. In such an example, the second state machine 506 may determine V based on a difference between the second digital signal 516 and the third digital signal 518 responsive to the first voltage applied to the gate 306 of the MOSFET304_DS318。

If V_DS318 does not satisfy V_DSThreshold, the second state machine 506 may generate the second digital code as the first digital signal 514 to cause the DAC512 to output for V_G316, wherein the second voltage is less than the first voltage. In some examples, the second state machine 506 may generate (e.g., repeatedly generate) a new digital code as the first digital signal 514 to cause the DAC512 to reduce V_G316 up to at least one of the following: BIST timer expiration, V_GS328 becomes negative and causes a zero crossing, or V, to occur_DS318 satisfy V_DSAnd (4) a threshold value. For example, when V_G316 to a second voltage such that V_GS328 becomes negative and causes a zero crossing to occur, the fourth comparator 348 may assert a fault short detect signal 368 to the second state machine 506. Thus, the second state machine 506 may assert the alarm signal 364 when the fault short detection signal 368 is asserted.

If V_DS318 satisfy V_DSThreshold, then the second state machine 506 may maintain V_G316 is at a second voltage (e.g., by not generating a different digital code as the first digital signal 514). For example, the second state machine 506 may change V_G316 remain at the second voltage until the BIST timer expires. When BIST timer expires and V_DS318 satisfy V_DSAt threshold, the second state machine 506 may determine that the MOSFET304 has no fault short. For example, the second state machine 506 may generate the third digital code as the first digital signal 514 to output the first voltage as V by directing the DAC512_G316 to terminate the BIST.

Although an example manner of implementing the second gate driver circuit 504 is illustrated in fig. 5, one or more of the elements, processes and/or devices illustrated in fig. 5 may be combined, divided, rearranged, omitted, eliminated and/or implemented in any other way. Further, the first comparator 332, the second comparator 334, the third comparator 336, the switch 338, the gate drive power supply 344, the fourth comparator 348, the first voltage divider 354, the second voltage divider 358, the third voltage divider 360, the second state machine 506, the first ADC 508, the second ADC 510, the DAC512, and/or, more generally, the second gate driver circuit 504 of fig. 5 may be implemented by hardware, software, firmware, and/or any combination of hardware, software, and/or firmware. Thus, for example, any of the first comparator 332, the second comparator 334, the third comparator 336, the switch 338, the gate drive power supply 344, the fourth comparator 348, the first voltage divider 354, the second voltage divider 358, the third voltage divider 360, the second state machine 506, the first ADC 508, the second ADC 510, the DAC512, and/or, more generally, the second gate driver circuit 504 may be implemented by one or more analog or digital circuits, logic circuits, programmable processor(s), programmable controller(s), GPU(s), DSP(s), ASIC(s), PLD(s), and/or FPLD(s). When reading any device claims or system claims of this patent to encompass a purely software and/or firmware implementation, at least one of the first comparator 332, the second comparator 334, the third comparator 336, the switch 338, the gate drive power supply 344, the fourth comparator 348, the first voltage divider 354, the second voltage divider 358, the third voltage divider 360, the second state machine 506, the first ADC 508, the second ADC 510, the DAC512, and/or, more generally, the second gate driver circuit 504 is hereby expressly defined to include a non-transitory computer readable storage device or memory disk, e.g., non-volatile memory, etc., containing software and/or firmware. Still further, the second gate driver circuit 504 of fig. 5 may include one or more elements, processes and/or devices in addition to or in place of those illustrated in fig. 5, and/or may include more than one of any or all of the illustrated elements, processes and devices.

FIG. 6 depicts a third example timing diagram 600 and a fourth example timing diagram 602 corresponding to the operation of the second BIST circuit 502 and/or, more generally, the second gate driver circuit 504 of FIG. 5. In FIG. 6, the third timing diagram 600 corresponds to the operation of the second BIST circuit 502 when the MOSFET304 of FIGS. 3 and 5 has no fault short. In FIG. 6, the fourth timing diagram 602 corresponds to the operation of the second BIST circuit 502 when the MOSFET304 has a fault short. Depicted in the timing diagrams 600, 602 of FIG. 6 are the first digital signals 514, V of FIG. 5_GS 328、V_D 320、V_S324. Example waveforms for second digital signal 516, third digital signal 518, and fault short detection signal 368.

In the timing diagrams 600, 602 of fig. 6, the gate drive power supply 344 of fig. 5 provides support for voltage outputs within the range designated by reference numeral 604. In the timing diagrams 600, 602 of FIG. 6, V is modeled as a representation or format_DSThreshold value (simulation V)_DSThreshold) is designated by reference numeral 606, and is a numerical representation or format of V_DSThreshold value (number V)_DSThreshold) is designated by reference numeral 608. Number V_DSThe threshold 608 corresponds to a difference between a first digital code as the second digital signal 516 and a second digital code as the third digital signal 518, wherein the difference between the value of the first digital code and the value of the second digital code corresponds to representing V_DS318, which indicates typical, normal, and/or other efficient operation of the MOSFET 304.

In the timing diagrams 600, 602 of FIG. 6, V is in a digital representation or format_GSThreshold value (number V)_GSThreshold) is designated by reference numeral 610. Number V_GSThe threshold 610 corresponds to a difference between a first digital code as the first digital signal 514 and a second digital code as the third digital signal 518, wherein the difference between the value of the first digital code and the value of the second digital code corresponds to representing V_GS328, which indicates a fault short circuit fault of the MOSFET 304.

In the third timing diagram 600, at a first example time (T)₁) At 612, second of FIG. 5The state machine 506 invokes, triggers, and/or otherwise enables the BIST of the MOSFET304 to direct the DAC512 of FIG. 5 to convert V to V by generating a first digital code as a first digital signal 514_G316 from the first voltage to a second voltage less than the first voltage. By mixing V_G316 to a second voltage, DAC512 makes V_GS328 decreases the voltage at a first time 612. At a first time 612, the second state machine 506 determines V by corresponding to approximately the same voltage based on the second digital signal 516 and the third digital signal 518_D320 and V_S324 determine V for approximately the same voltage_DS318 is approximately zero.

In the third timing diagram 600, at a second example time (T)₂) At 614, the second state machine 506 determines V_DS318 satisfy V_DSAnd (4) a threshold value. For example, the second state machine 506 may determine that a difference between digital values associated with the second digital signal 516 and the third digital signal 518 satisfies the digital V_DSThreshold 608 (e.g., a digital V stored in memory of second state machine 506)_DSThreshold 608) and, thus, indicates V_DS318 satisfies the simulation V_DSA threshold 606. At a second time 614, the second state machine 506 may determine that a difference between digital values associated with the first digital signal 514 and the third digital signal 518 does not satisfy the digital V_GSThreshold 610 (e.g., a digital V stored in memory of second state machine 506)_GSThreshold 610) and, thus, indicates V_GS328 does not perform a zero crossing.

In the third timing graph 600, the second state machine 506 ramps down V by generating (e.g., iteratively generating) a digital code_G316 and correspondingly ramps down V_GS328 to reduce (e.g., iteratively reduce) V_G316. At a second time 614, the second state machine 506 lowers V by not generating a digital code as the first digital signal 514_G316, thereby converting V_G316 are maintained at the same voltage. At a second time 614, V_GS328 is positive and MOSFET304 is not performing with V_GS328.

In the third timing diagram 600, at a third example time: (T₃) At 616, the second state machine 506 is based on V after the example BIST timer period 618 has expired_GS328 is positive to determine that MOSFET304 has no fault short. In the third timing diagram 600, the BIST timer period 618 begins at the first time 612 and ends at the third time 616. For example, the second state machine 506 may use a counter included in the second state machine 506 to trigger or instantiate the BIST timer period 618. At a third time 616, the second state machine 506 converts V by generating a digital code as the first digital signal 514_G316 to a first voltage (e.g., a first voltage at a first time 612) to terminate the BIST of MOSFET 304. Incrementing V in response to the second state machine 506_G 316，V_GS 328、V_D 320、V_S324 and V_DS318 returns to the value prior to the BIST.

In the fourth timing diagram 602, at a first example time (T1)620, the second state machine 506 activates the BIST of the MOSFET304 by generating a first digital code as the first digital signal 514 to direct the DAC512 to couple V_G316 from a first voltage to a second voltage, wherein the second voltage is less than the first voltage. By mixing V_G316 to a second voltage, DAC512 makes V_GS328 decreases the voltage at a first time 620. At a first time 620, the second state machine 506 determines V by corresponding to approximately the same voltage based on the second digital signal 516 and the third digital signal 518_D320 and V_S324 determine V for approximately the same voltage_DS318 is approximately zero.

In the fourth timing diagram 602, at a second example time (T)₂) At 622, when the difference between the digital values associated with the first and third digital signals 514, 518 satisfies the digital V_GSThe second state machine 506 detects a fault short at threshold 610 and, therefore, indicates V_GS328 performs a zero crossing by transitioning from a positive voltage to a negative voltage. At a second time 622, the second state machine 506 determines that the difference between the digital values associated with the second and third digital signals 516 and 518 does not satisfy the digital V_DSThreshold 608, and thus, indicates V_DS318 do not satisfy the simulation V_DSA threshold 606. At a second time 622, the fourth comparator 348 of fig. 3 and 5 asserts the fault short detection signal 368, V_GS328 becomes negative. At a second time 622, the second state machine 506 detects and/or otherwise determines that the MOSFET304 has a fault short fault based on the assertion of the fault short detection signal 368. At a second time 622, the second state machine 506 asserts the alarm signal 364 when a fault short circuit fault of the MOSFET304 is detected.

In the fourth timing diagram 602, at a third example time (T)₃) At 624, the BIST timer cycle 618 ends and the second state machine 506 deasserts the fault short detect signal 368. When the BIST timer period 618 ends, the second state machine 506 generates a digital code as the first digital signal 514 to convert V_G316 return to the level before the BIST (e.g., V at first time 620)_G316) of the voltage source). At a third time 624, the alarm signal 364 remains active after the BIST timer period 618 expires.

FIG. 7 is a schematic diagram of a fifth example power conversion system 700 that includes a third example BIST circuit 702 for detecting a fault short condition associated with the MOSFET304 of FIG. 3. In FIG. 7, a third example gate driver circuit 704 includes a third BIST circuit 702. In fig. 7, the third gate driver circuit 704 is an integrated circuit (e.g., an integrated circuit chip). Alternatively, the third gate driver circuit 704 may be implemented using hardware logic, machine readable instructions, a hardware implemented state machine, and/or any combination thereof.

The fifth power conversion system 700 includes the power supply 106 and the first power conversion stage 102 of fig. 1. Further depicted as coupled to the fifth power conversion system 700 is the load 124 of fig. 1. Alternatively, the load 124 may not be coupled to the fifth power conversion system 700. The fifth power conversion system 700 includes a MOSFET 304. In some examples, the first power conversion stage 102, the third gate driver circuit 704, and the MOSFET304 are included in the same integrated circuit. Alternatively, one or more of the first power conversion stage 102, the third gate driver circuit 704, and/or the MOSFET304 may be included in a separate integrated circuit.

In the illustrated example of fig. 7, the third gate driver circuit 704, and/or more generally, the fifth power conversion system 700 includes a third BIST circuit 702 to perform BIST on the MOSFETs 304, and the third BIST circuit 702 will control V when activated or enabled_G316 to convert V_DS318 to a target V_DS. In the illustrated example of fig. 7, the third gate driver circuit 704 includes the first comparator 332, the second comparator 334, the third comparator 336, the switch 338, the gate drive power supply 344, the first voltage divider 354, the second voltage divider 358, and the third voltage divider 360 of fig. 3, and the DAC512 of fig. 5.

In the illustrated example of fig. 7, the third gate driver circuit 704 facilitates switching operation of the MOSFET304 and, in some examples, triggers BIST of the MOSFET 304. For example, the third gate driver circuit 704 may be implemented by enabling V_GS328 is above the turn-on voltage threshold of the MOSFET304 to direct the DAC512 to increase V_G316 to turn on the MOSFET 304. In other examples, the third gate driver circuit 704 may be implemented by letting V_GS328 below the off voltage threshold of the MOSFET304 to direct the DAC512 to reduce V_G316 to turn off the MOSFET 304.

In the illustrated example of FIG. 7, the third BIST circuit 702 includes the second state machine 506, the first ADC 508, and the second ADC 510 of FIG. 5. In fig. 7, the output of the first ADC 508 is coupled to the second state machine 506. In fig. 7, the input of the first ADC 508 is coupled to the negative terminal of the gate drive power supply 344, the second voltage divider 358, and to the output of the first power conversion stage 102 of fig. 1 at the drain node 322 of fig. 3. In fig. 7, the second state machine 506 is coupled to an input of a DAC 512. In fig. 7, the positive terminal of the gate drive power supply 344 is coupled to the power input of the DAC 512. In fig. 7, the ground or reference input of DAC512 is coupled to ground rail 356. In fig. 7, the output of DAC512 is coupled to the gate 306 of MOSFET304 via switch 338. In fig. 7, the input of the second ADC 510 is coupled to the third voltage divider 360 and to the third comparator 336 via the third voltage divider 360. In fig. 7, the input of the second ADC 510 is coupled to the source 310 and the load 124 at the source node 326. In fig. 7, the output of the ADC 510 is coupled to the second state machine 506.

In some examples, the third BIST circuit 702 is an integrated circuit. For example, the third BIST circuit 702 may be included in a first integrated circuit, and the first comparator 332, the second comparator 334, the third comparator 336, the switch 338, the gate drive power supply 344, the first voltage divider 354, the second voltage divider 358, the third voltage divider 360, and/or the DAC512 are included in a second integrated circuit, wherein the first and second integrated circuits are included in a third integrated circuit corresponding to the third gate driver circuit 704 or the fifth power conversion system 700.

In operation, in response to assertion of the enable signal 362 of FIG. 3, the second state machine 506 triggers, enables, and/or otherwise activates the BIST of the MOSFET 304. In response to assertion of the enable signal 362, the second state machine 506 generates and transmits a first digital code as the first digital signal 514 to the DAC512 to lower V_G316 to convert V_DS318 to a target V_DS. In fig. 7, the second state machine 506 obtains a second digital signal 516 and a third digital signal 518. The second state machine 506 may be based on V indicated by the second digital signal 516_D320 and V indicated by third digital signal 518_S324 to determine V_DS 318。

In the illustrated example of fig. 7, the second state machine 506 is configured by determining whether the voltage difference indicated by the second digital signal 516 and the third digital signal 518 satisfies V_DSThreshold value to determine V_DS318 satisfy V_DSAnd (4) a threshold value. If V_DS318 does not satisfy V_DSThreshold, the second state machine 506 may generate a second digital code as the first digital signal 514 to cause the DAC512 to output for V_G316. In some examples, the second state machine 506 may generate (e.g., repeatedly generate) a new digital code as the first digital signal 514 to cause the DAC512 to reduce V_G316 up to at least one of the following: BIST timer expiration, V_GS328 becomes negative and causes a zero crossing, or V, to occur_DS318 satisfy V_DSAnd (4) a threshold value. If V is lowered_G316 makes V_GS328 becomes negative, the second state machine 506 can determine that the MOSFET304 has a fault short fault. The second state machine 506 can assert the alarm signal 364 when a fault short fault of the MOSFET304 is detected.

If the second state machine 506 determines V_DS318 satisfy V_DSA threshold value, then the second state machine 506 may set V to_G316 are maintained at the current voltage (e.g., by not generating a different digital code as the first digital signal 514). For example, the second state machine 506 may change V_G316 remain at the current voltage until the BIST timer expires. When BIST timer expires and V_DS318 satisfy V_DSAt threshold, the second state machine 506 may determine that the MOSFET304 has no fault short. For example, the second state machine 506 may generate the third digital code as the first digital signal 514 to output the voltage before BIST as V by directing the DAC512 to output the BIST as V_G316 to terminate the BIST.

Although an example manner of implementing the third gate driver circuit 704 is illustrated in fig. 7, one or more of the elements, processes and/or devices illustrated in fig. 7 may be combined, divided, rearranged, omitted, eliminated and/or implemented in any other way. Further, the first comparator 332, the second comparator 334, the third comparator 336, the switch 338, the gate drive power supply 344, the first voltage divider 354, the second voltage divider 358, the third voltage divider 360, the second state machine 506, the first ADC 508, the second ADC 510, the DAC512, and/or, more generally, the third gate driver circuit 704 of fig. 7 may be implemented by hardware, software, firmware, and/or any combination of hardware, software, and/or firmware. Thus, for example, any of the first comparator 332, the second comparator 334, the third comparator 336, the switch 338, the gate drive power supply 344, the first voltage divider 354, the second voltage divider 358, the third voltage divider 360, the second state machine 506, the first ADC 508, the second ADC 510, the DAC512, and/or, more generally, the third gate driver circuit 704 may be implemented by one or more analog or digital circuits, logic circuits, programmable processor(s), programmable controller(s), GPU(s), DSP(s), ASIC(s), PLD(s), and/or FPLD(s). When reading any apparatus claims or system claims of this patent to encompass a purely software and/or firmware implementation, at least one of the first comparator 332, the second comparator 334, the third comparator 336, the switch 338, the gate drive power supply 344, the first voltage divider 354, the second voltage divider 358, the third voltage divider 360, the second state machine 506, the first ADC 508, the second ADC 510, the DAC512, and/or, more generally, the third gate driver circuit 704 is hereby expressly defined to include a non-transitory computer readable storage device or memory disk, such as a non-volatile memory, a volatile memory, or the like, containing software and/or firmware. Still further, the third gate driver circuit 704 of fig. 7 may include one or more elements, processes and/or devices in addition to or in place of those illustrated in fig. 7, and/or may include more than one of any or all of the illustrated elements, processes and devices.

FIG. 8 depicts fifth and sixth example timing patterns 800, 802 corresponding to the operation of the third BIST circuit 702 and/or, more generally, the third gate driver circuit 704 of FIG. 7. In FIG. 8, the fifth timing diagram 800 corresponds to the operation of the third BIST circuit 702 when the MOSFET304 of FIGS. 3, 5, and 7 has no fault short. In FIG. 8, the sixth timing diagram 802 corresponds to the operation of the third BIST circuit 702 when the MOSFET304 has a faulty short. Depicted in the timing diagrams 800, 802 of FIG. 8 are the first digital signals 514, V of FIG. 7_GS 328、V_D 320、V_s324. Example waveforms of second digital signal 516 and third digital signal 518. In the timing diagrams 800, 802 of fig. 8. The gate drive power supply 344 of fig. 3, 5 and 7 provides support for voltage outputs within the range designated by reference numeral 604. Further depicted in the timing diagrams 800, 802 of FIG. 8 is a simulation V_DSThreshold 606, number V_DSThreshold 608 and number V_GSA threshold value 610.

In the fifth timing diagram 800, at a first example time (T)₁) At 804, the second state machine 506 invokes, triggers, and/or otherwise activates B of the MOSFET304 by generating a first digital code as a first digital signal 514IST to direct DAC512 to convert V_G316 from the first voltage to a second voltage less than the first voltage. By mixing V_G316 to a second voltage, DAC512 pulls V_GS328 decreases the voltage at a first time 804. At a first time 804, the second state machine 506 determines V by corresponding to approximately the same voltage based on the second digital signal 516 and the third digital signal 518_D320 and V_S324 is approximately the same voltage to determine V_DS318 is approximately zero.

In the fifth timing diagram 800, at a second example time (T)₂) At 806, the second state machine 506 determines V_DS318 satisfy V_DSAnd (4) a threshold value. For example, the second state machine 506 may determine that a difference between digital values associated with the second digital signal 516 and the third digital signal 518 satisfies the digital V_DSThreshold 608, and thus, indicates V_DS318 satisfies the simulation V_DSA threshold 606. At a second time 806, the second state machine 506 lowers V by not generating a subsequent digital code as the first digital signal 514_G316 to stop V_G316 (e.g., by stopping the ramping down of the digital code corresponding to the instance of the first digital signal 514). At a second time 806, V_GS328 is positive and no zero crossing is performed.

In the fifth timing diagram 800, at a third example time (T)₃) At 808, the second state machine 506 is based on V_GS328 is positive after the BIST timer period 618 of fig. 6 has expired to determine that MOSFET304 has no fault short. At a third time 808, the second state machine 506 converts V by generating a digital code as the first digital signal 514_G316 to a first voltage (e.g., a voltage at a first time 810) to terminate the BIST of MOSFET 304. Incrementing V in response to the second state machine 506_G316，V_GS 328、V_D320. Vs 324 and V_DS318 returns to the value prior to the BIST.

In the sixth timing diagram 802, at a first example time (T)₁) At 810, the second state machine 506 activates the BIST of the MOSFET304 by generating the first digital code as the first digital signal 514 to direct the DAC512 to convert V_G316 from a first voltageAnd reducing to a second voltage, wherein the second voltage is less than the first voltage. By mixing V_G316 to a second voltage, DAC512 pulls V_GS328 decreases the voltage at a first time 810. At a first time 810, the second state machine 506 determines V by corresponding to approximately the same voltage based on the second digital signal 516 and the third digital signal 518_D320 and V_S324 approximately the same voltage to determine V_DS318 is approximately zero.

In the sixth timing diagram 802, at a second example time (T)₂) At 812, when a difference between digital values associated with the first digital signal 514 and the third digital signal 518 satisfies the digital V_GSAt threshold 610, the second state machine 506 detects a fault short and, therefore, indicates V_GS328 has transitioned from a positive voltage to a negative voltage. For example, DAC512 may generate for V based on a first digital code as first digital signal 514_G316, and the second ADC 510 may provide a second digital code as a third digital signal 518 based on Vs 324, wherein the difference between the first digital code and the second digital code corresponds to V_GS328. In such an example, the difference between the first digital code and the second digital code satisfies the number V_GSAt threshold 610, the second state machine 506 can detect a fault short fault of the MOSFET 304. At a second time 812, when V is associated with the first digital signal 514_G316 and V associated with third digital signal 518_S324 satisfy the number V_GSAt threshold 610, the second state machine 506 may assert the alarm signal 364.

In the sixth timing diagram 802, at a third example time (T)₃) At 814, the second state machine 506 terminates the BIST by generating a digital code as the first digital signal 514 after the BIST timer period 618 has elapsed_G316 return to the level before BIST (e.g., V at first time 810)_GVoltage 810 of 316). Additionally or alternatively, when the BIST timer period 618 has elapsed at the third time 814, when V is indicated_D320 of the second digital signal 516 and an indication V_S324, of the third digital signal 518The difference between the character codes does not satisfy V_DSAt threshold, the second state machine 506 can detect a fault short fault of the MOSFET 304. Additionally or alternatively, when the BIST timer period 618 has elapsed at the third time 822, the second digital code of the third digital signal 518 when indicative of the Vs 324 does not cause V to be asserted_DS318 satisfy V_DSAt threshold, the second state machine 506 can detect a fault short fault of the MOSFET 304.

A state diagram representing example hardware logic, machine readable instructions, a hardware implemented state machine, and/or any combination thereof for implementing the first state machine 340 of fig. 3 and/or the second state machine 506 of fig. 5 and 7 is shown in fig. 9. A flowchart representative of example hardware logic, machine readable instructions, a hardware implemented state machine, and/or any combination thereof to implement the first state machine 340 of fig. 3 and/or the second state machine 506 of fig. 5 and/or 5 and 7 is shown in fig. 10. The machine-readable instructions may be executable programs or portions of executable programs executed by one or more computer processors, one or more microcontrollers, or the like. For example, the machine-readable instructions may be executed by one or more integrated circuits, logic circuits, microprocessors, GPUs, DSPs, or controllers from any desired family or manufacturer. For example, one or more integrated circuits, logic circuits, microprocessors, GPUs, DSPs, or controllers may be semiconductor-based (e.g., silicon-based) device(s). The program may be embodied in software stored on a non-transitory computer readable storage medium (such as non-volatile memory, etc.) associated with one or more computer processors, one or more microcontrollers, etc., but the entire program and/or portions thereof may instead be executed by a device other than one or more computer processors, one or more microcontrollers, etc., and/or embodied in firmware or dedicated hardware. Further, although the example program is described with reference to the state diagram illustrated in fig. 9 and/or the flowchart illustrated in fig. 10, many other methods of implementing the first state machine 340 of fig. 3 and/or the second state machine 506 of fig. 5 and 7 may alternatively be used. For example, the order of execution of the blocks may be changed, and/or some of the blocks described may be changed, eliminated, or combined. Additionally or alternatively, any or all of the blocks may be implemented by one or more hardware circuits (e.g., discrete and/or integrated analog and/or digital circuits, FPGAs, ASICs, comparators, operational amplifiers (op-amps), logic circuits, etc.) configured to perform corresponding operations without the execution of software or firmware.

As described above, the example processes of fig. 9-10 may be implemented using executable instructions (e.g., computer and/or machine readable instructions) stored on a non-transitory computer and/or machine readable medium such as a hard disk drive, a flash memory, a read-only memory, a compact disk, a digital versatile disk, a cache, a random access memory, and/or any other storage device or storage disk that stores information for any duration (e.g., for extended periods of time, permanently, brief instances, for temporarily buffering, and/or for caching the information). As used herein, the term non-transitory computer-readable medium is expressly defined to include any type of computer-readable storage device and/or storage disk and to exclude propagating signals and to exclude transmission media.

The terms "comprising" and "including" (and all forms and tenses thereof) are used herein as open-ended terms. Thus, whenever a claim employs any form of "including" or "comprising" (e.g., including, comprising, including, having, etc.) as a preamble or within any type of claim recitation, it is to be understood that additional elements, terms, etc. may be present without departing from the scope of the corresponding claim or recitation. As used herein, when the phrase "at least" is used as a transitional term, such as in the preamble of the claims, it is open-ended in the same manner that the terms "comprising" and "including" are open-ended. For example, the term "and/or" when used in a form such as A, B and/or C refers to any combination or subset of A, B, C, such as (1) a alone, (2) B alone (3) C alone, (4) a and B, (5) a and C, (6) B and C, and (7) a and B and C. As used herein in the context of describing structures, components, items, objects, and/or things, the phrase "at least one of a and B" is intended to refer to embodiments that include either (1) at least one a, (2) at least one B, and (3) at least one a and at least one B. Similarly, as used herein in the context of describing structures, components, items, objects, and/or things, the phrase "at least one of a or B" is intended to refer to embodiments that include either (1) at least one a, (2) at least one B, and (3) at least one a and at least one B. As used herein in the context of describing the execution or performance of processes, instructions, actions, activities, and/or steps, the phrase "at least one of a and B" is intended to refer to embodiments that include any of (1) at least one a, (2) at least one B, and (3) at least one a and at least one B. Similarly, as used herein in the context of describing the execution or performance of processes, instructions, actions, activities, and/or steps, the phrase "at least one of a or B" is intended to refer to embodiments that include either (1) at least one a, (2) at least one B, and (3) at least one a and at least one B.

Fig. 9 depicts an example state diagram 900 corresponding to the operation of the first state machine 340 of fig. 3 and/or the second state machine 506 of fig. 5 and 7. At a first example state 902, the first state machine 340 and/or the second state machine 506 are in an inactive BIST state. For example, the first state machine 340 in the first state 902 may disable the BIST output corresponding to the control signal 366 of fig. 3. In such an example, the first state machine 340 may disable the BIST output by not generating the control signal 366 when in the first state 902.

In the illustrated example of FIG. 9, the first state machine 340 and/or the second state machine 506 move and/or otherwise transition from the first state 902 to the second example state 904 when the BIST trigger is obtained. For example, the first state machine 340 may transition to the second state 904 when the BIST trigger corresponding to the enable signal 362 of FIG. 3 is active. At second state 904, first state machine 340 and/or second state machine 506 are in the active BIST state. For example, the first state machine 340 can generate the control signal 366 to invoke BIST of the MOSFET 304. In other examples, the second state machine 506 may generate a digital code as the first digital signal 514 of fig. 5 to invoke BIST of the MOSFET 304.

In the illustrated example of FIG. 9, when V of FIG. 3_DS318 meet a threshold (e.g., corresponding to a target V)_DS319 of voltage V_DSThreshold value) or V_DS318, the first state machine 340 and/or the second state machine 506 transition from the second state 904 to the third example state 906. For example, the first state machine 340 may move from the second state 904 to the third state 906 because V is not executed_DS318, so the first state machine 340 skips the measurement of V_DS318 satisfy V_DSAnd (5) checking a threshold value. In other examples, when the second state machine 506 determines V based on the difference between the second digital signal 516 and the third digital signal 518 of fig. 5_DS318 satisfy the V associated with BIST_DSThreshold (e.g. analog V)_DSThreshold 606, number V_DSThreshold 608, etc.), the second state machine 506 may move from the second state 904 to the third state 906.

When in the third state 906, the first state machine 340 and/or the second state machine 506 hold the BIST output. For example, the first state machine 340 may cause V to be present by maintaining the control signal 366 at the current signal level_G316 are maintained at the same voltage to maintain the BIST output corresponding to the control signal 366. In other examples, the second state machine 506 may maintain the BIST output corresponding to the first digital signal 514 by not generating a different digital code for the first digital signal 514 (e.g., maintaining the currently used digital code). The first state machine 340 and/or the second state machine 506 may move from the third state 906 to the first state 902 when the BIST timer expires. For example, when V_DS318 corresponds to the target V_DS319 and the BIST timer period 409 of fig. 4 has elapsed, the first state machine 340 may move from the third state 906 to the first state 902. In such an example, the first state machine 340 can determine that the MOSFET304 has no fault short and therefore terminate the BIST by disabling the control signal 366.

In the illustrated example of FIG. 9, when V is_GS328 satisfies the threshold, the first state machine 340 and/or the second state machine 506 move from the third state 906 to a fourth example state 908. For example, when the fourth comparator 348 makes a fault short-circuit detectionWhen the test signal 368 is valid, the first state machine 340 and/or the second state machine 506 may move from the third state 906 to the fourth state 908. In other examples, the difference between the respective digital codes of the first and third digital signals 514, 514 when determined by the second state machine 506 satisfies the digital V of fig. 6 and 8_GSAt threshold 610, the second state machine 506 may move from the third state 906 to the fourth state 908 and, thus, indicate V_GS328 has occurred. At the fourth state 908, the first state machine 340 and/or the second state machine 506 assert an alarm signal 364 indicating that a fault short fault of the MOSFET304 is detected. In fig. 9, the first state machine 340 and/or the second state machine 506 move from the fourth state 908 to the first state 902 when the alarm signal 364 is inactive.

In the illustrated example of FIG. 9, when V is_GS328 satisfies the threshold, the first state machine 340 and/or the second state machine 506 move from the second state 904 to a fourth state 908. For example, when the fourth comparator 348 is based on V_GS328 renders the fault short detection signal 368 valid, the first state machine 340 and/or the second state machine 506 may detect a fault short condition of the MOSFET 304. In other examples, when the digital code associated with first digital signal 514 corresponds to making V_GS328 becomes negative V_G316, the second state machine 506 can detect a fault short condition of the MOSFET 304.

In the illustrated example of FIG. 9, the first state machine 340 and/or the second state machine 506 move from the second state 904 to the fifth example state 910 when the BIST timer expires. At the fifth state 910, the first state machine 340 and/or the second state machine 506 are in a BIST fault detection state. For example, if V is at the expiration of the BIST timer_GS328 neither satisfies V_GThreshold value, V_DS318 also do not satisfy V_DSThreshold, the first state machine 340 and/or the second state machine 506 may detect a fault associated with the BIST circuit 302, 502, 702 of fig. 3, 5, and/or 7. In such an example, if the BIST circuit 302, 502, 702 cannot raise V_DS318. By lowering V_GS328, etc., satisfy V_GSThreshold value, V_DSThe BIST timer period 409 of fig. 4, the BIST timer period 618 of fig. 6 and 8, etc., expires before the threshold value, etc. For example, while in the fifth state 910, the first state machine 340 and/or the second state machine 506 may detect that one or more components of the BIST circuitry 302, 502, 702 and/or the gate driver circuitry 303, 504, 704 have failed.

At a fifth state 910, the first state machine 340 and/or the second state machine 506 generate an alarm indicating that the BIST has failed. For example, when in the fifth state 910, the first state machine 340 and/or the second state machine 506 may assert the alarm signal 364. Alternatively, when in the fifth state 910, the first state machine 340 and/or the second state machine 506 may assert an alarm signal (e.g., a BIST fault alarm signal) separate from the alarm signal 364. In fig. 9, the first state machine 340 and/or the second state machine 506 move from the fifth state 910 to the first state 902 when the alarm signal 364 is inactive.

Fig. 10 is a flow diagram representative of example machine readable instructions 1000 that may be executed to implement the first state machine 340 of fig. 3 and/or the second state machine 506 of fig. 5 and 7 to detect a fault short condition associated with the MOSFET304 of fig. 3. The machine-readable instructions 1000 begin at block 1002 where the first state machine 340 and/or the second state machine 506 determine whether to obtain a BIST trigger at block 1002. For example, the first state machine 340 may determine the enable signal 362 of fig. 3 to be valid. In other examples, the second state machine 506 may obtain assertion of the enable signal 362.

If at block 1002, the first state machine 340 and/or the second state machine 506 determine that a BIST trigger is not obtained, then at block 1002 control waits. If at block 1002 the first state machine 340 and/or the second state machine 506 determine that a BIST trigger is obtained, at block 1004 the first state machine 340 and/or the second state machine 506 enable a BIST output to lower a MOSFET gate voltage. For example, when the enable signal 362 is active, the first state machine 340 can generate the control signal 366 of FIG. 3 to trigger the BIST of the MOSFET 304. In such an example, the first state machine 340 can cause the variable voltage source 342 to direct the amplifier 346 to lower the V of the MOSFET304_G316. In other examples, the second state machine 506 mayTo generate first digital signal 514 of fig. 5 to lower V of MOSFET304_G 316。

At block 1006, the first state machine 340 and/or the second state machine 506 determine V_GSWhether the threshold is met. For example, when V_GS328 becomes negative, the first state machine 340 may determine V based on the assertion of the fault short detection signal 368 from the fourth comparator 348_GS328 satisfies V_GSAnd (4) a threshold value. In other examples, when V_GS328 becomes negative, the second state machine 506 may determine V based on the assertion of the fault short detection signal 368 from the fourth comparator 348_GS328 satisfies V_GSAnd (4) a threshold value. Alternatively, the second state machine 506 may be based on V indicated by the second digital signal 516_D320 and V indicated by third digital signal 518_S324 value based on V_DS318 satisfy V_DSThreshold value to determine V_GS328 satisfies V_GSAnd (4) a threshold value.

If at block 1006, the first state machine 340 and/or the second state machine 506 determine V_GSIf the threshold is met, control proceeds to block 1014 to generate an alarm indicating that a fault short circuit fault of the MOSFET is detected. For example, the first state machine 340 and/or the second state machine 506 may assert the alarm signal 364 when the fault short detection signal 368 is asserted. In response to generating an alarm at block 1014 indicating that a fault short fault of the MOSFET is detected, the machine readable instructions 1000 of fig. 10 end.

If at block 1006, the first state machine 340 and/or the second state machine 506 determine V_GSThe threshold is not met, and then, at block 1008, the first state machine 340 and/or the second state machine 506 determine V_DSWhether or not the threshold value or V is satisfied_DSIt is checked whether it has been skipped. For example, the first state machine 340 may skip pairs V_DS318 satisfy V_DSAnd (5) checking a threshold value. In other examples, when V is indicated by the second digital signal 516_DThe value of 320 and V indicated by the third digital signal 518_S324 corresponds to a target V_DS319, the second state machine 506 may determine V_DS318 has reached the target V_DS 319。

If at block 1008, the first state machine 340 and/or the second state machine 506 determine V_DSIf the threshold is met, then at block 1010, the first state machine 340 and/or the second state machine 506 determines whether the BIST timer has elapsed. For example, the first state machine 340 may determine that the BIST timer period 409 of FIG. 4 has elapsed. In other examples, the second state machine 506 may determine that the BIST timer period 618 of fig. 6 has expired.

If at block 1010, first state machine 340 and/or second state machine 506 determine that the BIST timer has not elapsed, then control waits at block 1010. If at block 1010 the first state machine 340 and/or the second state machine 506 determine that the BIST timer has elapsed, then at block 1012 the first state machine 340 and/or the second state machine 506 disable the BIST output because no MOSFET fault short is detected. For example, when the BIST timer period 409 of FIG. 4 has expired, the first state machine 340 may not detect a fault short fault of the MOSFET304 when the fault short detection signal 368 is not valid. In such examples, when a fault short is not detected, the first state machine 340 can disable the control signal 366 to terminate the BIST. In other examples, when the BIST timer period 618 of fig. 6 has expired, the second state machine 506 may generate a digital code as the first digital signal 514 to terminate the BIST when the fault short detection signal 368 is not valid. In other examples, V is when V after the BIST timer period 618 elapses_D320 and V_S324 satisfy V_DSAt threshold, the second state machine 506 may generate a digital code as the first digital signal 514 to terminate the BIST. In response to disabling the BIST output at block 1012, control returns to block 1002 to determine whether another BIST trigger is obtained to trigger the MOSFET 304.

If at block 1008, the first state machine 340 and/or the second state machine 506 determine V_DS318 do not satisfy the threshold or V_DSThe check has been skipped, control proceeds to block 1016 to determine if the BIST timer has elapsed. If at block 1016 the first state machine 340 and/or the second state machine 506 determine that the BIST timer has not elapsed, then control returns to block 1004 to enable the BIST output to lowerThe MOSFET gate voltage. For example, the second state machine 506 may generate a different digital code as the first digital signal 514 to convert V_G316 from the first voltage to a second voltage less than the first voltage.

If, at block 1016, the first state machine 340 and/or the second state machine 506 determines that the BIST timer has expired, then, at block 1018, the first state machine 340 and/or the second state machine 506 generates an alarm indicating a BIST failure. For example, the first state machine 340 can assert an alarm signal 364 indicating that the BIST has failed. In other examples, the second state machine 506 may cause an indication that one or more components of the BIST circuitry 502, 702 and/or the gate driver circuitry 504, 704 of fig. 5 and/or 7 cannot increase V_DS318. Reduction of V_GS328, etc. is active. Alternatively, the first state machine 340 and/or the second state machine 506 may assert an alarm signal (e.g., a BIST fault alarm signal) separate from the alarm signal 364. For example, the BIST failure alarm signal may indicate that the BIST has failed or that one or more components of the BIST circuit 502, 702 and/or the gate driver circuit 504, 704 of FIG. 5 and/or FIG. 7 cannot increase V_DS318. Reduction of V_GS328, and so on. In response to generating the alarm indicating the BIST failure, the machine readable instructions 1000 of FIG. 10 end.

As can be appreciated from the foregoing, example systems, methods, apparatus, and articles of manufacture have been disclosed that facilitate BIST detection of fault short faults associated with power switching devices. Systems, methods, apparatus, and articles of manufacture are disclosed to control a gate voltage of a power switching device to regulate a drain-to-source voltage of the power switching device to a target drain-to-source voltage. Advantageously, the target drain-to-source voltage corresponds to a voltage level that ensures that the relevant components of the power conversion system have sufficient supply voltage while being able to detect a potential fault short circuit fault. The disclosed systems, methods, articles of manufacture, and articles of manufacture detect a fault short circuit fault of a power switching device when a gate-to-source voltage of the power switching device is below zero volts (indicative of a zero crossing). The disclosed systems, methods, articles of manufacture, and articles of manufacture allow for the use of one power switching device and one power conversion device to create a supply voltage that remains below a maximum operating voltage of a load having a limited maximum operating voltage for up to two faults in the power conversion system.

Example BIST circuits and related methods are disclosed herein. Further examples and combinations thereof include the following:

example 1 includes a built-in self-test (BIST) circuit, the circuit comprising a state machine to: generating a control signal to reduce a gate voltage associated with a transistor from a first voltage to a second voltage when an enable signal is active, the transistor being enabled at the first voltage and the second voltage; and when the gate voltage decreases to the second voltage, asserting an alarm signal when a gate-to-source voltage associated with the transistor satisfies a threshold.

Example 2 includes the BIST circuit of example 1, further comprising a variable voltage source coupled to the state machine, and wherein the BIST circuit is included in the gate driver circuit, the gate driver circuit is coupled to the transistor, and the gate driver circuit includes an amplifier coupled to the variable voltage source and the gate of the transistor, the amplifier decreasing the gate voltage to the second voltage when the state machine decreases a third voltage at an input of the amplifier by adjusting a fourth voltage associated with the variable voltage source.

Example 3 includes the BIST circuit of example 1, further comprising a comparator, an output of the comparator coupled to the state machine, a first input of the comparator to measure a gate voltage, a second input of the comparator to measure a source voltage associated with the transistor, and the comparator to assert the detection signal when the gate-to-source voltage satisfies a threshold.

Example 4 includes the BIST circuit of example 1, wherein the state machine is to invalidate the control signal to increase the gate voltage to the first voltage when the gate-to-source voltage does not meet the threshold value after the BIST timer period has expired.

Example 5 includes the BIST circuit of example 1, wherein the threshold is a first voltage, and the BIST circuit is included in a gate driver circuit, the gate driver circuit is coupled to the transistor, and the gate driver circuit includes: a switch coupled to the gate of the transistor, the switch coupling the gate to the ground rail when switching from a first state to a second state; a gate drive power supply coupled to the transistor; a first comparator that switches the switch to a second state when a third voltage associated with the gate driving power supply satisfies a second threshold; a second comparator to switch the switch to a second state when a drain voltage associated with the transistor satisfies a third threshold; and a third comparator to switch the switch to the second state when the source voltage associated with the transistor satisfies a fourth threshold.

Example 6 includes the BIST circuit of example 1, wherein the control signal is a first digital signal, and further comprising: a first analog-to-digital converter (ADC) that measures a drain voltage associated with the transistor by converting the drain voltage to a second digital signal; and a second ADC to measure the source voltage by converting the source voltage associated with the transistor to a third digital signal.

Example 7 includes the BIST circuit of example 6, wherein the control signal is a first control signal, the threshold is a first threshold, and the state machine is to: determining a drain-to-source voltage associated with the transistor based on a difference between the second digital signal and the third digital signal; determining that the transistor has no fault short condition when the difference satisfies a second threshold; and generating a second control signal to increase the gate voltage to the first voltage.

Example 8 includes the BIST circuit of example 6, wherein the threshold is a first threshold, and the state machine is to: determining a drain-to-source voltage associated with the transistor based on a difference between the second digital signal and the third digital signal; detecting a fault short condition associated with the transistor when the difference does not satisfy the second threshold and the BIST timer period has expired; and when a fault short circuit condition is detected, asserting an alarm signal.

Example 9 includes a power conversion system, comprising: a power conversion stage; a transistor coupled to the power conversion stage; and a built-in self-test (BIST) circuit, the BIST circuit comprising a state machine to: generating a control signal to reduce a gate voltage associated with a transistor from a first voltage to a second voltage when an enable signal is active, the transistor being enabled at the first voltage and the second voltage; and when the gate voltage decreases to the second voltage, asserting an alarm signal when a gate-to-source voltage associated with the transistor satisfies a threshold.

Example 10 includes the power conversion system of example 9, wherein the BIST circuit includes a variable voltage source coupled to the state machine, and further comprising: an amplifier coupled to the variable voltage source and the gate of the transistor, the amplifier to decrease the gate voltage to the second voltage when the state machine decreases the third voltage at the input of the amplifier by adjusting a fourth voltage associated with the variable voltage source.

Example 11 includes the power conversion system of example 9, further comprising a comparator, an output of the comparator coupled to the state machine, a first input of the comparator to measure a gate voltage, a second input of the comparator to measure a source voltage associated with the transistor, and the comparator to assert the detection signal when the gate-to-source voltage satisfies a threshold.

Example 12 includes the power conversion system of example 9, wherein the state machine is to invalidate the control signal to increase the gate voltage to the first voltage when the gate-to-source voltage does not meet the threshold value after the BIST timer period has expired.

Example 13 includes the power conversion system of example 9, wherein the threshold is a first voltage, and further comprising a gate driver circuit comprising: a switch coupled to the gate of the transistor, the switch coupling the gate to the ground rail when switching from the first state to the second state, the transistor being off when the gate is coupled to the ground rail, the load being disconnected from the power conversion stage when the transistor is off; a gate drive power supply coupled to the transistor; a first comparator that switches the switch to a second state when a third voltage associated with the gate driving power supply satisfies a second threshold; a second comparator to switch the switch to a second state when a drain voltage associated with the transistor satisfies a third threshold; and a third comparator to switch the switch to the second state when the source voltage associated with the transistor satisfies a fourth threshold.

Example 14 includes the power conversion system of example 9, wherein the control signal is a first digital signal, and the BIST circuit further comprises: a first analog-to-digital converter (ADC) that measures a drain voltage associated with the transistor by converting the drain voltage to a second digital signal; and a second ADC to measure the source voltage by converting the source voltage associated with the transistor to a third digital signal.

Example 15 includes the power conversion system of example 14, wherein the control signal is a first control signal, the threshold is a first threshold, and the state machine is to: determining a drain-to-source voltage associated with the transistor based on a difference between the second digital signal and the third digital signal; determining that the transistor has no fault short condition when the difference satisfies a second threshold; and generating a second control signal to increase the gate voltage to the first voltage.

Example 16 includes the power conversion system of example 14, wherein the threshold is a first threshold, and the state machine is to: determining a drain-to-source voltage associated with the transistor based on a difference between the second digital signal and the third digital signal; detecting a fault short condition associated with the transistor when the difference does not satisfy the second threshold and the BIST timer period has expired; and when a fault short circuit condition is detected, asserting an alarm signal.

Example 17 includes a gate driver circuit comprising a state machine; a variable voltage source coupled to the state machine, a first terminal of the variable voltage source coupled to a first current terminal of the transistor; an amplifier, a first input of the amplifier coupled to the second terminal of the variable voltage source, an output of the amplifier coupled to the gate of the transistor, a second input of the amplifier coupled to the second current terminal of the transistor; and a comparator, an output of the comparator being coupled to the state machine, a first input of the comparator being coupled to the output of the amplifier, a first input of the comparator being coupled to the gate of the transistor, a second input of the comparator being coupled to the second current terminal of the transistor.

Example 18 includes the gate driver circuit of example 17, further comprising a gate drive power supply, a first terminal of the gate drive power supply coupled to the first terminal of the variable voltage source, a first terminal of the gate drive power supply coupled to the first current terminal of the transistor, and a second terminal of the gate drive power supply coupled to the third input of the amplifier.

Example 19 includes the gate driver circuit of example 17, wherein the output of the amplifier is coupled to a switch, the switch being coupled to the gate of the transistor.

Example 20 includes the gate driver circuit of example 17, wherein the second input of the amplifier is coupled to a load, the load being at least one of one or more processors associated with the vehicle, a non-volatile memory, or a volatile memory.

Although certain example systems, methods, apparatus, and articles of manufacture have been disclosed herein, the scope of coverage of this patent is not limited thereto. On the contrary, this patent covers all systems, methods, apparatus, and articles of manufacture fairly falling within the scope of the appended claims either literally or under the doctrine of equivalents.