阅读说明：本技术 一种基于fpga的dma设备及dma数据搬移方法 (DMA (direct memory access) equipment based on FPGA (field programmable Gate array) and DMA data transfer method ) 是由 王峰 张闯 任智新 于 2021-01-20 设计创作，主要内容包括：本申请公开了一种基于FPGA的DMA设备及DMA数据搬移方法,DMA设备包括：配置模块用于获取主机发送的配置信息,并基于配置信息向多通道模块中多个数据搬移通道分别下发数据搬移任务；配置信息包括每个通道待搬移的数据量、源地址、目的地址；多通道模块用于通过每个数据搬移通道基于对应的搬移任务向仲裁模块发送搬移请求；仲裁模块用于基于预设通道优先级从多个搬移请求中确定出第一目标请求,并处理第一目标请求以通过对应的数据搬移通道将第一存储设备中的目标数据搬移至第二存储设备,当第一存储设备中数据量不足,则基于预设通道优先级确定出第二目标请求进行处理。能够满足多个外部存储设备之间的数据搬移需求,提升数据搬移效率。(The application discloses DMA equipment and a DMA data moving method based on FPGA, wherein the DMA equipment comprises: the configuration module is used for acquiring configuration information sent by the host computer and respectively issuing data transfer tasks to the multiple data transfer channels in the multi-channel module based on the configuration information; the configuration information comprises the data volume to be moved, a source address and a destination address of each channel; the multi-channel module is used for sending a moving request to the arbitration module through each data moving channel based on the corresponding moving task; the arbitration module is used for determining a first target request from the plurality of moving requests based on the preset channel priority, processing the first target request to move target data in the first storage device to the second storage device through the corresponding data moving channel, and determining the second target request to process based on the preset channel priority when the data amount in the first storage device is insufficient. The data transfer requirements among a plurality of external storage devices can be met, and the data transfer efficiency is improved.)

1. The DMA device based on the FPGA is characterized by comprising a configuration module, a multi-channel module and an arbitration module, wherein,

the configuration module is used for acquiring configuration information sent by the host computer and respectively issuing corresponding data moving tasks to a plurality of corresponding data moving channels in the multi-channel module based on the configuration information; the configuration information comprises the data volume to be moved, a source address and a destination address of each data moving channel;

the multi-channel module is used for sending a moving request to the arbitration module through each data moving channel based on the corresponding data moving task;

the arbitration module is configured to determine a first target request from the plurality of move requests based on a preset channel priority, process the first target request to move target data in a first storage device to a second storage device through the data move channel corresponding to the first target request, and determine a second target request to process based on the preset channel priority when the amount of data in the first storage device corresponding to the first target request is insufficient.

2. The FPGA-based DMA device of claim 1, wherein the arbitration module is specifically configured to determine the second target request to process based on the preset channel priority and the destination address corresponding to the move request.

3. The FPGA-based DMA device of claim 1, wherein the arbitration module is further configured to suspend processing the second target request and resume processing the first target request when the amount of data in the first storage device satisfies a resume read condition.

4. The FPGA-based DMA device of claim 1, wherein the arbitration module is specifically configured to read the target data from the first storage device based on the first target request, place the target data in a cache of the data move channel corresponding to the first target request, and read the target data from the cache and write the target data in the second storage device.

5. The FPGA-based DMA device of claim 1, further comprising:

and the state module is used for recording the moving states corresponding to all the data moving channels.

6. The FPGA-based DMA device of claim 5, wherein the arbitration module is further configured to:

and writing the moving state into the state module.

7. The FPGA-based DMA device of claim 5, wherein the multi-channel module is further configured to:

and writing the moving state into the state module.

8. The FPGA-based DMA device of claim 1, further comprising:

and the interrupt module is used for sending corresponding interrupt to the host after any data moving task is completed.

9. A DMA data moving method based on FPGA is characterized by comprising the following steps:

the configuration information sent by the host is acquired through the configuration module, and corresponding data moving tasks are respectively issued to a plurality of corresponding data moving channels in the multi-channel module based on the configuration information;

sending a moving request to an arbitration module through each data moving channel in the multi-channel module based on the corresponding data moving task;

determining a first target request from the plurality of moving requests based on a preset channel priority through the arbitration module, processing the first target request to move target data in a first storage device to a second storage device through the data moving channel corresponding to the first target request, and determining the second target request to process based on the preset channel priority when the data volume in the first storage device corresponding to the first target request is insufficient.

10. The FPGA-based DMA data transfer method of claim 9, wherein said determining a second target request for processing based on said predetermined channel priority comprises:

and determining the second target request to process based on the preset channel priority and the destination address corresponding to the moving request.

Technical Field

The present application relates to the field of data transmission technologies, and in particular, to a DMA device based on an FPGA and a DMA data transfer method.

Background

With the increasingly widespread application of heterogeneous acceleration, the accelerator cards based on the FPGA (Field Programmable Gate Array) are also rapidly developed. The accelerator card FPGA is connected with the server host through a PCIE interface, the server host sends data to be accelerated to the accelerator card FPGA through the PCIE (peripheral component interconnect express, a high-speed serial computer expansion bus standard) interface, and the accelerator card FPGA returns related data through the PCIE interface after processing is completed. In the data transmission process, a DMA (direct memory access) is a common data transfer device, and is used to receive a transfer instruction of a host, apply for a bus control right, and perform data transfer.

At present, if there are many peripheral devices in the system, the existing DMA can only receive a move instruction once, and then it needs a plurality of DMAs to work simultaneously to meet the requirement, which obviously increases the complexity of the system. And because all are hung on the same bus, a plurality of DMA can not move data at the same time, only one DMA can obtain the bus at the same time to move the data. This requires the bus to switch between multiple DMAs, which is inefficient.

Disclosure of Invention

In view of this, an object of the present application is to provide a DMA device based on an FPGA and a DMA data transfer method, which can meet a data transfer requirement between a plurality of external storage devices, avoid a bus switching among a plurality of DMAs, and improve data transfer efficiency. The specific scheme is as follows:

in a first aspect, the present application discloses an FPGA-based DMA apparatus, comprising a configuration module, a multi-channel module, and an arbitration module, wherein,

the configuration module is used for acquiring configuration information sent by the host computer and respectively issuing corresponding data moving tasks to a plurality of corresponding data moving channels in the multi-channel module based on the configuration information; the configuration information comprises the data volume to be moved, a source address and a destination address of each data moving channel;

the multi-channel module is used for sending a moving request to the arbitration module through each data moving channel based on the corresponding data moving task;

the arbitration module is configured to determine a first target request from the plurality of move requests based on a preset channel priority, process the first target request to move target data in a first storage device to a second storage device through the data move channel corresponding to the first target request, and determine a second target request to process based on the preset channel priority when the amount of data in the first storage device corresponding to the first target request is insufficient.

Optionally, the arbitration module is specifically configured to determine the second target request to process based on the preset channel priority and the destination address corresponding to the moving request.

Optionally, the arbitration module is further configured to suspend processing of the second target request and continue processing of the first target request when the data amount in the first storage device meets a condition for continuing reading.

Optionally, the method is specifically configured to read the target data from the first storage device based on the first target request, place the target data in a cache of the data moving channel corresponding to the first target request, read the target data from the cache, and write the target data into the second storage device.

Optionally, the method further includes:

and the state module is used for recording the moving states corresponding to all the data moving channels.

Optionally, the arbitration module is further configured to:

and writing the moving state into the state module.

Optionally, the multi-channel module is further configured to:

and writing the moving state into the state module.

Optionally, the method further includes:

and the interrupt module is used for sending corresponding interrupt to the host after any data moving task is completed.

In a second aspect, the application discloses a DMA data transfer method based on an FPGA, which includes:

the configuration information sent by the host is acquired through the configuration module, and corresponding data moving tasks are respectively issued to a plurality of corresponding data moving channels in the multi-channel module based on the configuration information;

sending a moving request to an arbitration module through each data moving channel in the multi-channel module based on the corresponding data moving task;

determining a first target request from the plurality of moving requests based on a preset channel priority through the arbitration module, processing the first target request to move target data in a first storage device to a second storage device through the data moving channel corresponding to the first target request, and determining the second target request to process based on the preset channel priority when the data volume in the first storage device corresponding to the first target request is insufficient.

Optionally, the determining, based on the preset channel priority, that the second target request is processed includes:

and determining the second target request to process based on the preset channel priority and the destination address corresponding to the moving request.

The configuration module is used for acquiring configuration information sent by a host and respectively issuing corresponding data moving tasks to a plurality of corresponding data moving channels in the multi-channel module based on the configuration information; the configuration information comprises the data volume to be moved, a source address and a destination address of each data moving channel; the multi-channel module is used for sending a moving request to the arbitration module through each data moving channel based on the corresponding data moving task; the arbitration module is configured to determine a first target request from the plurality of move requests based on a preset channel priority, process the first target request to move target data in a first storage device to a second storage device through the data move channel corresponding to the first target request, and determine a second target request to process based on the preset channel priority when the amount of data in the first storage device corresponding to the first target request is insufficient. That is, according to the data transfer method and device, a plurality of data transfer tasks are executed through a plurality of data transfer channels by configuring a source address, a destination address and a transfer data volume of data transfer, a target request is determined through an arbitration module to carry out data transfer, if the data of the storage device corresponding to the current target request is insufficient, a new target request is determined to carry out data transfer, and a waiting time process is avoided.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, it is obvious that the drawings in the following description are only embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.

Fig. 1 is a schematic structural diagram of a DMA apparatus based on an FPGA according to the present disclosure;

fig. 2 is a schematic structural diagram of a specific FPGA-based DMA apparatus disclosed in the present application;

fig. 3 is a schematic structural diagram of a specific FPGA-based DMA apparatus disclosed in the present application;

FIG. 4 is a schematic diagram of a specific data movement disclosed herein;

fig. 5 is a flowchart of a DMA data transfer method based on FPGA according to the present disclosure.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

At present, if there are many peripheral devices in the system, the existing DMA can only receive a move instruction once, and then it needs a plurality of DMAs to work simultaneously to meet the requirement, which obviously increases the complexity of the system. And because all are hung on the same bus, a plurality of DMA can not move data at the same time, only one DMA can obtain the bus at the same time to move the data. This requires the bus to switch between multiple DMAs, which is inefficient. Therefore, the DMA scheme based on the FPGA is provided, the data moving requirements among a plurality of external storage devices can be met, the bus is prevented from being switched among a plurality of DMA, and the data moving efficiency is improved.

Referring to fig. 1, an embodiment of the present application discloses an FPGA-based DMA apparatus, which includes a configuration module 11, a multi-channel module 12, and an arbitration module 13, wherein,

the configuration module 11 is configured to obtain configuration information sent by a host, and issue corresponding data moving tasks to a plurality of corresponding data moving channels in the multi-channel module 12 based on the configuration information; the configuration information includes the data volume to be moved, the source address and the destination address of each data moving channel.

The multi-channel module 12 is configured to send a transfer request to the arbitration module 13 through each data transfer channel based on the corresponding data transfer task.

The number of channels in the multi-channel module may be set according to actual requirements, such as 4, 16, and the like, and is not specifically limited herein.

The arbitration module 13 is configured to determine a first target request from the plurality of move requests based on a preset channel priority, process the first target request to move target data in a first storage device to a second storage device through the data move channel corresponding to the first target request, and determine a second target request to process based on the preset channel priority when the amount of data in the first storage device corresponding to the first target request is insufficient.

That is, the implementation may set the priority of the channel, and process the request corresponding to the channel with the highest priority first. For example, the priorities of the lanes 1 to 4 are sequentially lowered, and when both the lanes 1 and 2 have a transfer task, the transfer task of the lane 1 is preferentially executed. But when the task of channel1 is in a waiting state due to insufficient data corresponding to the device to be read, the task of channel2 is started to be executed, thus avoiding waiting, because the DMA loses bus control right after waiting too long, and the bus control right is applied again if necessary.

And when the data volume in the first storage device corresponding to the first target request is insufficient, recording the state corresponding to the moving task as waiting. Specifically, the storage device itself performs data amount determination, and when the data is less than a read amount, the storage device raises a wait signal to notify the DMA to wait. That is, the pull-up signal informs the arbitration module that the amount of data is insufficient. For example, a DMA is reading from storage and another device is writing to storage, and if the DMA reads faster, the stored data will be read empty and wait.

In a specific implementation manner, the arbitration module 13 is specifically configured to read the target data from the first storage device based on the first target request, place the target data in a cache of the data transfer channel corresponding to the first target request, and read the target data from the cache and write the target data in the second storage device.

Specifically, the arbitration module generates request data meeting an Avalon bus protocol format based on the first target request and sends the request data to an FPGA Avalon bus, the Avalon bus sends the request data to the first storage device, the target data is read out and returned to the arbitration module, and the arbitration module stores the target data into a corresponding cache.

The arbitration module 13 is specifically configured to determine the second target request to process based on the preset channel priority and the destination address corresponding to the move request.

Specifically, a request with a different destination address and a highest channel priority corresponding to the first target request is determined from the movement requests that have not been processed, and the second target request is determined and processed.

It should be noted that if an address conflict occurs, the post-processing request destroys the moved data of the same destination address.

Further, the arbitration module is further configured to suspend processing of the second target request and continue processing of the first target request when the data amount in the first storage device satisfies a condition for continuing reading.

Specifically, when the amount of data in the first storage device is sufficient, the wait signal is pulled low, and the arbitration module is notified to continue processing the first target request.

That is, when the amount of data in the first storage device is sufficient, the processing of the second target request is suspended, and the processing of the first target request is continued.

It can be seen that the DMA device based on the FPGA disclosed in the embodiment of the present application includes a configuration module, a multi-channel module, and an arbitration module, where the configuration module is configured to obtain configuration information sent by a host, and based on the configuration information, respectively issue corresponding data moving tasks to a plurality of corresponding data moving channels in the multi-channel module; the configuration information comprises the data volume to be moved, a source address and a destination address of each data moving channel; the multi-channel module is used for sending a moving request to the arbitration module through each data moving channel based on the corresponding data moving task; the arbitration module is configured to determine a first target request from the plurality of move requests based on a preset channel priority, process the first target request to move target data in a first storage device to a second storage device through the data move channel corresponding to the first target request, and determine a second target request to process based on the preset channel priority when the amount of data in the first storage device corresponding to the first target request is insufficient. That is, in the embodiment of the present application, a plurality of data transfer tasks are executed through a plurality of data transfer channels by configuring a source address, a destination address, and a transfer data volume of data transfer, a target request is determined by an arbitration module to perform data transfer, and if data of a storage device corresponding to a current target request is insufficient, a new target request is determined to perform data transfer, so that a waiting time process is avoided.

Referring to fig. 2, the embodiment of the present application discloses a specific FPGA-based DMA apparatus, which includes a configuration module 21, a multi-channel module 22, an arbitration module 23, a status module 24, and an interrupt module 25, wherein,

the configuration module 21 is configured to obtain configuration information sent by a host, and issue corresponding data moving tasks to the corresponding multiple data moving channels in the multi-channel module 22 based on the configuration information; the configuration information comprises the data volume to be moved, a source address and a destination address of each data moving channel;

the multi-channel module 22 is configured to send a move request to the arbitration module 23 through each data move channel based on the corresponding data move task;

the arbitration module 23 is configured to determine a first target request from the move requests based on a preset channel priority, process the first target request to move target data in a first storage device to a second storage device through the data move channel corresponding to the first target request, and determine a second target request to process based on the preset channel priority when the amount of data in the first storage device corresponding to the first target request is insufficient.

And the state module 24 is used for recording the moving states corresponding to all the data moving channels.

Wherein, the moving state comprises: the internal fifo (First Input First Output) of each data transfer channel is in an empty state, and the task state of the current data transfer channel includes moving, waiting, ending, residual data amount and the like.

In a specific embodiment, the arbitration module 23 is further configured to: and writing the moving state into the state module.

In another specific embodiment, the multi-channel module 22 is further configured to: and writing the moving state into the state module.

That is, the shift status can be written into the status module through the arbitration module 23 or the multi-channel module 22.

And the interrupt module 25 is configured to send a corresponding interrupt to the host after any one of the data moving tasks is completed.

In particular embodiments, an interrupt or other message may be sent to inform the host of the task completion. Of course, the host may also mask these interrupts and obtain the corresponding information by reading the status module.

For example, referring to fig. 3, the embodiment of the present application discloses a specific FPGA-based DMA apparatus. The work flow of the whole DMA is illustrated by data movement among three devices of SRAM, DDR and flash. As shown in fig. 4, fig. 4 is a specific data movement diagram disclosed in the embodiment of the present application. The configuration information issued by Host to the configuration module is that channel1 moves 256M data from address A of SRAM to address C of DDR, channel2 moves 256M data from address E of flash to address D of DDR, channel3 moves 256M data from address B of SRAM to address E of flash, and channel4 moves 100M data from address F of flash to address G of DDR. And after receiving the configuration information issued by the host, the configuration module starts the DMA to start working. Since only one device can occupy the bus at the same time, channel1 has the highest priority, the DMA first starts to perform a-C data movement, and the status module records the status. At this time, the arbitration module starts processing the request of channel2 according to the situation, executes the data transfer of E- > D, when channel2 is moved to 64M, the data of SRAM is sufficient, channel1 enters the transfer state again, at this time, channel2 is suspended, and the transfer of a- > C is continuously executed. When the channel1 is executed to the 192M shift amount, the SRAM waits again, at this time, the channel enters the waiting again, and the channel2 starts to continue executing. When channel2 executes to 128M, channel2 also enters a wait state if the flash also experiences data starvation or otherwise needs to wait. At this time, normally, channel3 should be started to execute data transfer of B- > E, but since there is transfer related to address E in channel2 and priority of channel2 is high, if there is no software order restriction in the host application layer, if data transfer of B- > E is executed at this time, data of E is destroyed, and data transfer of E- > D is erroneous. The arbitration module prevents the channel with the lower priority from starting when there is an address conflict, so that the channel3 is not executed at this time, and the channel4 is started at this time. When a certain channel finishes the moving task, the interrupt module sends out a corresponding interrupt to inform host. Thus, macroscopically, the tasks of channel1 and channel2 and channel4 are executed almost in parallel, and if channel1 is waiting, channel2 continues to execute, and if channel2 is waiting, channel4 continues to execute. If the number of the channels is enough, the situation that all the channels wait at the same time is difficult to occur at the same time, the DMA always has the control right of the bus, and the data transmission efficiency is high, so that a plurality of DMA are not needed to finish a plurality of moving tasks together. Furthermore, host does not need to avoid collision of channel2 with channel3 at the software level, and the DMA's own logic can ensure that no collision occurs.

Therefore, the time division multichannel DMA is realized based on the FPGA, the realization logic of the DMA can be encapsulated into IP for independent use, and the method can be suitable for data transfer among a plurality of peripheral equipment. The flexibility, the transportability and the expandability are improved, the direct calling can be realized, the convenience is provided for the development of corresponding products, and the development period is shortened.

Referring to fig. 5, an embodiment of the present application discloses a DMA data transfer method based on an FPGA, including:

step S11: the configuration information sent by the host is obtained through the configuration module, and corresponding data moving tasks are respectively issued to the corresponding data moving channels in the multi-channel module based on the configuration information.

Step S12: and sending a moving request to an arbitration module through each data moving channel in the multi-channel module based on the corresponding data moving task.

Step S13: determining a first target request from the plurality of moving requests based on a preset channel priority through the arbitration module, processing the first target request to move target data in a first storage device to a second storage device through the data moving channel corresponding to the first target request, and determining the second target request to process based on the preset channel priority when the data volume in the first storage device corresponding to the first target request is insufficient.

In a specific implementation manner, the arbitration module reads the target data from the first storage device based on the first target request, places the target data in a cache of the data move channel corresponding to the first target request, and reads the target data from the cache and writes the target data into the second storage device.

In a specific embodiment, the second target request may be determined to be processed by the arbitration module based on the preset channel priority and the destination address corresponding to the move request.

And when the data volume in the first storage device meets the condition of continuously reading, suspending the processing of the second target request through the arbitration module, and continuously processing the first target request.

Further, the method further comprises:

and recording the moving states corresponding to all the data moving channels through a state module.

Correspondingly, the method further comprises the following steps: and writing the moving state into the state module through the arbitration module, or writing the moving state into the state module through the multi-channel module.

In addition, the method further comprises:

and sending corresponding interrupt to the host by the interrupt module after any data moving task is completed.

As can be seen, in the embodiment of the present application, the configuration information sent by the host is obtained by the configuration module, and the corresponding data moving tasks are respectively issued to the corresponding multiple data moving channels in the multi-channel module based on the configuration information; sending a moving request to an arbitration module through each data moving channel in the multi-channel module based on the corresponding data moving task; determining a first target request from the plurality of moving requests based on a preset channel priority through the arbitration module, processing the first target request to move target data in a first storage device to a second storage device through the data moving channel corresponding to the first target request, and determining the second target request to process based on the preset channel priority when the data volume in the first storage device corresponding to the first target request is insufficient. That is, in the embodiment of the present application, a plurality of data transfer tasks are executed through a plurality of data transfer channels by configuring a source address, a destination address, and a transfer data volume of data transfer, a target request is determined by an arbitration module to perform data transfer, and if data of a storage device corresponding to a current target request is insufficient, a new target request is determined to perform data transfer, so that a waiting time process is avoided.

The embodiments are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same or similar parts among the embodiments are referred to each other. The method disclosed by the embodiment corresponds to the equipment disclosed by the embodiment, so that the description is simple, and the relevant points can be referred to the equipment part for description.

The steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in Random Access Memory (RAM), memory, Read Only Memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.

The above provides detailed descriptions for the DMA device based on the FPGA and the DMA data transfer method, and specific examples are applied in this document to explain the principle and the implementation of the present application, and the descriptions of the above embodiments are only used to help understand the method and the core idea of the present application; meanwhile, for a person skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.