阅读说明：本技术 先进制程下时延驱动的层分配方法 (Delay-driven layer distribution method under advanced process ) 是由 刘耿耿 鲍晨鹏 郭文忠 陈国龙 于 2021-01-22 设计创作，主要内容包括：本发明提出一种先进制程下时延驱动的层分配方法,在每一阶段线网布线的动态规划过程中,层分配器都通过使用轨道数感知层选择策略进行目标代价的计算；包括以下步骤：步骤S1：均衡排序初始化,包括：运用多指标驱动初始线网排序策略为各个线网建立层分配优先级,并基于线网的优先级大小,依次为每个线网进行初始层分配；步骤S2：基于下游电容的时延优化层分配,包括：线网段调整策略和线网段时延优化策略；所述线网段调整策略将下游电容较大的上游段调整到上层的可布线轨道；所述线网段时延优化策略通过排序各线网段的下游电容,按照数值递增的顺序对线网进行拆线重绕,用于消除布线区域中的大量溢出。(The invention provides a time delay driven layer distribution method under an advanced process.A layer distributor calculates target cost by using a track number perception layer selection strategy in the dynamic planning process of each stage of wire network wiring; the method comprises the following steps: step S1: equalizing sequencing initialization, comprising: establishing layer distribution priority for each net by using a multi-index driving initial net sorting strategy, and sequentially performing initial layer distribution for each net based on the priority of the net; step S2: a downstream capacitance-based time delay optimization layer assignment comprising: a line network section adjusting strategy and a line network section time delay optimizing strategy; the wire mesh section adjusting strategy adjusts an upstream section with larger downstream capacitance to a routable track on an upper layer; the line network segment time delay optimization strategy is used for clearing and rewinding the line network according to the numerical value increasing sequence by sequencing the downstream capacitance of each line network segment, so as to eliminate a large amount of overflow in a wiring area.)

1. A time delay driven layer distribution method under advanced process is characterized in that:

in the dynamic planning process of the wire mesh wiring in each stage, the layer distributor calculates the target cost by using the track number perception layer selection strategy, and the target function of each dynamic planning process is as follows:

α×delay(n)+β×#via_n+∑_s∈ncong(s_e)

cong(e)＝M₀×trc(e)+M₁×ofc(e)

wherein delay (n) and # via_nRespectively representing the time delay and the number of vias, cong(s), of the wire mesh n_e) Representing the congestion cost of the line segment s at the edge e; trc (e) represents the track residual cost at e, ofc (e) represents the overflow cost at e; alpha, beta, M₀,M₁Is a custom weight coefficient;

the method comprises the following steps:

step S1: equalizing sequencing initialization, comprising: establishing layer distribution priority for each net by using a multi-index driving initial net sorting strategy, and sequentially performing initial layer distribution for each net based on the priority of the net;

step S2: a downstream capacitance-based time delay optimization layer assignment comprising: a line network section adjusting strategy and a line network section time delay optimizing strategy; the wire mesh section adjusting strategy adjusts an upstream section with larger downstream capacitance to a routable track on an upper layer; the line network segment time delay optimization strategy is used for clearing and rewinding the line network according to the numerical value increasing sequence by sequencing the downstream capacitance of each line network segment, so as to eliminate a large amount of overflow in a wiring area.

Step S3: post-optimization: and performing the last disconnection and rewinding on all the nets under the condition of not generating new overflow, and comparing the target cost of the rewinding scheme with the target cost of the original scheme to take the optimal selection scheme as the final layer distribution result.

2. The method of claim 1, wherein the method further comprises: the track number perception layer selection strategy allocates the wire mesh sections to the metal layer with the largest number of the remaining tracks in each wire mesh wiring process, so that the number of the remaining tracks of all the metal layers is not negative, and more selectable wiring layers are reserved for the next pre-allocated wire mesh.

3. The method of claim 1, wherein the method further comprises: the track remaining cost formula of the track number perception layer selection strategy is as follows:

wherein Remainc (e, l) represents the number of remaining tracks of e on l layer, then w (e) represents the ratio of the remaining tracks of l layer to the sum of the remaining tracks of each layer; the combination of formula cong (e) ═ M₀×trc(e)+M₁X ofc (e) and the upper twoThe formula is taken as the congestion cost of the objective function; k represents the number of wiring metal layers.

4. The method of claim 1, wherein the method further comprises: in step S1, the layer allocator drives the initial net sorting strategy layer allocator to calculate a score for each net according to the line length, the number of missing points, and the routing space density of the net according to the multiple indexes, where the higher the score is, the higher the initial routing priority of the net is:

wherein n is_iRepresenting a 2D global wiring net; m₂，M₃Is a self-defined variable; pinn (n)_i) Finger net n_iThe number of medium leakage points; len (n)_i) Representing a net n_iLine length in the 2D grid map; avgden (n)_i) Representing a net n_iRouting Density in 3D mesh graph, with size equal to Net n_iThe number of tracks required to be occupied is a ratio of the sum of the number of available tracks in each layer in the 3D grid map.

5. The method of claim 4, wherein the method further comprises: m₂，M₃Set to 1 and 0.5, respectively.

6. The method of claim 1, wherein the method further comprises: in step S2, the net segment adjustment comprises the following steps:

step S21: establishing a storage library for each edge in the 2D grid graph, and storing the downstream capacitance values of each layer of wire net passing through the edge in the library;

step S22: sequencing the values in the library from big to small;

step S23: each line network is removed and rewound, and all sections with smaller downstream capacitance but higher level are removed before each rewinding;

step S24: and recovering the removed wire mesh section.

7. The method of claim 1, wherein the method further comprises: in step S2, the method for optimizing the delay of the net segment includes the following steps:

step S25: traversing each edge according to the given 2D grid graph; establishing a corresponding library for each passing edge; if overflow exists on the 3D grid graph corresponding to the side, counting the downstream capacitance of the wire network passed by each layer, and storing the downstream capacitance in a library; if the overflow is not found during traversing each edge, obtaining a time delay optimization result of the line network section;

step S26: sorting all downstream capacitance values in the library in ascending order; and according to the sequence, the wire net where the wire network segment is located is removed and rewound;

step S27: if the edge still has overflow after rewinding, the historical cost and the time delay weight are increased, and the process returns to step S25.

8. The method of claim 1, wherein the method further comprises: in step S1, α, β, M in the objective function is set₀,M₁The values of (a) are set to 10,1, 12, 0.3, respectively; in step S2, the net section adjusting stage adjusts the length of the wire mesh₀All set to 2; beta, M in the post-optimization stage₀The values of (A) are all set to 1, 3.5.

Technical Field

The invention belongs to the technical field of computer aided design of integrated circuits, and particularly relates to construction of a layer distributor in a general wiring stage in a very large scale integrated circuit, and a layer distribution method of delay driving under an advanced process in the very large scale integrated circuit.

Background

As the scale of integrated circuits continues to expand, transistor and interconnect feature sizes move into the nanoscale regime. The continuing increase in the number of wiring nets required per unit area further increases the complexity of the overall wiring on the chip. Meanwhile, the increase of the net density causes the significant deterioration of the time delay, the interconnection time delay becomes the bottleneck of the sequential circuit, and the time delay of the replaced transistor becomes the determining factor of the chip performance. The layer allocation process is an intermediate step of overall wiring and detailed wiring, and can allocate the net sections in the 2D topology to each metal layer and optimize time delay. The good layer distribution method can effectively optimize indexes such as time delay, crosstalk and through holes, obtain high-quality wiring results for overall wiring, further reduce the workload of repairing various wiring violations in a detailed wiring stage, and has important significance for improving the performance of the chip.

Disclosure of Invention

Layer allocation is a very important step in converting a 2D wiring scheme into a 3D wiring scheme in the overall wiring stage. However, the existing layer distribution method focuses on minimizing the interconnection delay and the number of through holes, and mostly lacks reasonable distribution of a time sequence key section in a wire network, so that the final delay optimization effect is not obvious enough, and the performance of a chip is reduced due to insufficient wiring quality. In order to fill up the blank of the prior art, the invention provides a layer allocation method of delay driving under an advanced process, aiming at minimizing the total delay of a wire mesh, the maximum delay of the wire mesh and the number of through holes.

The invention provides a novel time delay driven layer distribution method under the background of introducing advanced process technology, and the method is based on the following 4 effective methods: 1) the track number perception layer selection strategy can enhance the ability of the distributor to select a proper wiring layer for the wire mesh section; 2) the method comprises the following steps that a multi-index driven initial wire network sorting strategy is adopted to obtain a high-quality initial wiring result for layer distribution; 3) a wire mesh section adjusting strategy, wherein the time sequence key section is adjusted to an upper layer wire mesh layer by rewinding a wire mesh, and the time delay of the wire mesh is optimized; 4) and the time delay optimization strategy of the net section can eliminate the overflow of the net while optimizing the time delay of the net by performing disconnection and rewinding on the overflow net. The invention can greatly optimize both the time delay and the number of the through holes under the condition of ensuring that no overflow is generated, thereby obtaining a high-quality overall wiring result.

Introduction of related art:

A. non-default ruled line:

non-default ruled line techniques in advanced manufacturing processes are mainly divided into parallel lines and wide lines. Due to industrial technological limitations, non-default ruled lines exist in the form of parallel lines at a lower level and wide lines at a higher level. The line width of the non-default ruled line is twice as large as the line width of the default ruled line on the same wiring layer. From the physical point of view, the wider line width enables the non-default ruled line to have lower resistance, thereby being capable of obtaining lower time delay. Meanwhile, in order to reduce the influence of signal crosstalk between the wires, the wider the wire width is, the larger the gap between the wires is. The non-default ruled line therefore needs to occupy more track resources than the default ruled line.

B. Capacitance estimation based on lookup tables:

the algorithm first builds a look-up table for the layer assigner before the layer assignment begins. The main key of the lookup table comprises three parts, namely a metal layer where a wire section is located, the wiring density of the 3D grid edge and the selected wire type. The values include capacitance values of corresponding conductive lines at different metal layers, different wiring densities, and different conductive line types. The construction method of the lookup table comprises the following steps: 1) distributing a certain line segment at the edge of the 3D grid by adopting a certain type of conducting wire; 2) randomly distributing the nets on adjacent layers to enable the estimated net density to be approximately equal to the wiring density of the final result; 3) the capacitance values of the parallel lines and the wide lines are calculated separately. Through multiple times of experimental calculation, the average value of the final result is stored in a lookup table to be used as a more accurate unit capacitance estimation value under different layers, different leads and different densities.

C. Segment weighting:

the amount of delay in a net segment depends largely on the downstream capacitance of that segment, so the timing criticality of the net segment near the source point is stronger than that near the drain point. Therefore, in the overlapping part of multiple paths of the same net, the weight value of the net section in the part needs to be increased properly. Meanwhile, as the congestion cost is increased continuously in the disconnecting and rewinding process, the delay weight of each network segment needs to be increased properly to ensure the delay optimization effect.

The method mainly comprises the following design processes:

1. and in the process of layer distribution of each net, a track number sensing layer selection strategy capable of enhancing the selection capability of the net segments on the proper wiring layer is used. The strategy compares the number of the remaining orbits of each layer, and determines the size of the congestion cost by taking the number of the remaining orbits as a parameter.

2. A multi-index driven initial net ordering strategy is used in the balanced ordering initialization stage. The strategy endows each net with initial wiring priority by measuring a plurality of indexes such as the number of pins, the wire length of the net, the wiring track resource and the like, and then enables the initial layer distribution to utilize the wiring resource to the maximum extent.

3. An effective line segment adjusting strategy is used for adjusting a time sequence key segment of a lower wiring layer in the early stage of a time delay optimization layer distribution stage based on downstream capacitance. The net section adjusting strategy is used for carrying out disconnection and rewinding on the net where unreasonably distributed wires are located by counting the downstream capacitance of competing nets. Finally, the timing critical section preferentially occupies the upper routable track.

4. And eliminating a large amount of overflow generated by the network segment adjustment strategy by using an effective network segment time delay optimization strategy at the later stage of the time delay optimization layer distribution stage based on the downstream capacitance. The net section time delay optimization strategy can eliminate net overflow while optimizing time delay by continuously disconnecting and rewinding the net and matching the influence of overflow cost.

The invention specifically adopts the following technical scheme:

a time delay driven layer distribution method under advanced process is characterized in that:

in the dynamic planning process of the wire mesh wiring in each stage, the layer distributor calculates the target cost by using the track number perception layer selection strategy, and the target function of each dynamic planning process is as follows:

α×delay(n)+β×#via_n+∑_s∈ncong(s_e)

cong(e)＝M₀×trc(e)+M₁×ofc(e)

wherein delay (n) and # via_nRespectively representing the time delay and the number of vias, cong(s), of the wire mesh n_e) Representing the congestion cost of the line segment s at the edge e; trc (e) represents the track residual cost at e, ofc (e) represents the overflow cost at e; alpha, beta, M₀,M₁Is a custom weight coefficient;

the method comprises the following steps:

step S1: equalizing sequencing initialization, comprising: establishing layer distribution priority for each net by using a multi-index driving initial net sorting strategy, and sequentially performing initial layer distribution for each net based on the priority of the net;

step S2: a downstream capacitance-based time delay optimization layer assignment comprising: a line network section adjusting strategy and a line network section time delay optimizing strategy; the wire mesh section adjusting strategy adjusts an upstream section with larger downstream capacitance to a routable track on an upper layer; the line network segment time delay optimization strategy is used for clearing and rewinding the line network according to the numerical value increasing sequence by sequencing the downstream capacitance of each line network segment, so as to eliminate a large amount of overflow in a wiring area.

Step S3: post-optimization: and performing the last disconnection and rewinding on all the nets under the condition of not generating new overflow, and comparing the target cost of the rewinding scheme with the target cost of the original scheme to take the optimal selection scheme as the final layer distribution result.

Preferably, the track number sensing layer selection strategy allocates the net segments to the metal layer with the largest number of remaining tracks in each net wiring process, so as to ensure that the number of remaining tracks of all the metal layers is not negative, and further reserve more selectable wiring layers for the next pre-allocated net.

Preferably, the track remaining cost formula of the track number sensing layer selection strategy is as follows:

wherein Remainc (e, l) represents the number of remaining tracks of e on l layer, then w (e) represents the ratio of the remaining tracks of l layer to the sum of the remaining tracks of each layer; the combination of formula cong (e) ═ M₀×trc(e)+M₁The congestion cost as a function of objective; k represents the number of wiring metal layers.

Preferably, in step S1, the layer distributor drives the initial net sorting strategy layer distributor according to the multiple indexes to calculate a score for each net according to the wire length, the number of missing points and the routing space density of the net, and the initialization routing priority of the net with higher score is larger:

wherein n is_iRepresenting a 2D global wiring net; m₂，M₃Is a self-defined variable; pinn (n)_i) Finger net n_iThe number of medium leakage points; len (n)_i) Representing a net n_iLine length in the 2D grid map; avgden (n)_i) Representing a net n_iRouting Density in 3D mesh graph, with size equal to Net n_iThe number of tracks required to be occupied is a ratio of the sum of the number of available tracks in each layer in the 3D grid map.

Preferably, M₂，M₃Set to 1 and 0.5, respectively.

Preferably, in step S2, the net segment adjustment includes the following steps:

step S21: establishing a storage library for each edge in the 2D grid graph, and storing the downstream capacitance values of each layer of wire net passing through the edge in the library;

step S22: sequencing the values in the library from big to small;

step S23: each line network is removed and rewound, and all sections with smaller downstream capacitance but higher level are removed before each rewinding;

step S24: and recovering the removed wire mesh section.

Preferably, in step S2, the method for optimizing the delay of the net segment includes the following steps:

step S25: traversing each edge according to the given 2D grid graph; establishing a corresponding library for each passing edge; if overflow exists on the 3D grid graph corresponding to the side, counting the downstream capacitance of the wire network passed by each layer, and storing the downstream capacitance in a library; if the overflow is not found during traversing each edge, obtaining a time delay optimization result of the line network section;

step S26: sorting all downstream capacitance values in the library in ascending order; and according to the sequence, the wire net where the wire network segment is located is removed and rewound;

step S27: if the edge still has overflow after rewinding, the historical cost and the time delay weight are increased, and the process returns to step S25.

Preferably, in step S1, α, β, M in the objective function is determined₀,M₁The values of (a) are set to 10,1, 12, 0.3, respectively; in step S2, the net section adjusting stage adjusts the length of the wire mesh₀All set to 2; beta, M in the post-optimization stage₀The values of (A) are all set to 1, 3.5.

Compared with the prior art, the invention and the preferred scheme aim to minimize the total time delay of the wire mesh, the maximum time delay of the wire mesh and the number of through holes. The method can achieve greater optimization on two indexes of time delay and the number of through holes under the condition of ensuring no overflow, thereby obtaining a high-quality overall wiring result.

Drawings

The invention is described in further detail below with reference to the following figures and detailed description:

FIG. 1 is a schematic diagram of processing and abstraction of a metal layer according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of an exemplary application of different types of wires according to an embodiment of the present invention;

FIG. 3 is a diagram illustrating an exemplary weighting according to an embodiment of the present invention;

FIG. 4 is a schematic flow chart of a method according to an embodiment of the present invention;

fig. 5 is a schematic diagram of an example of a selection policy of a track number sensing layer according to an embodiment of the present invention: (a) the environment before layer allocation, (b) the result of n1 according to the congestion sensing strategy, (c) the result of the congestion sensing strategy, (d) the result of the orbit number sensing layer selection strategy;

FIG. 6 is a schematic diagram illustrating a strategy for adjusting a net section according to an embodiment of the present invention;

fig. 7 is a schematic diagram of a policy flow for optimizing the delay of a net section according to an embodiment of the present invention.

Detailed Description

In order to make the features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail as follows:

1. problem model for this embodiment:

in the global routing problem, the metal layer in the multi-layer structure is divided into a plurality of rectangular regions of equal size, each of which is defined as a G-cell. A certain number of routable tracks exist between adjacent G-cells for allocating wire segments. Each metal layer is only in one horizontal or vertical wiring direction, and the wiring directions between two adjacent metal layers are mutually vertical. To facilitate routing, the layer distributor maps the multi-layer routing space into a 3D grid map, as shown in fig. 1. Because the specific routing conditions in each G-cell need not be processed in the global routing stage, each G-cell can be abstracted to a point in the 3D grid graph. The G-cells between the layers are connected through the through holes. The boundary between two adjacent G-cells in the same routing direction on the same layer is defined as an edge, corresponding to a routing track with a certain capacity, and each track can be provided with a default rule wire. For example, there are 4 routable tracks between two G-cells AB in fig. 1(a), and the capacity of the default ruled line corresponding to the two points AB in fig. 1(b) is 4. Since various obstacles may exist in the G-cell, the number of receivable tracks on different sides of the same layer may be different. When the number of the line segment distributed by the layer distributor on a certain 3D grid edge exceeds the routable track number of the edge, the 3D grid edge generates overflow. The formula for the overflow of edges is as follows:

where use (e) represents the number of net segments allocated at e, and cap (e) represents the number of tracks that can accommodate the net segments at e. When the number of wire mesh segments allocated is greater than the number of tracks that can accommodate a wire mesh segment, the overflow at e is equal to the difference between the two.

2. And (3) time delay calculation:

the present embodiment uses an Elmore delay model with good fidelity to calculate the net delay. A net has a source with a certain driving resistance and a plurality of drains with a certain load capacitance. The section of a net placed between two adjacent G-cells on the same wiring level is called a net segment. The collection of segments traversed from a source to a drain is defined as a path, and a net typically contains one or more paths. According to the time delay calculation formula of the Elmore model, the time delay calculation formula for a certain line segment s in the line network is as follows:

wherein R(s) and C(s) respectively represent resistance and capacitance of s segment, C_down(s) represents the downstream capacitance of the s segment. The delay of one path is equal to the sum of the delays of the network segments of the various lines.

delay(si)＝∑_s∈path(si)delay(s) (3)

Where path (si) represents the path where s segment is located, and si represents the missing point on the path. For a single net, the total net delay size is equal to the weighted sum of the individual path delays.

delay(N)＝∑_si∈S(N)α_si×delay(si) (4)

α_siIs the weight value of the missing point si, which represents the importance degree of the path to the located net. It is assumed here that the importance of each partial path is the same, so α will be_siSet to the inverse of the number of net leakage points.

3. Non-default ruled line:

the line width of the default regular line is called as default line width, the metal layers of different echelons have different default line widths, and the default line widths of the three echelons correspond to 1W,2W and 4W respectively. The default locations on the metal layer where the wires are placed are called tracks, and each track can accommodate a default ruled line.

The embodiment introduces the non-default ruled line technology in the advanced process on the basis of multi-layer wiring. The non-default ruled lines are divided into parallel lines and wide lines. The line width of the non-default ruled line is twice as large as the line width of the default ruled line on the same wiring layer. In order to reduce the influence of signal crosstalk between the wires, the wider the wire width, the larger the gap between the wires. The non-default ruled line therefore needs to occupy more track resources than the default ruled line. FIG. 2 is the result of replacing a default ruled line with a non-default ruled line. Where parallel lines of m1 layers need to occupy 2 routing tracks and wide lines of m5 layers need to occupy 3 routing tracks. Since the line width of the non-default ruled line is wider and the resistance of the non-default ruled line is smaller in physical characteristics, the time delay of the net can be effectively reduced by replacing the default ruled line in the graph 2.

4. And (3) congestion constraint:

to enhance the degree of matching between the overall routing and the detailed routing, the layer assignment phase needs to ensure that the nets meet the routable requirements. Thus, the layer allocator employs congestion constraints to ensure good layer allocation results.

TotalO(S^k)＝TotalO(S) (5)

S and S^kRespectively represent given 2D clothLine results and 3D routing results from 2D topology. k represents the number of wiring metal layers. TotalO and MaxO represent total edge overflow and maximum edge overflow, respectively. The total edge overflow quantity of the 2D routing result and the 3D routing result is guaranteed to be equal by the formula (5), namely, no extra overflow is generated in the 3D routing result. While equation (6) ensures that the maximum overflow of the 2D routing scheme is evenly distributed to the various metal layers in the 3D mesh graph.

5. Segment weighting:

each wire network segment in the 2D topology is distributed to different wiring layers, so that different wire network delay effects can be obtained. The impact of a net section on net timing is referred to herein as timing criticality. According to the delay calculation equation (2) of the Elmore model, the delay size of a net section depends greatly on the downstream capacitance of the section, so that the timing criticality of the net section close to the source point is stronger than that of the net section close to the drain point. In the process of continuously disconnecting and rewinding, the congestion cost of the line network is increased sharply, so that the proportion of the line network delay cost in the objective function is reduced. In order to further enhance the time delay optimization of the time sequence key segment, the layer distributor needs to perform segment weighting operation on the time sequence key segment in the layer distribution process. The following is a calculation formula of the middle section weighting of the distribution of the delay driving layer:

wherein w_s ⁱ⁺¹The delay weight, delay (si), of the s segment in the ith iteration is shown_j) The time delay of the leakage point of the path where the network segment s is located is represented, m represents the number of the leakage points in the network, δ is a custom constant used for controlling the updating strength of the weight of each network segment, and δ is set to be 1 in the experiment. r represents the number of sinks downstream of segment s. It can be seen from equation (7) that the weight of any segment is equal to the weighted sum of the average delays of its downstream leakage points.

As shown in FIG. 3, V₀Is the source point and the drain point V of the net₃,V₄The delay size of (2) is all. S₁,S₂,S₃The weights of all the network segments in the ith iteration process are respectively 1,0.5 and 0.5. After the iterative update calculation of the weight value once, the weight value of each line segment is updated to 3,1.5 and 1.5. Wire mesh segment S near the source point in FIG. 3(b)₁The weight of (A) is greater than that of other net segments in the same net, S₁Is the timing critical section of the net. Thus, during the routing of this net, the layer distributor will optimize the net section S heavily₁The delay size of (2) is allocated to the upper wiring layer.

6. The layer distribution method of time delay driving under the advanced process comprises the following steps:

the layer distribution method of time delay driving under the advanced process mainly comprises three stages: and a balanced sequencing initialization stage, namely a delay optimization layer distribution stage and a post optimization stage based on downstream capacitance. FIG. 4 is a flow chart of a delay-driven layer distribution method under an advanced process, wherein the layer distributor performs target cost calculation by using a track number aware layer selection strategy during the dynamic planning of net routing at each stage. In other words, each time the net wiring process distributes the net segments to the metal layer with the largest number of the remaining tracks as much as possible, so as to ensure that the number of the remaining tracks of all the metal layers is not negative, and further reserve more selectable wiring layers for the next pre-distributed net. Equations (8) and (9) are the objective functions for each dynamic planning process, as follows.

α×delay(n)+β×#via_n+∑_s∈ncong(s_e) (8)

cong(e)＝M₀×trc(e)+M₁×ofc(e) (9)

Wherein delay (n) and # via_nRespectively representing the time delay and the number of vias, cong(s), of the wire mesh n_e) Representing the congestion cost of the segment s at edge e. trc (e) represents the track residual cost at e, ofc (e) represents the overflow cost at e. Alpha, beta, M₀,M₁The weighting coefficients are self-defined, and in order to ensure different main optimization targets of each stage, the weighting coefficients (8) and (9) adopt different values in different stages.

(1) Equalized sorting initialization phase

The equalization sequencing initialization phase canThe pre-distribution wire net is uniformly distributed on the upper metal layer in a specific sequence, and an initial layer distribution result with better time delay is obtained. The equalization sequencing initialization stage is mainly divided into two steps: 1) establishing a layer distribution priority for each net by using a multi-index driving initial net sorting strategy; 2) and performing initial layer distribution for each net in sequence based on the priority of the net. In the process of initial layer distribution, the algorithm converts alpha, beta, M in the objective function₀,M₁The values of (d) are 10,1, 12, 0.3, respectively. Due to alpha, M₀The value of (2) is relatively large, so the layer distributor can ensure that the time delay is optimized while the balance of the number distribution of the remaining tracks of each layer is maintained as much as possible, and the wiring resources close to the upper layer are used as much as possible.

(2) Delay optimization layer distribution phase based on downstream capacitance

The time delay optimization layer distribution stage based on the downstream capacitance mainly comprises two strategies of network section adjustment and network section time delay optimization. The main role of the net section trimming strategy is to trim the upstream section with the larger downstream capacitance to the routable tracks of the upper layer as much as possible. At this stage, beta, M is defined herein as₀All set to 2 to further optimize the wire mesh and control the via count. The main goal of the net-segment delay optimization strategy is to eliminate a large amount of overflow in the routing area. Additional spillover occurs because the layer distributor refers partial segments to the upper layer in the network segment adjustment strategy. The time delay optimization strategy of the net sections can realize the effect of eliminating overflow by performing disconnection and rewinding on the net where each net section is positioned through a specific sequence. Beta, M in the objective function of this strategy and post-optimization stage₀The values of (A) are all set to 1, 3.5. And each time the 2D net is traversed, the layer distributor updates the overflow cost for the overflow edge, namely

ofc(e)＝pen_e×hist_e (10)

Wherein pen_eAnd hist_eRespectively representing the penalty term and the historical cost of the edge e. The value of the penalty term is related to the overflow of the edge, i.e.

pen_e＝max{0，a×(use(e)-cap(e))} (11)

Where use (e) and cap (e) respectively represent the track usage and the number of usable tracks at the edge e, and a is a custom coefficient for balancing the penalty strength, and is set to 1, i.e. the size of the penalty term is equal to the maximum value between 0 and the overflow value. The size of the history item is related to the history cost of the last iteration and the number of iterations.

Wherein hist_e ⁱAnd representing the historical cost of the e edge in the ith iteration process, wherein rho is a self-defined numerical value and is used for controlling the growth speed of the historical cost. When a layer distributor generates overflow on the e edge in a certain iteration process, the historical cost of the e edge is increased exponentially according to the iteration times. If a certain edge generates multiple overflows, the overflow cost of the edge is increased, so that the congestion cost is increased, and the algorithm avoids the overflow edge as much as possible when the routing layer is selected. The optimization strategy of the time delay of the line network segments is to perform disconnection and rewinding on the line network according to the numerical increasing sequence by sequencing the downstream capacitance of each line network segment, so that unreasonably distributed time sequence key segments can be further redistributed, and finally the effects of optimizing the time delay of the time sequence key segments and eliminating overflow of the line network are achieved.

(3) Post-optimization phase

The layer distributor further optimizes the first 5% of the timing critical net delay by using wide lines. And in the post-optimization stage, a larger congestion cost weight is defined, so that the last disconnection and rewinding can be carried out on all the nets under the condition of ensuring that no new overflow is generated, and the optimal selection scheme is used as a final layer distribution result by comparing the target cost of the rewinding scheme with that of the original scheme.

7. Selecting strategy of the track number perception layer:

the multilayer wiring structure divides the wiring layer into a plurality of gradients, and the default wire adopts default line widths with different specifications on the wiring layers with different gradients. Since the metal layer of the upper gradient is wider using the default line width of the conductive line, the assignment of the line net segments to the metal layer of the upper gradient can result in better time delay results. However, on the same gradient, due to the use of default ruled lines with the same line width between different metal layers, the layer assigner cannot effectively determine which layer the line net segment is assigned to more reasonably by only comparing the cost values of the objective function. For this situation, the present embodiment uses a track number sensing layer selection strategy, and the track remaining cost formula of the strategy is as follows:

where Remainc (e, l) represents the number of remaining tracks for e on the l layer, then w (e) represents the ratio of the remaining tracks on the l layer to the sum of the remaining tracks on each layer. The congestion cost combining equation (9) and equations (13) (14) as the objective function. Since the calculation formula (13) of the track residual cost is a modification of the sigmoid function, the larger the ratio of the number of the residual tracks of the l-th layer to the total number of the residual tracks, the smaller the track residual cost of the e-side at the l-layer, and accordingly, in combination with formula (9), the smaller the congestion cost of the e-side at the l-layer, the higher the possibility that the layer is selected as a wiring. The track number perception layer selection strategy is applied to the congestion cost of the objective function, relatively balanced track resource utilization rate can be kept for each wiring layer, so that track space is remained to a great extent for each layer, and richer wiring layers to be selected are provided for the next pre-wired line network.

As shown in fig. 5 a, in the illustrated two-layer wiring region, the total track capacity of each side of the upper and lower layers is 8, and the black, gray, and light gray portions correspond to the number of tracks occupied by the barrier being 8,4, and 1, respectively. Then n now needs to be paired₁，n₂The two nets are in turn layer distributed. Calculation formula according to congestion sensing policy, e_2,3Has a congestion cost less than e_2,1Thus n is₁The layer allocation result of (c) tends to FIG. 5(b), and when e_2,3Track space ofAfter being filled, n₂Routing to the underlying space is inevitably required under the constraints of routability, and thus an extra via count and via delay are generated in fig. 5 (c). The currently proposed track number sensing layer selection strategy does not focus on the utilization rate of the track resources of each layer, but selects the metal layer with the largest number of the rest tracks to carry out wire mesh section distribution. From the calculation formula (14) of the track number sensing layer selection strategy, w (e) in fig. 5(a)_2,3)＝1/3，w(e_2,1) 2/3, in combination with equations (9) and (13), the corresponding upper layer congestion cost is greater than the lower layer, net n₁The wiring pattern of (c) tends more to fig. 5 (d). In-progress net n₂The wire mesh can avoid additional winding under the guidance of the objective function when the layers are distributed. The layer allocation scheme obtained in fig. 5(d) is superior compared to the scheme of fig. 5(c) obtained by the existing congestion awareness policy.

8. The multi-index driving initial wire network sequencing strategy is as follows:

the initial net layer distribution needs to distribute pre-distributed nets to the 3D grid graph one by one, so that the available wiring resources are rich for each net to be distributed at the initial moment. In the stage of rewiring after initial allocation, most of the available wiring resources in the 3D wiring area are occupied by the nets and are affected by the overflow cost, and the flexibility of rewiring nets is greatly limited. Therefore, the layer allocation result of the initial net greatly influences the effective utilization of the upper layer resources by the later scheme. In order to obtain a relatively good initial layer distribution result, the layer distributor introduces a multi-index driving initial net sorting strategy, the strategy calculates a score for each net according to the line length, the number of leakage points and the wiring space density of the net, and the initial wiring priority of the net is higher when the score is higher.

Wherein n is_iA 2D global wiring net is shown. M₂，M₃Are custom variables that balance the importance of the two terms front and back, here setting them to 1 and 0.5。Pinn(n_i) Refers to the number of missing points in net ni. Len (n)_i) Representing a net n_iThe lines in the 2D grid graph are long. avgden (n)_i) Representing a net n_iRouting Density in 3D mesh graph, with size equal to Net n_iThe number of tracks required to be occupied is a ratio of the sum of the number of available tracks in each layer in the 3D grid map. In the first item, Pinn (n)_i)/Len(n_i) Is Len (n)_i)/Pinn(n_i) Inverse of (d), and Len (n)_i)/Pinn(n_i) Approximately represents the average length of a single leak in the net. The longer the average length of a single path, the more routing space and flexibility the path can be routed, thus giving a smaller score to the nets on which it is located. For the second term, the higher the routing density, the smaller the routing space for a single net, and therefore a higher score needs to be assigned to the net and the initial layer assignment to that net is performed first.

And the layer distributor distributes the nets to all the wiring layers according to the obtained priority level. By introducing a track number sensing layer selection strategy and setting a larger time delay coefficient in the objective function (8), the layer distributor can preferentially distribute the nets with higher priority and fully utilize the routable resources of the upper layer.

9. And (3) a net section adjusting strategy:

the segment weighting strategy is to update the weights of different segments in a new iteration on the basis of obtaining the time delay result of each line network in the last iteration process. It can be seen from formula (7) that the update value of each net segment weight in the segment weighting process is equal to the cumulative sum of the downstream leakage point time delays. The layer distributor updates the weights of the path overlapping sections with different dynamics to realize the weight differentiation of the time sequence key section and the non-time sequence key section. According to the Elmore time delay calculation formula (2), the timing criticality of the net section is closely related to the value of the downstream capacitance. Thus, the net segment adjustment strategy characterizes the timing criticality of the net segment approximately by the size of the downstream capacitance.

FIG. 6 is pseudo code for a net section alignment policy flow. First, for each edge in the 2D mesh graph, the row 2 to row 5 parts establish a storage bank for it, and store the downstream capacitance values of each layer of nets passing through the edge in the storage bank. Line 6 sorts the values in the bins in order of magnitude. The row 7 through row 20 sections then unwrap each net. All downstream net segments that have less capacitance but are located at a higher level are removed before each rewind, and the sections from row 15 to row 19 after the rewind restore the removed net segments. By the method, all sides are traversed finally, and the wiring layers of all the time sequence key sections are updated according to the size of the downstream capacitor. While employing a net segment scaling strategy increases the number of overflows in a wiring region, the overflows can be resolved by later steps. The later stage does not need to exchange wiring layers between the time sequence key section and the non-time sequence key section, and the wire network section adjusting strategy lays a good foundation for the wire disconnecting and rewinding of the later stage.

10. A network section time delay optimization strategy is as follows:

by adopting the wire mesh section adjusting strategy, the layer distributor can adjust the upstream time sequence key section to the upper layer wire mesh layer as much as possible, thereby limiting the effective position of the time sequence key section and providing a good initial result for the wire removing and rewinding process of the later stage. The existing method for removing and rewinding takes a wire net as a unit, and removes and rewinds the illegal wire nets which overflow. However, the optimal wiring method for a single net can only ensure the optimal wiring scheme under the condition that the single net is located, and cannot ensure that the effect of the overall wiring condition is optimal under the condition that a plurality of nets are superposed.

In order to ensure a better disconnecting and rewinding effect and match with an initial solution of a network segment adjustment strategy, the time delay optimization of the network segment is provided. Fig. 7 is a specific flowchart of the strategy for optimizing the delay of a net section. The specific flow of the algorithm is as follows:

1) the edges are traversed according to the given 2D grid graph. A corresponding library is built for each edge passed. And if overflow exists on the 3D grid graph corresponding to the edge, counting the downstream capacitance of the wire network passed by each layer, and storing the downstream capacitance in a library. And if no overflow is found during traversal of each edge, obtaining a time delay optimization result of the line network section.

2) All downstream capacitance values in the bank are sorted in ascending order. And according to the sequence, the wire net where the wire network segment is located is removed and rewound. Because the layer assigner has caused the timing-critical section to occupy the upper-layer routing track in the line segment adjustment strategy, net segments competing with the timing-critical section can be assigned to other routing layers in this order.

3) If the edge still has overflow after rewinding, the existing congestion cost is not enough to make the wire mesh avoid the 3D mesh edge. Therefore, the historical cost and the delay weight need to be increased. The former enhancement layer distributor avoids the capability of overflow edges, and the latter guide layer distributor explores a routing layer with higher optimization degree of time delay.

The present invention is not limited to the above preferred embodiments, and any other various types of advanced process time delay-driven layer allocation methods can be derived from the present invention, and all equivalent changes and modifications made within the scope of the present invention shall fall within the scope of the present invention.