阅读说明：本技术 局部字线驱动器件、存储器件及其制造方法 (Local word line driving device, memory device and method of manufacturing the same ) 是由 甘程 刘威 黄诗琪 陈顺福 于 2019-11-28 设计创作，主要内容包括：提供了局部字线驱动器件、存储器件和制造方法。局部字线驱动器件包括衬底和在衬底上形成的晶体管结构的阵列。晶体管结构被配置在行和列中。衬底包括多个第一场区和多个第二场区,每个第一场区在晶体管结构的相邻行之间,以及每个第二场区在晶体管结构的相邻列之间。深沟槽隔离结构在衬底的多个第一场区或多个第二场区中的至少一个场区中形成。(Provided are a local word line driving device, a memory device and a method of manufacturing the same. The local wordline driver device includes a substrate and an array of transistor structures formed on the substrate. The transistor structures are arranged in rows and columns. The substrate includes a plurality of first field regions and a plurality of second field regions, each first field region between adjacent rows of the transistor structures and each second field region between adjacent columns of the transistor structures. A deep trench isolation structure is formed in at least one of the plurality of first field regions or the plurality of second field regions of the substrate.)

1. A local wordline driver device comprising:

a substrate;

an array of transistor structures formed on the substrate, the transistor structures being arranged in rows and columns, wherein the substrate comprises:

a plurality of first field regions, each first field region between adjacent rows of the transistor structure, an

A plurality of second field regions, each second field region between adjacent columns of the transistor structures; and

a deep trench isolation structure formed in at least one field region of the plurality of first field regions or the plurality of second field regions of the substrate,

wherein: the transistor structures in the array include N-type transistors and p-well taps are formed in one or more remaining field regions of the plurality of first field regions or the plurality of second field regions of the substrate.

2. The device of claim 1, wherein:

the deep trench isolation structure has a dimension less than 0.5 microns.

3. The device of claim 1, wherein:

the deep trench isolation structure is made of a material comprising silicon oxide, silicon nitride, or silicon oxynitride.

4. The device of claim 1, wherein:

the deep trench isolation structure passes through an entire thickness of the substrate.

5. The device of claim 1, further comprising:

a dielectric layer formed on the substrate at a side opposite the array of transistor structures.

6. The device of claim 1, wherein:

the deep trench isolation structure is formed in each of the plurality of first field regions or the plurality of second field regions of the substrate.

7. The device of claim 1, wherein:

columns of transistor structures in the array are sandwiched by a deep trench isolation structure and a p-well tap.

8. The device of claim 1, wherein:

the deep trench isolation structure is formed in each of the plurality of second field regions, and

the p-well tap is formed in each of the plurality of first field regions of the substrate.

9. The device of claim 1, wherein:

the deep trench isolation structure is formed in each of the plurality of first field regions, and

the p-well taps and the deep trench isolation structures are alternately formed in the plurality of second field regions of the substrate.

10. A memory device, comprising:

a local wordline driver device comprising:

a substrate;

an array of transistor structures formed on the substrate, the transistor structures being arranged in rows and columns, wherein the substrate comprises:

a plurality of first field regions, each first field region between adjacent rows of the transistor structure, an

A plurality of second field regions, each second field region between adjacent columns of the transistor structures; and

a deep trench isolation structure formed in at least one field region of the plurality of first field regions or the plurality of second field regions of the substrate,

wherein: the transistor structures in the array include N-type transistors and p-well taps are formed in one or more remaining field regions of the plurality of first field regions or the plurality of second field regions of the substrate.

11. A method for forming a memory device, comprising:

providing a first wafer comprising:

a first substrate, an array of transistor structures configured in rows and columns and formed on the first substrate, isolation structures formed in the first substrate and between adjacent transistor structures, and a first dielectric layer formed on the array of transistor structures;

providing a second wafer comprising a second substrate and a second dielectric layer formed on the second substrate;

bonding the second dielectric layer of the second wafer with the first dielectric layer of the first wafer;

thinning the first substrate to provide a thinned first substrate;

forming a back side deep trench through the thinned first substrate, wherein the back side deep trench is connected to the isolation structure of the first wafer; and

forming backside deep trench isolation structures on the respective isolation structures by forming a dielectric material in the backside deep trenches,

wherein: the transistor structures in the array include N-type transistors and p-well taps are formed in one or more remaining field regions of the plurality of first field regions or the plurality of second field regions of the substrate.

12. The method of claim 11, wherein the first substrate comprises:

a plurality of first field regions, each first field region between adjacent rows of transistor structures, an

A plurality of second field regions, each second field region between adjacent columns of transistor structures.

13. The method of claim 12, wherein:

the transistor structure in the array comprises N-type transistors, and

the method further comprises the following steps:

forming a p-well tap in one or more field regions without any backside deep trench isolation structures subsequently formed in the first wafer prior to bonding the second dielectric layer of the second wafer with the first dielectric layer of the first wafer.

14. The method of claim 11, further comprising:

forming a third dielectric layer on the thinned first substrate, and

wherein forming the backside deep trench further comprises:

forming the backside deep trench through the third dielectric layer and the thinned first substrate.

15. The method of claim 11, wherein:

the second wafer includes a memory array.

16. The method of claim 11, wherein:

the backside deep trench isolation structure and the isolation structure are made of different materials.

17. The method of claim 11, wherein:

the backside deep trench isolation structure is made of a material comprising silicon oxide or silicon oxynitride.

18. The method of claim 11, wherein:

the backside deep trench isolation structure is formed by a deposition process comprising Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), or Atomic Layer Deposition (ALD).

19. The method of claim 11, wherein:

the backside deep trenches at least partially expose surfaces of respective isolation structures.

Technical Field

In general, the present disclosure relates to the field of memory devices. More particularly, the present disclosure relates to a local word line driver device and a method of fabricating the same.

Background

In high density memory, an array of memory cells is divided into blocks of memory cells. Each block may include local word lines, requiring a corresponding local word line driver. The global word line drivers drive groups of global word lines for columns of blocks in the array. Each word line in the global word line group is set according to the operation applied to the selected block, such as reading, programming, and erasing of high density devices. Some word lines may require high voltages. The word line driver may include pass transistors for transferring voltages from the global word lines to the local word lines.

In a three-dimensional NAND memory, chip size limitations may cause the pitch between HVN (i.e., high voltage NMOS) devices in an XDEC pass transistor circuit to become smaller in both the X and Y directions. During a cell programming operation, the pass transistor requires a high voltage of 25V to pass the source/drain region at a gate voltage of 29V. The voltage difference between adjacent HVN devices may be about 25V. Conventionally, p-type field implants are formed between HVN devices in the X-direction to suppress punch-through, and p + taps are formed between HVN devices in the Y-direction to suppress latch-up.

A problem arises, however, because the field implant requires the implantation of the same type of ions as in the substrate, which may worsen the drain-source breakdown voltage (BVDss) of the HVN device. Furthermore, to ensure the function of the p + tap, the pitch between HVN devices in the Y direction cannot continue to shrink, and thus affects the Y-pitch shrink of the memory device.

The disclosed devices and methods of manufacture are directed to solving one or more of the problems set forth above and other problems in the art.

Disclosure of Invention

One aspect of the present disclosure provides a local wordline driver device including a substrate and an array of transistor structures formed on the substrate. The transistor structures are arranged in rows and columns. The substrate includes a plurality of first field regions and a plurality of second field regions, each first field region between adjacent rows of the transistor structures and each second field region between adjacent columns of the transistor structures. A deep trench isolation structure is formed in at least one of the plurality of first field regions or the plurality of second field regions of the substrate.

Another aspect of the present disclosure provides a memory device. The memory device includes a local word line driver device. The local wordline driver device includes a substrate and an array of transistor structures formed on the substrate. The transistor structures are arranged in rows and columns. The substrate includes a plurality of first field regions and a plurality of second field regions, each first field region between adjacent rows of the transistor structures and each second field region between adjacent columns of the transistor structures. A deep trench isolation structure is formed in at least one of the plurality of first field regions or the plurality of second field regions of the substrate.

Another aspect of the present disclosure provides a method for forming a memory device. The first wafer includes a first substrate, an array of transistor structures arranged in rows and columns and formed on the first substrate, isolation structures formed in the first substrate and between adjacent transistor structures, and a first dielectric layer formed on the array of transistor structures. The second wafer includes a second substrate and a second dielectric layer formed on the second substrate. The second dielectric layer of the second wafer is bonded to the first dielectric layer of the first wafer. The first substrate is thinned to provide a thinned first substrate. A backside deep trench is formed through the thinned first substrate, and the backside deep trench is connected to the isolation structure of the first wafer. Backside deep trench isolation structures are formed on the respective isolation structures by forming a dielectric material in the backside deep trenches.

Other aspects of the disclosure may be understood by those skilled in the art in light of the description, claims, and drawings of the disclosure.

Drawings

The following drawings are merely examples for illustrative purposes according to various disclosed embodiments and are not intended to limit the scope of the present disclosure.

FIG. 1 illustrates a portion of an exemplary local wordline driver device consistent with various disclosed embodiments in this disclosure;

FIG. 2 illustrates an exemplary transistor structure along the y-y' direction in FIG. 1 consistent with various disclosed embodiments in this disclosure;

FIG. 3 illustrates a portion of another exemplary local wordline driver device consistent with various disclosed embodiments in this disclosure;

FIG. 4 illustrates a portion of another exemplary local wordline driver device consistent with various disclosed embodiments in this disclosure;

FIG. 5 illustrates a flow chart of an exemplary method for forming an exemplary memory device including a local wordline driver device consistent with various disclosed embodiments in the present disclosure; and

fig. 6-10 show schematic diagrams of semiconductor structures at certain stages during the fabrication process of an exemplary memory device, consistent with various disclosed embodiments in this disclosure.

Detailed Description

Reference will now be made in detail to exemplary embodiments of the invention, which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts.

The present disclosure provides a local wordline driver device, a memory device and a method of manufacturing. The local wordline driver device includes a substrate and an array of transistor structures formed on the substrate. The transistor structures are arranged in rows and columns. The substrate includes a plurality of first field regions and a plurality of second field regions, each first field region between adjacent rows of the transistor structures and each second field region between adjacent columns of the transistor structures. A deep trench isolation structure is formed in at least one of the plurality of first field regions or the plurality of second field regions of the substrate.

Fig. 1 illustrates a portion of an exemplary Local Word Line Driver (LWLD) device 100 of a memory device according to various embodiments of the present disclosure. Fig. 2 illustrates a cross-sectional view of an exemplary transistor structure along the y-y' direction of the LWLD device 100 of fig. 1, according to various embodiments of the present disclosure.

As shown in fig. 1-2, an exemplary LWLD device 100 may include a substrate 110, an array of transistor structures 101 formed on the substrate 110, and at least one Deep Trench Isolation (DTI) structure 140 formed in the substrate 110. Alternatively and additionally, one or more p-well taps 180 may be formed in the substrate 110.

In one embodiment, the transistor structures 101 in the array may be N-type transistors. In various embodiments, the transistor structure 101 may also be referred to as a high voltage nmos (hvn) structure. The transistor structure 101 may comprise a single transistor or back-to-back transistors. For example, the transistor structure 101 may include a transistor having a shared/common drain region. The transistor structures in the array may be used as pass transistors for connecting global word lines to local word lines in a high density memory device. One of the source/drain electrodes of the transistor may be connected to a word line of the memory device. A word line may be coupled to a plurality of memory cells.

As shown in fig. 2, a transistor structure may be formed in an exemplary triple well structure to support a high voltage applied to a local word line. For example, the transistor structure 101 or the pass transistor may be formed in a substrate 110 (such as a p-type substrate). The substrate 110 may be made of a material including silicon, germanium, SiGe, SiC, silicon-on-insulator (SOI), germanium-on-insulator (GOI), glass, III-V compounds (e.g., GaN, GaAs, InAs, etc.), or any other suitable semiconductor material. In one embodiment, the substrate 110 is a silicon substrate.

An N-well 112, such as a deep N-well (DNW), may be formed in the p-type substrate. The N-well 112 may be doped with N-type ions including P ions, As ions, Sb ions, and the like. A P-well 114, such as a high voltage P-well (HVPW), may be formed in the n-well 112. P-well 114 may be doped with P-type ions including B ions, Ga ions, In ions, and the like. The triple well structure provides isolation of the channel region of the pass transistor from the ground structure.

The gate structure may include a gate electrode 165 formed on the gate dielectric layer 163. A gate structure may be formed on the substrate 110. Source/drain regions 150 may be formed in the substrate 110 on each side of the gate structure. Source/drain regions 150 may be, for example, doped n-regions. Such doped n-regions may be high voltage n-type (HVN) regions. Source/drain electrodes 155 may be formed on the source/drain regions 150. Conductive plugs or other interlayer connections may be electrically connected to the source/drain electrodes.

Referring to fig. 1, the transistor structures 101 in the array may be arranged along an X-direction (e.g., a row direction) and a Y-direction (e.g., a column direction). For example, the array may include rows and columns of transistor structures 101. In one embodiment, the Y direction may be a direction parallel to a channel length between a source region and a drain region of a transistor. The X direction may be substantially perpendicular to the Y direction.

The LWLD device 100 may also include field regions 190 having a size or providing a spacing between any adjacent transistor structures 101. The field regions 190 may include a first field region 190a between adjacent transistor structures 101 in the Y direction (e.g., between adjacent rows of transistor structures 101) and a second field region 190b between adjacent transistor structures 101 in the X direction (e.g., between adjacent columns of transistor structures 101).

At least one DTI structure 140 may be formed in the first and/or second field regions 190a-b of the substrate 110 between any adjacent rows and/or columns of transistor structures 101. For example, as shown in fig. 1, the LWLD device 100 may include one DTI structure 140 formed in a first field region 190a between adjacent rows of transistor structures, and one DTI structure 140 formed in a second field region 190b between adjacent columns of transistor structures.

The DTI structure 140 may be made of a dielectric material including silicon oxide, silicon nitride, silicon oxynitride, or any other suitable material. In one embodiment, the DTI structure 140 is silicon oxide. The DTI structure may have a dimension of less than about 0.5 microns.

The thickness of the DTI structure 140 may be controlled according to the thickness of the substrate 110. For example, DTI structure 140 may be formed through the entire thickness of substrate 110.

In one embodiment, the LWLD device 100 may further include a dielectric layer 190 on the substrate 110 at a side opposite the array of transistor structures 101. In this case, the DTI structure 140 may be formed through the entire thickness of each of the substrate 110 and the dielectric layer 190. Accordingly, the thickness of the DTI structure 140 may be further controlled, depending on the thickness of each of the substrate 110 and the dielectric layer 190.

Referring back to fig. 1, in addition to the at least one DTI structure 140, well taps (such as p-well taps 180 or p + taps) may be formed in one or more remaining first and second field regions 190a-b between adjacent rows or columns of the transistor structure 101. For example, as shown in fig. 1, the p-well tap 180 may be formed in one of the second field regions 190b between corresponding adjacent columns of the transistor structure 101. In some embodiments, the p-well tap may also be referred to as a p-type high voltage (PHV) rod.

In one embodiment, one p-well tap 180 and one DTI structure 140 may be formed on the second field regions 190b located on both sides of one of the columns of the transistor structures 101. In a particular example, the p-well taps 180 and the DTI structures 140 may be alternately formed on the second field regions 190b between the columns of the transistor structures 101. In some embodiments, one column of the transistor structure 101 is sandwiched by the p-well tap 180 and the DTI structure 140.

In conventional memory devices, p-type field implants may be formed in the field regions between adjacent columns of n-type transistor structures to suppress punch-through. However, field implants require the same type of ion implantation in the substrate, which may worsen the drain-source breakdown voltage (BVDss) of the transistor structure. Furthermore, during manufacturing, field implants may be formed that require additional masks and processes, which increase the cost and complexity of the manufacturing process.

Instead, the field implants are eliminated from the disclosed LWLD device. Alternatively, forming a DTI structure in an LWLD device may effectively solve the punch-through problem and may also reduce the cost and complexity of the manufacturing process. Furthermore, the DTI structure provides more controllable dimensions than the conventionally used field implants and p + well regions. For example, the formation of DTI structures may provide a reduced surface area (or reduced pitch) of the field regions between adjacent rows and columns of transistor structures. Even further, DTI structures may be formed based on (e.g., aligned with and formed over) isolation structures between transistor structures without occupying additional field regions of the substrate. In fact, due to the formation of the DTI structure, the conventionally formed p + wells located adjacent to the isolation structure may thus be eliminated to save more pitch for the disclosed device. This allows for significant scaling of the resulting LWLD device and significantly increases the storage density of the resulting memory device.

According to various embodiments, the LWLD device may include various configurations including at least one DTI structure. For example, the DTI structure may be formed in all of the first and second field regions between adjacent rows and columns of the transistor structure. In another example, any combination of DTI structures and p-well taps may be included in the disclosed LWLD device. Fig. 3-4 illustrate other exemplary local wordline driver devices consistent with various disclosed embodiments in this disclosure.

Referring to fig. 3, in the exemplary LWLD device 300, the DTI structure 340 may be formed on all of the second field regions 390b between all of the adjacent columns of the transistor structure 301, and the p-well tap 380 may be formed on all of the first field regions 390a between all of the adjacent rows of the transistor structure 301. In this case, the size of the field regions or spaces between adjacent columns can be significantly reduced. Such a configuration may be used, for example, in a three finger block scheme of a memory device.

Of course, alternatively in another exemplary LWLD device, the DTI structure may be formed on all of the first field regions, and the p-well tap may be formed on all of the second field regions. In this case, the size of the field regions or spaces between adjacent rows can be significantly reduced.

Referring to fig. 4, in the exemplary LWLD device 400, the DTI structures 440 may include a first plurality of DTI structures formed in all of the first field regions 490a between all of the adjacent rows of the transistor structures 401, and may include a second plurality of DTI structures formed in some of the second field regions 490b between corresponding adjacent columns of the transistor structures 401. In addition, one or more p-well taps 480 may be formed in some of the second field regions 490b between respective adjacent columns of transistor structures 401. For example, as shown in fig. 4, the DTI structure 440 and the p-well tap 480 may be alternately formed in the second field region 490 b. Such a configuration may be used, for example, in a three finger block scheme of a memory device.

Various embodiments may also provide memory devices including the disclosed LWLD devices. For example, a memory device may include a memory array that includes blocks of memory cells. A block of memory cells may include a plurality of NAND strings. Multiple NAND strings may share a set of word lines. The row decoder may be coupled to a plurality of word lines arranged along rows in the memory array. The row decoder may include an LWLD device including a Local Word Line (LWL) group driver that drives a respective word line in the group of word lines in the block of memory cells.

Various embodiments also provide methods for forming word line driver (LWLD) devices and memory devices including LWLD devices. Fig. 5 illustrates an exemplary method for forming an exemplary memory device consistent with various disclosed embodiments in this disclosure. Fig. 6-10 show schematic views of a semiconductor structure at certain stages of an exemplary formation process.

Referring to fig. 5, at the beginning of the manufacturing process, a first wafer is provided (S502). The first wafer may include an array of transistor structures arranged in rows and columns and formed on a first substrate, isolation structures formed in the first substrate and between adjacent transistor structures, and a first dielectric layer formed on the array of transistor structures. Fig. 6 shows a schematic cross-sectional view of a corresponding semiconductor structure.

In fig. 6, a first wafer 600 is provided. The first wafer 600 may include a first substrate 610 and an array of transistor structures 601 formed on the first substrate 610.

The transistor structure 601 may be formed in a triple well structure to support high and negative voltages applied to local word lines. For example, the first substrate 610 may be a p-type substrate; an n-well 612, such as a deep n-well (DNW), may be formed in the first substrate 610; and a p-well 614, such as a high voltage p-well (HVPW), may be formed in n-well 612. Any suitable substrate may be used for substrate 610. The substrate 610 may be the same as or different from the substrate 110 of fig. 1-2.

In the transistor structure 601, a gate structure may be formed on a first substrate 610. Source/drain regions may be formed in the p-well 614 on each side of the gate structure of the transistor structure. Transistor structure 601 may include any transistor used as a pass transistor. Pass transistors may be used to connect global word lines to local word lines in a high density memory device.

Any suitable transistor structures may be formed in the first wafer 601. For example, although not shown in fig. 6, transistor structure 601 may also include transistor structures 101, 200, 301, and 401 as shown in fig. 1-4 along with their respective configurations. For example, the transistor structures 601 in the array may be arranged along an X-direction (e.g., a row direction) and a Y-direction (e.g., a column direction). The array may include rows and columns of transistor structures 601 formed on a first substrate 610.

Isolation structures 670 may be formed in the first substrate 610 and between the transistor structures 601. The isolation structure 670 may include a shallow trench isolation structure formed of a dielectric material.

A first dielectric layer 680 may be formed on the first substrate 610. The first dielectric layer 680 may include an interlayer dielectric layer. Conductive interconnect 685 may be formed in first dielectric layer 680. Conductive interconnect 685 can be electrically connected to the gate structure and source/drain regions of each transistor structure 601.

In various embodiments, the first wafer 600 may optionally include a single p-well tap or multiple p-well taps, including those shown in fig. 1 and 3-4, formed in an appropriate field region. In the case where p-well taps are included in the formed memory device, the p-well taps may be pre-fabricated prior to bonding the first wafer to the second wafer (e.g., a memory array wafer) and/or prior to formation of the deep trench isolation structures.

Referring back to fig. 5, a second wafer may be provided and bonded with the first wafer (S504). The second wafer may include a second substrate and a second dielectric layer on the second substrate. The second dielectric layer of the second wafer may be bonded to the first dielectric layer of the first wafer. Fig. 7 shows a schematic cross-sectional view of a corresponding semiconductor structure.

In fig. 7, a second wafer 700 may include a second substrate 706 and a second dielectric layer 708 on the second substrate 706. The second dielectric layer 708 of the second wafer 700 may be bonded with the first dielectric layer 680 of the first wafer 600 such that the first and second wafers are bonded together.

For example, when bonding the second wafer 700 with the first wafer 600, the second dielectric layer 708 may adhere to the first dielectric layer 680. In various embodiments, the second wafer 700 may be a memory array wafer including a memory array of memory devices. Any suitable materials and processes for the dielectric layers and the substrate of the memory array wafer may be used for the disclosed second substrate 706 and second dielectric layer 708 and are encompassed by this disclosure.

Referring back to fig. 5, the first substrate of the first wafer may be thinned to provide a thinned first substrate, and a third dielectric layer may be formed on the thinned first substrate (S506). Fig. 8 shows a schematic cross-sectional view of a corresponding semiconductor structure.

In fig. 8, a thinning process may be performed from the backside of the first wafer 600. The thinning process may include one or more of a chemical mechanical polishing process (CMP), a wet etch process, or a dry etch process. The first substrate 610 may be thinned to form a thinned first substrate 610 a. In one embodiment, after thinning, n-well 612 may (or may not) be exposed.

Optionally, a third dielectric layer 810 may be deposited on the thinned first substrate 610 a. For example, the third dielectric layer 810 may comprise any suitable dielectric material and may be deposited by a process of Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), or Atomic Layer Deposition (ALD).

Referring back to fig. 5, a backside deep trench may be formed through the optional third dielectric layer and/or the thinned first substrate, the backside deep trench being connected to the isolation structure (S508). Fig. 9 shows a schematic cross-sectional view of a corresponding semiconductor structure.

In fig. 9, a backside deep trench 910 (e.g., a via) can be formed through the third dielectric layer 810 and/or the thinned first substrate 610a and between the transistor structures 601. Backside deep trenches 910 can be formed that connect to respective isolation structures 670.

To form the backside deep trench 910, a patterned layer (not shown) may be formed on the third dielectric layer 810. The patterned layer may expose portions of the third dielectric layer 810 on the thinned first substrate 610 a. The exposed portions of the third dielectric layer 810 and the underlying thinned first substrate 610a may be removed by an etching process using the patterned layer as an etch mask. After the etching process, the patterned layer may be removed. Any suitable etching process may be used depending on the materials used for the third dielectric layer 810 and the thinned first substrate 610 a. For example, a wet and/or dry etching process may be used to remove the third dielectric layer 810 and/or the thinned portion of the first substrate 610a to form the backside deep trench 910.

The backside deep trenches 910 may be aligned with the isolation structures 670 such that the backside deep trenches 910 are connected to the respective isolation structures 670 to partially or fully expose surfaces of the respective isolation structures 670. For example, an orthogonal projection of each backside deep trench 910 may partially or fully cover an orthogonal projection of a respective isolation structure 670 on an interface between the thinned first substrate 610a and the second dielectric layer 680.

Referring back to fig. 5, a Backside Deep Trench Isolation (BDTI) structure may be formed on the isolation structure to fill the backside deep trench (S510). Fig. 10 shows a schematic cross-sectional view of a corresponding semiconductor structure.

In fig. 10, a backside dti (bdti) structure 930 may be formed in each backside deep trench 910 through the thinned first substrate 610a and/or the third dielectric layer 810. The BDTI structure 930 is formed between the transistor structures 601. The BDTI structure 930 may be formed at least partially connected to the isolation structure 670. The BDTI structure 930 may "extend" the isolation structure 670 through the first substrate and/or further through a third dielectric layer on the first substrate.

The orthogonal projection of each BDTI structure 930 may partially or fully cover the orthogonal projection of the corresponding isolation structure 670 on the interface between the thinned first substrate 610a and the second dielectric layer 680.

The BDTI structure 930 may be made of a dielectric material including silicon oxide, silicon nitride, silicon oxynitride, or any other suitable material. The BDTI structure 930 may be formed by a deposition process, such as Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), or Atomic Layer Deposition (ALD). In one embodiment, the BDTI structure 930 may be formed by an oxidation process. The BDTI structure 930 is made of silicon oxide. The deep trench isolation (BDTI) structure may have one dimension less than about 0.5 microns.

For example, to form the BDTI structure 930, a BDTI material film may be deposited on the backside deep trench 910 and on the surface of the third dielectric layer 810. A planarization process may then be performed to remove a portion of the BDTI material film on the third dielectric layer 810 to expose a surface of the third dielectric layer 810.

The thickness of the BDTI structure 930 may be controlled depending on the thinning process of the first substrate 610 and the thickness of the third dielectric layer 810.

Thus, the combination of the BDTI structure 930 and the isolation structure 670 may form the disclosed Deep Trench Isolation (DTI) structure 940. The BDTI structure 930 and the isolation structure 670 may be made of the same or different materials in the DTI structure 940.

Such DTI structures (including BDTI and isolation structures) may be formed along rows and/or columns of transistor structures in field regions to enhance LWLD devices, as similarly described in fig. 1 and 3-4. By forming the DTI structure based on the isolation structure, a field region of the first substrate 610 can be saved or reduced. Furthermore, conventionally formed p + wells located adjacent to the isolation structures may be eliminated to save more space and provide field regions with reduced surface area of the resulting device.

Furthermore, the DTI structure can effectively address punch-through issues of the resulting device, and can also reduce the cost and complexity of the fabrication process, as compared to conventional p-type field implants (which can be eliminated from the disclosed LWLD device) formed in the field regions between adjacent columns of n-type transistor structures. Furthermore, the DTI structure provides more controllable dimensions than the conventionally used combination of field implants and p + well regions, which allows for significant scaling of the resulting device and significantly improves the storage density of the resulting memory device.

The description set forth above illustrates only certain exemplary embodiments of the disclosure and is not intended to limit the scope of the disclosure. It will be appreciated by those skilled in the art that the features of the specification as a whole and in various embodiments may be combined into other embodiments as would be understood by one of ordinary skill in the art. Any equivalents or modifications thereof fall within the true scope of the present invention without departing from the spirit and principles of the invention.