阅读说明：本技术 存储器装置及其修复方法 (Memory device and repair method thereof ) 是由 柳睿信 吴伦娜 金玄基 于 2020-09-10 设计创作，主要内容包括：提供了存储器装置及其修复方法。存储器装置包括行解码器、列解码器和修复控制电路,修复控制电路被配置为：(i)将行地址与存储的故障行地址进行比较,(ii)将列地址与存储的故障列地址进行比较,(iii)当行地址对应于故障行地址时控制行解码器激活多条冗余字线中的至少一条,以及(iv)当列地址对应于故障列地址时控制列解码器激活多条冗余位线中的至少一条。修复控制电路在修复操作期间根据输入的地址来改变修复单元。(A memory device and a repair method thereof are provided. The memory device includes a row decoder, a column decoder, and a repair control circuit configured to: (i) comparing the row address to a stored failed row address, (ii) comparing the column address to a stored failed column address, (iii) controlling the row decoder to activate at least one of the plurality of redundant word lines when the row address corresponds to the failed row address, and (iv) controlling the column decoder to activate at least one of the plurality of redundant bit lines when the column address corresponds to the failed column address. The repair control circuit changes the repair unit according to an inputted address during a repair operation.)

1. A memory device, comprising:

an address buffer configured to store a plurality of bits of a received address;

a first non-volatile memory configured to store a plurality of bits of a fail address;

a plurality of first logic circuits each configured to compare one bit of the received address stored in the address buffer with a corresponding bit of the failed address stored in the first non-volatile memory;

a first selector configured to output a selected one of two output values from two first logic circuits among the plurality of first logic circuits in response to a selection signal;

a second logic circuit configured to output an address matching signal based on the selected output value and output values of the remaining first logic circuits except for the two first logic circuits;

a second nonvolatile memory configured to store an address bit value corresponding to the selection signal;

a second selector configured to output one bit of the address bits corresponding to the two first logic circuits in response to the inverted selection signal; and

a third logic circuit configured to perform an AND operation on the address matching signal and an output value of the second selector.

2. The memory device of claim 1, wherein the received address is a row address or a column address.

3. The memory device of claim 1, wherein each of the plurality of first logic circuits is configured to perform an exclusive-nor operation; and wherein the second logic circuit performs an and operation.

4. The memory device of claim 1, wherein each of the plurality of first logic circuits is configured to perform an exclusive-or operation; and wherein the second logic circuit performs a nand operation.

5. The memory device of claim 1, wherein the received address is a 16-bit row address; and wherein each of the first and second selectors receives first and sixteenth address bits among address bits of the row address.

6. The memory device of claim 5, wherein the second non-volatile memory stores bit values of a sixteenth address bit.

7. The memory device of claim 5, wherein each of the first non-volatile memory and the second non-volatile memory comprises at least one fuse.

8. The memory device according to any one of claims 5, 6, and 7, wherein the first nonvolatile memory stores mapping information on a logical address and a physical address corresponding to the logical address; and wherein a bit type of the address corresponding to the mapping information and the number of addresses are variable.

9. A memory device, comprising:

a memory cell array having a redundant region corresponding to a redundant word line and/or a redundant bit line and a normal region corresponding to the word line and the bit line;

a row decoder configured to activate at least one of the word lines and/or activate at least one of the redundant word lines in response to a row address;

a column decoder configured to activate at least one of the bit lines and/or activate at least one of the redundant bit lines in response to a column address; and

a repair control circuit configured to: comparing the row address with a stored failed row address, comparing the column address with a stored failed column address, controlling the row decoder to activate the at least one of the redundant word lines when the row address corresponds to the failed row address, and controlling the column decoder to activate the at least one of the redundant bit lines when the column address corresponds to the failed column address.

10. The memory device of claim 9, wherein the repair unit comprises: the type of address bits and/or the number of address bits.

11. The memory device of claim 9, wherein the repair control circuit comprises:

a fail address memory configured to store a fail row address and/or a fail column address;

a repair unit determiner configured to determine a repair unit corresponding to the input address; and

an address comparator configured to compare the row address with a failed row address and/or to compare the column address with a failed column address.

12. The memory device of claim 11, wherein the failed address memory comprises: a first non-volatile memory storing a plurality of address bits corresponding to a failed address.

13. The memory device of claim 12, wherein the repair unit determiner comprises:

a second nonvolatile memory configured to store at least one address bit, which is ignored in a repair operation, among the plurality of address bits and output a selection signal; and

an inverter configured to invert the selection signal.

14. The memory device of claim 13, wherein the address comparator comprises:

a plurality of first logic circuits each configured to: receiving one of input address bits and an address bit stored in a first non-volatile memory corresponding to the one address bit, and performing an exclusive-nor operation on the one address bit and the stored address bit;

a selector configured to select one output value of at least two first logic circuits among the plurality of first logic circuits in response to a selection signal; and

a second logic circuit configured to output the address matching signal by performing a logical AND operation on the output value of the selector and output values of the remaining first logic circuits except for the at least two first logic circuits of the plurality of first logic circuits.

15. The memory device of claim 13, wherein the address comparator comprises:

a plurality of first logic circuits each configured to: receiving one of input address bits and an address bit stored in a first non-volatile memory corresponding to the one address bit, and performing an exclusive-or operation on the one address bit and the stored address bit;

a selector configured to select one output value of at least two first logic circuits among the plurality of first logic circuits in response to a selection signal; and

a second logic circuit configured to output the address matching signal by performing a logical nand operation on the output value of the selector and output values of the remaining first logic circuits except for the at least two first logic circuits of the plurality of first logic circuits.

16. The memory device according to claim 14 or 15, wherein the redundant word line and/or the redundant bit line is activated in response to an address matching signal of the address comparator and an inverted selection signal of the repair cell determiner.

17. A repair method of a memory device, comprising:

receiving an address;

determining a repair unit using at least one address bit to be ignored in a repair operation among address bits of the received address;

comparing the received address with a stored failed address; and

when the received address corresponds to the stored failed address, the redundant cell array having the repair cell is accessed in response to the address.

18. The repair method of claim 17, further comprising: mapping information about logical addresses and physical addresses corresponding to the addresses is stored in a non-volatile memory in a test operation.

19. The repair method according to claim 17 or 18, wherein the step of determining a repair unit comprises: the type of address bits and the number of address bits are determined in the repair operation.

20. A repair method according to claim 17 or 18, further comprising:

storing repair mapping information on the redundant cell; and

repairing the normal cell using the repair map information with the redundant cell, and

wherein the memory cell area corresponding to the repair map information is variable.

Technical Field

The inventive concepts relate to memory devices having variable memory cell repair capabilities and methods of repairing memory devices using memory cell redundancy.

Background

Generally, as miniaturization in a process of manufacturing a Dynamic Random Access Memory (DRAM) progresses, the incidence of memory cells having hard defects or soft defects (i.e., defective memory cells) increases. In this case, a memory cell having a hard defect may represent a memory cell having a relatively permanent defect, and a memory cell having a soft defect may represent a memory cell having a relatively slight defect of a temporary defect. In order to secure the full memory capacity of the DRAM, a repair method of replacing a defective cell with a spare cell or a redundant cell provided independently of a normal cell may be adopted as a method of repairing the defective cell. For example, a repair method of replacing an entire row including a defective cell with a spare row or a redundant row (i.e., row repair) or replacing a column including a defective cell with a spare column or a redundant column (i.e., column repair) may be employed.

Disclosure of Invention

An aspect of the inventive concept is to provide a memory device to change a repair unit and a repair method thereof.

According to an aspect of the inventive concept, there is provided a memory device including: an address buffer configured to store a plurality of bits of a received address (e.g., a row address, a column address); and a first non-volatile memory configured to store a plurality of bits of the fail address. A plurality of first logic circuits are also provided and each of the logic circuits is configured to compare one bit of the received address stored in the address buffer with a corresponding bit of the failed address stored in the first non-volatile memory. A first selector is provided, the first selector being configured to output a selected one of two output values from two first logic circuits among the plurality of first logic circuits in response to a selection signal. A second logic circuit configured to output an address matching signal based on the selected output value and output values of the remaining first logic circuits other than the two first logic circuits is provided. A second non-volatile memory is provided that is configured to store address bit values corresponding to the select signals. A second selector is provided, the second selector configured to output one of the address bits corresponding to the two first logic circuits in response to a true version or an inverted version of the selection signal. A third logic circuit is provided, the third logic circuit configured to perform an AND operation on the address matching signal AND the output value of the second selector. According to some of these embodiments of the invention, each of the first logic circuits is configured to perform an XNOR (or XOR) operation, while the second logic circuit performs an AND (or NAND) operation.

A memory device according to another embodiment of the invention may include: the memory cell array has a redundant region (corresponding to a redundant word line and/or a redundant bit line) and a normal region (corresponding to a word line and a bit line). A row decoder is provided that is configured to activate at least one of the word lines and/or to activate at least one of the redundant word lines in response to a row address. A column decoder is provided that is configured to activate at least one of the bit lines and/or to activate at least one of the redundant bit lines in response to a column address. There is provided a repair control circuit configured to: (i) comparing the row address to a stored failed row address, (ii) comparing the column address to a stored failed column address, (iii) controlling the row decoder to activate the at least one of the redundant word lines when the row address corresponds to the failed row address, and (iv) controlling the column decoder to activate the at least one of the redundant bit lines when the column address corresponds to the failed column address. According to further aspects of these embodiments, the repair control circuit is operable to change the repair location according to an input address during the repair operation.

According to another aspect of the inventive concept, a memory device includes: and a memory cell array having a redundant region corresponding to the redundant word line or the redundant bit line and a normal region corresponding to the word line and the bit line. The memory device further includes: a row decoder configured to activate at least one of the word lines or activate at least one of the redundant word lines in response to a row address; and a column decoder configured to activate at least one of the bit lines or at least one of the redundant bit lines in response to a column address. There is provided a repair control circuit configured to: comparing the row address with a stored failed row address, comparing the column address with a stored failed column address, controlling the row decoder to activate the at least one of the redundant word lines when the row address corresponds to the failed row address, and controlling the column decoder to activate the at least one of the redundant bit lines when the column address corresponds to the failed column address. The repair control circuit may change the repair unit according to an inputted address during the repair operation.

According to another embodiment of the inventive concept, a repair method of a memory device includes: receiving an address; at least one address bit (among address bits of the received address) to be ignored in the repair operation is used to determine a repair location, and the received address is compared with the stored failed address. And, when the received address corresponds to the stored failed address, an operation is performed to access the redundant cell array having the repair cell in response to the address.

Drawings

The above and other aspects, features and advantages of the present inventive concept will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

fig. 1 is a diagram illustrating a memory device 100 according to one example of the inventive concept.

Fig. 2 is a diagram illustrating a memory cell array according to one example of the inventive concept.

Fig. 3 is a block diagram illustrating a repair control circuit 140 according to one example of the inventive concept.

Fig. 4 is a diagram illustrating an example of the repair control circuit 140 according to an example of the inventive concept.

Fig. 5 is a diagram illustrating an example of a repair control circuit 140a according to another example of the inventive concept.

Fig. 6 is a diagram illustrating a repair operation according to a fixed repair unit.

Fig. 7 is a diagram illustrating a repair operation according to a variable repair unit according to an example of the inventive concept.

Fig. 8 is a flowchart illustrating a repair method of the memory device 100 according to an example.

Fig. 9 is a flowchart illustrating a process of repairing a memory device in a test operation according to one example of the inventive concepts.

Fig. 10 is a diagram illustrating a memory device 100a according to another example of the inventive concept.

Fig. 11 is a diagram illustrating a memory device 100b according to another example of the inventive concept.

Fig. 12 is a diagram illustrating a memory device according to another example of the inventive concept.

FIG. 13 is a block diagram illustrating a memory chip according to one example of the disclosure.

Fig. 14 is a diagram illustrating a mobile device 3000 according to one example.

Fig. 15 is a diagram illustrating a computing system 4000 according to one example.

Fig. 16 is a diagram illustrating a data server system 5000 according to one example of the inventive concepts.

Detailed Description

The present invention now will be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein, but rather should be provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Like reference numerals refer to like elements throughout.

It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms also are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises," "comprising," "includes," "including," "has," "having" and variations thereof, when used in this specification, specify the presence of stated features, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, steps, operations, elements, components, and/or groups thereof. Rather, the term "consists of", when used in this specification, specifies recited features, steps, operations, elements and/or components and excludes additional features, steps, operations, elements and/or components.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

Fig. 1 is a diagram illustrating a memory device 100 according to one example of the inventive concept. Referring to fig. 1, a memory device 100 may include a memory cell array 110, a row decoder 120, a column decoder 130, and a repair control circuit 140. The memory cell array 110 may include a normal area 112 provided with a plurality of memory cells and a redundant area 114 provided with a plurality of redundant memory cells. In one example, the normal region 112 may include a plurality of memory cells that may be respectively disposed in crossing regions of a plurality of word lines WL and a plurality of bit lines BL. In this case, each of the plurality of memory cells may include a volatile memory cell or a nonvolatile memory cell. In one example, a first portion of the redundant region 114 may be disposed adjacent to the normal region 112 in an extending direction of the word line WL. For example, the redundancy region 114 may include a plurality of redundant memory cells that may be respectively disposed in intersection regions of a plurality of redundancy bit lines RBL and a plurality of word lines WL. Further, a second portion of the redundant region 114 may be disposed adjacent to the normal region 112 in the extending direction of the bit line BL. For example, the redundancy region 114 may include a plurality of redundancy memory cells that may be respectively disposed in crossing regions of a plurality of redundancy word lines RWL and a plurality of bit lines BL.

A failure may occur in at least one of the memory cells set in the normal area 112. The failing cell that fails may be a single bit (single bit), a weak cell (weak cell), or a defective cell (defective cell). The defective cells generated in the normal area 112 may be replaced by the redundant memory cells included in the redundant area 114. This replacement operation may be referred to as a "repair operation". Through the repair operation, data to be stored in or read from the failed cell may be stored in or read from the "replacement" redundant memory cell.

The row decoder 120 may select at least one word line from among the plurality of word lines WL and activate the selected word line in response to a Row Address (RA). In addition, the row decoder 120 may select at least one redundancy word line from among the plurality of redundancy word lines RWL and activate the selected redundancy word line in response to a row address matching signal. For example, the row decoder 120 may deactivate a Row Address (RA) and activate a selected redundant word line in response to a row address match signal.

The column decoder 130 may select at least one bit line from among the plurality of bit lines BL and activate the selected bit line in response to a Column Address (CA). In addition, the column decoder 130 may select at least one redundancy bit line from among the plurality of redundancy bit lines RBL and activate the selected redundancy bit line in response to a column address matching signal. For example, the column decoder 130 may deactivate a Column Address (CA) and activate a selected redundant bit line in response to a column address matching signal.

The repair control circuit 140 may be implemented to perform a repair operation on a defective cell among the plurality of memory cells. For example, when the input Row Address (RA) corresponds to a defective cell, the repair control circuit 140 may generate a row address matching signal. Further, when the input Column Address (CA) corresponds to a defective cell, the repair control circuit 140 may generate a column address matching signal.

In addition, the repair control circuit 140 may change the range of the repair area according to the type of failure, such as a short-circuit error, a disconnection error, or a progressive error. In this case, the repair area may be an area corresponding to a single redundant address (CRENI). For example, repair control circuit 140 may change the type of address bits (e.g., normal address, redundant address, row address, or column address) or the number of address bits corresponding to the failed cell. The repair control circuit 140 may store repair mapping information regarding the type of address bits or the number of address bits in a non-volatile memory, such as a fuse (fuse).

The general memory device may compare an input address with a stored fail address, and may perform a repair operation changed to a repaired address according to the comparison result. The repair operation may perform repair in a fixed repair unit.

In the memory device 100 according to one example of the inventive concept, it may be expected to improve yield by differently performing repair operations according to failure types of memory cells, and by changing repair cells (e.g., types and numbers of addresses) according to failure types even in the case of the same redundancy resource.

Fig. 2 is a diagram illustrating a memory cell array according to one example of the inventive concept. Referring to fig. 2, the memory cell array may include a normal cell array NCA and a redundant cell array RCA. The normal cell array NCA 112 may include a plurality of memory cells disposed at intersections between word lines WL1 to WLm and bit lines BL1 to BLn, where m is an integer of two or more and n is an integer of two or more. The redundant cell array RCA 114 may include a plurality of redundant memory cells disposed at intersections between redundant word lines RWL1 to RWLi and redundant bit lines RBL1 to RBLj, where "i" is an integer of two or more and j is an integer of two or more.

The redundant word lines RWL1 to RWLi shown in fig. 2 may be disposed above the word lines WL1 to WLm, but the positions of the redundant word lines RWL1 to RWLi are not limited thereto. Accordingly, the redundant word lines RWL1 to RWLi may be disposed below the word lines WL1 to WLm, may be disposed as a single group between the word lines WL1 to WLm, or may be arranged as a plurality of groups between the word lines WL1 to WLm.

The redundant bit lines RBL1 to RBLj shown in fig. 2 may be disposed on the right side of the bit lines BL1 to BLn, but the positions of the redundant bit lines RBL1 to RBLj are not limited thereto. Accordingly, the redundant bit lines RBL1 through RBLj may be disposed at the left side of the bit lines BL1 through BLn, may be disposed as a single group between the bit lines BL1 through BLn, or may be arranged as a plurality of groups between the bit lines BL1 through BLn.

Fig. 3 is a block diagram illustrating a repair control circuit 140 according to one example of the inventive concept. Referring to fig. 3, the repair control circuit 140 may include a fail address memory 142, a repair cell determiner 144, and an address comparator 146. The fail address memory 142 may be implemented to store addresses of cells detected as failed in a test operation. In one example, the failed address memory 142 may comprise non-volatile memory. The repair unit determiner 144 may store ignore address bit information corresponding to address bits that are ignored in the test operation, and may determine a repair unit corresponding to the received Address (ADDR) using the ignore address bit information. In this case, the repair location may include the type of address bits and the number of address bits. Finally, the address comparator 146 may compare the received Address (ADDR) with the address stored in the fail address memory 142. The address comparator 146 may generate an address match signal (HIT) when the received Address (ADDR) matches the stored address.

Fig. 4 is a diagram illustrating an example of the repair control circuit 140 according to an example of the inventive concept. Referring to fig. 4, the repair control circuit 140 may include a fail address memory 142, a repair cell determiner 144, and an address comparator 146. The fail address memory 142 may store address bit values corresponding to failed cells. For example, the failure address memory 142 may include a first non-volatile memory NVM storing address bits (a0, …, Ai, Aj, and Ak). In an example, the first non-volatile memory may include a plurality of fuses corresponding to the address bits (a0, …, Ai, Aj, and Ak). The repair cell determiner 144 can include a second non-volatile memory 144-1NVM and an inverter 144-2 (e.g., a third logic circuit). The nonvolatile memory 144-1 may store bit values of address bits that may be ignored among the received address bits. These bit values may be used as selection Signals (SEL). The inverter 144-2 may receive an output value of the nonvolatile memory 144-1 and may invert the received output value to output an inverted select Signal (SELB). The address comparator 146 may include a first logic circuit 146-1, a first selector 146-2, AND a second logic circuit 146-3 (e.g., an AND (AND) gate).

Each of the first logic circuits 146-1 may be implemented to receive one of the address bits of the address buffer 151 and one of the address bits of the fail address memory 142 corresponding thereto, and perform an exclusive nor (XNOR) operation. In one example, the address buffer 151 may be implemented to store an Address (ADDR) received from an external device (see fig. 3). The received Address (ADDR) may store address bit values of "1" or "0" corresponding to a plurality of address bit storage locations. Further, at least two address bits (e.g., Ak and Aj)) among the plurality of address bits (a0, …, Ai, Aj, and Ak) may be used to determine a type and number of address bits used to determine a repair unit in a repair operation. The repair address bits (Aj and Ak) may be bits that may be ignored ("don't care") to determine the repair location.

The first selector 146-2 may be implemented as: in response to a selection Signal (SEL), any one of output values of the first logic circuit (for example, one corresponding to SEL) corresponding to the address bits (Ak and Aj) is output. The second logic circuit 146-3(AND) may be implemented as: the output value of the first logic circuit corresponding to the first address bit (a0, …, Ai) AND the output value of the selector 146-2 are received, AND the address matching signal (HIT) is output by performing an AND operation on the received output values.

The repair line activator 125 may operate in response to the address match signal (HIT) described above to perform a repair operation. Repair line activator 125 may include a second selector 125-1 and a third logic circuit 125-2. The second selector 125-1 may select any one of the address bits (Ak and Aj) in response to the inverted select Signal (SELB). For example, in the case where the first selector 146-2 outputs the output value of the first logic circuit corresponding to the address bit Ak, the second selector 125-1 selects Aj; in the case where the first selector 146-2 outputs the output value of the first logic circuit corresponding to the address bit Aj, the second selector 125-1 selects Ak. The third logic circuit 125-2 may receive an address matching signal (HIT) AND an output value of the selector 125-1, AND may perform an AND operation such that a word line WL or a column selection line CSL required to drive the redundant cell may be activated.

Although the repair control circuit 140 illustrated in fig. 4 performs an XNOR operation using the logic circuit 146-1 when comparing address bits, the inventive concept is not limited thereto. For example, the repair control circuit of the inventive concept may also be implemented by a logic circuit that performs an exclusive or (XOR) operation.

Fig. 5 is a diagram illustrating an example of a repair control circuit 140a according to another example of the inventive concept. Referring to fig. 5, in contrast to the "complementary" repair control circuit 140 shown in fig. 4, the repair control circuit 140a may be implemented with a logic circuit 146-1a that performs an XOR operation and a logic circuit 146-3a, the logic circuit 146-3a performing a NAND (NAND) operation on an output value of the logic circuit corresponding thereto and an output value of the selector 146-2.

In the following description, for convenience of explanation, it is assumed that an address is a Row Address (RA), the row address includes 16 address bits (RA1, …, RA14, RA15, and RA16), and the repair control circuit includes a plurality of FUSE circuits (e.g., FUSE circuits FUSE1 to FUSE4 that may generate address matching signals HIT1 to HIT 4) having a fail address memory and an address comparator. Under these assumptions, fig. 6 is a diagram illustrating a repair operation according to a fixed repair unit. Referring to fig. 6, the FUSE circuits FUSE1 through FUSE4 may perform repair operations through two redundant word lines, respectively. As shown in fig. 6, three FUSE circuits FUSE1, FUSE2, and FUSE3 may be required to repair a faulty cell having a first shape a and a faulty cell having a second shape B.

Fig. 7 is a diagram illustrating a repair operation according to a variable repair unit according to an example of the inventive concept. Referring to fig. 7, the repair operation of the first repair unit RU1 may be performed by the FUSE circuit FUSE1, and the repair operation of the second repair unit RU2 may be performed by the FUSE circuit FUSE 3. In this case, the first repair cell RU1 may be a cell corresponding to four redundant word lines RWL1 to RWL4, and the second repair cell RU2 may be a cell corresponding to two redundant word lines RWL5 and RWL 6.

According to the shapes a and B of the defective cells shown in fig. 7, the repair operation can be performed by the type of address bit of RA16 and the number of two repair address bits, where RA16_ H denotes a16 th bit value (high level) of RA, and RA16_ L denotes a16 th bit value (low level) of RA. However, it should be understood that the repair operations contemplated by the present invention are not limited to such types and numbers of address bits.

The repair control circuit 140 (refer to fig. 1) according to one example may convert resources of a fixed redundant cell (e.g., [2KB,2PXI ]) into a flexible redundant cell (e.g., [2KB,2PXI ]), [1KB,4BXI ], etc.). Therefore, even if the same fuse and redundancy flag signal prepi are used, flexibility can be increased. That is, repair control circuit 140 may provide switchable redundancy to the memory chip.

As the page size of the circuit is reduced, the existing circuit can be used by not adding the sub word line driver SWD and the word line enable signal PXB. By adding a multiplexing MUX for the redundancy enable signal PRENI, 1MUX/1PRENI may be required at the compare address for generating the match signal HIT. In addition, redundant row addresses may be separated and mode register address MA1 and MA2 logic may be added. The reference fuse F-ref may be changed to be the counter input for the data row address DRA. The first fuse address may be changed such that only the first row address RA0 starts with another word line WL (+1/-1), and the second fuse address may be input as a redundant row address.

In general, the smallest page unit (e.g., [1K, 512M ]) is feasible without adding the SWD, but changes in circuitry such as the SWD may be required when implementing more compact page units. It is possible to unblock a column blockable failure by advancing the line through the resource. It is possible to operate other units (add 1 bit/2 prepi) in a single chip, but the test mode register set flag TMRSF may be set for each chip in consideration of the row address RA or the like.

Fig. 8 is a flowchart illustrating a repair method of the memory device 100 according to an example. Referring to fig. 1 to 8, a repair method of the memory device 100 may be performed as follows. When a read operation or a write operation is performed, the memory device 100 may receive a corresponding command and Address (ADDR) (see fig. 3) from an external device, e.g., a memory controller (S110). The repair unit determiner 144 (refer to fig. 3) may determine at least one address bit to be ignored among the received Addresses (ADDR) (S120). For example, as shown in fig. 7, when the Address (ADDR) is a Row Address (RA), bits of a sixteenth row address (RA16) may be ignored by the FUSE circuit FUSE1 and the repair unit determiner 144 (see fig. 4). The address controller 140 (refer to fig. 3) may compare the received Address (ADDR) with an address stored in the fail address memory 142 (refer to fig. 3) (S130). As a result of the address comparison, an address match signal (HIT) may be generated. Thereafter, in response to an address match signal (HIT), a redundant word line or a redundant column selection line corresponding to a physical address associated with the received Address (ADDR) may be activated. Thereafter, a read operation may be performed on the memory cells connected to the activated redundant word line or the activated redundant column selection line, or a write operation may be performed on the memory cells connected to the activated redundant word line or the activated redundant column selection line (S140).

Fig. 9 is a flowchart illustrating a process of repairing a memory device in a test operation according to one example of the inventive concepts. Referring to fig. 1 to 9, a repair process in a test operation of the memory device 100 may be performed as follows. The test operation may be performed in the memory device 100 at a wafer level (S210). The repair process may be performed according to a failure of the memory cell. The address bits to be ignored may be set through a fuse cutting operation according to the type of the defective memory cell (S220). For example, bit values corresponding to address bits to be ignored may be stored in the non-volatile memory 144-1 shown in FIG. 4. Thereafter, fuse information corresponding to the fail address may be stored through a fuse cutting operation (S230).

Although both the row address and the column address have the redundant area in fig. 1, the inventive concept is not limited thereto. For example, fig. 10 is a diagram illustrating a memory device 100a according to another example of the inventive concept. Referring to fig. 10, in comparison with the memory device 100 shown in fig. 1, the memory device 100a may include a memory cell array 110a having a redundant cell array corresponding to a row address and a repair control circuit 140a performing a repair operation corresponding to the redundant row address. In contrast, fig. 11 is a diagram illustrating a memory device 100b according to another example of the inventive concept. Referring to fig. 11, in comparison with the memory device 100 shown in fig. 1, the memory device 100b may include a memory cell array 110b having a redundant cell array corresponding to a column address and a repair control circuit 140b performing a repair operation corresponding to the redundant column address.

Fig. 12 is a diagram illustrating a memory device according to another example of the inventive concept. Referring to fig. 12, the memory device 200 may include a memory cell array 210, a row decoder 220, a column decoder 230, a sense amplifier circuit 240, an address register 250, bank control logic 252, a refresh counter 254, a row address multiplexer 256, a column address latch 258, control logic 260, a repair control circuit 266, a timing control circuit 264, an input/output gating circuit 270, an error correction circuit 280, and a data input/output buffer 282.

The memory cell array 210 may include the first to eighth bank arrays 211 to 218, however, the number of bank arrays constituting the memory cell array 210 is not limited thereto. The row decoder 220 may include first to eighth bank row decoders 221 to 228 connected to the first to eighth bank arrays 211 to 218, respectively. The column decoder 230 may include first to eighth bank column decoders 231 to 238 connected to the first to eighth bank arrays 211 to 218, respectively. The sense amplifier circuit 240 may include first to eighth bank sense amplifiers 241 to 248 connected to the first to eighth bank arrays 211 to 218, respectively.

The first to eighth bank arrays 211 to 218, the first to eighth bank row decoders 221 to 228, the first to eighth bank column decoders 231 to 238, and the first to eighth bank sense amplifiers 241 to 248 may configure the first to eighth banks, respectively. Each of the first through eighth memory bank arrays 211 through 218 may include a plurality of memory cells MC formed at intersections between word lines WL and bit lines BL.

In one embodiment of the inventive concept, each of the first through eighth bank arrays 211 through 218 may include the normal area 112 and the redundant area 114 of the memory cell array 110 shown in fig. 1. The address register 250 may receive and store an Address (ADDR) having a BANK address (BANK _ ADDR), a ROW address (ROW _ ADDR), and a column address (COL _ ADDR) from an external memory controller. Address register 250 may provide a received BANK address (BANK _ ADDR) to BANK control logic 252, a received ROW address (ROW _ ADDR) to ROW address multiplexer 256, and a received column address (COL _ ADDR) to column address latch 258.

The BANK control logic 252 may generate a BANK control signal in response to the BANK address (BANK _ ADDR). In response to the BANK control signal, a BANK row decoder corresponding to a BANK address (BANK _ ADDR) among the first to eighth BANK row decoders 221 to 228 may be activated. In response to the BANK control signal, a BANK column decoder corresponding to a BANK address (BANK _ ADDR) among the first to eighth BANK column decoders 231 to 238 may be activated.

ROW address multiplexer 256 may receive a ROW address (ROW _ ADDR) from address register 250 and a refresh ROW address (REF _ ADDR) from refresh counter 254. The ROW address multiplexer 256 may selectively output a ROW address (ROW _ ADDR) or a refresh ROW address (REF _ ADDR) as a ROW Address (RA). The Row Addresses (RA) output from the row address multiplexer 256 may be applied to the first to eighth bank row decoders 221 to 228, respectively.

The bank row decoder activated by the bank control logic 252 among the first to eighth bank row decoders 221 to 228 may decode a Row Address (RA) output from the row address multiplexer 256 to activate a word line corresponding to the row address. For example, the activated bank row decoder may apply a word line driving voltage to a word line corresponding to a row address. The activated bank row decoder may also activate a word line corresponding to a row address, and may simultaneously activate a redundant word line corresponding to a Spare Row Address (SRA) (also referred to as a 'redundant row address') output from the repair control circuit 266.

The column address latch 258 may receive a column address (COL _ ADDR) from the address register 250 and may temporarily store the received column address (COL _ ADDR). In addition, the column address latch 258 may gradually increase the received column address (COL _ ADDR) in the burst mode. The column address latch 258 may apply a temporarily stored or gradually increasing column address (COL _ ADDR) to the first to eighth memory bank column decoders 231 to 238, respectively.

The BANK column decoder activated by the BANK control logic 252 among the first to eighth BANK column decoders 231 to 238 may activate the sense amplifiers corresponding to the BANK address (BANK _ ADDR) and the column address (COL _ ADDR) through the input/output gate 270. Further, the activated bank column decoder may perform a column repair operation in response to a column repair signal (CRP) output from the repair control circuit 266.

Each of the input/output strobes 270 may further include input data masking logic, a read data latch for storing data output from the first through eighth bank arrays 211 through 218, and a write driver for writing data into the first through eighth bank arrays 211 through 218, in addition to a circuit for strobing input/output data.

A Codeword (CW) read from one bank array among the first to eighth bank arrays 211 to 218 may be sensed by a sense amplifier corresponding to the one bank array and may be stored in a read data latch. After the ECC decoding operation is performed by the error correction circuit 280, the Codeword (CW) stored in the read data latch may be provided to the memory controller through the data input/output buffer 282. After the ECC encoding operation is performed by the error correction circuit 280, Data (DQ) to be written to one memory bank array among the first through eighth memory bank arrays 211 through 218 may be written to the one memory bank array through a write driver.

The data input/output buffer 282 may provide Data (DQ) to the error correction circuit 280 based on a clock signal (CLK) provided from the memory controller in a write operation, and may provide Data (DQ) provided from the error correction circuit 280 to the memory controller in a read operation.

The error correction circuit 280 may generate parity bits based on data bits of the Data (DQ) supplied from the data input/output buffer 282 in a write operation, and may supply a Codeword (CW) including the Data (DQ) and the parity bits to the input/output strobe circuit 270, and the input/output strobe circuit 270 may write the Codeword (CW) to the memory bank array.

Further, in a read operation, error correction circuit 280 may receive a Codeword (CW) read in one memory bank array from input/output gating circuit 270. The error correction circuit 280 may perform an ECC decoding operation for the Data (DQ) by using parity bits included in the read Codeword (CW) to correct at least one erroneous bit included in the Data (DQ), and provide the corrected bit to the data input/output buffer 282.

The control logic 260 may be implemented to control the operation of the memory device 200. For example, the control logic circuit 260 may generate a control signal so that the semiconductor memory device 200 performs a write operation or a read operation. The control logic circuit 260 may include a command decoder 261 for decoding a command CMD received from the memory controller and a mode register 262 for setting an operation mode of the memory device 200.

For example, the command decoder 261 may decode a write enable signal (/ WE), a row address strobe signal (/ RAS), a column address strobe signal (/ CAS), a chip select signal (/ CS), and the like to generate operation control signals (ACT, PCH, WR, and RD) corresponding to the command CMD. The control logic 260 may provide operation control signals (ACT, PCH, WR, and RD) to the timing control circuit 264. The control signals (ACT, PCH, WR, and RD) may include an active signal (ACT), a precharge signal (PCH), a write signal (WR), and a read signal (RD). The timing control circuit 264 may generate a first control signal (CTL1) controlling a voltage level of the word line WL and a second control signal (CTL2) controlling a voltage level of the bit line BL in response to the operation control signals (ACT, PCH, WR, and RD), and may provide the first control signal (CTL1) and the second control signal (CTL2) to the memory cell array 210.

The repair control circuit 266 may generate repair control signals (CRP, SEL, EN, and SRA) that control a repair operation of the first cell region and the second cell region in at least one memory bank array based on fuse information of each of the word lines of the ROW address (ROW _ ADDR), the column address (COL _ ADDR), and the Address (ADDR) (or access address). The repair control circuit 266 may provide Spare Row Addresses (SRAs) (or redundant row addresses) to the corresponding bank row decoders, may provide column repair signals (CRP) to the corresponding bank column decoders, and may provide select Signals (SEL) and enable signals (EN) to block control circuits associated with the corresponding spare array blocks (or redundant array blocks).

The repair control circuit 266 may be configured to change the repair unit according to an inputted address during a repair operation. For example, repair control circuit 266 may change the repair location based on the Address (ADDR) and fuse information. For example, repair control circuitry 266 may change the type and number of repair address bits based on the Address (ADDR) and fuse information.

A memory device according to one example of the inventive concept may store mapping information of a logical address and a physical address having a plurality of bits in a nonvolatile memory NVM, and may change the type and number of address bits corresponding to one piece of mapping information. According to one example, when all addresses composed of a plurality of bits match each other (when a mapping condition is established), the type and number of the plurality of address bits used to generate such a condition may vary. In another example, the type and number of the plurality of address bits may be determined in a test operation and may be stored in the NVM.

A memory device according to one example of the inventive concept may include a plurality of redundant cells, repair mapping information of the redundant cells may be stored in a single nonvolatile memory NVM, and a specific range of normal cells may be repaired to the same range of redundant cells due to one repair mapping information. In this case, the range of the unit area corresponding to the repair map information may be changed.

In one example, in a test operation to store repair map information, repair units may be set independently for all maps. The repair unit set in this case may be stored in each nonvolatile memory NVM. Alternatively, in a test operation of storing repair map information, a repair unit may be set for all the maps in common. In this case, the set repair unit may be stored in a single nonvolatile memory NVM.

The memory chip of the inventive concept may be implemented as a stacked memory chip. For example, fig. 13 is a block diagram illustrating a memory chip according to one example of the inventive concept. Referring to fig. 13, the memory chip 1000 may include first to third memory dies 1100 to 1300 and Through Silicon Vias (TSVs) stacked in a vertical direction on a substrate. In this case, the number of stacked memory dies will not be limited to the number shown in fig. 13. For example, the first and second memory dies 1100, 1200 can be slave dies (slave die), while the third memory die 1300 can be a master die or a buffer die.

The first memory die 1100 can include a first array of memory cells 1110 and a first through electrode region 1120 for accessing the first array of memory cells 1110. The second memory die 1200 may include a second memory cell array 1210 and a second through electrode region 1220 for accessing the second memory cell array 1210. In this case, the first through electrode region 1120 may represent a region of the first memory die 1100 where through electrodes for communication between the first memory die 1100 and the third memory die 1300 are disposed. Similarly, the second through electrode region 1220 can represent an area in the second memory die 1200 where through electrodes for communication between the second memory die 1200 and the third memory die 1300 are disposed. The through-electrodes can provide an electrical path between the first memory die 1100 to the third memory die 1300.

The first through third memory dies 1100-1300 can be electrically connected to each other through-electrodes. For example, the number of the through electrodes may be hundreds to thousands, and the through electrodes may be arranged in a matrix arrangement. The third memory die 1300 may include first peripheral circuitry 1310 and second peripheral circuitry 1320. In this case, the first peripheral circuitry 1310 may include circuitry for accessing the first memory die 1100, and the second peripheral circuitry 1320 may include circuitry for accessing the second memory die 1200. In one example, each of peripheral circuitry 1310 and peripheral circuitry 1320 may be implemented by methods and apparatus for performing repair operations described with reference to fig. 1-13.

According to a further embodiment of the inventive concept, the inventive concept is applicable to a mobile device. For example, fig. 14 is a diagram illustrating a mobile device 3000 in which the inventive concept can be implemented. Referring to fig. 14, a mobile device 3000 may include an application processor 3100, at least one DRAM 3200, at least one storage device 3300, at least one sensor 3400, a display device 3500, an audio device 3600, a network processor 3700, and at least one input/output device 3800. For example, the mobile device 3000 may be implemented as a laptop computer, a mobile phone, a smart phone, a tablet personal computer, or a wearable computer.

The application processor 3100 may be implemented to control overall operation of the mobile device 3000. Application processor 3100 may execute applications that provide internet browsers, games, videos, and the like. In one example, application processor 3100 may include a single core or multiple cores. For example, application processor 3100 may include multiple cores (such as dual cores, quad cores, six cores, etc.). In one example, application processor 3100 may also include cache memory, either internal or external.

Application processor 3100 may include a controller 3110, a Neural Processor (NPU)3120, and an interface 3130. In one example, the NPU 3120 may optionally be provided. In one example, application processor 3100 may be implemented as a system on a chip (SoC). A core of an operating system running in a system on a chip (SoC) may include an input/output (I/O) scheduler and a device driver that controls a memory device 3300. The device driver may control access performance of the storage device 3300 with reference to the number of synchronization queues managed by the input/output scheduler, or may control a CPU mode, a DVFS level, and the like in the SoC.

The DRAM 3200 may be connected to the controller 3110. DRAM 3200 may store data required for the operation of application processor 3100. For example, the DRAM 3200 may temporarily store an Operating System (OS) and application data, or may be used as an execution space of various software codes.

The DRAM 3200 may perform on-die mirroring operations as requested by the application processor 3100 or selected by a user. DRAM 3200 can be connected to NPU 3120. DRAM 3200 may store data related to Artificial Intelligence (AI) calculations.

DRAM 3200 may have relatively lower latency and greater bandwidth than I/O devices or flash memory. The DRAM 3200 may be initialized when the mobile device is powered on, may be used as a temporary storage location of OS and application data by loading the OS and application data, or may be used as an execution space of various software codes. The mobile device performs a multitasking operation in which several applications are loaded at the same time, and the switching between applications and the execution speed may be used as a performance index of the mobile device.

The storage device 3300 may be connected to the interface 3130. In one example, interface 3130 may be operated by any one of DDR, DDR2, DDR3, DDR4, low power DDR (lpddr), Universal Serial Bus (USB), multimedia card (MMC), embedded MMC, Peripheral Component Interconnect (PCI), non-volatile memory express (NVMe), peripheral component interconnect express (PCIe), Serial Advanced Technology Attachment (SATA), Small Computer System Interface (SCSI), serial connection (SCSI sas), Universal Storage Bus (USB) connected SCSI (uas), Internet Small Computer System Interface (iSCSI), fibre channel, and over ethernet fibre channel (FCoE) communication protocols. In one example, any one of the storage devices 3300 may be included in the mobile device 3000 in an embedded form. In another example, any one of the storage devices 3300 may be included in the mobile device 3000 in a detachable manner.

Storage 3300 may be implemented to store user data. For example, the storage device 3300 may store data collected from the sensor 3400, or may store data network data, Augmented Reality (AR)/Virtual Reality (VR) data, or High Definition (HD)4K content. The storage device 3300 may include at least one non-volatile memory device. For example, the storage 3300 may include a Solid State Drive (SSD), an embedded multimedia card (eMMC), and the like.

In one example, the storage device 3300 may be implemented as a separate chip in the application processor 3100, or may be implemented together with the application processor 3100 as a single package. In another example, various types of packages may be used to mount the storage device 3300. For example, the storage device 3300 may be mounted using a package such as a package on package (PoP), a Ball Grid Array (BGA), a Chip Scale Package (CSP), a Plastic Leaded Chip Carrier (PLCC), a plastic dual in-line package (PDIP), a wafer in wafer package (die in wafer pack), a die in wafer form (die in wafer form), a Chip On Board (COB), a ceramic dual in-line package (CERDIP), a plastic Metric Quad Flat Package (MQFP), a Thin Quad Flat Package (TQFP), a Small Outline Integrated Circuit (SOIC), a Shrink Small Outline Package (SSOP), a Thin Small Outline Package (TSOP), a System In Package (SIP), a multi-chip package (MCP), a wafer level fabricated package (WFP), and a wafer level processed stack package (WSP).

The sensor 3400 may be implemented to sense an external environment of the mobile device 3000. In one example, the sensor 3400 may include an image sensor that senses an image. In this case, the sensor 3400 may transmit the generated image information to the application processor 3100. In another example, the sensor 3400 may include a biosensor that senses biometric information. For example, the sensor 3400 may sense a fingerprint, an iris pattern, a blood vessel pattern, a heart rate, a blood glucose level, or the like, and may generate sensing data corresponding to the sensed information. On the other hand, the sensor 3400 is not limited to an image sensor and a biosensor. For example, the sensor 3400 may include other types of sensors (such as an illuminance sensor, an acoustic sensor, an acceleration sensor, and the like).

Display device 3500 may be implemented to output data. For example, the display device 3500 may output image data sensed using the sensor 3400 or output data calculated using the application processor 3100.

The audio device 3600 may be implemented to externally output voice data or sense external voice. The network processor 3700 can be implemented to communicate with external devices through a wired or wireless communication method. The input/output device 3800 may be implemented to input data to the mobile device 3000 or output data from the mobile device 3000. The input/output device 3800 may include devices that provide digital input and output functions (such as USB, storage devices, digital cameras, SD cards, touch screens, DVD, modems, and network adapters).

Embodiments of the inventive concept are also applicable to various types of computing systems (e.g., CPU/GPU/NPU platforms). For example, fig. 15 is a diagram illustrating a computing system 4000 according to one example of the inventive concepts. Referring to fig. 15, computing system 4000 may include a Central Processing Unit (CPU)4110, a Graphics Processing Unit (GPU)4120, and/or a Neural Processing Unit (NPU)4130 (or a special-purpose processor) connected to a system bus 4001; a memory device 4210 and/or a storage device 4220 connected to the system bus 4001; and an input/output device 4310, a modem 4320, a network device 4330, and/or a storage device 4340 connected to the expansion bus 4002. In this case, the expansion bus 4002 can be connected to the system bus 4001 through an expansion bus interface 4003.

In one example, the CPU4110, GPU4120, and NPU 4130 may include on-chip caches 4111, 4121, and 4131, respectively. In another example, the CPU4110 may include an off-chip cache 4112. Although not shown in fig. 15, each of the GPU4120 and NPU 4130 may also include an off-chip cache. In one example, the off-chip cache 4112 may be internally connected to the CPU4110, GPU4120, and NPU 4130 through different buses.

In one example, the on-chip/off-chip cache may include volatile memory (such as Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), etc.) or non-volatile memory (such as NAND flash, Phase Random Access Memory (PRAM), Resistive Random Access Memory (RRAM), etc.).

In one example, main memories 4114, 4124, and 4134 may be connected to CPU4110, GPU4120, and NPU 4130 through respective memory controllers 4113, 4123, and 4133. In one example, the memories 4116, 4126, and 4136 may be connected to the CPU4110, GPU4120, and NPU 4130 through the bridges 4115, 4125, and 4135. The network bridges 4115, 4125, and 4135 may include memory controllers that control the respective memories 4116, 4126, and 4136. In one example, the bridges 4115, 4125, and 4135 may be implemented as network devices, wireless network devices, switches, buses, clouds, or optical channels, respectively.

In one example, memories 4124 and 4126 may comprise GPU memory. The GPU memory may hold instructions and data that may interact with the GPU. Commands and data may be copied from main memory or storage devices. The GPU memory may store image data and may have a larger bandwidth than the memory. The GPU memory may separate the clock from the CPU. The GPU may read and process the image data in the GPU memory and may then write into the GPU memory. The GPU memory may be configured to accelerate graphics processing.

In one example, memories 4134 and 4136 may comprise NPU memories. The NPU memory may hold instructions and data that may interact with the NPU. Commands and data may be copied from main memory or storage devices. The NPU memory may hold weight data for the neural network. The NPU memory may have a larger bandwidth than the memory. The NPU memory may separate the clock from the CPU. The NPU may read and update the weight data in the NPU memory and then write to the NPU memory during training. The NPU memory may be configured to accelerate machine learning (such as neural network training and inference).

In some examples, each of the main memories 4114, 4116, 4124, 4126, 4134, and 4136 may be implemented as a memory chip that performs the repair operations described with reference to fig. 1-13.

In one example, the main memory may include volatile memory (such as DRAM, SRAM, etc.) or non-volatile memory (such as NAND flash, PRAM, RRAM, etc.). The primary storage has a lower latency and lower capacity than the latency and capacity of the secondary storage devices 4210 and 4220.

The CPU4110, GPU4120, or NPU 4130 may access the secondary storage devices 4210 and 4220 via the system bus 4001. The memory device 4210 may be controlled by a memory controller 4211 connected to the system bus 4001. The storage 4220 may be controlled by a storage controller 4221. A memory controller 4221 may be connected to the system bus 4001.

Storage 4220 may be implemented to store data. The memory controller 4221 may be implemented to read data from the memory device 4220 and transmit the read data to a host. The storage controller 4221 may be implemented to store the transmitted data in the storage 4220 in response to a request from a host. Each of the storage device 4220 and the storage controller 4221 may include a buffer that stores metadata, reads a cache for storing frequently accessed data, or stores a cache for improving write efficiency. For example, a write cache may receive and process a particular number of write requests. Also, the storage 4220 may include volatile memory, such as a Hard Disk Drive (HDD), and non-volatile memory, such as NVRAM, SSD, SCM, or new memory.

One example of the inventive concept is applicable to a data server system. For example, fig. 16 is a diagram illustrating a data server system 5000 according to one example of the inventive concepts. Referring to fig. 16, the data server system 5000 may include a first server 5100 (application server), a second server 5200 (storage server), a memory device 5310 and at least one storage device 5320.

Each of the first server 5100 and the second server 5200 may include at least one processor and memory. In one example, each of the first server 5100 and the second server 5200 may be implemented as a memory processor pair. In another example, each of the first server 5100 and the second server 5200 may be implemented with different amounts of processors and memory suitable for use.

In one example, the first server 5100 and the second server 5200 may perform communication over a first network 5010. In one example, each of the first server 5100 and the second server 5200 can access the memory device 5310 over the first network 5010 and/or the second network 5020. In one example, each of the first server 5100 and the second server 5200 can access the storage 5320 directly or indirectly through a first network 5010 and a second network 5020.

In one example, the interface I/F of storage 5320 may comprise a SATA, SAS, PCIe, DIMM, HBM, HMC, or NVDIMM. In one example, the second network 5020 can be a connection type of a Direct Attached Storage (DAS), Network Attached Storage (NAS), and Storage Area Network (SAN) scheme.

In one example, memory device 5310 and storage device 5320 may each send device information to server 5200 via a command or by themselves. In one example, the memory device 5310 can be implemented as a memory chip that performs the repair operation described with reference to fig. 1-13. The data server system 5000 may perform big data AI calculations. In this case, the big data may include audio, photos, video, or weight data/training data.

In a memory device and a repair method thereof according to examples of the inventive concept, a repair unit is variable by differently setting a bit type of an address or the number of addresses according to a defective address.

Although examples have been shown and described above, it will be clear to a person skilled in the art that modifications and variations can be made without departing from the scope of the inventive concept as defined by the appended claims.