阅读说明：本技术 铁电存储器及其存储数据读取方法 (Ferroelectric memory and method for reading stored data thereof ) 是由 孔繁生 周华 于 2020-12-10 设计创作，主要内容包括：本发明提供了一种铁电存储器及其存储数据读取方法,所述铁电存储器包括延第一方向延伸的数条字线和数条板线、延第二方向延伸的数条位线、以及位于所述字线、板线、位线之间的数个铁电存储单元,每一所述铁电存储单元均包括第一晶体管和第一电容,所述第一晶体管的栅极连接至所述字线,所述第一晶体管的漏极连接至所述位线,所述第一晶体管的源极连接至所述第一电容的第一端,所述第一电容的第二端连接至所述板线,当读取所述第一电容中存储的数据时,从所述第一电容中输出的电流经过放大后输出至所述位线,从而提升感测裕度和读取鲁棒性,并且由于本申请的铁电存储器仅包括一个电容和一个晶体管,因此其面积更小,成本更低。(The invention provides a ferroelectric memory and a stored data reading method thereof, the ferroelectric memory comprises a plurality of word lines and a plurality of plate lines which extend along a first direction, a plurality of bit lines which extend along a second direction, and a plurality of ferroelectric memory units which are positioned among the word lines, the plate lines and the bit lines, each ferroelectric memory unit comprises a first transistor and a first capacitor, the grid electrode of the first transistor is connected to the word line, the drain electrode of the first transistor is connected to the bit line, the source electrode of the first transistor is connected to the first end of the first capacitor, the second end of the first capacitor is connected to the plate line, when the data stored in the first capacitor is read, the current output from the first capacitor is amplified and then output to the bit line, thereby improving the sensing margin and the reading robustness, and because the ferroelectric memory only comprises one capacitor and one transistor, therefore, the area is smaller and the cost is lower.)

1. A method for reading stored data of a ferroelectric memory is characterized in that the ferroelectric memory comprises a plurality of word lines and a plurality of plate lines which extend along a first direction, a plurality of bit lines which extend along a second direction, and a plurality of ferroelectric memory units which are arranged among the word lines, the plate lines and the bit lines, each ferroelectric memory unit comprises a first transistor and a first capacitor, a grid electrode of the first transistor is connected to the word lines, a drain electrode of the first transistor is connected to the bit lines, a source electrode of the first transistor is connected to a first end of the first capacitor, a second end of the first capacitor is connected to the plate lines, and when data stored in the first capacitor is read, current output from the first capacitor is amplified and then output to the bit lines.

2. A stored data reading method according to claim 1, wherein the ferroelectric memory further comprises an amplifier circuit between the drain of the first transistor and the bit line, and the current outputted from the first capacitor is amplified by the amplifier circuit and outputted to the bit line.

3. A method for reading stored data according to claim 1, wherein the first capacitance is a ferroelectric capacitor.

4. A method for reading stored data according to claim 3, wherein the type of data stored in the memory cell is determined by determining the polarity of the ferroelectric material in the ferroelectric capacitor.

5. The method of claim 1, wherein the bit line is connected to a sensing unit, the method further comprising: and detecting the voltage difference on the bit line by the detection unit.

6. A ferroelectric memory comprising a plurality of word lines and a plurality of plate lines extending along a first direction, a plurality of bit lines extending along a second direction, and a plurality of ferroelectric memory cells located between the word lines, the plate lines and the bit lines, each of the ferroelectric memory cells comprising a first transistor and a first capacitor, a gate of the first transistor being connected to the word line, a drain of the first transistor being connected to the bit line, a source of the first transistor being connected to a first end of the first capacitor, a second end of the first capacitor being connected to the plate line, and an amplification circuit for: when reading the data stored in the first capacitor, the current output from the first capacitor is amplified and then output to the bit line.

7. The ferroelectric memory according to claim 6, wherein the amplifier circuit is provided between the drain of the first transistor and the bit line, and wherein the current outputted from the first capacitor is amplified by the amplifier circuit and outputted to the bit line.

8. The ferroelectric memory according to claim 7, wherein said amplifying circuit comprises an amplifier and a first resistor and a second resistor, wherein a forward input terminal of said amplifier is electrically connected to a drain of said first transistor, an output terminal of said amplifier is electrically connected to said bit line, said first resistor is connected to said inverting input terminal and said output terminal, and said second resistor is electrically connected to said inverting input terminal and ground.

9. The ferroelectric memory of claim 6, wherein the first capacitance is a ferroelectric capacitor.

10. A ferroelectric memory as in claim 6, wherein said bit line is connected to a sensing unit for sensing a voltage on said bit line when reading data stored in said first capacitor.

Technical Field

The invention relates to the technical field of memories, in particular to a ferroelectric memory and a stored data reading method thereof.

Background

Ferroelectric memory (FeRAM) is a non-volatile memory that utilizes a ferroelectric material, such as Strontium Bismuth Tantalate (SBT), lead zirconate titanate (PZT), or zirconium oxide (HZO), as the capacitor dielectric between a bottom electrode and a top electrode. Both read and write operations are performed against the FeRAM. Memory size and memory architecture can affect FeRAM read and write access times. Also, there are large differences between different memory types.

The main difference between DRAM and FeRAM is the operation of the capacitor plate electrode and the pre-charging to connect it to the bit line prior to reading. When the DRAM Plate Line (PL) is grounded (or held at half the supply voltage (VDD/2)) and the bit lines are precharged to VDD/2 prior to sensing, in the FeRAM case the plate line needs to be pulsed and the bit lines need to be precharged to 0V. Thus, the memory cell slows down due to the high capacitance of PL.

Several types of ferroelectric memory cells are commonly used, such as single capacitor memory cells and dual capacitor memory cells. Furthermore, individual capacitor memory cells are generally divided into two types: a 1C cell (one capacitor or just a capacitor) and a 1T1C cell (one transistor and one capacitor). The 1C cell has the distinct advantage of requiring a fewer access/isolation transistors and corresponding silicon area, but may require more plate lines to limit the capacitance of the lines coupling all commonly wired cells together. Due to this capacitance limitation, 1C cells are rarely used. Both single capacitor memory cell types require less silicon area than the dual capacitor type (thereby increasing the density of the memory array), but are less immune to noise and process variations. In addition, the 1C and 1T1C cells require a reference voltage to determine the stored memory state.

A dual capacitor memory cell (referred to as a 2T2C memory cell) requires more silicon area and it stores complementary signals so that the stored information can be sampled differentially. The 2T2C memory cell is more stable than the 1T1C memory cell.

Compared to a conventional 1T-1C cell, the 2T-2C design, with or without any optimization, provides better sensing margin and read robustness. However, 2T-2C requires higher cost in terms of area since it requires two transistors per cell.

Therefore, in view of the above problems, the present application provides a ferroelectric memory, a method for reading stored data thereof, and an electronic device.

Disclosure of Invention

Embodiments of the present invention provide a ferroelectric memory and a method for reading stored data thereof to solve at least one of the above problems.

According to a first aspect of the present invention, there is provided a stored data reading method of a ferroelectric memory, the stored data reading method comprising: a method for reading stored data of a ferroelectric memory is characterized in that the ferroelectric memory comprises a plurality of word lines and a plurality of plate lines which extend along a first direction, a plurality of bit lines which extend along a second direction, and a plurality of ferroelectric memory units which are arranged among the word lines, the plate lines and the bit lines, each ferroelectric memory unit comprises a first transistor and a first capacitor, a grid electrode of the first transistor is connected to the word lines, a drain electrode of the first transistor is connected to the bit lines, a source electrode of the first transistor is connected to a first end of the first capacitor, a second end of the first capacitor is connected to the plate lines, and when data stored in the first capacitor is read, current output from the first capacitor is amplified and then output to the bit lines.

In one example, the ferroelectric memory further includes an amplification circuit between the drain of the first transistor and the bit line, and the current output from the first capacitor is amplified by the amplification circuit and then output to the bit line.

In one example, the first capacitance is a ferroelectric capacitor.

In one example, the type of data stored by the memory cell is determined by determining the polarity of the ferroelectric material in the ferroelectric capacitor.

In one example, the bit line is connected to a sensing unit, and the stored data reading method further includes:

and detecting the voltage difference on the bit line by the detection unit.

The second aspect of the present application further provides a ferroelectric memory, which includes a plurality of word lines and a plurality of plate lines extending along a first direction, a plurality of bit lines extending along a second direction, and a plurality of ferroelectric memory cells located between the word lines, the plate lines, and the bit lines, and an amplifying circuit, each of the ferroelectric memory cells includes a first transistor and a first capacitor, a gate of the first transistor is connected to the word line, a drain of the first transistor is connected to the bit line, a source of the first transistor is connected to a first end of the first capacitor, a second end of the first capacitor is connected to the plate line, and the amplifying circuit is configured to: when reading the data stored in the first capacitor, the current output from the first capacitor is amplified and then output to the bit line.

In one example, the amplifying circuit is located between the drain of the first transistor and the bit line, and the current output from the first capacitor is amplified by the amplifying circuit and then output to the bit line.

In one example, the amplifying circuit includes an amplifier, a first resistor and a second resistor, wherein a positive input terminal of the amplifier is electrically connected to a drain of the first transistor, an output terminal of the amplifier is electrically connected to the bit line, the first resistor is connected to the negative input terminal and the output terminal, and the second resistor is electrically connected to the negative input terminal and the ground.

In one example, the first capacitance is a ferroelectric capacitor.

In one example, the bit line is connected to a sensing unit for sensing a voltage on the bit line when reading data stored in the first capacitor.

According to the ferroelectric memory and the stored data reading method thereof of the embodiment of the present invention, when reading the data stored in the first capacitor, the current output from the first capacitor is amplified and then output to the bit line, so as to increase the voltage of the bit line, so that the voltage difference between the bit line when reading the first state data in the stored data and when reading the second state data in the stored data is increased, thereby improving the sensing margin and the reading robustness, and since the ferroelectric memory of the present invention only includes one capacitor and one transistor, the area thereof is smaller and the cost is lower.

Drawings

The above and other objects, features and advantages of the present invention will become more apparent by describing in more detail embodiments of the present invention with reference to the attached drawings. The accompanying drawings are included to provide a further understanding of the embodiments of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention and not to limit the invention. In the drawings, like reference numbers generally represent like parts or steps.

FIG. 1 is a schematic circuit diagram of a ferroelectric memory according to one embodiment of the present invention;

fig. 2 is a timing diagram of a read operation of the ferroelectric memory cell in fig. 1.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, exemplary embodiments according to the present invention will be described in detail below with reference to the accompanying drawings. It is to be understood that the described embodiments are merely a subset of embodiments of the invention and not all embodiments of the invention, with the understanding that the invention is not limited to the example embodiments described herein. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the invention described herein without inventive step, shall fall within the scope of protection of the invention.

The following describes typical methods for 2T-2C read operations and typical methods for several commonly used 1T1C read operations.

A fully differential cell consists of two transistors and two capacitors (2T-2C). The 2T-2C cell can be considered as two adjacent 1T-1C cells that share the same WL and PL, but store the opposite data. C_FEDump its charge to BL when C _FE Dump its charge toBLThe above. Due to C _FE Always store and C_FEOpposite data value, therefore, according to C_FEWhether the data stored therein is "1" or "0", BL andBLa voltage difference therebetween isOne of V1-V0 or V0-V1. This is twice the voltage level available for sensing in the 1T-1C architecture. The penalty paid to double the signal is to double the cell area. While this can be used for lower density memories (less than 256kb), there is a current trend to use the 1T-1C architecture for higher density memories (over 1 Mb).

As if one reference cell, C, is used per row combination_FEAnd C _FE The fatigue is the same because they are accessed simultaneously. Also, the physical proximity of the two capacitors results in better matching characteristics compared to previous solutions. This makes the 2T-2C cell one of the most robust cells in ferroelectric memories.

Generally, two detection methods are used in ferroelectric capacitor based memories. The read operation is initiated by pre-discharging the BL to 0, and then asserting WL (assert). In the first method, also called step sensing, the PL voltage increases, which will either keep the polarization of the ferroelectric capacitor at a positive value or switch it from negative to positive. In the former case, the current in the ferroelectric capacitor is small, and thus the BL voltage (V)_BLP) The increase in (c) is small. But the latter case will result in the BL voltage (V)_BLN) A relatively large increase, which can also be understood from the following equation:

V_BLN＝[C_FEN/(C_BL+C_FEN)]V_DD (1a)

V_BLP＝[C_FEP/(C_BL+C_FEP)]V_DD (1b)

here, C_FENAnd C_FEPAverage capacitances of negative and positive polarization of the ferroelectric capacitor, respectively, and C_BLIs the bit line capacitance. As described in the previous section, C_FEN>C_FEPThen, the sense amplifier utilizes the difference (V) between the BL voltages_DIFF＝V_BLN-V_BLP) Discharging BL to 0 (if the original ferroelectric capacitor is polarized positive) or charging it to V_DD(if the original ferroelectric capacitor is polarized negative). After that, PL is driven to 0 so that in the latter case (BL is V)_DD) Negative charge appearing across a ferroelectric capacitorVoltage, at which point the ferroelectric capacitor polarization is switched back to the original negative value.

In the second method, called a pulse sensing method (pulse sensing approach), sensing is performed by first increasing the PL voltage. Similar to step sensing, the BL voltage increases to a greater extent when the initial polarization is negative than when it is positive. Therefore, as described above, the difference of the BL voltage is V_DIFF. After this process, the final polarization of the ferroelectric capacitor is positive, regardless of the initial state of the ferroelectric capacitor. Prior to sensing, the PL voltage is reduced to zero, which results in a reduction in the BL voltage. Since the polarization remains positive in both cases during the reduction of the PL voltage, the reduction of the BL voltage is the same. This means that the BL voltages of the two logic states maintain the initial difference. Thus, if the initial polarization is positive, the BL voltage will return to 0 (V)_BLP0); if the initial polarization is negative, then the BL voltage V_BLN＝V_DIFF. The sense amplifier uses this difference to charge BL to VDD or discharge it to 0V. After a full swing is obtained on the BL, when the BL voltage is VDD (initial polarization)<0) At this time, the voltage across the ferroelectric capacitor is negative. Thus, in this case, the ferroelectric capacitor polarity switches to a negative value, and the initial logic state is restored (similar to step sensing).

The advantages of step sensing over pulse sensing are as follows. First, step sensing is faster because in pulse sensing, activation of the sense amplifier is performed after waiting for the PL voltage to drop. Second, the common-mode BL voltage for step sensing (═ V)_BLP+V_BLN) /2) greater than pulse sensing (═ V)_DIFF/2＝(V_BLN-V_BLP) 2), which makes the bias efficiency of the sense amplifier higher. Third, in step sensing, the ferroelectric capacitor storing positive polarity undergoes 0 → V_DDThe period → 0, and in pulse detection, the voltage period is 0 → (V)_DD-V_BLP) → 0. The full voltage period helps to more effectively maintain positive polarity in the step sensing, thereby shortening the hold time. As a result, pulsed sensing may require an additional pulse to enhance positive polarization, which may degrade its performance. The advantage of pulse sensing is that process variations can be mitigatedInfluence. Thus, when the initial polarization is positive, the polarization returns to its initial value before the sense amplifier in the pulse sense is activated. In step sensing, on the other hand, the sensed polarization is greater than the stored value. This increase in polarization may be different for different cells due to process variations. As a result, the polarization and the sensed BL voltage exhibit a distribution for step sensing. However, in the pulse sensing, since the polarization is restored to its original value, the influence of process variation and the distribution of the sensing BL voltage are reduced.

Therefore, a ferroelectric memory and a method for reading stored data are needed to improve sensing margin and read robustness without occupying too much area and increasing the cost.

In view of the above problem, an embodiment of the present invention provides a ferroelectric memory, which includes a plurality of word lines and a plurality of plate lines extending along a first direction, a plurality of bit lines extending along a second direction, and a plurality of ferroelectric memory cells located between the word lines, the plate lines, and the bit lines, each of the ferroelectric memory cells includes a first transistor and a first capacitor, a gate of the first transistor is connected to the word line, a drain of the first transistor is connected to the bit line, a source of the first transistor is connected to a first end of the first capacitor, a second end of the first capacitor is connected to the plate line, and when data stored in the first capacitor is read, a current output from the first capacitor is amplified and then output to the bit line. According to the ferroelectric memory of the embodiment of the present invention, when reading data stored in the first capacitor, a current output from the first capacitor is amplified and then output to the bit line, so that a voltage of the bit line is increased, a voltage difference between the bit line when reading first state data in the stored data and when reading second state data in the stored data is increased, a sensing margin and reading robustness are improved, and since the ferroelectric memory of the present application includes only one capacitor and one transistor, an area thereof is smaller and a cost thereof is lower.

A ferroelectric memory and a stored data reading method thereof in an embodiment of the present application are described below with reference to fig. 1 and fig. 2, where fig. 1 is a schematic circuit diagram of a ferroelectric memory according to an embodiment of the present invention; fig. 2 is a timing diagram of a read operation of the ferroelectric memory cell in fig. 1.

As an example, as shown in fig. 1, a ferroelectric memory in an embodiment of the present application includes a plurality of word lines WL and a plurality of plate lines PL extending along a first direction, a plurality of bit lines BL extending along a second direction, and a plurality of ferroelectric memory cells located between the word lines WL, the plate lines PL, and the bit lines BL, each of the ferroelectric memory cells includes a first transistor 101 and a first capacitor 102, a gate of the first transistor 101 is connected to the word line WL, a drain of the first transistor 101 is connected to the bit line BL, a source of the first transistor 101 is connected to a first end of the first capacitor 102, a second end of the first capacitor 102 is connected to the plate line PL, and the amplifier circuit 103 is configured to: when reading the data stored in the first capacitor 102, the current output from the first capacitor 102 is amplified and then output to the bit line BL.

In one example, the first direction may be a row direction and the second direction may be a column direction. In particular, the method can be reasonably changed according to the actual architecture requirement.

Alternatively, the first capacitance 102 of the ferroelectric memory cell may comprise a ferroelectric capacitor comprising a bottom electrode and a top electrode, and a capacitor dielectric disposed between the bottom electrode and the top electrode, such as a ferroelectric material such as Strontium Bismuth Tantalate (SBT), lead zirconate titanate (PZT), or zirconium oxide (HZO).

For the ferroelectric memory of the embodiment of the present application, in order to perform the write operation, the bit line BL voltage is driven to a high level, for example, the power supply voltage V_DDTo switch the polarity of the ferroelectric capacitor to a positive value (i.e., positive polarity) while holding it at 0 to set a negative polarity in the ferroelectric capacitor, the word line WL is asserted, and a pulse is applied to the plate line PL. During the plate line PL being at 0V, the bit line BL of the cell is at V_DDSo that the two ends of the ferroelectric capacitor arePositive pressure (>V_C) This will cause the polarity of the ferroelectric capacitor to switch to positive polarity. When plate line PL voltage switches to V_DDWhile the cell with bit line BL at 0V is under negative voltage across the ferroelectric capacitor: (<-V_C) Thereby switching the polarity of the ferroelectric capacitor to a negative polarity, and in the holding state, the ferroelectric capacitor is polarized to + PR or-PR (i.e., remanent polarization). Wherein a positive polarity may correspond to one data state of the stored data, such as one binary signal value state (e.g., 0), and a negative polarity may correspond to another data state of the stored data, such as another binary signal value state (e.g., 1).

Further, the above ferroelectric memory further comprises a detection unit, such as a sense amplifier 1031, electrically connected to the bit line BL for detecting a voltage on the bit line BL and driving the bit line BL to a full logic "1" or "0" level by comparing the voltage with a reference voltage, thereby implementing a read operation.

In one example, as shown in fig. 1, the ferroelectric memory in the embodiment of the present application further includes an amplifying circuit 103, where the amplifying circuit 103 is located between the drain of the first transistor 101 and the bit line BL, and the current output from the first capacitor 102 is amplified by the amplifying circuit 103 and then output to the bit line BL.

The amplifying circuit 103 is configured to: when reading the data stored in the first capacitor 102, the current output from the first capacitor 102 is amplified and then output to the bit line BL, so that the voltage of the bit line BL is increased, the voltage difference between the bit line BL when reading the first state data in the stored data and the bit line BL when reading the second state data in the stored data is increased, and the sensing margin and the reading robustness are improved.

In another example, the amplifying circuit 103 may also be used to reduce the voltage V of the bit line BL when the polarity of the ferroelectric capacitor is negative_BLNAnd also for increasing the voltage V of the bit line BL when the polarity of the ferroelectric capacitor is positive_BLPThereby increasing a voltage difference between the two voltages in order to improve sensing margin and read robustness.

The amplifying circuit 103 may be any circuit known to those skilled in the art to implement the functions of the present application, for example, as shown in fig. 1, the amplifying circuit 103 includes an amplifier 1031, a first resistor 1033 and a second resistor 1032, wherein a forward input terminal of the amplifier 1031 is electrically connected to the drain of the first transistor 101, an output terminal of the amplifier 1031 is electrically connected to the bit line BL, the first resistor 1033 is connected to the inverting input terminal and the output terminal, and the second resistor 1032 is electrically connected to the inverting input terminal and the ground.

The amplifier 1031 may be an amplifier 1031 with any structure, and the resistance values of the first resistor 1033 and the second resistor 1032 may be reasonably selected according to implementation requirements, and are not specifically limited herein.

Next, a stored data reading method of the ferroelectric memory of the present application is described with reference to fig. 2. Specifically, when reading data stored in a first capacitance such as a ferroelectric capacitor, a current output from the first capacitance is amplified and output to the bit line.

As shown in FIG. 2, a read operation of a ferroelectric memory to precharge bit lines to a low voltage, e.g., V_DDStarting with/2, after the bit line is precharged, the word line is energized to turn on the first transistor and couple the first capacitance, e.g., ferroelectric capacitor, to the amplifier circuit input, the amplifier circuit output being coupled to the bit line. Next, as shown in FIG. 2, the voltage of plate line PL is increased from a low voltage to a high voltage V_DDTo access the polarization capacitance of the first capacitance. Energization of plate line PL induces a read current to flow through the amplification circuit onto the bit line to develop a voltage on the bit line. The voltage level on the bit line is dependent on the polarity of the capacitance exhibited by the ferroelectric capacitor, e.g., if the polarity of the first capacitance is positive, the read current will be relatively low and the voltage of the corresponding bit line will be low, whereas if the polarity of the first capacitance is negative, the read current will be relatively high and the voltage of the corresponding bit line will be high. The current output from the first capacitor is amplified by the amplifying circuit and then output to the bit line, so that the voltage of the bit line is increased, and the voltage difference of the bit line is increased. The type of data (i.e., data states, such as binary information value states, 0 and 1) stored by the memory cell is determined by determining the polarity of the ferroelectric material in the ferroelectric capacitor.

The pulse post sensing described above may be employed in embodiments of the present application as well as a step sensing method, wherein preferably a step sensing method is employed, wherein the step sensing method activates a detection cell, e.g., activates a sense amplifier of the detection cell, during a plateline pulse, e.g., at time t2 shown in fig. 2), the sense amplifier comparing a bitline voltage with a reference voltage from a reference voltage generator (not shown). To identify the stored data states, at respectively expected low data state levels V_BLPAnd a high data state level V_BLNThe reference voltage is set at a nominal voltage in between (i.e., between the levels corresponding to 0 and 1 in fig. 2). The detection unit responds to the detection of a high data state level V_BLNThe bit line is driven to a full logic "1" level and in response to detecting a low data state level V_BLPThe bit lines are driven to a full logic '0' level to thereby implement a read operation, and since a voltage difference of the bit lines of the present application is increased by the amplification circuit, a sensing margin and read robustness are increased.

In summary, according to the ferroelectric memory and the stored data reading method thereof in the embodiments of the present invention, when reading the data stored in the first capacitor, the current output from the first capacitor is amplified and then output to the bit line, so as to increase the voltage of the bit line, so that the voltage difference between the bit line when reading the first state data in the stored data and the bit line when reading the second state data in the stored data is increased, thereby improving the sensing margin and the reading robustness, and since the ferroelectric memory of the present application only includes one capacitor and one transistor, the area thereof is smaller, and the cost is lower.

Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.

In the several embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other ways. For example, the above-described device embodiments are merely illustrative, and for example, the division of the units is only one logical functional division, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another device, or some features may be omitted, or not executed.

In the description provided herein, numerous specific details are set forth. It is understood, however, that embodiments of the invention may be practiced without these specific details. In some instances, well-known methods, structures and techniques have not been shown in detail in order not to obscure an understanding of this description.

Similarly, it should be appreciated that in the description of exemplary embodiments of the invention, various features of the invention are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the invention and aiding in the understanding of one or more of the various inventive aspects. However, the method of the present invention should not be construed to reflect the intent: that the invention as claimed requires more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive aspects lie in less than all features of a single disclosed embodiment. Thus, the claims following the detailed description are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate embodiment of this invention.

It will be understood by those skilled in the art that all of the features disclosed in this specification (including any accompanying claims, abstract and drawings), and all of the processes or elements of any method or apparatus so disclosed, may be combined in any combination, except combinations where such features are mutually exclusive. Each feature disclosed in this specification (including any accompanying claims, abstract and drawings) may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise.

Furthermore, those skilled in the art will appreciate that while some embodiments described herein include some features included in other embodiments, rather than other features, combinations of features of different embodiments are meant to be within the scope of the invention and form different embodiments. For example, in the claims, any of the claimed embodiments may be used in any combination.

It should be noted that the above-mentioned embodiments illustrate rather than limit the invention, and that those skilled in the art will be able to design alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word "comprising" does not exclude the presence of elements or steps not listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The invention may be implemented by means of hardware comprising several distinct elements, and by means of a suitably programmed computer. In the unit claims enumerating several means, several of these means may be embodied by one and the same item of hardware. The usage of the words first, second and third, etcetera do not indicate any ordering. These words may be interpreted as names.

The above description is only for the specific embodiment of the present invention or the description thereof, and the protection scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and the changes or substitutions should be covered within the protection scope of the present invention. The protection scope of the present invention shall be subject to the protection scope of the claims.