阅读说明：本技术 一种硅反外延片的制备方法 (Preparation method of silicon anti-epitaxial wafer ) 是由 李杨 傅颖洁 李明达 薛兵 唐发俊 于 2020-12-28 设计创作，主要内容包括：本发明涉及一种硅反外延片的制备方法,反应腔体内通入氯化氢气体；将直筒式石墨基座表面沉积一层无掺杂致密多晶硅；向反应腔体内直筒式石墨基座上装入硅衬底片；磷烷气体进入反应腔体,使磷烷气体充满反应腔体；在硅衬底片上进行第一层硅外延层生长；第一层硅外延层生长完成后,磷烷气体进入反应腔体,使磷烷气体充满反应腔体；在第一层硅外延层上进行第二层硅外延层生长；第二层硅外延层生长完成后,磷烷气体进入反应腔体,使磷烷气体充满反应腔体；在第二层硅外延层上进行第三层硅外延层生长；第三层硅外延层生长完成后得到硅反外延片。本方法显著提升了硅外延片的硅外延层掺杂浓度一个数量级,硅外延层厚度达到250～260μm的超厚状态。(The invention relates to a preparation method of a silicon anti-epitaxial wafer, wherein hydrogen chloride gas is introduced into a reaction cavity; depositing a layer of undoped compact polysilicon on the surface of a straight cylinder type graphite base; a silicon substrate slice is arranged on a straight cylinder type graphite base in the reaction cavity; allowing the phosphine gas to enter the reaction cavity to fill the reaction cavity with the phosphine gas; growing a first silicon epitaxial layer on a silicon substrate; after the growth of the first silicon epitaxial layer is finished, allowing phosphine gas to enter the reaction cavity, so that the reaction cavity is filled with the phosphine gas; growing a second silicon epitaxial layer on the first silicon epitaxial layer; after the growth of the second silicon epitaxial layer is finished, allowing phosphine gas to enter the reaction cavity, so that the reaction cavity is filled with the phosphine gas; growing a third silicon epitaxial layer on the second silicon epitaxial layer; and obtaining the silicon reverse epitaxial wafer after the growth of the third silicon epitaxial layer is finished. The method obviously improves the doping concentration of the silicon epitaxial layer of the silicon epitaxial wafer by one order of magnitude, and the thickness of the silicon epitaxial layer reaches an ultra-thick state of 250-260 mu m.)

1. A preparation method of a silicon reverse epitaxial wafer is characterized by comprising the following steps:

(1) introducing hydrogen chloride gas into the reaction cavity, setting the flow of the hydrogen chloride gas to be 34-36L/min, etching residual deposited substances on the straight-tube graphite base of the reaction cavity at high temperature, setting the etching temperature to be 1160-1180 ℃, and setting the etching time to be 3.0-3.5 min;

(2) setting the hydrogen flow to be 300-305L/min, carrying gaseous trichlorosilane to enter a reaction cavity, setting the trichlorosilane flow to be 36.0-37.0L/min, setting the reaction time to be 55-60 sec, and depositing a layer of undoped dense polycrystalline silicon on the surface of the straight-tube graphite base;

(3) loading a silicon substrate slice on the straight-barrel type graphite base in the reaction cavity, wherein the diameter of the silicon substrate slice is 150-200 mm, and then heating the reaction cavity to 1130-1160 ℃;

(4) allowing the phosphine gas to enter the reaction cavity, wherein the flow rate of the phosphine gas is set to be 800-820 sccm, and the entering time is set to be 2-3 min, so that the phosphine gas is filled in the reaction cavity;

(5) growing a first silicon epitaxial layer on a silicon substrate, dividing hydrogen into two paths to enter a reaction cavity, setting the flow of one path of hydrogen to be 300-305L/min, simultaneously carrying gaseous trichlorosilane to enter the reaction cavity, setting the flow of trichlorosilane to be 35-36L/min, setting the reaction time to be 17-21 min, setting the flow of the other path of hydrogen to be 0.1L/min, simultaneously carrying phosphine gas to enter the reaction cavity, and setting the flow of the phosphine gas to be 800-820 sccm;

(6) after the growth of the first silicon epitaxial layer is finished, allowing phosphine gas to enter the reaction cavity, wherein the flow rate of the phosphine gas is set to be 800-820 sccm, and the entering time is set to be 2-3 min, so that the phosphine gas is filled in the reaction cavity;

(7) growing a second silicon epitaxial layer on the first silicon epitaxial layer, dividing hydrogen into two paths to enter a reaction cavity, setting the flow of one path of hydrogen to be 300-305L/min, simultaneously carrying gaseous trichlorosilane to enter the reaction cavity, setting the flow of trichlorosilane to be 35-36L/min, setting the reaction time to be 17-21 min, setting the flow of the other path of hydrogen to be 0.1L/min, simultaneously carrying phosphine gas to enter the reaction cavity, and setting the flow of the phosphine gas to be 800-820 sccm;

(8) after the growth of the second silicon epitaxial layer is finished, allowing phosphine gas to enter the reaction cavity, wherein the flow rate of the phosphine gas is set to be 800-820 sccm, and the entering time is set to be 2-3 min, so that the phosphine gas is filled in the reaction cavity;

(9) growing a third silicon epitaxial layer on the second silicon epitaxial layer, dividing hydrogen into two paths to enter a reaction cavity, setting the flow of one path of hydrogen to be 300-305L/min, simultaneously carrying gaseous trichlorosilane to enter the reaction cavity, setting the flow of trichlorosilane to be 35-36L/min, setting the reaction time to be 9-11 min, setting the flow of the other path of hydrogen to be 0.1L/min, simultaneously carrying phosphine gas to enter the reaction cavity, and setting the flow of the phosphine gas to be 800-820 sccm;

(10) and after the growth of the third silicon epitaxial layer is finished, obtaining a silicon reverse epitaxial wafer, cooling, and taking out the silicon reverse epitaxial wafer from the straight-barrel graphite base after the temperature of the silicon reverse epitaxial wafer is reduced to 60 ℃.

2. A method for preparing a silicon anti-epitaxial wafer according to claim 1, characterized in that: the resistivity of the silicon substrate sheet is 1000-1500 omega cm.

Technical Field

The invention relates to the technical field of preparation of semiconductor epitaxial materials, in particular to a preparation method of a silicon anti-epitaxial wafer.

Background

The working principle of the photodetector is the photoelectric effect, when the energy of an incident photon is larger than or equal to the band gap energy of a semiconductor, an electron on an excited valence band absorbs the energy of the photon and jumps to a conduction band, and the process generates a free electron-hole pair. The N-type semiconductor with low concentration is introduced into the middle of the PN junction of the photodiode, so that the width of a depletion region can be increased, and the aims of reducing the influence of diffusion motion and improving the response speed are fulfilled. This structure becomes a PIN photodiode because this doped layer is called an I layer because of its low doping concentration, nearly Intrinsic semiconductor. The I layer is thick and occupies almost the entire depletion region. The vast majority of incident light is absorbed within the I layer and a large number of electron-hole pairs are generated. The P-type and N-type semiconductors with high doping concentration are arranged on two sides of the I layer, the P layer and the N layer are very thin, and the proportion of absorbing incident light is very small. The drift component of the light-generating current is thus dominant, which greatly increases the response speed.

The PIN photodiode requires ultra-high resistivity and ultra-thick layer for silicon material, and the epitaxial process can not be realized. For a long time, the research units of devices all adopt a zone-melting silicon single crystal substrate as a base, but the performance of the devices is greatly restricted due to overlarge contact resistance.

The silicon anti-epitaxial wafer and the silicon epitaxial wafer are used in the opposite way, the zone-melting silicon single crystal is used as an active region of a device, the doping concentration of the prepared epitaxial layer is high, the prepared epitaxial layer is super-thick, the potential gradient is formed, and the metal electrode and the heavily-doped epitaxial layer region form ohmic contact. Therefore, the doping concentration of the silicon epitaxial layer of the silicon anti-epitaxial wafer needs to be reached>4×10¹⁹cm^-3The thickness of the silicon epitaxial layer needs to reach an ultra-thick state of 250-260 mu m, the crystal integrity of the silicon epitaxial layer is good, and the epitaxial layer is prevented from being broken due to defectsDamage and debris. The conventional method for directly growing the low-defect heavily-doped epitaxial layer in the super-thick state is difficult, and the doping concentration of the silicon epitaxial layer can only reach 1 × 10¹⁸cm^-3~6×10¹⁸cm^-3The magnitude of (1) is lower than the target value, and the practical application of the device is seriously influenced.

Disclosure of Invention

The invention aims to solve the problem that the existing silicon epitaxial wafer is difficult to control the compatibility of heavy doping concentration and low-defect ultra-thick epitaxial growth in the conventional epitaxial growth process, and the preparation method of the silicon epitaxial wafer is obtained by designing a method for multi-stage epitaxial growth and pre-feeding high-concentration phosphine gas into a reaction cavity, so that the doping concentration of a silicon epitaxial layer of the silicon epitaxial wafer and the lattice integrity of the silicon epitaxial layer in an ultra-thick state are obviously improved, and the use requirement is met.

The technical scheme adopted by the invention is as follows: a preparation method of a silicon anti-epitaxial wafer comprises the following steps:

(1) introducing hydrogen chloride gas into the reaction cavity, setting the flow of the hydrogen chloride gas to be 34-36L/min, etching residual deposited substances on the straight-tube graphite base of the reaction cavity at high temperature, setting the etching temperature to be 1160-1180 ℃, and setting the etching time to be 3.0-3.5 min;

(2) setting the hydrogen flow to be 300-305L/min, carrying gaseous trichlorosilane to enter a reaction cavity, setting the trichlorosilane flow to be 36.0-37.0L/min, setting the reaction time to be 55-60 sec, and depositing a layer of undoped dense polycrystalline silicon on the surface of the straight-tube graphite base;

(3) loading a silicon substrate slice on the straight-barrel type graphite base in the reaction cavity, wherein the diameter of the silicon substrate slice is 150-200 mm, and then heating the reaction cavity to 1130-1160 ℃;

(4) allowing the phosphine gas to enter the reaction cavity, wherein the flow rate of the phosphine gas is set to be 800-820 sccm, and the entering time is set to be 2-3 min, so that the phosphine gas is filled in the reaction cavity;

(5) growing a first silicon epitaxial layer on a silicon substrate, dividing hydrogen into two paths to enter a reaction cavity, setting the flow of one path of hydrogen to be 300-305L/min, simultaneously carrying gaseous trichlorosilane to enter the reaction cavity, setting the flow of trichlorosilane to be 35-36L/min, setting the reaction time to be 17-21 min, setting the flow of the other path of hydrogen to be 0.1L/min, simultaneously carrying phosphine gas to enter the reaction cavity, and setting the flow of the phosphine gas to be 800-820 sccm;

(6) after the growth of the first silicon epitaxial layer is finished, allowing phosphine gas to enter the reaction cavity, wherein the flow rate of the phosphine gas is set to be 800-820 sccm, and the entering time is set to be 2-3 min, so that the phosphine gas is filled in the reaction cavity;

(7) growing a second silicon epitaxial layer on the first silicon epitaxial layer, dividing hydrogen into two paths to enter a reaction cavity, setting the flow of one path of hydrogen to be 300-305L/min, simultaneously carrying gaseous trichlorosilane to enter the reaction cavity, setting the flow of trichlorosilane to be 35-36L/min, setting the reaction time to be 17-21 min, setting the flow of the other path of hydrogen to be 0.1L/min, simultaneously carrying phosphine gas to enter the reaction cavity, and setting the flow of the phosphine gas to be 800-820 sccm;

(8) after the growth of the second silicon epitaxial layer is finished, allowing phosphine gas to enter the reaction cavity, wherein the flow rate of the phosphine gas is set to be 800-820 sccm, and the entering time is set to be 2-3 min, so that the phosphine gas is filled in the reaction cavity;

(9) growing a third silicon epitaxial layer on the second silicon epitaxial layer, dividing hydrogen into two paths to enter a reaction cavity, setting the flow of one path of hydrogen to be 300-305L/min, simultaneously carrying gaseous trichlorosilane to enter the reaction cavity, setting the flow of trichlorosilane to be 35-36L/min, setting the reaction time to be 9-11 min, setting the flow of the other path of hydrogen to be 0.1L/min, simultaneously carrying phosphine gas to enter the reaction cavity, and setting the flow of the phosphine gas to be 800-820 sccm;

(10) and after the growth of the third silicon epitaxial layer is finished, obtaining a silicon reverse epitaxial wafer, cooling, and taking out the silicon reverse epitaxial wafer from the straight-barrel graphite base after the temperature of the silicon reverse epitaxial wafer is reduced to 60 ℃.

The invention has the advantages that the problem that the heavy doping concentration and the low defect ultra-thick epitaxial growth of the conventional silicon reverse epitaxial wafer are difficult to be compatible in the conventional epitaxial growth process is solved, and the method for pre-entering the reaction cavity before the growth of multi-stage epitaxy and the growth of high-concentration phosphine gas is designed, so that the invention provides the method for preparing the silicon reverse epitaxial wafer with high doping concentration and low defect ultra-thick epitaxial growthThe preparation method of the silicon anti-epitaxial wafer with doping concentration and ultra-thick state and low defect realizes the doping concentration of the silicon epitaxial wafer>4×10¹⁹cm^-3Compared with the conventional epitaxial process, the doping concentration of the silicon epitaxial layer of the silicon epitaxial wafer can be obviously improved by one order of magnitude, and meanwhile, the thickness of the silicon epitaxial layer can reach an ultra-thick state of 250-260 mu m and a good control level without crystal defects.

Detailed Description

The diameter of the silicon substrate sheet used in the invention is 150-200 mm, the resistivity is 1000-1500 omega cm, and the thickness and the doping concentration of the prepared silicon reverse epitaxial wafer are obtained by testing the central point of the silicon reverse epitaxial wafer.

Example 1

(1) Introducing hydrogen chloride gas into the reaction cavity, setting the flow of the hydrogen chloride gas at 35L/min, etching residual deposited substances on the straight-barrel graphite pedestal of the reaction cavity at high temperature, setting the etching temperature at 1170 ℃, and setting the etching time at 3.2 min;

(2) setting the hydrogen flow rate to be 302L/min, carrying gaseous trichlorosilane to enter a reaction cavity, setting the trichlorosilane flow rate to be 36.5L/min, setting the reaction time to be 58 sec, and depositing a layer of undoped dense polycrystalline silicon on the surface of the straight-tube graphite base;

(3) loading a silicon substrate slice with the diameter of 150mm on a straight-barrel type graphite base in a reaction cavity, and then heating the reaction cavity to 1140 ℃;

(4) allowing the phosphine gas to enter the reaction cavity, wherein the flow rate of the phosphine gas is set to be 810sccm, and the entering time is set to be 2.5min, so that the phosphine gas is filled in the reaction cavity;

(5) growing a silicon epitaxial layer on a silicon substrate, dividing hydrogen into two paths to enter a reaction cavity, setting the flow of one path of hydrogen to be 302L/min, simultaneously carrying gaseous trichlorosilane to enter the reaction cavity, setting the flow of trichlorosilane to be 35.5L/min, setting the reaction time to be 50 min, setting the flow of the other path of hydrogen to be 0.1L/min, simultaneously carrying phosphine gas to enter the reaction cavity, and setting the flow of the phosphine gas to be 810 sccm;

(6) and after the growth of the silicon epitaxial layer is finished, obtaining a silicon anti-epitaxial wafer, starting cooling, and taking out the silicon anti-epitaxial wafer from the straight-barrel graphite base after the temperature of the silicon anti-epitaxial wafer is reduced to 60 ℃.

The silicon epitaxial wafer obtained in example 1 had a silicon epitaxial layer doping concentration of only 2X 10¹⁸cm^-3The thickness of the silicon epitaxial layer reaches 255 mu m, and the surface defect density is high, so that the single-step epitaxial growth cannot meet the use requirement of the device.

Example 2

(1) Introducing hydrogen chloride gas into the reaction cavity, setting the flow of the hydrogen chloride gas at 35L/min, etching residual deposited substances on the graphite base of the reaction cavity at a high temperature, setting the etching temperature at 1170 ℃, and setting the etching time at 3.2 min;

(2) setting the hydrogen flow rate to be 302L/min, allowing gaseous trichlorosilane to enter a reaction cavity, setting the trichlorosilane flow rate to be 36.5L/min, setting the reaction time to be 58 sec, and depositing a layer of undoped dense polycrystalline silicon on the surface of the straight-tube graphite base;

(3) loading a silicon substrate slice with the diameter of 150mm on a straight-barrel type graphite base in a reaction cavity, and then heating the reaction cavity to 1140 ℃;

(4) allowing the phosphine gas to enter the reaction cavity, wherein the flow rate of the phosphine gas is set to be 600sccm, and the entering time is set to be 2.5min, so that the phosphine gas is filled in the reaction cavity;

(5) growing a first silicon epitaxial layer on a silicon substrate, dividing hydrogen into two paths to enter a reaction cavity, setting the flow of one path of hydrogen to be 302L/min, simultaneously carrying gaseous trichlorosilane to enter the reaction cavity, setting the flow of trichlorosilane to be 35.5L/min, setting the reaction time to be 20min, setting the flow of the other path of hydrogen to be 0.1L/min, simultaneously carrying phosphine gas to enter the reaction cavity, and setting the flow of the phosphine gas to be 810 sccm;

(6) after the growth of the first silicon epitaxial layer is finished, allowing phosphine gas to enter the reaction cavity, wherein the flow rate of the phosphine gas is set to 600sccm, and the entering time is set to 2.5min, so that the phosphine gas is filled in the reaction cavity;

(7) growing a second silicon epitaxial layer on the first silicon epitaxial layer, dividing hydrogen into two paths to enter a reaction cavity, setting the flow of one path of hydrogen to be 302L/min, simultaneously carrying gaseous trichlorosilane to enter the reaction cavity, setting the flow of trichlorosilane to be 35.5L/min, setting the reaction time to be 20min, setting the flow of the other path of hydrogen to be 0.1L/min, simultaneously carrying phosphine gas to enter the reaction cavity, and setting the flow of the phosphine gas to be 810 sccm;

(8) allowing the phosphine gas to enter the reaction cavity, wherein the flow rate of the phosphine gas is set to be 600sccm, and the entering time is set to be 2.5min, so that the phosphine gas is filled in the reaction cavity;

(9) growing a third silicon epitaxial layer on the second silicon epitaxial layer, dividing hydrogen into two paths to enter a reaction cavity, setting the flow of one path of hydrogen to be 302L/min, carrying gaseous trichlorosilane to enter the reaction cavity, setting the flow of trichlorosilane to be 35.5L/min, setting the reaction time to be 10 min, setting the flow of the other path of hydrogen to be 0.1L/min, simultaneously carrying phosphine gas to enter the reaction cavity, and setting the flow of the phosphine gas to be 810 sccm;

(10) and (3) finishing the growth of the third silicon epitaxial layer to obtain a silicon reverse epitaxial wafer, starting cooling, and taking out the silicon reverse epitaxial wafer from the straight-barrel graphite base after the temperature of the silicon reverse epitaxial wafer is reduced to 60 ℃.

The doping concentration of the silicon epitaxial layer of the silicon anti-epitaxial wafer prepared in the example 2 is only 6 multiplied by 10¹⁸cm³The thickness of the silicon epitaxial layer reaches 255 mu m, and the surface defect density is higher, so that the surface quality and the doping concentration of the silicon reverse epitaxial wafer can not meet the use requirement of a device only by adopting two-step epitaxial growth.

Example 3

(1) Introducing hydrogen chloride gas into the reaction cavity, setting the flow of the hydrogen chloride gas at 35L/min, etching residual deposited substances on the straight-tube graphite base of the reaction cavity at a high temperature, setting the etching temperature at 1170 ℃, and setting the etching time at 3.2 min;

(2) setting the hydrogen flow rate to be 302L/min, carrying gaseous trichlorosilane to enter a reaction cavity, setting the trichlorosilane flow rate to be 36.5L/min, setting the reaction time to be 58 sec, and depositing a layer of undoped dense polycrystalline silicon on the surface of the straight-tube graphite base;

(3) loading a silicon substrate slice with the diameter of 150mm on a straight-barrel type graphite base in a reaction cavity, and then heating the reaction cavity to 1140 ℃;

(4) allowing the phosphine gas to enter the reaction cavity, wherein the flow rate of the phosphine gas is set to be 810sccm, and the entering time is set to be 2.5min, so that the phosphine gas is filled in the reaction cavity;

(5) growing a first silicon epitaxial layer on a silicon substrate, dividing hydrogen into two paths to enter a reaction cavity, setting the flow of one path of hydrogen to be 302L/min, simultaneously carrying gaseous trichlorosilane to enter the reaction cavity, setting the flow of trichlorosilane to be 35.5L/min, setting the reaction time to be 20min, setting the flow of the other path of hydrogen to be 0.1L/min, simultaneously carrying phosphine gas to enter the reaction cavity, and setting the flow of the phosphine gas to be 810 sccm;

(6) after the growth of the first silicon epitaxial layer is finished, allowing phosphine gas to enter the reaction cavity, wherein the flow rate of the phosphine gas is set to 810sccm, and the entering time is set to 2.5min, so that the phosphine gas is filled in the reaction cavity;

(7) growing a second silicon epitaxial layer on the first silicon epitaxial layer, dividing hydrogen into two paths to enter a reaction cavity, setting the flow of one path of hydrogen to be 302L/min, simultaneously carrying gaseous trichlorosilane to enter the reaction cavity, setting the flow of trichlorosilane to be 35.5L/min, setting the reaction time to be 20min, setting the flow of the other path of hydrogen to be 0.1L/min, simultaneously carrying phosphine gas to enter the reaction cavity, and setting the flow of the phosphine gas to be 810 sccm;

(8) after the growth of the second silicon epitaxial layer is finished, allowing phosphine gas to enter the reaction cavity, wherein the flow rate of the phosphine gas is set to 810sccm, and the entering time is set to 2.5min, so that the phosphine gas is filled in the reaction cavity;

(9) growing a third silicon epitaxial layer on the second silicon epitaxial layer, dividing hydrogen into two paths to enter a reaction cavity, setting the flow of one path of hydrogen to be 302L/min, simultaneously carrying gaseous trichlorosilane to enter the reaction cavity, setting the flow of trichlorosilane to be 35.5L/min, setting the reaction time to be 10 min, setting the flow of the other path of hydrogen to be 0.1L/min, simultaneously carrying phosphine gas to enter the reaction cavity, and setting the flow of the phosphine gas to be 810 sccm;

(10) and after the growth of the third silicon epitaxial layer is finished, obtaining a silicon reverse epitaxial wafer, cooling, and taking out the silicon reverse epitaxial wafer from the straight-barrel graphite base after the temperature of the silicon reverse epitaxial wafer is reduced to 60 ℃.

The doping concentration of the silicon epitaxial layer prepared in example 3 reached 6 × 10¹⁹cm^-3The thickness of the silicon epitaxial layer reaches 255 mu m, and the surface is free of defects.

Compared with the embodiment 1 and the embodiment 2, under the corresponding process conditions, the embodiment 3 adopts three-step silicon epitaxial layer growth, and before each step of silicon epitaxial layer growth, a mode of introducing phosphine gas into a reaction cavity and filling the cavity is adopted in advance, so that the silicon epitaxial layer doping concentration of the prepared silicon anti-epitaxial wafer is highest, the crystal quality is best under an ultra-thick state, and the use requirement of a device can be met, therefore, the embodiment 3 is the best embodiment of the invention.

It is apparent that those skilled in the art can make various changes and modifications to the preparation method of the present invention without departing from the spirit and scope of the present invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is intended to include such modifications and variations.