阅读说明：本技术 一种滤波器晶圆级封装工艺及滤波器晶圆级封装结构 (Filter wafer level packaging process and filter wafer level packaging structure ) 是由 朱其壮 李永智 吕军 赖芳奇 于 2020-12-24 设计创作，主要内容包括：本发明涉及半导体封装技术领域,公开了一种滤波器晶圆级封装工艺及滤波器晶圆级封装结构。滤波器晶圆包括基板,基板的上表面设置有功能区和多个焊垫,滤波器晶圆级封装工艺包括：在硅片的一侧开设凹槽以形成覆盖晶圆；通过胶水层将覆盖晶圆设置有凹槽的一侧粘合于基板的上侧,以形成配合体,功能区容纳于基板与凹槽围成的空间；从覆盖晶圆一侧,对配合体开设盲孔,以使焊垫的导电层露出；将微凸焊点与所述导电层电性连接。本发明的滤波器晶圆级封装工艺,封装过程简单、不易污染功能区,且有利于降低封装结构的厚度。本发明的滤波器晶圆级封装结构,通过采用上述的滤波器晶圆及封装工艺,生产过程更简单方便,且整体更轻薄、封装效果好。(The invention relates to the technical field of semiconductor packaging, and discloses a filter wafer level packaging process and a filter wafer level packaging structure. The filter wafer comprises a substrate, wherein a functional area and a plurality of welding pads are arranged on the upper surface of the substrate, and the filter wafer-level packaging process comprises the following steps: forming a groove on one side of the silicon wafer to form a cover wafer; the side, provided with the groove, of the cover wafer is bonded to the upper side of the substrate through the glue layer to form a matching body, and the functional area is accommodated in a space formed by the substrate and the groove; forming a blind hole on the matching body from one side of the covering wafer so as to expose the conductive layer of the welding pad; and electrically connecting the micro-bump with the conductive layer. The wafer-level packaging process of the filter has the advantages of simple packaging process, difficulty in polluting functional areas and contribution to reducing the thickness of a packaging structure. By adopting the filter wafer and the packaging process, the production process is simpler and more convenient, the whole structure is thinner and thinner, and the packaging effect is good.)

1. A filter wafer level packaging process, wherein a filter wafer (1) comprises a substrate (11), a functional region (12) and a plurality of bonding pads (13) are arranged on the upper surface of the substrate (11), and the process comprises the following steps:

forming a groove (21) on one side of the silicon wafer to form a cover wafer (2);

bonding one side, provided with a groove (21), of the cover wafer (2) to the upper side of the substrate (11) through a glue layer (3) to form a matching body (4), wherein the functional region (12) is accommodated in a space formed by the substrate (11) and the groove (21);

forming a blind hole (41) in the matching body (4) from one side of the cover wafer (2) so as to expose the conductive layer (132) of the bonding pad (13);

and electrically connecting the micro-bump (5) with the conductive layer (132).

2. The process for wafer-level packaging of filters according to claim 1, characterized in that the cover wafer (2) is thinned to 10 μm to 500 μm before the blind holes (41) are opened to the mating body (4).

3. The process of claim 1, wherein the substrate (11) is thinned to 20 μm to 300 μm after the micro bump (5) is electrically connected to the conductive layer (132).

4. The process of claim 3, wherein before thinning the substrate (11), a grinding tape (6) is adhered to the cover wafer (2), the grinding tape (6) covers the micro-bump (5), and after thinning the substrate (11), the grinding tape (6) is torn off.

5. The filter wafer level packaging process of any one of claims 1-4, further comprising:

after the blind holes (41) are machined, sputtering a metal layer (7) on the matching body (4) in a physical vapor deposition mode, wherein the metal layer (7) covers the surface, far away from the substrate (11), of the cover wafer (2) and the inner surface of the blind holes (41);

and filling the blind hole (41) sputtered with the metal layer (7) with a Cu connector (8) through an electroplating process, wherein the micro bump (5) is electrically connected with the Cu connector (8).

6. The process for wafer-level packaging of filters according to claim 5, characterized in that the area of the upper side of the cover wafer (2) within the predetermined size range of the blind via (41) is a predetermined area, and after the Cu connector (8) fills up the blind via (41), the metal layer (7) is removed from the cover wafer (2) except the predetermined area, and only the reserved area (71) is reserved; and plating an under-ball metal layer (9) on the reserved area (71) in a chemical plating mode, wherein the under-ball metal layer (9) is electrically connected with the micro-bump (5).

7. The process for wafer level packaging of filters according to any of claims 1 to 4, wherein the method for forming the recess (21) comprises:

manufacturing a region to be grooved on the lower surface of the silicon wafer by adopting a photoetching method; etching the groove (21) in the region to be grooved by adopting a dry etching or wet etching silicon mode; or

And directly manufacturing the groove (21) on the cover wafer (2) by adopting a laser ablation method.

8. The process of wafer level packaging of filter according to any of claims 1-4, wherein the blind via (41) is formed by a laser drilling process, the blind via (41) penetrating the bonding pad (13) to expose the conductive layer (132) of the bonding pad (13).

9. A filter wafer level package structure, characterized by being manufactured by the method for packaging a filter wafer according to any one of claims 1 to 8.

10. The filter wafer level package structure of claim 9, comprising:

a filter wafer (1);

the cover wafer (2) is made of a silicon wafer, the cover wafer (2) is bonded to the upper surface of the substrate (11) through a glue layer (3), a groove (21) is formed in one side, close to the substrate (11), of the cover wafer (2), and the functional area (12) is contained in the substrate (11) and the groove (21);

and the micro-bump (5) is convexly arranged on the covering wafer (2), and the micro-bump (5) is electrically connected with the welding pad (13).

Technical Field

The invention relates to the technical field of semiconductor packaging, in particular to a filter wafer level packaging process and a filter wafer level packaging structure.

Background

The filter is a frequency selection device, which can pass specific frequency components in the signal, and greatly attenuate other frequency components, so that the filter can be used for filtering interference noise. As shown in fig. 1, the wafer level 1 ' of the filter includes a substrate 11 ', a functional region 12 ' and a pad 13 ' are disposed on an upper surface of the substrate 11 ', and the functional region 12 ' is required to be located in a cavity when the wafer level 1 ' of the filter is packaged according to the performance and function requirements of the filter. As shown in fig. 1, in the prior art, when a filter wafer 1 'is packaged, a patterned support cofferdam 2' is formed on one side of a substrate 11 'where a functional region 12' is disposed, a protective layer 3 'is further disposed on the support cofferdam 2', the substrate 11 ', the support cofferdam 2' and the protective layer 3 'together enclose a closed accommodating cavity 4', the functional region 12 'is located in the accommodating cavity 4', and a bonding pad 13 'is electrically connected with an external structure through a micro-bump 5'. In the packaging process in the prior art, on one hand, the supporting cofferdam is usually formed on the substrate by adopting a dry film photoetching process, and the pollution of a functional area is easily caused in the processing process; on the other hand, the supporting cofferdam and the protective layer are packaged together, the process is complex, the supporting cofferdam, the substrate and the protective layer are bonded by adhesives, and the finally obtained packaging structure is thick in whole thickness.

Therefore, it is desirable to provide a filter wafer level packaging process and a filter wafer level packaging structure to solve the above technical problems.

Disclosure of Invention

The first objective of the present invention is to provide a wafer level package process for a filter, which has a simple package process, is not easy to contaminate a functional area, and is beneficial to reduce the thickness of a package structure.

The second objective of the present invention is to provide a wafer level package structure of a filter, which is more simple and convenient in production process, thinner and thinner as a whole, and has a good packaging effect by using the above-mentioned filter wafer and packaging process.

In order to achieve the purpose, the invention adopts the following technical scheme:

a wafer-level packaging process for a filter, wherein the filter wafer comprises a substrate, a functional area and a plurality of welding pads are arranged on the upper surface of the substrate, and the wafer-level packaging process for the filter comprises the following steps:

forming a groove on one side of the silicon wafer to form a cover wafer;

bonding one side of the cover wafer, provided with the groove, to the upper side of the substrate through a glue layer to form a matching body, wherein the functional area is accommodated in a space formed by the substrate and the groove;

forming a blind hole in the matching body from one side of the cover wafer so as to expose the conductive layer of the welding pad;

and electrically connecting the micro-bump with the conductive layer.

Optionally, before the blind holes are opened on the matching body, the cover wafer is thinned to 10 μm to 500 μm.

Optionally, after the micro-bump is electrically connected with the conductive layer, the substrate is thinned to 20 μm to 300 μm.

Optionally, before the base plate is thinned, a grinding adhesive tape is adhered to the cover wafer, the grinding adhesive tape covers the micro-convex welding points, and after the base plate is thinned, the grinding adhesive tape is torn down.

Optionally, the filter wafer level packaging process further includes:

after the blind holes are machined, sputtering a metal layer on the matching body in a physical vapor deposition mode, wherein the metal layer covers the surface of the cover wafer far away from the substrate and the inner surface of the blind holes;

and filling the blind hole sputtered with the metal layer with a Cu connector through an electroplating process, wherein the micro-projection welding point is electrically connected with the Cu connector.

Optionally, an area on the upper side of the cover wafer, which is located within a preset size range of the blind hole, is a preset area, after the blind hole is filled with the Cu connector, the part of the metal layer on the cover wafer, except for the preset area, is removed, and only a reserved area is reserved; and plating an under-ball metal layer on the reserved area in a chemical plating mode, wherein the under-ball metal layer is electrically connected with the micro-bump welding points.

Optionally, the forming method of the groove comprises:

manufacturing a region to be grooved on the lower surface of the silicon wafer by adopting a photoetching method; etching the groove in the region to be grooved by adopting a dry etching or wet etching silicon mode; or

And directly manufacturing the groove on the cover wafer by adopting a laser ablation method.

Optionally, the blind hole is formed by a laser drilling process, and the blind hole penetrates through the pad to expose the conductive layer of the pad.

A wafer-level packaging structure of a filter is manufactured by the packaging method of the wafer of the filter.

Optionally, the filter wafer level package structure includes:

a filter wafer;

the cover wafer is made of a silicon wafer, the cover wafer is bonded on the upper surface of the substrate through a glue layer, a groove is formed in one side, close to the substrate, of the cover wafer, and the functional area is contained in the substrate and the groove;

and the micro-bump welding points are convexly arranged on the covering wafer and are electrically connected with the welding pads.

The invention has the beneficial effects that:

according to the packaging process of the filter wafer, the groove is directly processed on the silicon wafer to form the covering wafer, which is equivalent to integrally forming the supporting cofferdam and the protective layer, so that the whole structure is simple, and the assembly is convenient; only one glue layer is needed between the cover wafer and the substrate, so that the thickness of the whole packaging structure is reduced, and the substrate and the cover wafer are made of silicon materials and are firmly and stably connected after being bonded through the glue layer; in addition, the groove is processed before the covering wafer is bonded with the substrate, so that the functional area on the wafer level cannot be polluted. The packaging process of the filter wafer is simple in packaging process, the functional area is not easily polluted, and the thickness of the packaging structure is favorably reduced.

By adopting the filter wafer and the packaging process, the production process is simpler and more convenient, the whole structure is thinner and thinner, and the packaging effect is good.

Drawings

FIG. 1 is a diagram of a prior art filter wafer level package structure;

fig. 2 is a schematic structural diagram of a filter wafer according to an embodiment of the present invention;

FIG. 3 is a flow chart of a wafer level packaging process for a filter according to an embodiment of the present invention;

FIG. 4 is a schematic diagram of a cover wafer according to an embodiment of the present invention;

FIG. 5 is a schematic diagram of a structure of a mating body according to an embodiment of the present invention;

FIG. 6 is a schematic view of a thinned cover wafer of a mating body according to an embodiment of the present invention;

FIG. 7 is a schematic structural diagram of a mating body according to an embodiment of the present invention after forming a blind hole therein;

FIG. 8 is an enlarged view taken at A in FIG. 7;

FIG. 9 is a schematic diagram of a structure of a mating body after a metal layer is sputtered on a cover wafer according to an embodiment of the present invention;

FIG. 10 is a schematic structural diagram of a mating body according to an embodiment of the present invention, in which a Cu connecting body is filled in a blind hole;

FIG. 11 is a schematic diagram of a structure of a mating body with a portion of a metal layer removed according to an embodiment of the present invention;

FIG. 12 is a schematic structural diagram of a metal layer under balls plated on a reserved area of a mating body according to an embodiment of the present invention;

FIG. 13 is a schematic structural diagram of a metal layer under a serving ball of a mating body welded with micro bump pads according to an embodiment of the present invention;

FIG. 14 is a schematic view of a mating body with a polishing tape adhered to a cover wafer according to an embodiment of the present invention;

FIG. 15 is a schematic diagram of a structure of a mating body of the invention after thinning the substrate;

fig. 16 is a flowchart of another wafer level packaging process for a filter according to an embodiment of the invention.

In the figure:

1' -a filter wafer; 11' -a substrate; a 12' -functional region; 13' -pad; 2' -supporting the cofferdam; a 3' -protective layer; 4' -a containment chamber; 5' -micro bump;

1-a filter wafer; 11-a substrate; 12-a functional region; 13-a pad; 131-a passivation layer; 132-a conductive layer;

2-covering the wafer; 21-a groove;

3-glue layer;

4-a ligand; 41-blind hole;

5-micro bump welding;

6-grinding the adhesive tape;

7-a metal layer; 71-a reserved area;

an 8-Cu linker;

9-under-ball metal layer.

Detailed Description

The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.

In the description of the present invention, unless expressly stated or limited otherwise, the terms "connected," "connected," and "fixed" are to be construed broadly, e.g., as meaning permanently connected, removably connected, or integral to one another; can be mechanically or electrically connected; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.

In the present invention, unless otherwise expressly stated or limited, "above" or "below" a first feature means that the first and second features are in direct contact, or that the first and second features are not in direct contact but are in contact with each other via another feature therebetween. Also, the first feature being "on," "above" and "over" the second feature includes the first feature being directly on and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly under and obliquely below the second feature, or simply meaning that the first feature is at a lesser elevation than the second feature.

In the description of the present embodiment, the terms "upper", "lower", "right", etc. are used in an orientation or positional relationship based on that shown in the drawings only for convenience of description and simplicity of operation, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first" and "second" are used only for descriptive purposes and are not intended to have a special meaning.

The embodiment provides a wafer level packaging process for a filter, which can be used for packaging the wafer level of an FBAR (film bulk acoustic resonator) filter and the wafer level of a BAW (bulk acoustic wave) filter. As shown in fig. 2, the filter wafer 1 includes a substrate 11, and a functional region 12 and a plurality of bonding pads 13 are disposed on an upper surface of the substrate 11, and as shown in fig. 3 to fig. 15, the filter wafer level packaging process includes:

forming a groove 21 on one side of the silicon wafer to form a cover wafer 2;

the side, provided with the groove 21, of the cover wafer 2 is bonded to the upper side of the substrate 11 through the glue layer 3 to form a matching body 4, and the functional area 12 is accommodated in a space formed by the substrate 11 and the groove 21;

forming a blind via 41 in the mating body 4 from the side of the cover wafer 2 to expose the conductive layer 132 of the pad 13;

the micro-bump 5 is electrically connected to the conductive layer 132.

In the packaging process of the filter wafer 1 of the embodiment, the cover wafer 2 is formed by directly processing the groove 21 on the silicon wafer, which is equivalent to integrally forming the support cofferdam and the protective layer, so that the whole structure is simple and the assembly is convenient; only one glue layer 3 is needed between the cover wafer 2 and the substrate 11, which is beneficial to reducing the thickness of the whole packaging structure, and the substrate 11 and the cover wafer 2 are made of silicon materials and are firmly and stably connected after being bonded by the glue layer 3; in addition, the grooves 21 are processed before the cover wafer 2 is bonded to the substrate 11, so that the functional regions 12 on the wafer level are not contaminated. The packaging process of the filter wafer of the embodiment has a simple packaging process, is not easy to pollute the functional region 12, and is beneficial to reducing the thickness of the packaging structure.

Specifically, in this embodiment, when the cover wafer 2 and the substrate 11 are bonded, the glue is printed on the non-groove 21 region on the cover wafer 2 to prevent the glue from contaminating the groove 21 and the functional region 12, then the cover wafer 2 and the substrate 11 are aligned and bonded permanently, the cover wafer 2 and the bonding pad 13 are tightly bonded through the glue layer 3 after bonding, and the functional region 12 is sealed between the groove 21 and the substrate 11. Optionally, in this embodiment, the thickness of the glue layer 3 is 0.1 μm to 100 μm, and a thinner thickness is ensured as much as possible on the premise of ensuring the adhesive strength.

Preferably, the method of forming the groove 21 includes: firstly, a region to be grooved is manufactured on the lower surface of a silicon wafer by adopting a photoetching method, and then a groove 21 is etched in the region to be grooved by adopting a dry etching or wet etching silicon mode. The groove 21 is formed through an etching process, so that the forming precision is high, and the surface quality of the groove 21 is good. In other embodiments, the groove 21 may also be formed by laser ablation, so that the groove 21 is directly formed on the cover wafer 2, which is more efficient and convenient to process. Optionally, in this embodiment, the depth of the groove 21 is 5 μm to 100 μm, the size of the cross section of the groove 21 is not smaller than the size of the functional region 12, and after the cover wafer 2 is bonded to the substrate 11, the center of the groove 21 coincides with the projection of the center of the functional region 12 on the substrate 11, so as to ensure that the functional region 12 is centrally disposed in the space formed by the groove 21.

In order to make the package structure finally obtained thinner and lighter as a whole, as shown in fig. 6, after the cover wafer 2 is bonded to the substrate 11, that is, before the blind holes 41 are opened to the mating body 4, the cover wafer 2 is thinned to 10 μm to 500 μm. That is, before the cover wafer 2 is bonded to the substrate 11, the cover wafer 2 exists in a thick state, so that operations such as glue printing, grabbing and aligning are facilitated, damage to the cover wafer 2 is avoided, after the cover wafer 2 is bonded to the substrate 11, the cover wafer 2 is supported by the substrate 11, and then the cover wafer 2 is thinned, so that damage to the cover wafer 2 in a packaging process is not easily caused, and a thin packaging structure is obtained. Specifically, in the present embodiment, the thinning process of the cover wafer 2 is performed by grinding, and finally the cover wafer 2 is ground to a thickness of 50 μm.

After the cover wafer 2 is polished, the matching body 4 is provided with the blind hole 41, as shown in fig. 7 and 8, for some filter wafers 1, the bonding pad 13 includes a conductive layer 132, the upper and lower sides of the conductive layer 132 are respectively provided with passivation layers 131, and the passivation layers 131 cannot be electrically connected. Preferably, blind via 41 is formed by a laser drilling process, blind via 41 penetrating through bonding pad 13 to expose conductive layer 132 of bonding pad 13. Laser drilling is to irradiate the processed material with a high-density laser beam to rapidly heat the material to a vaporization temperature to form a cavity, so that laser drilling can be realized for different materials, namely, the laser beam can sequentially penetrate the cover wafer 2, the glue layer 3 and the bonding pad 13, thereby smoothly ensuring that the conductive layer 132 of the bonding pad 13 is exposed and preparing for electrically connecting the bonding pad 13 with the micro-bump 5.

Preferably, after the blind via 41 is punched, the conductive layer 132 needs to be electrically connected to the micro bump 5, as shown in fig. 9 and 10, the metal layer 7 is sputtered onto the mating body 4 by physical vapor deposition, the metal layer 7 covers the surface of the wafer 2 away from the substrate 11 and the inner surface of the blind via 41, the Cu connector 8 is filled with the blind via 41 sputtered with the metal layer 7 by electroplating, and the micro bump 5 is electrically connected to the Cu connector 8. If the Cu connector 8 is directly plated in the blind via 41, the passivation layer 131 and the plated Cu material are not the same, and the Cu connector 8 cannot grow on the passivation layer 131, so the blind via 41 is difficult to fill, and finally the connection between the Cu connector 8 and the conductive layer 132 is weak, resulting in poor reliability of the electrical connection between the micro bump 5 and the pad 13. In the embodiment, by means of physical vapor deposition (bombarding the target material with high-energy particles under a vacuum condition, so that target material atoms escape and are finally deposited on the surface of the to-be-deposited part), the inner surface of the blind hole 41, that is, the whole cut surface of the pad 13, can be uniformly covered with the metal layer 7, so that when the Cu connector 8 is electroplated, the Cu connector 8 can be ensured to fully fill the blind hole 41, and further, the electrical connection between the micro-bump 5 and the pad 13 is reliable. In this embodiment, the thickness of the metal layer 7 is 2 μm, and in other embodiments, the thickness of the metal layer 7 is set reasonably according to the bottom size of the blind hole 41 and other factors. Further, in the process of electroplating the Cu in the blind holes 41, the pulse electroplating equipment is matched with additives such as leveling agent, accelerator and inhibitor, and the Cu connector 8 is ensured to be filled in the blind holes 41.

The micro bump 5 is usually made of tin material, and is connected by a welding process, the metal layer 7, the Cu connector 8 and the micro bump 5 are made of different materials, the direct welding difficulty is very high, in order to ensure the firm connection between the micro bump 5 and the metal layer 7 and/or the Cu connector 8, as shown in fig. 11 and 12, the region on the upper side of the cover wafer 2 within the preset size range of the blind hole 41 is a preset region, after the Cu connector 8 fills the blind hole 41, the part of the metal layer 7 on the cover wafer 2 except the preset region is removed, only the reserved region 71 is reserved, the under-ball metal layer 9 is plated on the reserved region 71 by adopting a chemical plating mode, and the under-ball metal layer 9 is electrically connected with the micro bump 5. By means of the metal layer 9 under the ball, on the basis of ensuring that the conductive layer 132 can be electrically connected with the micro-bump 5, the connection firmness of the micro-bump 5 and the reserved area 71 can also be realized. Specifically, in this embodiment, the metal layer 9 under the ball includes two layers, which are a Ni plating layer and an Au plating layer in sequence, and the Ni plating layer and the Au plating layer can be uniformly distributed on the reserved area 71 by chemical plating, and when the micro-bump 5 is welded, the Ni plating layer and the Au plating layer can diffuse and permeate to the micro-bump 5 and the reserved area 71 respectively at the welding temperature, so as to finally ensure the connection firmness of the micro-bump 5. In this embodiment, the thickness of the Ni plating layer and the Au plating layer are both 3 μm, and the cost is controlled as much as possible while securing the connection firmness.

Further, as shown in fig. 13, after the under-ball metal layer 9 is plated, the micro bump 5 is soldered on the under-ball metal layer 9, so as to electrically connect the micro bump 5 and the solder pad 13. Alternatively, the micro-bump 5 may be formed by directly using a finished solder ball, or by printing a solder paste on the reserved area 71 and then forming the micro-bump 5 from the solder paste by a high-temperature reflow method. The specific process of making the ball by printing solder paste is prior art and will not be described herein.

Preferably, as shown in fig. 14 and 15, after the micro-bump 5 is electrically connected to the conductive layer 132, the substrate 11 is thinned to 20 μm to 300 μm. Since the cover wafer 2 and the substrate 11 are made of silicon materials and can support each other, the substrate 11 is further thinned, the strength requirement of the package structure can still be met, and the thickness of the whole package structure is greatly reduced. In this embodiment, the substrate 11 is also thinned by polishing. Specifically, as shown in fig. 14, before thinning the substrate 11, a polishing tape 6 is adhered to the cover wafer 2, the micro bumps 5 are covered with the polishing tape 6, and after thinning the substrate 11, the polishing tape 6 is torn off. The micro-bump welding points 5 are protected by the grinding adhesive tape 6, and damage caused in the grinding process is avoided.

In general, when the filter wafer 1 is shipped, a plurality of functional regions 12 are disposed on the substrate 11, each functional region 12 is correspondingly provided with a specific number of pads 13, one functional region 12 and the corresponding pad 13 form a unit, a plurality of the units are distributed on the substrate 11 in a matrix manner, and as shown in fig. 15, after the substrate 11 is thinned, the unit is cut to obtain an independent filter wafer level package structure. Before dicing, a dicing film (not shown) is preferably attached to the substrate 11, and dicing is performed according to dicing streets on the dicing film. Alternatively, the cutting process may employ metal blade cutting or laser cutting, and is not particularly limited herein.

In summary, as shown in fig. 16, the wafer level packaging process of the filter of the present embodiment includes:

forming a groove 21 on one side of the silicon wafer by an etching process to form a cover wafer 2;

the side, provided with the groove 21, of the cover wafer 2 is bonded to the upper side of the substrate 11 through the glue layer 3 to form a matching body 4, and the functional area 12 is accommodated in a space formed by the substrate 11 and the groove 21;

grinding and thinning the cover wafer 2 to 10-500 μm;

forming a blind hole 41 in the matching body 4 from one side of the cover wafer 2 by a laser drilling process so as to expose the conductive layer 132 of the bonding pad 13;

sputtering a metal layer 7 on the matching body 4 by a physical vapor deposition mode, wherein the metal layer 7 covers the surface of the covering wafer 2 far away from the substrate 11 and the inner surface of the blind hole 41;

filling the blind hole 41 sputtered with the metal layer 7 with the Cu connector 8 through an electroplating process;

removing the part of the metal layer 7 on the cover wafer 2 except the preset area, and only reserving the reserved area 71;

plating an under-ball metal layer 9 on the reserved area 71 by adopting a chemical plating mode;

welding the micro-bump welding point 5 on the metal layer 9 under the ball;

a grinding adhesive tape 6 is adhered on the cover wafer 2, and the micro-bump welding points 5 are coated by the grinding adhesive tape 6;

grinding and thinning the substrate 11 to 20-300 μm;

tearing off the grinding adhesive tape 6;

and attaching a cutting film on the substrate 11, and cutting according to the cutting lines on the cutting film to obtain an independent filter wafer-level packaging structure.

The embodiment also provides a filter packaging structure, and by adopting the filter wafer-level packaging process, the production process is simpler and more convenient, and the whole structure is thinner and has a good packaging effect.

It should be understood that the above-described embodiments of the present invention are merely examples for clearly illustrating the invention and are not to be construed as limitations of the embodiments of the present invention, but may be modified in various embodiments and applications by those skilled in the art according to the spirit of the present invention, and the content of the present description should not be construed as a limitation of the present invention. Any modification, equivalent replacement, and improvement made within the spirit and principle of the present invention should be included in the protection scope of the claims of the present invention.