阅读说明：本技术 基于阻变电阻的非易失抗辐射存储单元 (Nonvolatile anti-radiation memory cell based on resistance change resistor ) 是由 杨东 陈思为 于 2020-12-16 设计创作，主要内容包括：本发明涉及基于阻变电阻的非易失抗辐射存储单元,本设计由9个晶体管和4个阻变电阻组成。该存储单元可将阻变电阻的阻值高低转换为电平的高低,具有多次编程、信息加载速度快等特点,并且具有抗单粒子翻转(SEU)的抗辐照性能。可应用于非易失存储器件、可编程逻辑器件的配置信息存储等。可用较小的面积实现高性能且具备抗单粒子翻转的抗辐照非易失存储单元。利用阻变电阻,上电时可把信息从存储电阻快速读入存储单元。本设计基于阻变电阻的电学特性实现。由9个晶体管和4个阻变存储电阻组成的存储单元。(The invention relates to a nonvolatile anti-radiation memory unit based on a resistance change resistor, which consists of 9 transistors and 4 resistance change resistors. The storage unit can convert the resistance value of the resistance change resistor into the level value, has the characteristics of multiple programming, high information loading speed and the like, and has the radiation resistance of Single Event Upset (SEU). The method can be applied to the storage of configuration information of nonvolatile memory devices and programmable logic devices. The irradiation-resistant nonvolatile memory cell with high performance and single event upset resistance can be realized by using a small area. By using the resistance change resistor, information can be quickly read into the memory cell from the memory resistor when the memory cell is powered on. The design is realized based on the electrical characteristics of the resistance change resistor. The memory cell comprises 9 transistors and 4 resistance change memory resistors.)

1. The nonvolatile anti-radiation memory cell based on the resistance change resistor is characterized by comprising transistors N0-N6, transistors P1-P2, a resistor R1 and a resistor R2;

the drain of the transistor N5 is connected with the bit line BL through a resistor R1 and is used for accessing a resistor conversion control level signal; the drain electrode of the N5 is also connected with the drain electrode of the transistor N3, and the grid electrode of the N5 is connected with a word line WLL which is used for accessing a gating control signal; the source of the N5 is connected with the source of the N6, is used as a source line position SL and is used for accessing a resistance conversion control level signal;

the grid of the transistor N3 is connected with a READ line READ and used for accessing a READ signal; the source of N3 is connected with the drain of P2 and the source of N2; the source electrode of the P2 is connected with the source electrode of the P1 and is connected with the power supply as a power supply wire PWR; the gate of the P2 is connected with the gate of the N2, the drain of the P1 and the source of the N1; the gate of the P1 is connected with the gate of the N1; the drain of N1 and the drain of N2 are grounded; the source of N1 and the source of N2 are respectively connected with the drain of N0 and the source of N0, and the gate of N0 is connected with a READ line READ; a resistor R3 is connected between the drain of the transistor P2 and the gate of the transistor P1; a resistor R4 is connected between the gate of the transistor P2 and the drain of the transistor P1;

the grid of the N6 is connected with a word line WLR which is used for accessing a gating control signal; the drain of N6 is connected to BL through resistor R2, the drain of N6 is connected to the drain of N4, the source of N4 is connected to the drain of P1, and the gate of N4 is connected to READ line READ.

2. The resistance-change resistance-based nonvolatile radiation-resistant memory cell according to claim 1, wherein R1 and N5 constitute a first 1T1R cell, and R2 and N6 constitute a second 1T1R cell; p1, P2, N1, N2, N3, N4, and R3 and R4 constitute radiation-resistant SRAM cells.

3. The nonvolatile anti-radiation storage method based on the resistance change resistor is characterized by comprising the following steps of:

when the load signal Read is at low level, the opposite value of the stored information is directly written into the resistors R1 and R2 through the peripheral circuit; the memory cell is loaded with memory information represented by the resistance value each time the memory cell is powered up.

4. The nonvolatile radiation-resistant storage method based on the resistance change resistor as claimed in claim 3, characterized by comprising the following steps:

step1, information write resistances R1 and R2: the signal Read is low, WLL is firstly effective, excitation is applied to BL and SL to carry out write operation on a resistor R1, then WLR is effective, excitation is applied to BL and SL to carry out complementary write operation on a resistor R2, and finally the resistance values of R1 and R2 are in a relative high-resistance state, and the other resistance value is in a low-resistance state;

step2, loading the configuration information stored in R1 and R2 into the radiation-resistant SRAM cell: when the storage unit is powered on, BL is connected with low level, both WLL and WLR are invalid, and the Read signal is temporarily high level, so that a node Q, P1 between the drain of P2 and the source of N2 in the SRAM unit and a node QB between the drain of N1 are all pulled to be within the metastable point floating threshold range; the node close to the low level of Q and QB is finally low, and the other node is finally high, so that the configuration information loading and storing unit starts to work normally.

5. The nonvolatile radiation-resistant storage method based on the resistance change resistor as claimed in claim 4, further comprising Step3, when the storage unit is powered up after being powered down, only information needs to be loaded into the SRAM unit from two complementary 1T1R structures in the storage unit, so that the storage unit can work normally.

Technical Field

The invention belongs to the field of integrated circuit design. And more particularly to a nonvolatile radiation-resistant memory cell design based on a resistive switching device.

Background

Semiconductor memories are one of the most basic components of electronic devices and are an important component of modern information technology. With the rapid development of over forty years, nonvolatile memories typified by flash have experienced rapid development. In the face of the technical bottleneck that will appear in the future, how nonvolatile memories should continue to be developed is a problem that designers should carefully think about. In recent years, resistance change resistors, which are emerging devices, have shown great potential. Besides the advantages of low power consumption, high density, high speed and the like, the resistance change resistor stores information by using the characteristic of resistance change, and the problem that other types of memories are easily influenced by irradiation is solved. In addition, the resistance change resistor does not need to introduce the technology beyond the traditional CMOS technology, and has good compatibility with the traditional CMOS technology. This means that the development and achievement conversion period can be greatly shortened without adding extra equipment and cost in development and production. Has strong technical expansion capability and wide development prospect.

Disclosure of Invention

The invention aims to provide a nonvolatile anti-radiation storage unit which supports multiple times of programming, has no information loss after power failure and has the capability of resisting single event upset.

The technical scheme adopted by the invention for realizing the purpose is as follows: the nonvolatile anti-radiation memory cell based on the resistance change resistor comprises transistors N0-N6, transistors P1-P2, a resistor R1 and a resistor R2;

the drain of the transistor N5 is connected with the bit line BL through a resistor R1 and is used for accessing a resistor conversion control level signal; the drain electrode of the N5 is also connected with the drain electrode of the transistor N3, and the grid electrode of the N5 is connected with a word line WLL which is used for accessing a gating control signal; the source of the N5 is connected with the source of the N6, is used as a source line position SL and is used for accessing a resistance conversion control level signal;

the grid of the transistor N3 is connected with a READ line READ and used for accessing a READ signal; the source of N3 is connected with the drain of P2 and the source of N2; the source electrode of the P2 is connected with the source electrode of the P1 and is connected with the power supply as a power supply wire PWR; the gate of the P2 is connected with the gate of the N2, the drain of the P1 and the source of the N1; the gate of the P1 is connected with the gate of the N1; the drain of N1 and the drain of N2 are grounded; the source of N1 and the source of N2 are respectively connected with the drain of N0 and the source of N0, and the gate of N0 is connected with a READ line READ; a resistor R3 is connected between the drain of the transistor P2 and the gate of the transistor P1; a resistor R4 is connected between the gate of the transistor P2 and the drain of the transistor P1;

the grid of the N6 is connected with a word line WLR which is used for accessing a gating control signal; the drain of N6 is connected to BL through resistor R2, the drain of N6 is connected to the drain of N4, the source of N4 is connected to the drain of P1, and the gate of N4 is connected to READ line READ.

R1 and N5 constitute a first 1T1R unit, R2 and N6 constitute a second 1T1R unit; p1, P2, N1, N2, N3, N4, and R3 and R4 constitute radiation-resistant SRAM cells.

The nonvolatile anti-radiation storage method based on the resistance change resistor comprises the following steps:

when the load signal Read is at low level, the opposite value of the stored information is directly written into the resistors R1 and R2 through the peripheral circuit; the memory cell is loaded with memory information represented by the resistance value each time the memory cell is powered up.

Step1, information write resistances R1 and R2: the signal Read is low, WLL is firstly effective, excitation is applied to BL and SL to carry out write operation on a resistor R1, then WLR is effective, excitation is applied to BL and SL to carry out complementary write operation on a resistor R2, and finally the resistance values of R1 and R2 are in a relative high-resistance state, and the other resistance value is in a low-resistance state;

step2, loading the configuration information stored in R1 and R2 into the radiation-resistant SRAM cell: when the storage unit is powered on, BL is connected with low level, both WLL and WLR are invalid, and the Read signal is temporarily high level, so that a node Q, P1 between the drain of P2 and the source of N2 in the SRAM unit and a node QB between the drain of N1 are all pulled to be within the metastable point floating threshold range; the node close to the low level of Q and QB is finally low, and the other node is finally high, so that the configuration information loading and storing unit starts to work normally.

Step3, when the memory cell is powered on after power off, only information needs to be loaded into the SRAM cell from two complementary 1T1R structures in the memory cell, so that the memory cell can work normally.

The invention has the following beneficial effects and advantages:

the storage unit can convert the resistance value of the resistance change resistor into the level value, has the characteristics of multiple programming, high information loading speed and the like, and has the radiation resistance of Single Event Upset (SEU). The method can be applied to the storage of configuration information of nonvolatile memory devices and programmable logic devices.

Drawings

FIG. 1, a schematic circuit diagram;

FIG. 2 is a flow chart of the operation of the memory cell.

Detailed Description

The present invention will be described in further detail with reference to the accompanying drawings and examples.

The invention designs a high-performance and radiation-resistant memory cell design which comprises 9 transistors and 4 resistance change resistors (9T 4R). Under the condition of realizing high speed and low power consumption of the memory cell, the anti-irradiation design is added, so that the memory cell has the capability of resisting single event upset. And finishing the design of the memory cell circuit schematic diagram. The design can be used in memory devices and can also be applied to replace SRAM in other types of circuits. The irradiation-resistant nonvolatile memory cell with high performance and single event upset resistance can be realized by using a small area. By using the resistance change memory resistor, the configuration information can be quickly read into the memory cell from the memory resistor when the memory cell is powered on. The design is realized by the electrical characteristics of the resistance change resistor.

1. Non-volatile memory cell designs.

The 9T4R memory cell is composed of 9 transistors and 4 resistive memory resistors. Wherein, it comprises a six-tube SRAM unit with resistors R3, R4, a voltage-equalizing tube N0 and two 1T1R structures (R1, N5, R2, N6) to form basic functions. The source end and the drain end of the voltage-equalizing pipe N0 are respectively connected with the storage nodes Q and QB in the SRAM unit.

In designing a six-transistor SRAM cell, in order to ensure the correctness and stability of the read operation and the write operation, it is necessary to consider the rationality of designing the width-to-length ratio of the driving transistor and the transfer transistor.

Nodes between gate tubes (N5, N6) and storage resistors (R1, R2) of two 1T1R units are respectively connected to original bit lines and complementary bit lines (points A and B) of the SRAM units, source ends of the gate tubes (N5, N6) of two resistance change units (namely the storage resistors R1 and R2) are connected together to SL (source line), the other ends of the two resistance change storage resistors are connected together to a bit line BL, and the gate tubes of the two resistance change units are respectively controlled by a word line WLL and a word line WLR.

Two access transistors, N3 and N4, are used to implement the function of the storage node. Applying proper excitation to BL and SL to write the resistors R1 and R2, so that the resistances of R1 and R2 are in a high resistance state and the other resistance state, and completing the writing of information; the configuration information is then quickly read into the SRAM cells from the storage resistors R1 and R2 at power up.

The reverse value of the 9T4R cell information is stored in complementary form in the storage resistors R1 and R2 after power down, and then quickly read information from the storage resistors R1 and R2 into the SRAM cell again at power up, with the time required for loading being hundreds of picoseconds. Therefore, the device adopting the 9T4R storage unit has high safety and can be quickly powered on and started. The 9T4R memory cells are very symmetric in structure and thus are not prone to errors when loading information.

2. And (5) designing radiation resistance.

In order to improve the performance of the memory cell for resisting a Single Event Upset (SEU) effect, resistance change resistors R3 and R4 are added into the 9T4R memory cell, the two resistors adopt an initial state before forming, and the resistance value is set to be 1M omega. When a single particle is incident on the 9T4R storage unit, and the storage node is lowered or raised, there are two competing processes: one is recovery process and one is feedback process. By adding the resistance change resistors R3 and R4, the time required by the recovery process is less than the time required by the feedback process, so that the incidence of charged particles cannot cause single-particle upset.

The operation flow and the working sequence are as follows:

when the load signal Read is at a low level, the 1T1R cells and the SRAM cells on two sides of the 9T4R memory cell are isolated by two gate tubes N3 and N4 of the SRAM, the opposite values of the stored information can be directly written into the resistive memory resistors R1 and R2 through the peripheral circuit, and then the SRAM is only responsible for loading the stored information represented by the resistance value into the memory cell to play a role each time the memory cell is powered on. Therefore, the operation flow of the 9T4R structure is relatively simple, as shown in fig. 1 and 2, specifically as follows:

step 1-information is written R1 and R2. Read is low to isolate the SRAM cell from its 1T1R cells on either side, WLL is active first, appropriate stimuli are applied to BL and SL to write to storage resistor R1, WLR is active then appropriate stimuli are applied to BL and SL to write to storage resistor R2 in a complementary fashion, and finally the resistances of R1 and R2 are one in a high resistance state and the other in a low resistance state.

Step 2-load the configuration information stored in R1 and R2 into SRAM. When the storage unit is electrified, BL is connected with low level, WLL and WLR are both invalid, Read signal is high level for a short time (the effective pulse width is about 100-200ps), so that internal nodes Q and QB of SRAM are pulled to be close to a metastable point, but R1 and R2 have different resistance values, one storage node connected with low resistance in Q and QB is pulled to be close to low level, and the other storage node is pulled to be close to high level; then Read is low, and the node of Q and QB near low is finally low and the other node is finally high due to the positive feedback mechanism existing inside the SRAM cell. Since the level of 9T4R is read from the adjacent complementary resistive random access cells each time the memory cell is powered on, the loading speed of the configuration information is very fast, and can reach 100ps level. After the information is loaded successfully, the storage unit starts to work normally.

Step 3-when the memory cell is powered down and then powered up, the configuration information is loaded into the SRAM cell from two complementary 1T1R cells in the 9T4R memory cell, and then the memory cell can continue to operate normally.

The 9T4R memory cell supports unipolar and bipolar write operation mechanisms of the resistive switching cell. The device of the 9T4R memory cell has high safety and can be quickly powered on and started. The 9T4R unit has symmetrical structure, and can not be programmed by mistake in the working process, thereby ensuring the correct storage information.