阅读说明：本技术 单粒子自检测电路和方法 (Single-particle self-detection circuit and method ) 是由 蔡洁明 顾林 邹家轩 张国贤 于 2020-12-28 设计创作，主要内容包括：本申请公开了一种单粒子自检测电路和方法,涉及单粒子自检测技术领域,所述电路包括：自检测使能管脚、自检测控制逻辑和自检测状态寄存器；所述自检测使能管脚用于使能所述自检测控制逻辑进行自检测；所述自检测控制逻辑在执行自检测之后将检测结果存储在所述自检测状态寄存器中。解决了现有技术中的自检测方式会消耗大量CPU时间降低系统性能的问题,达到了可以通过增加自检测使能管脚、自检测控制逻辑和自检测状态寄存器即可简单实现自检测,进而减少所需消耗的CPU资源提高系统性能的效果。(The application discloses single particle self-detection circuit and method relates to single particle self-detection technical field, the circuit includes: the self-detection control system comprises a self-detection enabling pin, a self-detection control logic and a self-detection state register; the self-detection enabling pin is used for enabling the self-detection control logic to perform self-detection; the self-test control logic stores a test result in the self-test status register after performing a self-test. The problem that the self-detection mode in the prior art can consume a large amount of CPU time to reduce the system performance is solved, the self-detection can be simply realized by adding a self-detection enabling pin, a self-detection control logic and a self-detection state register, and the effects that the CPU resource required to be consumed is reduced and the system performance is improved are achieved.)

1. A single-particle self-detection circuit, the circuit comprising: the self-detection control system comprises a self-detection enabling pin, a self-detection control logic and a self-detection state register;

the self-detection enabling pin is used for enabling the self-detection control logic to perform self-detection;

the self-test control logic stores a test result in the self-test status register after performing a self-test.

2. The circuit of claim 1, wherein the self-test enable pin comprises: and at least one of a first enabling pin and a second enabling pin, wherein the first enabling pin is used for enabling the register single event detection, and the second enabling pin is used for enabling the NC and NT function detection.

3. The circuit of claim 2, wherein when the self-test enable pin comprises a first enable pin, the circuit further comprises a self-test data register in which an initial value of each register is stored;

the self-detection control logic performs self-detection according to the current value of each register and the initial value stored in the self-detection data register.

4. The circuit of claim 3,

and triggering and starting register single-particle detection when the first enabling pin is at a low level, and triggering and stopping detection when the first enabling pin is at a high level.

5. The circuit of claim 2, wherein when the self-test enable pin comprises a second enable pin, the test to start NC and NT is triggered when the second enable pin is low, and the test to stop is triggered when the second enable pin is high.

6. A single-particle self-detection method used in the single-particle self-detection circuit according to any one of claims 1 to 5, the method comprising:

receiving an enabling signal input by the self-detection enabling pin;

after receiving the enabling signal, carrying out self-detection according to the self-detection control logic;

and storing the detection result to the self-detection state register.

7. The method of claim 6, wherein the self-test enable pin comprises: and at least one of a first enabling pin and a second enabling pin, wherein the first enabling pin is used for enabling the register single event detection, and the second enabling pin is used for enabling the NC and NT function detection.

8. The method of claim 7, wherein when the self-test enable pin comprises the first enable pin, the self-testing according to the self-test control logic after receiving the enable signal comprises:

after receiving an enable signal of the first enable pin, acquiring initial values of registers stored in a self-detection data register, wherein the initial values of the registers are stored in the self-detection data register;

and carrying out overturn detection according to the current value of each register and the obtained initial value.

9. The method of claim 8, wherein the enable signal is low, and wherein the detecting is stopped when the signal on the first enable pin is high.

10. The method of claim 7, wherein when the self-test enable pin comprises the second enable pin, the self-testing according to the self-test control logic after receiving the enable signal comprises:

after receiving the enabling signal, detecting a communication state in the data transmitting and receiving process, wherein the communication state comprises at least one of a command frame, an encoding format of a data frame and a status frame, a check bit, a data number, a frame interval time and a response time.

Technical Field

The invention relates to a single-particle self-detection circuit and a single-particle self-detection method, and belongs to the technical field of single-particle self-detection.

Background

With the rapid development of computer technology and data communication technology, the aerospace electronic system needs to further realize the integration of signal and data processing and sensors, and the requirements on the speed and bandwidth of a bus network are higher and higher. The traditional MIL-STD-1553B can not meet the development requirement of the modern aerospace electronic system. Fibre channel enables high capacity, high rate information transmission including data, video, audio signals, providing a practical, inexpensive and extensible data exchange standard for network storage devices and data transfer devices. The outstanding advantages of the optical fiber channel in the aspects of transmission rate, transmission bandwidth, reliability and the like meet the development requirements of aerospace electronic systems, and therefore FC-AE-1553 is produced. The bus not only has the basic characteristics of the MIL-STD-1553B traditional bus, but also has good high-speed network performance of a fiber channel. In addition, FC-AE-1553 also can bridge the traditional MIL-STD-1553B network. Therefore, FC-AE-1553 is well reserved and inherited by the traditional MIL-STD-1553B.

With the large-scale application of FC-AE-1553 in military equipment, the radiation-resistant reinforced FC-AE-1553 protocol chip is gradually applied to radiation environments of satellites, space stations and the like. When the digital integrated circuit is exposed to a space radiation environment, high-energy particles are incident into the semiconductor device and undergo a series of reactions with materials therein, such as ionization, excitation, collision, etc., which in turn cause a series of chain reactions, affect the operation of the semiconductor device, and even damage the semiconductor. The most common of these is Single Event Effect (SEE), which mainly refers to device failure caused by the incidence of a single energetic charged particle on a sensitive area of an electronic device. SEE may cause the stored data to flip, system malfunction, or even system damage.

A space electronic system is a complex system comprising a number of sub-units, typically including a main processor unit, an electromechanical control unit, a power management unit, an interface processing unit, etc. When the system which normally works originally suddenly has an abnormality, a whole system reinitialization measure is generally not adopted, but whether the system is caused by a SEE event occurring in a certain device in the system is judged firstly, so that a system recovery measure which influences the minimization is adopted. In order to effectively judge whether an SEE event occurs in an FC-AE-1553 protocol chip in space equipment in time, a corresponding detection measure needs to be added in a system. The traditional detection scheme is that a main processor detects corresponding registers, memories and functions after a system fails, but due to the complex function of an FC-AE-1553 protocol chip, the detection mode consumes a large amount of CPU time, and further affects the realization of other normal functions of the system.

Disclosure of Invention

The invention aims to provide a single-particle self-detection circuit and a single-particle self-detection method, which are used for solving the problems in the prior art.

In order to achieve the purpose, the invention provides the following technical scheme:

according to a first aspect, an embodiment of the present invention provides a single-particle self-detection circuit, including: the self-detection control system comprises a self-detection enabling pin, a self-detection control logic and a self-detection state register;

the self-detection enabling pin is used for enabling the self-detection control logic to perform self-detection;

the self-test control logic stores a test result in the self-test status register after performing a self-test.

Optionally, the self-detection enable pin includes: and at least one of a first enabling pin and a second enabling pin, wherein the first enabling pin is used for enabling the register single event detection, and the second enabling pin is used for enabling the NC and NT function detection.

Optionally, when the self-detection enable pin includes the first enable pin, the circuit further includes a self-detection data register, and an initial value of each register is stored in the self-detection data register;

the self-detection control logic performs self-detection according to the current value of each register and the initial value stored in the self-detection data register.

Optionally, the single-event detection of the start register is triggered when the first enable pin is at a low level, and the stop detection is triggered when the first enable pin is at a high level.

Optionally, when the self-detection enable pin includes a second enable pin, the detection of starting NC and NT is triggered when the second enable pin is at a low level, and the detection of stopping is triggered when the second enable pin is at a high level.

In a second aspect, there is provided a single-particle self-detection method, which is used in the single-particle self-detection circuit of the first aspect, and the method includes:

receiving an enabling signal input by the self-detection enabling pin;

after receiving the enabling signal, carrying out self-detection according to the self-detection control logic;

and storing the detection result to the self-detection state register.

Optionally, the self-detection enable pin includes: and at least one of a first enabling pin and a second enabling pin, wherein the first enabling pin is used for enabling the register single event detection, and the second enabling pin is used for enabling the NC and NT function detection.

Optionally, when the self-test enable pin includes the first enable pin, after receiving the enable signal, performing self-test according to the self-test control logic, including:

after receiving an enable signal of the first enable pin, acquiring initial values of registers stored in a self-detection data register, wherein the initial values of the registers are stored in the self-detection data register;

and carrying out overturn detection according to the current value of each register and the obtained initial value.

Optionally, the enable signal is at a low level, and the detection is stopped when the signal of the first enable pin is at a high level.

Optionally, when the self-test enable pin includes the second enable pin, after receiving the enable signal, performing self-test according to the self-test control logic, including:

after receiving the enabling signal, detecting a communication state in the data transmitting and receiving process, wherein the communication state comprises at least one of a command frame, an encoding format of a data frame and a status frame, a check bit, a data number, a frame interval time and a response time.

By providing a single-particle self-detection circuit, the circuit comprising: the self-detection control system comprises a self-detection enabling pin, a self-detection control logic and a self-detection state register; the self-detection enabling pin is used for enabling the self-detection control logic to perform self-detection; the self-test control logic stores a test result in the self-test status register after performing a self-test. The problem that the self-detection mode in the prior art can consume a large amount of CPU time to reduce the system performance is solved, the self-detection can be simply realized by adding a self-detection enabling pin, a self-detection control logic and a self-detection state register, and the effects that the CPU resource required to be consumed is reduced and the system performance is improved are achieved.

The foregoing description is only an overview of the technical solutions of the present invention, and in order to make the technical solutions of the present invention more clearly understood and to implement them in accordance with the contents of the description, the following detailed description is given with reference to the preferred embodiments of the present invention and the accompanying drawings.

Drawings

Fig. 1 is a circuit schematic diagram of a single-event self-detection circuit according to an embodiment of the present invention;

fig. 2 is a circuit schematic diagram of a single-event self-detection circuit according to an embodiment of the present invention;

fig. 3 is a schematic flow chart of the single-event self-detection circuit for detecting self-inversion according to an embodiment of the present invention;

FIG. 4 is a schematic flow chart of the single-particle self-detection circuit for detecting the NC/NT function according to an embodiment of the present invention;

fig. 5 is a flowchart of a method for single particle self-detection according to an embodiment of the present invention.

Detailed Description

The technical solutions of the present invention will be described clearly and completely with reference to the accompanying drawings, and it should be understood that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, but do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.

In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.

In addition, the technical features involved in the different embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.

Referring to fig. 1, a schematic structural diagram of a single-particle self-detection circuit according to an embodiment of the present application is shown, as shown in fig. 1, the circuit includes: a self-test enable pin 11, a self-test control logic 12 and a self-test status register 13;

the self-detection enabling pin is used for enabling the self-detection control logic to perform self-detection;

the self-test control logic stores a test result in the self-test status register after performing a self-test.

The above description is only given in the sense that the self-test circuit can be applied to a variety of possible chips, the present application is illustrated as applied to an FC-AE-1553 chip, and the above is only illustrated by the fact that the self-test circuit includes the above devices, in practical implementation, other general-purpose devices may also be included, for example, referring to fig. 2, the self-test circuit may further include a CPU main processor, host interface logic, an FC protocol state machine (including an NC state machine, an NT state machine, an NM state machine, etc.), an FC register group (including a control register, an interrupt register, a test register, etc., and in general, the FC register group may include 32 sets of registers), and an FC-AE-1553 protocol map, of course, in actual implementation, other more or fewer components may be included, which is not limited by this embodiment, and the present application mainly protects the portion shown by the dashed line in fig. 2.

The self-test enable pin includes: and at least one of a first enable pin and a second enable pin, wherein the first enable pin is used for enabling register single event detection (SEE detection), and the second enable pin is used for enabling NC and NT function detection. Taking the example that the self-test enable pin includes the first enable pin and the second enable pin, referring to fig. 2, the first enable pin may be a start _ reg _ test, and the second enable pin may be a start _ func _ test.

Optionally, when the self-detection enable pin includes the first enable pin, the circuit further includes a self-detection data register, and an initial value of each register is stored in the self-detection data register;

the self-detection control logic performs self-detection according to the current value of each register and the initial value stored in the self-detection data register.

And triggering and starting register single-particle detection when the first enabling pin is at a low level, and triggering and stopping detection when the first enabling pin is at a high level.

For example, referring to fig. 2, the chip pin start _ reg _ test is used for SEE detection of the control register, and low level is start detection and high level is stop detection. When start _ reg _ test is set to "0", the circuit enables register roll-over self-test. The register inversion self-detection mainly completes the comparison between the internal register of the FC-AE-1553 protocol chip and the initialized state value, when one or more bits are different from the initial value, the register inversion occurs, the self-detection does not pass, and the current register address can be marked in a register inversion detection result register of 0x 41H. The functional block diagram of register roll-over self-test is shown in FIG. 3. The initial value of the register is initialized and configured in the self-test data register when the circuit is powered on, for example, if there are 32 groups of registers, the initial value is configured in the 32-bit self-test data register of 0x 20H-0 x3FH when the circuit is powered on. Referring to table 1, one possible configuration is shown.

Table 1 the register flip detect result, i.e., the self-test status register (41H) is defined as table 2.

TABLE 2

When the self-detection enabling pin comprises a second enabling pin, the detection of starting NC and NT is triggered when the second enabling pin is in low level, and the detection is triggered to stop when the second enabling pin is in high level.

For example, referring to fig. 2, the pin start _ func _ test is used to control the communication detection in NC and NT modes, the low level is start detection, and the high level is stop detection.

Specifically, when start _ func _ test is set to "0", the circuit initiates NC/NT communication self-detection. The NC/NT communication self-detection mainly completes the communication state detection when the FC-AE-1553 protocol chip data is sent and received, and the communication state comprises at least one of the coding formats of a command frame, a data frame and a status frame, check bits, the number of data, frame interval time and response time. In practical implementation, please refer to fig. 4, the detection of the message transmission status, the command frame and the data frame in the communication process can be completed through the self-detection control logic and the NM function of the chip itself. When one or more conditions which do not conform to the FC-AE-1553 protocol appear, the functional abnormity occurs and the self-detection is not passed. The current exception type is marked in the NC/NT function test result register at address 0x 42H. The register definition of the NC/NT function test result, i.e., the self-test result, is shown in Table 3.

Bit	Description of the invention	Bit	Description of the invention
				31(MSB)	Sending command word errors	15	Retention
30	Sending data word errors	14	·
				29	Receiving command word errors	13	·
28	Received data word error	12	·
				27	Non-response	11	·
26	Time-out response	10	·
				25	Retention	9	·
24	·	8	Retention
				23	·	7	Error flag
22	·	6	Status word set
				21	·	5	Format error
20	·	4	Channel retry
				19	·	3	Word count error
18	·	2	Illegal frame header
				17	·	1	Error of source address
16	Retention	0(LSB)	Destination address error

TABLE 3

When the self-test enable pin includes both start _ reg _ test and start _ func _ test, each self-test result may be recorded in the self-test status register with address 4C in order to facilitate the user to know the self-test condition of the current operation in real time. The user can read the value of the status register at any time to obtain the current self-detection status and result. The definition and description of each bit in the self-test status register are described in detail in

Table 4.

TABLE 4

In summary, by providing a single-particle self-detection circuit, the circuit includes: the self-detection control system comprises a self-detection enabling pin, a self-detection control logic and a self-detection state register; the self-detection enabling pin is used for enabling the self-detection control logic to perform self-detection; the self-test control logic stores a test result in the self-test status register after performing a self-test. The problem that the self-detection mode in the prior art can consume a large amount of CPU time to reduce system performance is solved, self-detection can be simply realized by adding a self-detection enabling pin, self-detection control logic and a self-detection state register in the original circuit foundation, and further, the CPU resource required to be consumed is reduced, and the system performance is improved. Because the original circuit structure is not required to be changed, the compatibility of the logic and the existing circuit is ensured, and the cost of logic design and development is saved. Meanwhile, the self-detection can be started at any time through the added enabling pins without excessive intervention of a main CPU (Central processing Unit), so that the single-particle self-detection can be comprehensively and effectively completed on the premise of not influencing other units in the system, and the rapid positioning of faults is guaranteed. In addition, the circuit can be used by simply adjusting according to other circuit interfaces, and has good reusability.

Referring to fig. 5, it shows a flowchart of a method of the single-particle self-detection method provided in the present application, which can be applied to the single-particle self-detection circuit described above, as shown in fig. 5, the method includes:

step 501, receiving an enable signal input by the self-detection enable pin;

step 502, after receiving the enabling signal, performing self-detection according to the self-detection control logic;

step 503, storing the detection result to the self-detection status register.

Optionally, the self-detection enable pin includes: and at least one of a first enabling pin and a second enabling pin, wherein the first enabling pin is used for enabling the register single event detection, and the second enabling pin is used for enabling the NC and NT function detection.

Optionally, when the self-test enable pin includes the first enable pin, after receiving the enable signal, performing self-test according to the self-test control logic, including:

after receiving an enable signal of the first enable pin, acquiring initial values of registers stored in a self-detection data register, wherein the initial values of the registers are stored in the self-detection data register;

and carrying out overturn detection according to the current value of each register and the obtained initial value.

Optionally, the enable signal is at a low level, and the detection is stopped when the signal of the first enable pin is at a high level.

Optionally, when the self-test enable pin includes the second enable pin, after receiving the enable signal, performing self-test according to the self-test control logic, including:

after receiving the enabling signal, detecting a communication state in the data transmitting and receiving process, wherein the communication state comprises at least one of a command frame, an encoding format of a data frame and a status frame, a check bit, a data number, a frame interval time and a response time.

The above-mentioned single-particle self-detection method is similar to the detection method described in the above-mentioned embodiment, and please refer to the above-mentioned embodiment for details of the technology, which is not described herein again.

In summary, the enable signal input by receiving the self-detection enable pin; after receiving the enabling signal, carrying out self-detection according to the self-detection control logic; and storing the detection result to the self-detection state register. The problem that the self-detection mode in the prior art can consume a large amount of CPU time to reduce the system performance is solved, the self-detection can be simply realized by adding a self-detection enabling pin, a self-detection control logic and a self-detection state register, and the effects that the CPU resource required to be consumed is reduced and the system performance is improved are achieved.

The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.

The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.