阅读说明：本技术 半导体存储装置及其测试方法 (Semiconductor memory device and method of testing the same ) 是由 李钟哲 李炯尚 于 2020-12-30 设计创作，主要内容包括：本发明涉及一种半导体存储装置及其测试方法,该半导体存储装置包括：存储单元阵列,所述存储单元阵列中包括多个存储单元,所述多个存储单元被划分为多个页,每个页中的多个存储单元与同一字线相连接；页缓存阵列,通过位线与所述存储单元阵列相连接,所述页缓存阵列包括多个页缓存器组,每个所述页缓存器组中包括多级页缓存器,所述多级页缓存器中包括至少一个第一页缓存器,所述第一页缓存器中包括错误计数单元,所述错误计数单元适于累计与所述页缓存器组连接的多个目标存储单元中的错误页数量。根据该半导体存储装置,半导体芯片尺寸增加的较小,可以进行半导体芯片的自动化测试,可以减少测试时间,提高了芯片面积利用率和测试效率。(The present invention relates to a semiconductor memory device and a test method thereof, the semiconductor memory device including: the memory device comprises a memory cell array, a word line and a word line, wherein the memory cell array comprises a plurality of memory cells which are divided into a plurality of pages, and the plurality of memory cells in each page are connected with the same word line; the page cache array is connected with the storage unit array through a bit line and comprises a plurality of page cache groups, each page cache group comprises a multi-level page cache, the multi-level page cache comprises at least one first page cache, the first page cache comprises an error counting unit, and the error counting unit is suitable for accumulating the number of error pages in a plurality of target storage units connected with the page cache groups. According to the semiconductor storage device, the size of the semiconductor chip is slightly increased, the automatic test of the semiconductor chip can be carried out, the test time can be reduced, and the chip area utilization rate and the test efficiency are improved.)

1. A semiconductor memory device, comprising:

the memory device comprises a memory cell array, a word line and a word line, wherein the memory cell array comprises a plurality of memory cells which are divided into a plurality of pages, and the plurality of memory cells in each page are connected with the same word line;

the page cache array is connected with the storage unit array through a bit line and comprises a plurality of page cache groups, each page cache group comprises a multi-level page cache, the multi-level page cache comprises at least one first page cache, the first page cache comprises an error counting unit, and the error counting unit is suitable for accumulating the number of error pages in a plurality of target storage units connected with the page cache groups.

2. The semiconductor memory device according to claim 1, wherein the error counting unit includes a first latch whose logic value of latched data is inverted when an error page exists in the plurality of target memory cells, and the number of inversions is counted as the error page.

3. The semiconductor memory device according to claim 2, further comprising:

a signal generator adapted to generate test data written into the plurality of target memory cells;

input-output circuitry adapted to receive target data stored in the plurality of target storage units from the page cache array; and

and the comparison unit is suitable for comparing whether the test data and the target data are the same or not, outputting a comparison result to the error counting unit, and indicating that an error page exists in the target storage units when the comparison result is different.

4. The semiconductor memory device according to claim 1, wherein the first page buffer further includes a second latch therein, the second latch being adapted to store data of a first target memory cell connected to the first page buffer.

5. The semiconductor memory device according to claim 1, further comprising a plurality of second page buffers in the multi-level page buffer, the plurality of second page buffers not including the error count unit therein.

6. The semiconductor memory device according to claim 5, wherein a third latch is included in the second page buffer, the third latch being adapted to store data of a second target memory cell connected to the second page buffer.

7. The semiconductor memory device according to claim 3, further comprising an address decoder including an and operation unit, wherein the and operation unit includes a first input terminal, a second input terminal, and an output terminal, wherein an address selection signal is connected to the first input terminal, wherein the comparison result is connected to the second input terminal, and wherein the output terminal is connected to a first reset terminal of the first latch.

8. The semiconductor memory apparatus of claim 3, further comprising a controller generating a comparison enable signal, the controller controlling the comparison unit to perform a comparison operation during an active period of the comparison enable signal.

9. The semiconductor memory apparatus of claim 8, wherein the controller further controls a plurality of the error count units in the plurality of page buffer groups to sequentially accumulate the number of error pages in a plurality of target memory units connected to each of the page buffer groups.

10. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is an SPI NAND flash memory.

11. A method of testing a semiconductor memory device, comprising:

writing test data into a plurality of target storage units;

receiving target data stored in the target storage units from a page cache group, wherein the target storage units are connected with the page cache group through bit lines, the page cache group comprises a plurality of levels of page caches, the plurality of levels of page caches comprise at least one first page cache, and the first page cache comprises an error counting unit;

and comparing whether the test data and the target data are the same or not, and outputting a comparison result to the error counting unit, wherein the error counting unit accumulates the number of error pages in a plurality of target storage units connected with the page cache group according to the comparison result.

12. The test method of claim 11, wherein the error counting unit includes a first latch, and when the comparison result is different, a logic value of latched data of the first latch is inverted, and the number of inversions is counted as the error page.

13. The method of testing according to claim 12, wherein the first page buffer further comprises a second latch therein, the second latch adapted to store data of a first target memory cell connected to the first page buffer.

14. The test method of claim 11, further comprising a plurality of second page buffers in the multi-level page buffer, the plurality of second page buffers not including the error count unit.

15. The test method of claim 14, wherein the second page buffer includes a third latch therein, the third latch adapted to store data of a second target memory cell connected to the second page buffer.

16. The test method of claim 11, further comprising: providing a comparison enable signal, and comparing whether the test data and the target data are the same in an effective period of the comparison enable signal.

17. The test method of claim 11, further comprising: the error counting unit in a plurality of page buffer groups sequentially accumulates the number of error pages in a plurality of target storage units connected to each of the page buffer groups.

18. The test method of claim 13, further comprising: transmitting the error page count to the second latch.

19. The test method of claim 11, wherein the semiconductor memory device is an SPI NAND flash memory.

Technical Field

The present invention relates to the field of semiconductor device manufacturing, and more particularly, to a semiconductor memory device and a test method thereof.

Background

The SPI NAND flash memory is a Serial Peripheral Interface (SPI) NAND flash memory. The SPI protocol is simple and convenient, the application range of the SPI NAND is wide, and the requirement on the market of the memory chip is increased day by day. Testing of SPI NAND flash is required to ensure the stability of the flash. However, the testing time of the conventional SPI NAND flash memory is long, and the testing process is complicated; in order to facilitate the test, some electronic elements for testing need to be added to the circuit of the SPI NAND flash memory, which results in an increase in chip size and a decrease in chip area utilization.

Disclosure of Invention

The invention aims to provide a semiconductor storage device and a test method thereof, which can reduce the increment of chip size and improve the test speed of a chip.

In order to solve the above-described problems, the present invention provides a semiconductor memory device, including: the memory device comprises a memory cell array, a word line and a word line, wherein the memory cell array comprises a plurality of memory cells which are divided into a plurality of pages, and the plurality of memory cells in each page are connected with the same word line; the page cache array is connected with the storage unit array through a bit line and comprises a plurality of page cache groups, each page cache group comprises a multi-level page cache, the multi-level page cache comprises at least one first page cache, the first page cache comprises an error counting unit, and the error counting unit is suitable for accumulating the number of error pages in a plurality of target storage units connected with the page cache groups.

In an embodiment of the present invention, the error counting unit includes a first latch, and when an error page exists in the target memory cells, a logic value of latched data of the first latch is inverted, and the number of times of inversion is counted as the error page.

In an embodiment of the present invention, the method further includes: a signal generator adapted to generate test data written into the plurality of target memory cells; input-output circuitry adapted to receive target data stored in the plurality of target storage units from the page cache array; and the comparison unit is suitable for comparing whether the test data and the target data are the same or not, outputting a comparison result to the error counting unit, and indicating that an error page exists in the target storage units when the comparison result is different.

In an embodiment of the invention, the first page buffer further includes a second latch therein, and the second latch is adapted to store data of a first target memory cell connected to the first page buffer.

In an embodiment of the invention, the multi-level page buffer further includes a plurality of second page buffers, and the plurality of second page buffers do not include the error counting unit.

In an embodiment of the invention, the second page buffer includes a third latch therein, and the third latch is adapted to store data of a second target memory cell connected to the second page buffer.

In an embodiment of the present invention, the first latch further includes an address decoder, the address decoder includes an and operation unit, the and operation unit includes a first input terminal, a second input terminal, and an output terminal, an address selection signal is connected to the first input terminal, the comparison result is connected to the second input terminal, and the output terminal is connected to a first reset terminal of the first latch.

In an embodiment of the present invention, the apparatus further includes a controller, the controller generates a comparison enable signal, and the controller controls the comparison unit to perform a comparison operation during an active period of the comparison enable signal.

In an embodiment of the present invention, the controller further controls the error counting units in the page buffer groups to sequentially accumulate the number of error pages in the target storage units connected to each of the page buffer groups.

In one embodiment of the present invention, the semiconductor memory device is an SPI NAND flash memory.

In order to solve the above-mentioned problems, the present invention further provides a method for testing a semiconductor memory device, comprising: writing test data into a plurality of target storage units; receiving target data stored in the target storage units from a page cache group, wherein the target storage units are connected with the page cache group through bit lines, the page cache group comprises a plurality of levels of page caches, the plurality of levels of page caches comprise at least one first page cache, and the first page cache comprises an error counting unit; and comparing whether the test data and the target data are the same or not, and outputting a comparison result to the error counting unit, wherein the error counting unit accumulates the number of error pages in a plurality of target storage units connected with the page cache group according to the comparison result.

In an embodiment of the present invention, the error counting unit includes a first latch, and when the comparison result is different, a logic value of latched data of the first latch is inverted, and the number of times of inversion is regarded as the error page count.

In an embodiment of the invention, the first page buffer further includes a second latch therein, and the second latch is adapted to store data of a first target memory cell connected to the first page buffer.

In an embodiment of the invention, the multi-level page buffer further includes a plurality of second page buffers, and the plurality of second page buffers do not include the error counting unit.

In an embodiment of the invention, the second page buffer includes a third latch therein, and the third latch is adapted to store data of a second target memory cell connected to the second page buffer.

In an embodiment of the present invention, the method further includes: providing a comparison enable signal, and comparing whether the test data and the target data are the same in an effective period of the comparison enable signal.

In an embodiment of the present invention, the method further includes: the error counting unit in a plurality of page buffer groups sequentially accumulates the number of error pages in a plurality of target storage units connected to each of the page buffer groups.

In an embodiment of the present invention, the method further includes: transmitting the error page count to the second latch.

In one embodiment of the present invention, the semiconductor memory device is an SPI NAND flash memory.

The semiconductor memory device of the present invention is provided with at least one first page buffer in a page buffer group, the first page buffer including an error counting unit adapted to accumulate the number of error bits in a plurality of target memory cells connected to the page buffer group. According to the semiconductor storage device, the size of the semiconductor chip is slightly increased, and the semiconductor storage device can be used for carrying out automatic testing on the semiconductor chip, so that the testing time can be reduced, and the chip area utilization rate and the testing efficiency are improved.

Drawings

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below, wherein:

fig. 1 is a schematic structural diagram of a semiconductor memory device according to an embodiment of the present invention;

fig. 2 is a schematic partial structure diagram of a semiconductor memory device according to an embodiment of the present invention;

FIG. 3 is a diagram illustrating a first page register of a semiconductor memory device according to an embodiment of the present invention;

FIG. 4 is a diagram illustrating a second page register of the semiconductor memory device according to an embodiment of the present invention;

fig. 5 is a block diagram of a semiconductor memory device according to another embodiment of the present invention;

fig. 6 is a partial structural view of a semiconductor memory device according to an embodiment of the present invention;

FIG. 7 is a timing diagram illustrating signals in a semiconductor memory device according to an embodiment of the present invention;

fig. 8 is an exemplary flowchart of a test method of a semiconductor memory apparatus according to an embodiment of the present invention.

Detailed Description

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.

In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, but the present invention may be practiced in other ways than those specifically described herein, and thus the present invention is not limited to the specific embodiments disclosed below.

As used in this application and the appended claims, the terms "a," "an," "the," and/or "the" are not intended to be inclusive in the singular, but rather are intended to be inclusive in the plural unless the context clearly dictates otherwise. In general, the terms "comprises" and "comprising" merely indicate that steps and elements are included which are explicitly identified, that the steps and elements do not form an exclusive list, and that a method or apparatus may include other steps or elements.

In describing the embodiments of the present invention in detail, the cross-sectional views illustrating the structure of the device are not enlarged partially in a general scale for convenience of illustration, and the schematic drawings are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.

For convenience in description, spatial relational terms such as "below," "beneath," "below," "under," "over," "upper," and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these terms of spatial relationship are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary words "below" and "beneath" can encompass both an orientation of up and down. The device may have other orientations (rotated 90 degrees or at other orientations) and the spatial relationship descriptors used herein should be interpreted accordingly. Further, it will also be understood that when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.

In the context of this application, a structure described as having a first feature "on" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed in between the first and second features, such that the first and second features may not be in direct contact.

It should be noted that the terms "first", "second", and the like are used to define the components, and are only used for convenience of distinguishing the corresponding components, and the terms have no special meanings unless otherwise stated, and therefore, the scope of protection of the present application is not to be construed as being limited.

Flow charts are used herein to illustrate operations performed by systems according to embodiments of the present application. It should be understood that the preceding or following operations are not necessarily performed in the exact order in which they are performed. Rather, various steps may be processed in reverse order or simultaneously. Meanwhile, other operations are added to or removed from these processes.

Fig. 1 is a schematic structural diagram of a semiconductor memory device according to an embodiment of the present invention. Referring to fig. 1, the semiconductor memory device includes a memory cell array 110 and a page buffer array 120. The memory cell array 110 includes a plurality of memory cells, the memory cells are divided into a plurality of pages (pages), and the memory cells in each Page are connected to a same Word Line (WL). The page buffer array 120 is connected to the memory cell array 110 through a Bit Line (BL). The page buffer array 120 includes a plurality of page buffer sets (not shown), each page buffer set includes a plurality of levels of page buffers, each level of page buffer includes at least one first page buffer, and the first page buffer includes an error counting unit, which is adapted to accumulate the number of error pages in a plurality of target memory cells connected to the page buffer set.

The memory cell array 110 may include a plurality of memory cells arranged in a row direction and a column direction, and each memory cell may store one or more bits therein.

The page buffer array 120 may be connected to the memory cell array 110 through a plurality of bit lines BL and connected to the I/O circuit 140 through data lines DL.

Referring to fig. 1, the semiconductor memory device of the present invention may further include a controller 130, an input-output I/O circuit 140, a voltage generator 150, an address decoder 160, and the like.

The address decoder 160 may be connected to the memory cell array 110 through word lines WL, string select lines, ground select lines, and the like. The address decoder 160 may decode an address command from an external controller, and the address decoder 160 selects at least one of the word lines WL as a selected word line according to the decoded address, so that the controller 130 drives the selected word line and controls the voltage thereof.

The voltage generator 150 may generate various voltages required for the semiconductor memory apparatus, such as a program voltage, a read voltage, a verify voltage, a turn-on voltage, and the like.

The controller 130 may control the page buffer array 120, the I/O circuit 140, the address decoder 160, the voltage generator 150, and the like in response to commands and control signals from an external device.

Under the control of the controller 130, the page buffer array 120 may read data stored in the memory cell array 110 and may also store (write) data from the I/O circuit 140 in the memory cell array 110.

Fig. 2 is a schematic partial structural diagram of a semiconductor memory device according to an embodiment of the present invention, in which a memory cell array 110 and a page buffer array 120, and a related high-voltage switch array 151 and an address decoder array 161 in the semiconductor memory device in fig. 1 are shown. Referring to fig. 2, a memory cell array 110 is represented by a plurality of vertical lines arranged in parallel, and the memory cell array 110 includes a plurality of memory cells, including a plurality of memory cell strings, distributed in rows and columns. Each vertical line in the memory cell array 110 in fig. 2 represents one memory cell string. In each memory cell string, the memory cells are connected in series with each other, and each memory cell string is connected to one bit line. Referring to fig. 2, BLe/o denotes a pair of parity bit line pairs, one memory cell string is connected, and each two vertical lines denote a pair of parity bit line pairs. In the memory cell array 110, a plurality of word lines (not shown) are connected to each row of memory cells in a row arrangement, and a plurality of memory cells connected to the same word line belong to the same page.

Referring to fig. 2, in which the page buffer array 120 is represented by tables, each of the tables represents a page buffer, and each pair of parity bit line pairs in the memory cell array 110 is connected to one page buffer in the page buffer array 120, the page buffer corresponding to a plurality of memory cells in the pair of parity bit line pairs. A plurality of page buffers in the same column belong to a page buffer group, for example, the first column in the table, 8 page buffers numbered 0-7 belong to a page buffer group, and the group of page buffer groups is called G1; the 8 page buffers numbered 8-15 in the second column belong to a page buffer group, which is referred to as G2, and so on. Each page buffer group includes a plurality of levels of page buffers. For example, in the page buffer group G1, the page buffers numbered 0 to 7 belong to the 0 to 7 levels, respectively, that is, 8 levels of page buffers are included in the page buffer group G1. Accordingly, in the embodiment shown in FIG. 2, page buffers numbered 0, 8, 16, 24, 32, 40 all belong to level 0, page buffers numbered 1, 9, 17, 25, 33, 41 all belong to level 1, and so on.

In the embodiment shown in FIG. 2, 8 page buffers are included in each page buffer group, corresponding to 8 pairs of parity bit lines. For example, page buffers numbered 0-7 in page buffer array 120 correspond to 8 pairs of parity bit line pairs BLe/o <0:7> in memory cell array 110, page buffers numbered 8-15 in page buffer array 120 correspond to 8 pairs of parity bit line pairs BLe/o <8:15> in memory cell array 110, and so on. The number in the tip brackets of the parity bit line pair in fig. 2 may be taken as the number of the parity bit line pair, which corresponds one-to-one to the number of the page buffer.

Fig. 2 shows a total of 6 groups of page buffers, 48 page buffers, corresponding to a plurality of memory cells to which 48 pairs of parity bit lines are connected.

The illustration in fig. 2 is merely an example, and is not intended to limit the number of page buffer groups in the semiconductor memory apparatus of the present invention, and the number of page buffers in each page buffer group.

Referring to fig. 2, in which a high voltage switch array 151 is also shown, the high voltage switch array 151 is connected to the high voltage generator 150 shown in fig. 1, and the high voltage switch array 151 may also be included in the high voltage generator 150. Fig. 2 shows, in table form, the high-voltage switch array 151, in which the numbers correspond one-to-one to the numbers in the page buffer array 120 and also to the numbers of the odd-even word line pairs in the memory cell array 110, as switches for controlling the voltages applied to the selected word lines.

Referring to FIG. 2, there is also shown an address decoder array 161, which may be a specific embodiment of the address decoder 160 shown in FIG. 1. In fig. 2, the address decoder array 161 includes 6 address decoders Y _ DEC <0>, …, Y _ DEC <5> corresponding to 6 sets of page buffer groups.

Referring to fig. 2, in the embodiment of the present invention, the multi-level page buffer includes at least one first page buffer 121, and the first page buffer 121 includes an error counting unit adapted to accumulate the number of error pages in a plurality of target memory cells connected to the page buffer group.

When testing the semiconductor device, the target memory cells may be selected page by page according to the order of the word lines, the multi-level page buffers in each page buffer group respectively read a plurality of stored data in the target memory cells in the same page, and if there is an error bit in the plurality of stored data, it indicates that there is an error in the page, and then the number of error pages is accumulated once. According to this test method, it is not known which memory cell in the page has an erroneous bit. The present invention does not limit the number of pages in the memory cell array 110.

In the embodiment shown in fig. 2, a first page buffer 121, i.e., the page buffer numbered 7, is included in the page buffer group G1. Taking the page buffer group G1 as an example, the first page buffer 121 with the number of 7 includes an error counting unit, which can accumulate the number of error pages in the target memory cells connected to the page buffer group G1. The plurality of target memory cells herein refers to a plurality of memory cells connected to the parity word line pair BLe/o <0:7> in the memory cell array 110. The invention is not limited to the specific implementation of the error counting unit.

In some embodiments, a second page buffer is also included in each page buffer set. As shown in fig. 2, each of the remaining 7 page buffers except the first page buffer 121 is a second page buffer 122, the second page buffers 122 are only used for realizing the function of a common page buffer, and the second page buffers 122 do not include the error counting unit in the first page buffer 121.

According to the semiconductor memory device of the present invention, by providing the error counting unit in at least one first page buffer 121 in the page buffer group, the number of error pages in the plurality of target memory cells to which the page buffer group is connected can be counted. Assuming that a plurality of target memory cells connected to each group of page buffer groups belong to one memory column in the memory cell array 110, in a test mode of the semiconductor memory apparatus, when an error page is found to occur in the memory cells in the memory column or the number of error pages occurring exceeds a predetermined threshold, the memory column is replaced with a spare memory column.

In some embodiments, the error counting unit in the first page buffer 121 includes a first latch, and when there is an error page in the plurality of target memory cells, a logic value of latched data of the first latch is inverted, and the number of inversion times is counted as an error page.

In some embodiments, the first page buffer 121 further comprises a second latch therein, the second latch being adapted to store data of the first target memory cell connected to the first page buffer.

Fig. 3 is a schematic structural diagram of a first page register in a semiconductor memory apparatus according to an embodiment of the present invention. Referring to fig. 3, the first page buffer 121 includes a first latch 310 and a second latch 320. Wherein the first latch 310 and the second latch 320 are both R-S (Reset-Set) latches, the first latch 310 is connected to the memory cell array 110 through a sensing element 331, and the second latch 320 is connected to the high voltage switch array 151 through a precharge element 332.

Referring to fig. 3, the first latch 310 includes a first latch element 311, a first Reset (Reset) terminal 312, and a first Set (Set) terminal 313. When sensing an error in data in the first target memory cell connected to the first latch 310, a signal indicating the error may be input to a first Reset (Reset) terminal 312, so that the logic value of the latched data of the first latch element 311 is inverted, and the inverted logic value is recorded as an error.

In some embodiments, the error counting unit is initialized through the first set terminal 313, that is, the initialization signal INIT _ P is input to the first set terminal 313, so that the logic value in the first latch 310 is restored to the zero potential, and the number of error pages is cleared.

Referring to fig. 3, the second latch 320 includes a second latch element 321, a second reset terminal 322 and a second set terminal 323. The data switches 341 and 342 are respectively connected to two pins (Q1, Q1_ N) of the second latch element 321, the data switches 341 and 342 are also respectively connected to the data lines 343 and 344, and the second latch element 321 can store data written to or read from the first target memory cell, which can be from the data switches 341 and 342 or transferred to the data lines 343 and 344. In fig. 3, a data line 343 is denoted as LDL, a data line 344 is denoted as LDLb, and LDL and LDLb each represent one data bus line. LDLb is the opposite of LDL. As shown in fig. 3, the data switches 341 and 342 are transistors, and the address selection signal YI is connected to the bases of the data switches 341 and 342 and is used for selecting the memory cells corresponding to the page buffer; the data lines 343, 344 are connected to the drains or sources of the data switches 341, 342, respectively, for outputting data.

In some embodiments, a third latch is included in the second page buffer, the third latch adapted to store data of a second target memory cell coupled to the second page buffer. The first target storage unit and the second target storage unit together constitute a total storage unit corresponding to one page buffer group.

Fig. 4 is a schematic structural diagram of a second page register in the semiconductor memory apparatus according to an embodiment of the present invention. Referring to fig. 4, taking the second page buffer 122 in fig. 2 as an example, the second page buffer 122 includes a third latch 410, and the third latch 410 includes a third latch element 411, a third reset terminal 412 and a third set terminal 413. The third latch 410 is connected to the memory cell array 110 through a sensing element 431, and the third latch 410 is connected to the high voltage switch array 151 through a precharge element 432. The data switches 441 and 442 are respectively connected to two pins (Q1 and Q1_ N) of the third latch element 411, the data switches 441 and 442 are also respectively connected to the data lines 443 and 444, and the third latch element 411 can store data written to or read from the second target memory cell, and the data can be transmitted from or to the data lines 443 and 444. In fig. 4, the data line 443 is denoted as LDL, the data line 444 is denoted as LDLb, and it is indicated that the data outputted from the second page buffer 122 can be transferred via one data bus with the data outputted from the first page buffer 121, and LDL and LDLb each indicate one data bus. Corresponding to the embodiment shown in fig. 2, the data bus that transfers 8 data in the page buffer group G18 may be represented by LDL <0:7> and LDLb <0:7 >.

In the embodiment shown in fig. 3 and 4, the third latch 410 in the second page buffer 122 is identical in structure and function to the second latch 320 in the first page buffer 121. In other embodiments, the second latch 320 and the third latch 410 may be different structures.

The illustration of fig. 3 and 4 is merely an example, and is not intended to limit the embodiments of the first page buffer 121 and the second page buffer 122 of the present invention, and any other elements in the art may be used to form the first latch 310, the second latch 320, and the third latch 410, and implement the corresponding functions.

According to the embodiments shown in fig. 2 to 4, in each page buffer group of the semiconductor memory device, the error counting unit is arranged in a first page buffer for accumulating the number of error pages in a plurality of target memory cells connected to the page buffer group, without arranging the error counting unit in other second page buffers, so that the number of elements to be added can be reduced, and the chip area can be saved.

Fig. 5 is a block diagram of a semiconductor memory device according to another embodiment of the present invention. Referring to fig. 5, the semiconductor memory apparatus of this embodiment includes a signal generator 510, an input-output circuit 530, and a comparison unit 520, in addition to the memory cell array 110 and the page buffer array 120 in the embodiment shown in fig. 1. Wherein the signal generator 510 is adapted to generate test data to be written into a plurality of target memory cells; the input-output circuit 140 is adapted to receive target data stored in a plurality of target memory cells from the page buffer array 120; the comparing unit 520 is adapted to compare whether the test data and the target data are the same, and output a comparison result COMP _ FAIL to the error counting unit, and when the comparison result is different, it indicates that an error page exists in the plurality of target memory cells, and accordingly, a logic value of the latch data of the first latch is inverted.

Referring to fig. 5, the input/output circuit 530 may be the I/O circuit 140 shown in fig. 1, may be included in the I/O circuit 140, or may be a separate circuit. The signal generator 510 outputs test DATA _ E, which is identical to write DATA that has been written into a plurality of target memory cells, to the comparison unit 520. When an error occurs in a memory cell, the target DATA1 read from the memory cell does not coincide with the test DATA _ E. In performing the test, the signal generator 510 may generate test data to be written into the memory cell array 110.

Referring to fig. 5, target data in a target memory cell in the memory cell array 110 is input to the input-output circuit 530 through the data lines LDL, LDLb in the page buffers 121, 122 in the page buffer array 120.

In some embodiments, the input-output circuit 530 may perform analog-to-digital conversion on the target DATA in the DATA lines LDL, LDLb, so that the input-output circuit 530 outputs the digitized target DATA1 to the comparison unit 520.

In some embodiments, the semiconductor memory apparatus of the present invention further includes a controller (not shown) that generates the comparison enable signal STRB, and the controller controls the comparison unit 520 to perform the comparison operation during an active period of the comparison enable signal. The controller may be included in the controller 130 shown in fig. 1 or may be a separate controller.

Referring to fig. 5, the comparison enable signal STRB is simultaneously input to the comparison unit 520 and the input-output circuit 530, so that the comparison unit 520 compares the test DATA _ E and the target DATA1 during the valid period of the comparison enable signal STRB. And will be described in detail later in connection with the signal timing diagram.

In some embodiments, the semiconductor memory device of the present invention further includes an address decoder including an and operation unit including a first input terminal, a second input terminal, and an output terminal, the address selection signal being connected to the first input terminal, the comparison result being connected to the second input terminal, and the output terminal being connected to the first reset terminal of the first latch.

Fig. 6 is a partial structural schematic diagram of a semiconductor memory device according to an embodiment of the present invention, in which the page buffer array 120 and the address decoder array 161 in fig. 2 are shown. The address decoders in the address decoder array 161 are labeled Y _ DEC <0>, …, Y _ DEC <5> according to the connection relationship with the page buffer group, wherein Y _ DEC <0> corresponds to the page buffer group G1 in FIG. 2, Y _ DEC <1> corresponds to the page buffer group G2 in FIG. 2, and so on. Referring to fig. 6, the address decoder array 161 selects each address decoder according to the address command Y _ ADD < N:0>, and the comparison result COMP _ FAIL is input to each address decoder. The address selection signal YI of the selected address decoder is asserted, and the memory cell corresponding to the address decoder is selected. For example, the address decoder Y _ DEC <0> may output an address selection signal YI <0> to the page buffer group G1, and the address selection signal YI <0> may indicate that a plurality of target memory cells corresponding to the page buffer group G1 are selected.

The address decoders include an and operation unit (not shown) for performing an and operation on the address selection signal YI and the comparison result COMP _ FAIL, and the and result RSTF _ F output by the and operation unit is connected to the first reset terminal 312 of the first latch 310, as shown in fig. 3. Assuming that the comparison result COMP _ FAIL is 0, the comparison results are the same, and the comparison result COMP _ FAIL is 1, the comparison results are different. When the address selection signal YI is asserted and the comparison result COMP _ FAIL is 1, indicating that an error page has occurred in the target memory cells corresponding to the address selection signal YI, the and result RSTF _ F is 1, and the logic value of the latch data of the first latch element 311 is inverted.

The present invention is not limited to the specific implementation of the and operation unit. In some embodiments, the and operation unit is an and gate having two inputs and one output.

In some embodiments, the controller in the semiconductor memory apparatus of the present invention further controls the plurality of error count units in the plurality of page buffer groups to sequentially accumulate the number of error pages in the plurality of target memory units connected to each page buffer group.

In practical implementation, in the test process, each group of page buffer groups is sequentially selected through the data bus, that is, the address selection signals YI are sequentially enabled, so that the error counting units in each group of page buffer groups sequentially accumulate the number of error pages in the target storage units connected with each page buffer group, thereby realizing the automatic test of the whole chip, improving the test speed and reducing the test time.

As shown in fig. 5 and fig. 6, the comparison result COMP _ FAIL output by the comparing unit 520 may be input into the address decoder 160, that is, into the second input terminal of the and unit of the address decoder 160.

FIG. 7 is a timing diagram of signals in the semiconductor memory device according to an embodiment of the present invention. Referring to fig. 6 and 7, YI <0>, …, YI <4> respectively represent address selection signals corresponding to each page buffer group. Fig. 7 is only an illustration, and does not show the data of all 5 sets of page buffers. For example, YI <0> represents address selection signals in 8 page buffers corresponding to numbers 0-7. YI <0> being high indicates that 8 page buffers in the page buffer group G1 are selected. Referring to fig. 7, YI <0>, …, YI <4> are sequentially made high, thereby sequentially selecting the corresponding page buffer groups.

Referring to fig. 7, the comparison enable signal STRB is a square wave signal having a certain duty ratio. The period in which the comparison enable signal STRB is at the high level is an effective period, and the comparison unit 520 compares the test DATA _ E and the target DATA1 only during the effective period.

Referring to fig. 7, the comparison result COMP _ FAIL is the output signal of the comparison unit 520, where two error indications 710, 720 are shown. This embodiment indicates that the target DATA1 does not correspond to the test DATA _ E with the comparison result COMP _ FAIL at a high level.

The comparison result COMP _ FAIL is AND-ed with the address selection signals YI <0>, …, YI <4> to obtain RSTF _ F <0>, …, RSTF _ F <4>, RSTF _ F <0>, …, and RSTF _ F <4> as signals input to the first reset terminal 312 of the first latch 310 in the 5 page buffer groups, respectively, when RSTF _ F <0>, …, and RSTF _ F <4> are high, the logic value of the latch data of the first latch 311 is inverted, and the error count unit in the page buffer group accumulates one error page.

As shown in fig. 7, two error indications 710 and 720 in the comparison result COMP _ FAIL respectively correspond to the valid periods of the test data YI <1> and YI <3>, and then high levels are generated in the signal RSTF _ F <1> and the signal RSTF _ F <3>, respectively, so that the logic values of the latched data of 311 in the page buffer group to which the two signals are connected are inverted.

According to the embodiment shown in fig. 7, the automatic test of the memory chip can be realized, the test time is reduced, and the test efficiency is improved.

In some embodiments, the semiconductor memory device of the present invention is an SPI NAND flash memory. The SPI NAND flash memory may be connected to a host device through a serial interface such as SPI. The host device may be a processor, controller, computer, etc.

Fig. 8 is an exemplary flowchart of a test method of a semiconductor memory apparatus according to an embodiment of the present invention. The testing method of this embodiment can be implemented according to the semiconductor memory device described above, and therefore, the foregoing contents and the drawings can be used to describe the testing method of the semiconductor memory device of the present invention, and the same contents will not be described again. Referring to fig. 8, the test method of this embodiment includes the steps of:

step 810: test data is written into a plurality of target memory cells.

In some embodiments, the test data in step 810 may be generated by the signal generator 510 in the semiconductor memory apparatus of the present invention.

Step 820: the method comprises the steps that target data stored in a plurality of target storage units are received from a page cache group, the target storage units are connected with the page cache group through bit lines, the page cache group comprises a plurality of levels of page caches, the plurality of levels of page caches comprise at least one first page cache, and the first page cache comprises an error counting unit.

In some embodiments, the target data stored in the plurality of target memory cells may be received from the memory cell array 110 by the input-output circuit 530 in the semiconductor memory apparatus of the present invention.

In some embodiments, the error counting unit includes a first latch, and when the comparison result is different, a logic value of the latched data of the first latch is flipped, and the number of flips is counted as the error page.

In some embodiments, the first page buffer further comprises a second latch therein, the second latch adapted to store data of a first target memory cell connected to the first page buffer.

In some embodiments, a plurality of second page buffers are also included in the multi-level page buffer, and the plurality of second page buffers do not include the error count unit therein.

In some embodiments, a third latch is included in the second page buffer, the third latch adapted to store data of a second target memory cell connected to the second page buffer.

Step 830: and comparing whether the test data and the target data are the same or not, outputting a comparison result to an error counting unit, and accumulating the number of error pages in a plurality of target storage units connected with the page cache group according to the comparison result by the error counting unit.

In some embodiments, the comparison operation may be performed by the comparison unit 520 in the semiconductor memory apparatus of the present invention. The plurality of memory cells are divided into a plurality of pages, and the plurality of memory cells in each page are connected to the same word line.

In some embodiments, the testing method of the present invention further comprises: and providing a comparison enabling signal, and comparing whether the test data and the target data are the same in the valid period of the comparison enabling signal. The comparison enable signal STRB may be generated by a controller in the semiconductor memory apparatus of the present invention.

In some embodiments, the testing method of the present invention further comprises: an error counting unit in the plurality of page buffer groups sequentially accumulates the number of error pages in a plurality of target storage units connected to each page buffer group. The address decoder may be controlled by the controller in the semiconductor memory apparatus of the present invention to generate the address selection signal YI, and control may be performed according to the signal timing shown in fig. 7, thereby achieving sequential accumulation of the number of error pages in the plurality of target memory cells connected per page buffer group.

In some embodiments, the testing method of the present invention further comprises: the error page count is transmitted to the second latch. Referring to fig. 3, the error page count result in the first latch 310 may be transferred to the second latch 320, and may be read out from the second latch 320.

In some embodiments, after the testing of all the memory cells is completed in a page-by-page testing manner for the plurality of memory cells in one memory block in the chip using the testing method of the present invention, the error page count result in the first latch 310 is transmitted to the second latch 320. When an error page occurs in a found memory column or the number of error pages exceeds a predetermined threshold, the memory column is replaced with a spare memory column.

In some embodiments, the semiconductor memory device in the test method of the present invention is an SPI NAND flash memory.

According to the testing method, the testing time can be reduced, and the testing efficiency can be improved; and the size increase of the chip is small, so that the chip area is saved.

Although the present invention has been described with reference to the present specific embodiments, it will be appreciated by those skilled in the art that the above embodiments are merely illustrative of the present invention, and various equivalent changes and substitutions may be made without departing from the spirit of the invention, and therefore, it is intended that all changes and modifications to the above embodiments within the spirit and scope of the present invention be covered by the appended claims.