阅读说明：本技术 一种can控制单元和离子加速器电源控制器 (CAN control unit and ion accelerator power supply controller ) 是由 张帅 高大庆 吴凤军 黄玉珍 王晓俊 闫怀海 张华剑 冯秀明 谭玉莲 李雨航 于 2021-06-29 设计创作，主要内容包括：本发明属于电源控制器技术领域,涉及一种CAN控制单元和离子加速器电源控制器,包括：波特率分频器用于将系统时钟转换为通讯时钟,并分别发送至位时序逻辑处理器和位流处理器；验收滤波器用于接受数据,数据经过CRC校验器进入位时序逻辑处理器；位时序逻辑处理器,用于在信息开头的总线传输时同步CAN控制单元位流,并将经过同步的数据传输至位流处理器；位流处理器,用于进行错误检测仲裁和错误处理,并将正确的数据和控制信号传送至移位寄存器,数据从移位寄存器的输出端输出至数据接收装置。本发明具有使用灵活方便,节约成本等特点,尤其在加速器励磁电源模块较强的电磁干扰的环境中能够提供较强的抗干扰能力和较低的误码率。(The invention belongs to the technical field of power supply controllers, and relates to a CAN control unit and an ion accelerator power supply controller, which comprises: the baud rate frequency divider is used for converting a system clock into a communication clock and respectively sending the communication clock to the bit time sequence logic processor and the bit stream processor; the acceptance filter is used for receiving data, and the data enters the bit time sequence logic processor through the CRC checker; the bit sequential logic processor is used for synchronizing the bit streams of the CAN control unit during the bus transmission of the information head and transmitting the synchronized data to the bit stream processor; and the bit stream processor is used for carrying out error detection arbitration and error processing, transmitting correct data and control signals to the shift register, and outputting the data to the data receiving device from the output end of the shift register. The invention has the characteristics of flexible and convenient use, cost saving and the like, and can provide stronger anti-interference capability and lower error rate particularly in the environment of stronger electromagnetic interference of an accelerator excitation power supply module.)

1. A CAN control unit, comprising: the system comprises a baud rate frequency divider, an acceptance filter, a CRC checker, a bit sequence logic processor, a bit stream processor and a shift register;

the baud rate frequency divider is used for converting a system clock into a communication clock and respectively sending the communication clock to the bit sequential logic processor and the bit stream processor;

the acceptance filter is used for receiving data, and the data enters the bit sequential logic processor through the CRC checker;

the bit sequential logic processor is used for synchronizing the bit streams of the CAN control unit during bus transmission of the information head and transmitting the synchronized data to the bit stream processor;

the bit stream processor is used for carrying out error detection arbitration and error processing and transmitting correct data and control signals to the shift register, and the data is output to the data receiving device from the output end of the shift register;

or the shift register receives the transmitted data, transmits the transmitted data to the bit stream processor for error detection arbitration and error processing, transmits the correct data to the bit sequential logic processor, and transmits the transmitted data to the data receiving device.

2. The CAN control unit of claim 1, wherein the ACF acceptance filter filters using a single filter mode.

3. The CAN control unit of claim 1, wherein the bitstream processor arbitrates for error detection by: after receiving data transmitted by the in-place sequential logic processor, performing modulo-2 division on a preset number by using the data, and if the remainder is 0, determining that the data transmission is error-free; if the remainder is not 0, the data transmission is considered to be in error.

4. The CAN control unit of claim 1 wherein the shift register reads and writes to the register using a base plus offset.

5. The CAN control unit of claim 4, wherein the registers include internal control registers, command registers, status registers, and transceiver registers.

6. The CAN control unit of claim 5, wherein the transceiver register employs a FIFO.

7. An ion accelerator power supply controller, comprising: a master controller, a slave controller, a CAN control unit according to any one of claims 1-6 and an upper computer; the master controller is respectively connected with each slave controller through the CAN control unit;

the master controller is used for configuring the master controller and each slave controller according to control and debugging parameters sent by the upper computer and the debugging computer; each slave controller is used for acquiring data of the power unit cabinet connected with the slave controller and sending the data to the master controller; and the master controller processes the data collected by each slave controller and then sends a control instruction to the corresponding slave controller, and the slave controller processes the control instruction and then sends the control instruction to the corresponding power unit cabinet.

8. The ion accelerator power supply controller of claim 7, wherein the main controller comprises a first FPGA control unit, a RAM, an RJ45 network interface unit, an optical signal synchronous trigger interface, a touch screen, an RS232 debug interface unit, and a CAN control unit;

the first FPGA control unit is communicated with the upper computer through the RJ45 network interface unit to realize power on/off, state detection and current setting control;

the RS232 debugging interface unit is connected with a debugging computer to realize parameter configuration and fault diagnosis of the master controller and each slave controller;

data storage is realized through the RAM;

sending a synchronous trigger signal to each slave controller branch circuit through the optical signal synchronous trigger interface to realize trigger pulse current enabling;

data transmission between the CAN control unit and each slave controller branch is realized;

and displaying the information of the output voltage and current of the power supply, switching on and switching off and faults through the touch screen, and performing the functions of switching on and switching off and resetting the faults.

9. The ion accelerator power supply controller of claim 8, wherein the slave controller comprises a second FPGA control unit, an RS485 communication unit, a multi-way PWM driver unit, and a multi-way ADC unit;

the multi-channel ADC unit is used for collecting current and voltage data in the power unit cabinet and sending the current and voltage data to the second FPGA control unit;

the RS485 communication unit is used for communicating with the PLC in the power unit cabinet and sending temperature data and relay protection state data uploaded by the PLC to the second FPGA control unit;

and the second FPGA control unit respectively sends a switching-on/off command and a reset command to a PLC in the power unit cabinet through the RS485 communication unit, converts current given data sent by the main controller into a plurality of paths of PWM driving signals and then sends the signals to an IGBT driving circuit in the power unit cabinet through the plurality of paths of PWM driver units.

Technical Field

The invention relates to a CAN control unit and an ion accelerator power supply controller, belongs to the technical field of power supply controllers, and particularly relates to the technical field of power supply controllers comprising CAN control units.

Background

The accelerator power supply belongs to a high-precision special power supply, and comprises a high-stability direct-current power supply, a pulse power supply, a scanning power supply and the like. The controller as the core of the accelerator power supply directly determines the performance of the power supply, and the requirement on the power supply controller is higher and higher along with the continuous improvement of the overall design index of the accelerator. The boost from analog to digital has been accomplished by accelerator power controllers today. However, the power supply digital controller needs to be further improved in the aspects of anti-interference performance, system response speed, stability, flexibility and the like.

At present, a communication module of an accelerator power controller mainly adopts a can (controller Area network) control unit, however, such controllers generally have the problems of fixed chip interface, poor flexibility and difficulty in integrating into the existing embedded system, so that when the controllers need to be integrated into the system, an external circuit needs to be additionally arranged. Like the yangting (the design of vehicle electronic fault on-line monitoring system based on the CAN bus network ", yangting, the university of qiqi hal, the natural science version, volume 37, 3 rd phase, 5 months in 2021) discloses a vehicle electronic fault on-line monitoring system of CAN control unit network, its key feature is: under the support of hardware equipment and a database, a transmission protocol of a CAN control unit network is formulated, and data in the transmission protocol is loaded and called under the constraint of the protocol. And analyzing the running mode of the vehicle so as to obtain a specific vehicle electronic data acquisition result. And comparing the real-time acquired data with a fault diagnosis reference standard to realize the on-line monitoring function of the electronic fault of the vehicle, and starting an alarm program by combining the monitoring result. Therefore, the control system comprising the CAN control unit commonly used at present still uses the SJA1000 controller, and two buses are required to work independently due to the limitation of the chips, namely two chips are required, so that the flexibility is low, more PCB (printed Circuit Board) use areas are occupied, and the complexity of the whole system is improved.

Disclosure of Invention

In view of the above problems, the present invention provides a CAN control unit and an ion accelerator power supply controller that are flexible and convenient to use and cost-effective.

In order to achieve the purpose, the invention adopts the following technical scheme: a CAN control unit, comprising: the system comprises a baud rate frequency divider, an ACF acceptance filter, a CRC checker, a bit sequence logic processor, a bit stream processor and a shift register; the baud rate frequency divider is used for converting a system clock into a communication clock and respectively sending the communication clock to the bit time sequence logic processor and the bit stream processor; the ACF acceptance filter is used for receiving data, and the data enters the bit sequence logic processor through the CRC checker; the bit sequential logic processor is used for synchronizing the bit streams of the CAN control unit during the bus transmission of the information head and transmitting the synchronized data to the bit stream processor; the bit stream processor is used for carrying out error detection arbitration and error processing, transmitting correct data and control signals to the shift register, and outputting the data to the data receiving device from the output end of the shift register; or the shift register receives the transmitted data, transmits the transmitted data to the bit stream processor for error detection arbitration and error processing, transmits the correct data to the bit sequential logic processor, and transmits the transmitted data to the data receiving device.

Further, the ACF acceptance filter adopts a single filtering mode for filtering.

Further, the method for the bit stream processor to arbitrate error detection comprises the following steps: after receiving data transmitted by the in-place sequential logic processor, performing modulo-2 division on a preset number by using the data, and if the remainder is 0, determining that the data transmission is error-free; if the remainder is not 0, the data transmission is considered to be in error.

Furthermore, the shift register reads and writes the register by using a base address plus an offset address mode.

Further, the registers include an internal control register, a command register, a status register, and a transceiving register.

Further, the transceiving register adopts FIFO.

The invention also discloses a power supply controller of the ion accelerator, which comprises: the CAN control system comprises a main controller, a slave controller, a CAN control unit and an upper computer, wherein the CAN control unit comprises any one of the above controllers; the master controller is respectively connected with each slave controller through a CAN control unit; the master controller is used for configuring the master controller and each slave controller according to control and debugging parameters sent by the upper computer and the debugging computer; each slave controller is used for acquiring data of the power unit cabinet connected with the slave controller and transmitting the data to the master controller; and the master controller processes the data collected by each slave controller and then sends the control instruction to the corresponding slave controller, and the slave controller processes the control instruction and then sends the control instruction to the corresponding power unit cabinet.

Further, the main controller comprises a first FPGA control unit, an RAM, an RJ45 network interface unit, an optical signal synchronous trigger interface, a touch screen, an RS232 debugging interface unit and a CAN control unit; the first FPGA control unit is communicated with an upper computer through an RJ45 network interface unit to realize power on and off, state detection and current setting control; the RS232 debugging interface unit is connected with a debugging computer to realize parameter configuration and fault diagnosis of the master controller and each slave controller; data storage is realized through the RAM; sending a synchronous trigger signal to each slave controller branch through an optical signal synchronous trigger interface to realize trigger pulse current enabling; data transmission between each slave controller branch is realized through the CAN control unit; the touch screen displays the information of the output voltage and current of the power supply, and performs the functions of switching on and off and resetting faults.

Further, the slave controller comprises a second FPGA control unit, an RS485 communication unit, a multi-path PWM driver unit and a multi-path ADC unit; the multi-channel ADC unit is used for collecting current and voltage data in the power unit cabinet and sending the current and voltage data to the second FPGA control unit; the RS485 communication unit is used for communicating with a PLC in the power unit cabinet and sending temperature data and relay protection state data uploaded by the PLC to the second FPGA control unit; the second FPGA control unit respectively sends the on-off and reset commands to a PLC in the power unit cabinet through an RS485 communication unit, current given data sent by the main controller are converted into multi-path PWM driving signals, and then the multi-path PWM driving signals are sent to an IGBT driving circuit in the power unit cabinet through a multi-path PWM driver unit.

Due to the adoption of the technical scheme, the invention has the following advantages: the invention has the characteristics of flexible and convenient use, cost saving and the like, can provide stronger anti-jamming capability and lower error rate particularly in the environment of stronger electromagnetic interference of an accelerator excitation power supply module, adopts the controller with a master-slave structure, and reduces the number of controllers and the cost compared with the structure that a single digital controller corresponds to one power unit.

Drawings

FIG. 1 is a schematic diagram of a CAN control unit according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of a single filtering mode in accordance with an embodiment of the present invention;

FIG. 3 is a block diagram of FIFO data in one embodiment of the invention;

fig. 4 is a schematic structural diagram of a power supply controller of an ion accelerator according to an embodiment of the present invention.

Detailed Description

The present invention will be described in detail by way of specific examples in order to enable those skilled in the art to better understand the technical solutions of the present invention. It should be understood, however, that the detailed description is provided for a better understanding of the invention only and that they should not be taken as limiting the invention. In describing the present invention, it is to be understood that the terminology used is for the purpose of description only and is not intended to be indicative or implied of relative importance.

Example one

The present embodiment discloses a CAN control unit, as shown in fig. 1, including: baud rate frequency divider, acceptance filter ACF, CRC checker, bit sequence logic processor, bit stream processor and shift register.

The baud rate frequency divider is used for converting a system clock into a communication clock and respectively sending the communication clock to the bit time sequence logic processor and the bit stream processor;

the checking filter ACF is used for receiving data, the data enters the bit sequence logic processor through a CRC (cyclic redundancy check) checker, and the checking filter ACF adopts a single filtering mode for filtering. The schematic diagram of the single filtering mode is shown in fig. 2, and performs exclusive nor logic processing on the information bits and the acceptance code bits, performs exclusive nor processing on the processing result and the acceptance mask bits, and performs exclusive or operation on the processing result and the processing result of other bits to obtain an output logic, wherein if the output logic is 1, acceptance is passed, and if the output logic is 0, acceptance is not passed. That is, if one of the other bit processing results is 0, the acceptance is not passed. The processing results of other bits are all 1, the acceptance mask bit is 0, and the information bit is different from the acceptance code bit, so that the acceptance is not passed. The processing results of other bits are all 1, the checking and accepting mask bit is 0, the information bit and the checking and accepting code bit are the same, and the checking and accepting is passed. And if the processing results of other bits are all 1 and the acceptance mask bit is 1, the acceptance is passed. For extended frames, the frame ID and RTR bits are compared in the single filtering mode. Suppose that: the acceptance code registers ACR0-ACR3 are respectively 0x21, 0x00,0x 05 and 0x24, and the mask code registers AMR0-AMR3 are respectively 0x00,0x00,0x00 and 0x 03. The information corresponding to the AMR bit of 1 is directly checked and accepted without comparison, and the information corresponding to the AMR bit of 0 is identical to the checking and accepting code bit and can be checked and accepted.

The bit sequential logic processor is used for synchronizing the bit streams of the CAN control unit during the bus transmission of the information head and transmitting the synchronized data to the bit stream processor;

the bit stream processor is used for carrying out error detection arbitration and error processing, and the method for carrying out the error detection arbitration by the bit stream processor comprises the following steps: after receiving data transmitted by the in-place sequential logic processor, performing modulo-2 division on a preset number by using the data, and if the remainder is 0, determining that the data transmission is error-free; if the remainder is not 0, the data transmission is considered to be in error. Since it is not known where the error occurs, the error cannot be automatically corrected, so that if the error data is found, the data is directly deleted, and the correct data and control signal are transmitted to the shift register, and the data is output from the output terminal of the shift register to the data receiving device. The shift register reads and writes the register by using a base address plus an offset address mode. The registers include internal control registers, command registers, status registers, and transceiver registers. In this embodiment, the transceiver buffer FIFO has 64 bytes of information space in total, and the stored information includes address bits, data frame information, an identification code, and data, the frame information represents the start of a frame of data, the identification code determines whether to send or receive the buffer information, the buffer window polls the processed data in order of address, the data is sent or received according to the identification code, the corresponding address information is deleted after the task is completed, and the specific format of the FIFO data is shown in fig. 3.

Or the shift register receives the transmitted data, transmits the transmitted data to the bit stream processor for error detection arbitration and error processing, transmits the correct data to the bit sequential logic processor, and transmits the transmitted data to the data receiving device.

Example two

Based on the same inventive concept, the present embodiment discloses an ion accelerator power supply controller, as shown in fig. 4, including: a master controller 1, a slave controller 2, a CAN control unit according to any one of the above and an upper computer 3; the master controller 1 is respectively connected with each slave controller 2 through a CAN control unit; the master controller 1 is used for configuring the master controller and each slave controller 2 according to control and debugging parameters sent by the upper computer 3 and the debugging computer; each slave controller 2 is used for acquiring data of the power unit cabinet 4 connected with the slave controller and sending the data to the master controller 1; the master controller 1 processes data collected by the slave controllers 2 and then sends control instructions to the corresponding slave controllers 2, and the slave controllers 2 process the control instructions and then send the control instructions to the corresponding power unit cabinets 4.

The main controller 1 comprises a first FPGA control unit, an RAM, an RJ45 network interface unit, an optical signal synchronous trigger interface, a touch screen, an RS232 debugging interface unit and a CAN control unit; the first FPGA control unit is communicated with the upper computer 3 through an RJ45 network interface unit to realize power on/off, state detection and current setting control; the RS232 debugging interface unit is connected with a debugging computer to realize parameter configuration and fault diagnosis of the master controller 1 and each slave controller 2; data storage is realized through the RAM; sending a synchronous trigger signal to each slave controller 2 branch through an optical signal synchronous trigger interface to realize trigger pulse current enabling; data transmission between each branch of the slave controllers 2 is realized through the CAN control unit; the touch screen displays the information of the output voltage and current of the power supply, and performs the functions of switching on and off and resetting faults.

The slave controller 2 comprises a second FPGA control unit, an RS485 communication unit, a multi-path PWM (pulse width modulation) driver unit and a multi-path ADC (Analog-to-digital converter) unit; the multi-channel ADC unit is used for collecting current and voltage data in the power unit cabinet 4 and sending the current and voltage data to the second FPGA control unit; the RS485 communication unit is used for communicating with the PLC in the power unit cabinet 4 and sending the temperature data and the relay protection state data uploaded by the PLC to the second FPGA control unit; the second FPGA control unit respectively sends the on-off and reset commands to a PLC in the power unit cabinet 4 through an RS485 communication unit, and current given data sent by the main controller 1 are converted into multi-path PWM driving signals and then sent to an IGBT driving circuit in the power unit cabinet 4 through a multi-path PWM driver unit.

Finally, it should be noted that: the above embodiments are only for illustrating the technical solutions of the present invention and not for limiting the same, and although the present invention is described in detail with reference to the above embodiments, those of ordinary skill in the art should understand that: modifications and equivalents may be made to the embodiments of the invention without departing from the spirit and scope of the invention, which is to be covered by the claims. The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application. Therefore, the protection scope of the present application should be defined by the claims.