Method and system for providing FPGA device identification by a set of embedded signature registers

文档序号：880283 发布日期：2021-03-19 浏览：2次中文

阅读说明：本技术 由一组嵌入式签名寄存器提供fpga器件识别的方法和系统 (Method and system for providing FPGA device identification by a set of embedded signature registers ) 是由朱璟辉于 2020-12-22 设计创作，主要内容包括：本公开涉及由一组嵌入式签名寄存器提供FPGA器件识别的方法和系统。可编程集成电路(PIC)器件包括可配置逻辑块(LB)、路由连接阵列和配置存储器,用于执行用户定义的编程逻辑功能。每个可配置LB包括一组查找表(LUT)和相关的寄存器。LUT被配置为根据一组输入信号产生一个或更多个输出信号。每个寄存器对应一个LUT。与第一LUT相对应或物理位置上位于第一LUT附近的第一寄存器可指定为嵌入式签名寄存器,用于存储固定值或签名信息,以便于器件或集成电路被识别。(The present disclosure relates to a method and system for providing FPGA device identification from a set of embedded signature registers. A Programmable Integrated Circuit (PIC) device includes a configurable Logic Block (LB), a routing connection array, and a configuration memory for performing user-defined programmed logic functions. Each configurable LB includes a set of look-up tables (LUTs) and associated registers. The LUT is configured to generate one or more output signals from a set of input signals. One for each register. A first register corresponding to or physically located near the first LUT may be designated as an embedded signature register for storing a fixed value or signature information for ease of device or integrated circuit identification.)

1. A Programmable Integrated Circuit (PIC) device comprising configurable Logic Blocks (LBs), a routing connection array, and a configuration memory for performing programmed logic functions, at least one of said configurable logic blocks comprising:

a plurality of look-up tables (LUTs) configured to generate one or more output signals from a set of input signals; and

a plurality of registers coupled to the plurality of lookup tables and arranged such that one of the plurality of registers corresponds to one of the plurality of lookup tables, wherein a first register of the plurality of registers corresponding to a first lookup table of the plurality of lookup tables is designated for storing a fixed value to facilitate identification of the programmable integrated circuit device, wherein a second register of the plurality of registers corresponding to a second lookup table of the plurality of lookup tables is configured to store a second output signal produced by the second lookup table.

2. The device of claim 1, wherein a third register of the plurality of registers corresponding to a third lookup table of the plurality of lookup tables is designated to store a fixed value to facilitate identification of the programmable integrated circuit device.

3. The device of claim 2, wherein a fourth register of the plurality of registers corresponding to a fourth lookup table of the plurality of lookup tables is configured to store a fourth output signal produced by the fourth lookup table.

4. The device of claim 3,

a fifth register of the plurality of registers corresponding to a fifth lookup table of the plurality of lookup tables is configured to store a fifth output signal generated by the fifth lookup table; and

a sixth register of the plurality of registers corresponding to a sixth lookup table of the plurality of lookup tables is configured to store a sixth output signal generated by the sixth lookup table.

5. The device of claim 4,

a seventh register of the plurality of registers corresponding to a seventh lookup table of the plurality of lookup tables is configured to store a seventh output signal generated by the seventh lookup table; and

an eighth register of the plurality of registers corresponding to an eighth lookup table of the plurality of lookup tables is configured to store an eighth output signal generated by the eighth lookup table.

6. The device of claim 1, wherein the first register is configured to output a stored fixed value during a bitstream read to verify an identity of the programmable integrated circuit device.

7. The device of claim 1, wherein the fixed value of a first register of the plurality of registers is imposed by a local controller.

8. The device of claim 1, wherein the configurable logic block further comprises a plurality of multiplexers, each multiplexer coupled to one of the lookup tables and one of the registers corresponding to the lookup tables and configured to provide internal routing between the lookup tables and the registers.

9. The device of claim 1,

a third register of the plurality of registers corresponding to a third lookup table of the plurality of lookup tables is designated for storing signature information to facilitate identification of the programmable integrated circuit device; and

a fourth register of the plurality of registers corresponding to a fourth lookup table of the plurality of lookup tables is designated for storing signature information to facilitate identification of the programmable integrated circuit device.

10. A system capable of providing digital processing functions and network communications, characterized in that it comprises a programmable integrated circuit device according to any one of claims 1 to 9.

11. A method of identifying an identity of a Field Programmable Gate Array (FPGA) device, the method identified by a set of signature registers in a plurality of configurable Logic Blocks (LBs), the method comprising:

acquiring a first bit stream, and forwarding the first bit stream to a first field programmable gate array for configuring the first field programmable gate array;

initiating a verification command for the first field programmable gate array, requiring the first field programmable gate array to return a second bitstream reflecting configuration information for the first field programmable gate array, the second bitstream including a set of fixed identification values obtained from a set of signature registers located in one or more configurable logic blocks; and

and determining the identification of the first field programmable gate array according to a group of fixed identification values extracted from the second bit stream after the first bit stream is compared with the second bit stream.

12. The method of claim 11, wherein obtaining the first bit stream comprises: the first bitstream is retrieved according to user-defined logic and transmitted from a host to a system containing the first field programmable gate array over a communication network.

13. The method of claim 11, wherein the initiating a validation command for the first field programmable gate array comprises: register values are read from a plurality of registers located in a plurality of configurable logic elements of a configurable logic block.

14. The method of claim 13, wherein reading register values from a plurality of registers comprises: retrieving a stored value from a signature register in the configurable logic element.

15. The method of claim 13, wherein reading register values from a plurality of registers comprises: at least some of the plurality of registers that are hidden from user configuration and that are logically associated with the one or more look-up tables are identified from which register values are read.

16. The method of claim 11, wherein the determining the identity of the first field programmable gate array comprises: identifying the first field programmable gate array as a counterfeit device in response to a mismatch between a predefined field programmable gate array signature and a signature embedded in the second bitstream.

17. The method of claim 11, wherein the determining the identity of the first field programmable gate array comprises: determining a manufacturer of the first field programmable gate array in response to a comparison between a predefined field programmable gate array signature and a signature embedded in the second bitstream.

18. A method of determining an identity of a Programmable Logic Device (PLD), the method being identified by a set of signature registers located in a plurality of configurable Logic Blocks (LBs), the method comprising:

receiving a verification bit stream returned from the programmable logic device, wherein the verification bit stream reflects signature information and current programming information in the programmable logic device;

identifying a signature bit position embedded in the validation bitstream that is associated with a set of hidden signature registers, the signature registers located in one or more configurable logic blocks;

extracting a set of fixed Identification (ID) values from signature bit positions associated with the set of signature registers; and

comparing a set of fixed identification values with predefined programmable logic device identification values to identify authenticity of the programmable logic device.

19. The method of claim 18, further comprising: the fixed identification value is decrypted according to a host-defined timestamp.

20. The method of claim 18, further comprising: the fixed identification value is decrypted in response to a set of random bit values generated from the initial input bitstream.

21. A programmable integrated circuit device comprising a controller and a plurality of logic blocks coupled to the controller, the logic blocks comprising a plurality of configurable logic slices, at least one of the configurable logic slices comprising a plurality of look-up tables and registers in one-to-one correspondence with the look-up tables; wherein:

at least one register for storing a fixed value, the fixed value for identifying the programmable integrated circuit device;

the controller is for storing the fixed value in the register in response to a configuration command and for reading the fixed value from the register in response to an authentication command.

Technical Field

Exemplary embodiments of the present disclosure relate to the field of programmable semiconductor devices in computer hardware and software. More particularly, exemplary embodiments of the present disclosure relate to methods and systems for providing FPGA device identification from a set of embedded signature registers.

Background

With the increasing popularity of digital communication, Artificial Intelligence (AI), Internet of Things (IoT) and/or robotic control, there is an increasing demand for faster, efficient hardware and semiconductors with processing power. To meet this demand, high-speed, flexible semiconductor chips are generally more desirable. One conventional approach to meeting this need is to use Application-Specific Integrated circuits (ASICs) and/or Application-Specific Integrated circuits (ASICs). One drawback of the asic approach is the lack of flexibility while consuming a large amount of resources.

Another conventional approach that has become increasingly popular is to utilize Programmable Semiconductor Devices (PSDs), such as Programmable Logic Devices (PLDs) or Field Programmable Gate Arrays (FPGAs). One feature of the programmable semiconductor device is: allowing an end user to program one or more desired functions to suit the user's application after the programmable semiconductor device is manufactured.

However, a drawback associated with conventional field programmable gate arrays or programmable logic devices is that it is difficult to verify the authenticity of devices such as field programmable gate arrays or programmable logic devices after they are brought into the field or the user (or client) field.

Disclosure of Invention

In one aspect, one embodiment of the present disclosure discloses a Programmable Semiconductor Device (PSD) or Programmable Integrated Circuit (PIC) device including a configurable Logic block (Logic Blocks LBs), a routing connection array, and a configuration memory for performing user-defined programmed Logic functions. Each of the configurable logic blocks includes:

a plurality of look-up tables (LUTs) configured to generate one or more output signals from a set of input signals; and

In one example, each configurable logic block includes a set of Lookup Tables (LUTs) and associated registers. For example, the look-up table is configured to generate one or more output signals from a set of input signals. The registers are arranged in such a way that each register corresponds to a look-up table. In one embodiment, rather than being assigned to a set of look-up tables in a plurality of configurable logic blocks, a set of registers is assigned or configured as embedded signature registers (embedded signature registers) in a programmable semiconductor device. For example, a first register corresponding to or physically located near the first lookup table may be designated as an embedded signature register for storing a fixed value or signature information for facilitating identification of a device or Integrated Circuit (IC). A second register corresponding to the second lookup table is configured to store a second output signal of the second lookup table.

In another aspect, one embodiment of the present disclosure discloses a system capable of providing digital processing functionality and network communications, the system comprising the aforementioned programmable integrated circuit device.

In yet another aspect, an embodiment of the present disclosure discloses a method of identifying an identity of a Field Programmable Gate Array (FPGA) device by a set of signature registers in a plurality of configurable Logic Blocks (LBs), the method comprising:

acquiring a first bit stream, and forwarding the first bit stream to a first field programmable gate array for configuring the first field programmable gate array;

In yet another aspect, an embodiment of the present disclosure discloses a method of determining an identity of a Programmable Logic Device (PLD), the method being identified by a set of signature registers located in a plurality of configurable Logic Blocks (LBs), the method comprising:

extracting a set of fixed Identification (ID) values from signature bit positions associated with the set of signature registers; and

comparing a set of fixed identification values with predefined programmable logic device identification values to identify authenticity of the programmable logic device.

In yet another aspect, an embodiment of the present disclosure discloses a programmable integrated circuit device, including a controller and a plurality of logic blocks coupled to the controller, where each logic block includes a plurality of configurable logic slices, and at least one of the configurable logic slices includes a plurality of lookup tables and registers in one-to-one correspondence with the lookup tables; wherein:

at least one register for storing a fixed value, the fixed value for identifying the programmable integrated circuit device;

the controller is for storing the fixed value in the register in response to a configuration command and for reading the fixed value from the register in response to an authentication command.

Other features and advantages of exemplary embodiments of the present disclosure will become apparent from the detailed description, the drawings, and the claims set forth below.

Drawings

Example embodiments of the present disclosure will be understood more fully from the detailed description given below and from the accompanying drawings of various embodiments of the disclosure, which, however, should not be taken to limit the disclosure to the specific embodiments, but are for explanation and understanding only.

Fig. 1A-1B are block diagrams illustrating a Programmable Semiconductor Device (PSD) or Programmable Integrated Circuit (PIC) that includes a signature register for identifying a device identity (deviceID) according to one embodiment of the disclosure.

FIG. 2 is a block diagram illustrating a routing logic or routing fabric including a programmable interconnect array (programmable interconnect array) containing signature information routes, according to one embodiment of the present disclosure.

Fig. 3A-3B are block diagrams illustrating a configurable Logic Element (LE) including a signature register in a programmable semiconductor device according to one embodiment of the disclosure.

Fig. 4 is a block diagram illustrating a configurable logic element or logic array block containing a signature register according to one embodiment of the present disclosure.

Fig. 5 is a block diagram illustrating a configurable logic element, Configurable Logic Slice (CLS), or logic array block containing a signature register according to one embodiment of the present disclosure.

Fig. 6A-6B are block diagrams illustrating a process of identifying device identifications, according to one embodiment of the present disclosure.

Fig. 7 is a system or computer diagram illustrating the use of one or more programmable semiconductor devices containing a set of signature registers according to one embodiment of the present disclosure.

Fig. 8 is a block diagram illustrating various applications of a programmable semiconductor device containing a signature register for use in a cloud environment, according to one embodiment of the present disclosure.

FIG. 9 is a flowchart illustrating a process for determining device identification according to one embodiment of the present disclosure.

Detailed Description

Embodiments of the present disclosure disclose methods and/or apparatus for providing a Programmable Semiconductor Device (PSD) capable of identifying device identification using a set of signature registers.

The following detailed description is intended to provide an understanding of one or more embodiments of the disclosure. Those of ordinary skill in the art will realize that the following detailed description is illustrative only and is not intended to be in any way limiting. Other embodiments will be apparent to those skilled in the art having the benefit of this disclosure and/or this description.

In the interest of clarity, not all of the routine features of the implementations described herein are shown and described. It will of course be appreciated that in the development of any such actual embodiment, numerous implementation-specific decisions may be made to achieve the developers' specific goals, such as compliance with application-and business-related constraints, which will vary from one implementation to another and from one developer to another. Moreover, it will be appreciated that such a development effort might be complex and time-consuming, but would nevertheless be a routine undertaking of engineering for those of ordinary skill in the art having the benefit of this disclosure.

The various embodiments of the disclosure illustrated in the figures are not drawn to scale. On the contrary, the dimensions of the various features may be exaggerated or minimized for clarity. Furthermore, some of the figures may be simplified for clarity. Accordingly, not all components of a given apparatus (e.g., device) or method may be depicted in a figure. The same reference indicators will be used throughout the drawings and the following detailed description to refer to the same or like parts.

In accordance with embodiments of the present disclosure, the components, process steps, and/or data structures described herein may be implemented using various types of operating systems, computing platforms, computer programs, and/or general purpose machines. Moreover, those of ordinary skill in the art will recognize that devices of a less general purpose nature, such as hardware devices, Field Programmable Gate Arrays (FPGAs), Application Specific Integrated Circuits (ASICs), or the like, may also be used without departing from the scope and spirit of the concepts disclosed herein. If the method comprising a series of process steps is implemented by a computer or a machine, and the process steps can be stored as a machine-readable series of instructions, it can be stored on a tangible medium such as a computer storage device, for example but not limited to: magnetoresistive Random Access Memory (MRAM), phase change Memory or Ferroelectric Random Access Memory (FeRAM), Flash Memory (Flash Memory), Read Only Memory (ROM), Programmable Read Only Memory (PROM), Electrically Erasable Programmable Read Only Memory (EEPROM), Jump Drive (Jump Drive), magnetic storage medium (e.g., magnetic tape, magnetic disk Drive, etc.), optical storage medium (e.g., compact disc Read Only Memory (CD-ROM), digital compact disc Read Only Memory (DVD-ROM), paper card, paper tape, etc.), and other known types of program Memory.

The terms "system" or "device" are used generically herein to describe any number of components, elements, subsystems, devices, packet switch elements, packet switches, access switches, routers, networks, computer and/or communication devices or mechanisms, or combinations of components thereof. The term "computer" includes processors, memories, and buses capable of executing instructions, where a computer refers to a computer or a cluster of computers, a personal computer, a workstation, a mainframe, or a combination of computers.

As used herein, "one or more" and "one or more" are synonymous and include any one of: one, two or more than two. As used herein, "input/output" (I/O) includes input and/or output.

The programmable semiconductor device (or called programmable integrated circuit device, field programmable gate array or programmable logic device) is the basic control equipment in the key infrastructure, the security of the basic control equipment relates to the stable operation of the whole control system, and if an attacker utilizes communication or system bugs to tamper the functions of the programmable semiconductor device, the functions may not be detected by users, and the safe operation of the control system is threatened.

On the other hand, since the programmable semiconductor device itself has no anti-counterfeiting function, if a user inadvertently purchases or uses a counterfeit programmable semiconductor device, the service life and after-sale of the counterfeit programmable semiconductor device cannot be guaranteed, resulting in a loss of legitimate rights and interests of the user.

In view of the above, the applicant provides a Programmable Integrated Circuit (PIC) device (such as an FPGA or PLD) for performing programmed logic functions, comprising at least configurable Logic Blocks (LB), a routing connection array and a configuration memory, wherein at least one of the configurable logic blocks comprises:

a plurality of look-up tables (LUTs) configured to generate one or more output signals from a set of input signals; and

In some exemplary embodiments, each configurable logic block may include the plurality of lookup tables and the plurality of registers described above.

The register coupled to the plurality of lookup tables and arranged such that one of the plurality of registers corresponds to one of the plurality of lookup tables means: the registers are connected with the lookup tables in a one-to-one correspondence mode. The register for storing a fixed value may be any one of the registers in the configurable logic block. When one register is configured to store a fixed value, the output signals generated by the lookup table connected in one-to-one correspondence with the register may be stored in the other registers or directly output.

The programmable integrated circuit device may be identified by providing a register in the configurable logic block for storing a fixed value. The fixed value can be any value set by the user, and the user can realize anti-attack verification by regularly reading the value. The fixed value can be anti-counterfeiting information (such as signature information) set by a manufacturer, and a user can realize the anti-counterfeiting function of the product by reading the value.

In an exemplary embodiment, the fixed value in the first register may be imposed by a local controller. The local controller may write a fixed value into the first register in response to a command of an external controller (e.g., a host controller). The embodiment of the present disclosure does not limit the timing of writing the fixed value, and may be, for example, writing in the integrated circuit identification process.

In one exemplary embodiment, a programmable integrated circuit device may include a controller and a plurality of logic blocks coupled with the controller, the logic blocks including a plurality of configurable logic slices, at least one of the configurable logic slices including a plurality of look-up tables and registers in one-to-one correspondence with the look-up tables; wherein:

at least one register for storing a fixed value, the fixed value for identifying the programmable integrated circuit device;

the controller is for storing the fixed value in the register in response to a configuration command and for reading the fixed value from the register in response to an authentication command.

For example, a controller in a programmable integrated circuit device stores a pre-configured value of a preset position in a first bit stream as a fixed value for identifying the device in a register based on the control of an external controller, when a user needs to identify the device, the controller in the programmable integrated circuit device may read the fixed value from the register and write a second bit stream into the register based on the control of the external controller, and the second bit stream may flow back to the external controller, and determine whether the device is attacked or counterfeit according to whether the fixed value in the second bit stream matches the pre-configured value.

The embodiment of the disclosure provides a programmable integrated circuit device capable of realizing anti-counterfeiting and anti-attack, no additional element is needed, the realization cost is low, remote identification can be realized, and the operation of a user is convenient.

One embodiment of the present disclosure illustrates a programmable semiconductor device (or programmable integrated circuit device, field programmable gate array, or programmable logic device) having configurable logic blocks, routing connection arrays, and configuration memory for performing user-defined programmed logic functions. In one example, each configurable logic block includes a set of look-up tables and an associated plurality of registers. For example, each look-up table is configured to generate one or more output signals from a set of input signals. The registers are arranged in such a way that each register corresponds to a look-up table. In one embodiment, at least one register is not allocated to a set of look-up tables, but is allocated or configured as an embedded signature register in one or more configurable logic blocks. For example, a first register corresponding to or physically located near the first lookup table may be designated as an embedded signature register for storing fixed values or signature information to facilitate identification of the device or integrated circuit. A second register corresponding to the second lookup table is configured to store a second output signal of the second lookup table.

In an exemplary embodiment, a plurality of registers may be allocated for storing fixed values, e.g., a third register of a plurality of registers in the configurable logic block corresponding to a third lookup table of the plurality of lookup tables is designated for storing fixed values to facilitate identification of the programmable integrated circuit device. Providing a plurality of registers for storing fixed values may facilitate a user setting more information for identifying the programmable integrated circuit device.

When a plurality of registers for storing fixed values are provided, the registers may be located in the same configurable logic block or may be located in different configurable logic blocks. It is not excluded that the register can be specified by the user to increase the effect of the attack prevention.

In an exemplary embodiment, a fourth register of the plurality of registers corresponding to a fourth lookup table of the plurality of lookup tables is configured to store a fourth output signal generated by the fourth lookup table.

In an exemplary embodiment, a fifth register of the plurality of registers corresponding to a fifth lookup table of the plurality of lookup tables is configured to store a fifth output signal produced by the fifth lookup table; a sixth register of the plurality of registers corresponding to a sixth lookup table of the plurality of lookup tables is configured to store a sixth output signal generated by the sixth lookup table.

In an exemplary embodiment, a seventh register of the plurality of registers corresponding to a seventh lookup table of the plurality of lookup tables is configured to store a seventh output signal generated by the seventh lookup table; and an eighth register of the plurality of registers corresponding to an eighth lookup table of the plurality of lookup tables is configured to store an eighth output signal generated by the eighth lookup table.

In an exemplary embodiment, a third register of the plurality of registers corresponding to a third lookup table of the plurality of lookup tables is designated for storing signature information to facilitate identification of the programmable integrated circuit device; and a fourth one of the plurality of registers corresponding to a fourth one of the plurality of look-up tables is designated for storing signature information for facilitating identification of the programmable integrated circuit device. Wherein the signature information may be a product signature that can identify the authenticity of the device. Optionally, the programmable integrated circuit device may include both a first register for storing a fixed value and a third register for storing signature information, and at this time, the functions of product anti-counterfeiting and anti-attack may be simultaneously implemented. The first register for storing the fixed value and the third register for storing the signature information may be in the same configurable logic block or in different configurable logic blocks, which is not limited in this disclosure. The register for storing signature information may be one or more, and when there are multiple registers, the multiple registers for storing signature information may be located in the same configurable logic block or may be located in different configurable logic blocks.

In an exemplary embodiment, the configurable logic block may further comprise a plurality of multiplexers, each multiplexer coupled to one of the lookup tables and one of the registers corresponding to the lookup tables and configured to provide internal routing between the lookup tables and the registers.

Fig. 1A is a block diagram illustrating a programmable semiconductor device that contains a signature register to facilitate identification (identification ID) of the programmable semiconductor device, according to one embodiment of the present disclosure. A programmable semiconductor device, also known as a field programmable gate array or a Programmable Logic Device (PLD), includes a device identifier (device identifier) that enables the programmable semiconductor device to be verified using a set of embedded signature registers. For example, the device identifier can be implemented by a bitstream to verify authenticity of the field programmable gate array. The basic concepts of the exemplary embodiments of the present disclosure are not changed even if one or more blocks (circuits or elements) are added to or removed from the block diagram 170.

The Programmable semiconductor device includes an array of configurable logic Blocks 180 surrounded by Input/Output Blocks (IOs) 182, and Programmable Interconnect Resources (PIR) 188 including vertical interconnects and horizontal interconnects extending between the logic Blocks 180 and the rows and columns of the Input/Output Blocks 182. The Programmable interconnect resources 188 may also include Interconnect Array Decoders (IADs) or Programmable Interconnect Arrays (PIA). The terms "programmable interconnect resource," "interconnect array decoder," and "programmable interconnect array" are used interchangeably hereinafter.

In one example, each logic block includes a programmable combinational circuit and a selectable output register programmed to implement at least a portion of a user logic function. Programmable interconnects, connections, or channels of interconnect resources may use various switch configurations to create signal paths between logic blocks 180 for performing logic functions. Each input/output block 182 is programmable to selectively use input/output pins (not shown) of the programmable semiconductor device.

In one embodiment, the Programmable semiconductor device may be Partitioned into a plurality of Programmable Partitioned regions (Programmable Partitioned regions PPRs) 172, where each Programmable Partitioned Region 172 includes a portion of a logic block 180, some Programmable interconnect resources 188, and an input/output block 182. The benefit of organizing the programmable semiconductor devices into a plurality of programmable partition regions 172 is one or more of: optimizing storage capacity, facilitating power management and facilitating management of network output.

A bitstream is a binary sequence (or file) that contains programming information for a field programmable gate array or programmable logic device. The bitstream is created to reflect the user's logical functions and certain control information. In order for a field programmable gate array or programmable logic device to operate properly, at least a portion of the registers or flip-flops in the field programmable gate array need to be programmed or configured before they can operate. The bit stream is used as input configuration data of the field programmable gate array, and the read-back bit stream is a read-back binary sequence used for verifying the current configuration state of the field programmable gate array in use. The read-back bitstream is a binary sequence that is generated by retrieving bit values from at least a portion of a field programmable gate array register currently in use.

The benefit of using a read-back bitstream is to validate the field programmable gate array in use and to backup configuration information for emergency recovery.

In an exemplary embodiment, the aforementioned first register may be used to output a stored fixed value during a bitstream read-back to verify the identity of the programmable integrated circuit device.

Fig. 1B is a block diagram illustrating a programmable semiconductor device or programmable integrated circuit having an embedded signature register for identifying device identification according to one embodiment of the present disclosure. To simplify the discussion above, the terms "programmable semiconductor device", "programmable integrated circuit", "field programmable gate array", "programmable logic device" all refer to the same or similar devices and are used interchangeably hereinafter. The block diagram 100 includes a plurality of programmable partition regions 102 and 108, a programmable interconnect array 150, and a region input/output port 166. Any one or more of the programmable partition regions 102-108 includes a control unit 110 (or controller), a memory 112, and a logic block 116. The control unit 110 may be configured as a single control unit, and likewise, the memory 112 may be configured as a single memory to store the configuration. The basic concepts of the exemplary embodiments of the present disclosure are not changed even if one or more blocks (circuits or elements) are added to or removed from the block diagram 100.

The Logic Block 116 is also called a Configurable Function Unit (CFU) and includes a plurality of Logic Array Blocks (LABs) 118, which are also called Configurable Logic Units (CLUs). For example, each Logic array block 118 may be further organized to include a set of programmable Logic Elements (LEs), Configurable Logic Slices (CLSs), or macro cells (not shown in fig. 1B), or other circuitry. In one example, each logic array block may include 32-512 programmable logic elements. Input/output pins (not shown in fig. 1B), logic array blocks, and logic elements are connected by the programmable interconnect array 150 and/or other buses (e.g., the first bus 114 or the second bus 162) to facilitate communication between the programmable interconnect array 150 and the programmable partition area 102 and 108.

Each logic element may include programmable circuitry such as a product-term matrix (product-term matrix) in addition to look-up tables and registers. Logic elements are also referred to as cells, Configurable Logic Blocks (CLBs), slices, Configurable functional units, macro-cells, and the like. Each logic element may be independently configured to perform sequential and/or combinational logic operations. The basic concept of a programmable semiconductor device does not change even if one or more blocks and/or circuits are added to or removed from the programmable semiconductor device.

The control unit 110, also referred to as configuration logic, may be one single control unit. For example, the control unit 110 manages and/or configures individual logic elements in the logic array block 118 based on configuration information stored in the memory 112. Some input/output ports or input/output pins are configurable, so they can be configured as input pins and/or output pins. Some input/output pins are programmed as bi-directional pins (including input and output) while other input/output pins are programmed as uni-directional pins (including input or output). A control unit, such as unit 110, is used to process and/or manage programmable semiconductor device operations in accordance with a system clock signal.

The logic block 116 includes a plurality of logic array blocks that can be programmed by an end user. Each logic array block contains a plurality of logic elements, where each logic element further includes one or more look-up tables (LUTs) and one or more registers (or D-type flip-flops or latches). Depending on the application, the logic element may be configured to perform user-specific functions based on a predefined library of functions implemented by the configuration software. In some applications, the programmable semiconductor device may also include a fixed set of circuits for performing specific functions. For example, fixed circuitry includes, but is not limited to, one or more of the following: a processor, a Digital Signal Processing (Digital Signal Processing DSP) unit, a wireless transceiver, and the like.

The programmable interconnect array 150 is coupled to the logic block 116 through various internal buses, such as a first bus 114 or a second bus 162. Wherein the first bus 114 is a bus between the memory 112 and/or the controller 110 and the programmable interconnect array 150, and the second bus 162 is a bus between the logic block 116 and the programmable interconnect array 150. In some embodiments, either the first bus 114 or the second bus 162 is part of the programmable interconnect array 150. Each bus includes channels or conductors for transmitting signals. The terms "channel," "routing channel," "wire," "bus," "connection," and "interconnect" all refer to the same or similar connections and are used interchangeably herein. The programmable interconnect array 150 may also be used to receive data from and/or transmit data to other devices, either directly or indirectly through input/output pins and logic array blocks.

Memory 112 may include a plurality of memory cells located on programmable partition areas. In addition, the memory 112 may be combined into a single memory cell in a programmable semiconductor device. In one embodiment, memory 112 is a non-volatile memory storage unit that can be used for both configuration and user storage. The non-volatile memory storage unit may be, but is not limited to, a magnetoresistive random access memory, a flash memory, a ferroelectric random access memory, and/or a phase change memory (or chalcogenide random access memory). To simplify the preceding discussion, magnetoresistive random access memory is used as an exemplary non-volatile memory in all remaining discussions. Depending on the application, a portion of memory 112 may be designated, allocated, or configured as a Block Random Access Memory (BRAM) for storing large amounts of data in a programmable semiconductor device.

The programmable semiconductor device includes a plurality of programmable logic blocks 116 interconnected by a programmable interconnect array 150, wherein each programmable logic block is further divided into a plurality of logic array blocks 118. In an embodiment, each logic array block 118 may include a plurality of look-up tables, multiplexers, and registers. During configuration, the user programs a truth table for each look-up table to implement the desired logic function. Each Logic array block may be further organized to include a plurality of Logic Elements (LEs), which may be considered Configurable Logic Cells (CLC) or Configurable Logic slices. For example, a four-input (16-bit) lookup table receives the logical values of the input lookup table from the routing fabric (not shown in FIG. 1B). Based on a truth table programmed into the lookup table during configuration of the programmable semiconductor device, a combined output is generated from the programmed truth table of the lookup table in accordance with the logic values input into the lookup table. The combined output is then latched or buffered into a register or flip-flop before the end of the clock cycle.

In one embodiment, a set of signature registers is embedded and/or distributed across multiple logic elements. For example, the configured logic element may configure one or more registers dedicated to signature register 120. The function of the device identification is to allow a user or application to determine the identity of the field programmable gate array in use via a set of signature registers 120. For example, a user may use the device identification to determine whether a counterfeit device has been detected.

Accordingly, the benefit of using device identification is to improve overall device accountability and integrity by eliminating low quality counterfeit devices.

Fig. 2 is a block diagram 200 illustrating a routing logic or routing fabric including a programmable interconnect array containing route signature information according to one embodiment of the present disclosure. The block diagram 200 includes control logic 206, a programmable interconnect array 202, input/output pins 230, and a clock unit 232. Control logic 206, similar to the control unit shown in FIG. 1B, provides various control functions including channel assignment, differential input/output criteria, and clock management. The control logic 206 may comprise volatile memory, non-volatile memory, or a combination of volatile and non-volatile memory devices for storing information such as configuration data. In one embodiment, the control logic 206 may be integrated into the programmable interconnect array 202. The basic concepts of the exemplary embodiments of the present disclosure are not changed even if one or more blocks (circuits or elements) are added to or removed from the block diagram 200.

The input/output pins 230 connected to the programmable interconnect array 202 via the third bus 231 comprise a plurality of programmable input/output pins configured to receive and/or transmit signals to external devices. For example, each programmable input/output pin may be configured as an input pin, an output pin, or a bi-directional pin. Depending on the application, the input/output pins 230 may be incorporated into the control logic 206.

In one example, the clock unit 232 is coupled to the programmable interconnect array 202 via a fourth bus 233, receiving various clock signals from other components (e.g., a clock tree circuit or a global clock oscillator). In one example, the clock unit 232 generates clock signals for implementing input/output communications in response to the system clock and the reference clock. Depending on the application, for example, clock unit 232 provides a clock signal including the reference clock(s) to programmable interconnect array 202.

In one aspect, the programmable interconnect array 202 may be organized into an array scheme including a first lane group 210 and a second lane group 220, a fifth bus 204, and input/output buses (e.g., 154, 164, 174, 184 in the figure). The first lane group 210, the second lane group 220 are used to facilitate routing information between logic blocks based on a programmable interconnect array configuration. The channel groups may also communicate with each other via an internal bus or connection, such as the fifth bus 204. In the embodiment shown in FIG. 2, the first channel group 210 includes four Interconnected Array Decoders (IADs) 212 and 218. The second channel group 220 includes four interconnect array decoders 222 and 228. The function of the interconnect array decoder is to provide configurable routing resources for data transmission. In other embodiments, the number of interconnected array decoders in the channel group can be set according to the needs, which is not limited by the present disclosure.

Interconnect array decoders, such as interconnect array decoder 212, include routing multiplexers or selectors for routing signals between one or more of the following devices: input/output pins, feedback outputs, and logic array block inputs to reach their destinations. For example, an interconnect array decoder may include up to 36 multiplexers, which may be placed in four groups, where each group includes nine rows of multiplexers. The number of interconnected array decoders within each lane group is a function of the number of logic elements within the logic array block.

In one embodiment, programmable interconnect array 202 designates a special interconnect array decoder (e.g., interconnect array decoder 218) to facilitate routing of the tag information. For example, interconnect array decoder 218 is designated to handle connection and/or routing signature information during bit stream transmission. Additional interconnect array decoders may be allocated for processing device identification.

An advantage of using the interconnect array decoder 218 as a designated signature route in a programmable interconnect array is to facilitate routing of signature information for device identification in a programmable semiconductor device or field programmable gate array.

Fig. 3A is a block diagram 300 illustrating a configurable logic block, configurable logic element, or configurable logic slice 302 including an embedded signature register in a programmable semiconductor device according to one embodiment of the disclosure. The block diagram 300 includes a plurality of lookup tables 310-318, a multiplexer (multiplexer units) 330-338, an embedded signature register 320-322, and a register 326-328. In one example, multiplexers 330 and 338 are used in response to inputs to a lookup table, such as a logical value input to a lookup table (including, but not limited to, one or more of the following signals: A;)_1-z、B_1-z、......X_1-z、Data_1-z) And selecting the intermediate output. The basic concepts of the exemplary embodiments of the present disclosure are not changed even if one or more blocks (circuits or elements) are added to or removed from the block diagram 300.

In one aspect, the embedded signature registers 320-322, also referred to as signature registers, signature latches, or signature flip-flops, are used to store product-related signatures that can identify the authenticity of the device or to store fixed values that can identify whether the device is under attack. For example, the embedded signature registers 320 and 322 store a set of fixed values or signature information generated by the signature generator. The stored fixed value is subsequently retrieved during a bitstream read. In one embodiment, the fixed value or signature information may be passed through a look-up table (e.g., signal A in FIG. 3A)₁、B₁、......X₁-A_m、B_m、......X_m) The signature register is input, or the signature register may be input through a data line (e.g., data 1-data m in fig. 3A). In one embodiment, the embedded signature registers 320 and 322 may not be visible to a user or client.

As shown in fig. 3A, when the registers 320-322 are configured as signature registers, the outputs of the look-up tables LUT310-LUT312 corresponding to the registers may be configured to be stored in other registers or directly output.

The registers 326-328 are a set of registers corresponding to various lookup tables (e.g., the lookup tables 316-318). The function of the registers 326-328 is to latch the output generated by the lookup table 316-318 before the end of the clock cycle. Depending on the application, registers 326 and 328 are used for data integrity.

The function of the lookup table is essentially a truth table that generates an output based on a set of inputs, such as a1.. X1. In one example, a truth table determines or models how a combinational logic should behave. The look-up table typically comprises a set of logical and gates and a set of multiplexers capable of accepting four (4) to sixty-four (64) inputs.

Components or building blocks, such as look-up tables, multiplexers, and registers (or flip-flops) located within a field programmable gate array create logic function blocks that provide logic implementations to perform certain user-defined functions, such as, but not limited to, one or more of the following: mathematical computation, network communication, artificial intelligence, power regulation, safety monitoring and the like. Registers and/or flip-flops provide a storage function that is capable of storing the output of the look-up table during a clock cycle.

The configurable logic element 302 includes a plurality of lookup tables 310-318, multiplexers 330-338, embedded signature registers 320-322, and registers 326-328. In an exemplary embodiment, the embedded signature registers 320 and 322 may store signature information or fixed values that serve as device identifiers via the sixth bus 308. In one aspect, the device identifier may be written into each signature register (e.g., registers 320 and 322) by itself or otherwise under the control of a host controller (e.g., which may be an external controller), with the value written into the signature register being used as the value for device identification. In one example, the device identifier is configured to generate a set of fixed values from the bit values of an incoming bit stream (incoming bit stream) and a clock signal. In one example, the random number may be generated in response to an incoming bit stream and a clock signal. In one embodiment, the random number is used as or to generate a fixed value or signature information.

In one aspect, a portion of the lookup table in the configurable logic element 302 has no associated registers to latch the output or result because these registers are dedicated toThus acting as a signature register. For example, the lookup table 310-312 has no corresponding register or flip-flop to latch the output or result because the registers 320-322 may be allocated as a set of signature registers. Lookup tables 310-312 may be any number of lookup tables capable of receiving any number of inputs, respectively, such as A_1-mTo X_1-m. In addition, another portion of the lookup table (e.g., lookup table 316 and 318) is configured with a corresponding register (e.g., register 326 and 328). The lookup tables 316-318 may be any number of lookup tables capable of receiving any number of inputs, such as A_1-nTo X_1-z。

The advantage of using device identification is that it can identify the field programmable gate array manufacturer identity or model number from the signature information detected from the read-back bitstream.

Fig. 3B is a block diagram 301 illustrating a configurable logic slice 303 containing an embedded signature register in a programmable semiconductor device according to one embodiment of the present disclosure. Configurable logic slice 303 includes a plurality of lookup tables 310-318, multiplexers (Muxes)330-338, embedded signature registers 356-358, and registers 350-352. In one example, multiplexers 330 and 338 are used in response to inputs to the look-up table (e.g., including one or more of the following signals: A)_1-z、B_1-z、......X_1-z、Data_1-z) An intermediate output is selected. The block diagram 301 is similar to the block diagram 300 shown in FIG. 3A, except that the embedded signature registers 356 and 358 in the block diagram 301 are located at different physical locations than the embedded signature registers 320 and 322 in the block diagram 300. The basic concepts of the exemplary embodiments of the present disclosure are not changed even if one or more blocks (circuits or elements) are added to or removed from the block diagram 301.

The embedded signature registers 356 and 358, also known as signature registers, signature latches, or signature flip-flops, are used to identify the authenticity of the device in use. For example, embedded signature registers 356 and 358 store a set of fixed values or signature information generated by the signature generator. The stored fixed value or signature information is subsequently retrieved during a bitstream read. In one embodiment, embedded signature registers 356 and 358 are not visible to the user or customer. The physical location in which the embedded signature register is housed within the configurable logic slice 303 may be any location. For example, the physical location for housing the embedded signature registers may be at the top of configurable logic slice 303 (the location shown in fig. 3A), the middle of configurable logic slice 303, the bottom of configurable logic slice 303 (the location shown in fig. 3B), or a random location arranged in a disorderly order between the embedded signature registers and the registers.

The registers 350-352 are a set of registers corresponding to various lookup tables (e.g., 310-312). The function of the registers 350-352 is to latch the outputs generated by the lookup tables 310-312, respectively, before the end of the clock cycle. Depending on the application, registers 350 and 352 are used for data integrity.

An advantage of allowing flexible allocation of embedded signature registers within a configurable logic slice is that it may improve application-based resource allocation efficiency.

In an exemplary embodiment, the signature registers may be changed periodically, for example, during a first cycle, registers 356 and 358 are used as signature registers, and during a second cycle, the signature registers are changed to 350 and 352. By periodically changing the position of the signature register, the effect of attack prevention can be increased.

FIG. 4 is a block diagram 400 illustrating a configurable logic element, configurable logic slice, or logic array block 402 containing a signature register, 406, according to one embodiment of the present disclosure. In one embodiment, configurable logic element 402 includes a configurable routing cell or Programmable interconnect Array 426, eight (8) lookup tables 410-. In one embodiment, registers 430-432 are designated or allocated as embedded signature registers and are thus not visible to the end user. The basic concepts of the exemplary embodiments of the present disclosure are not changed even if one or more blocks (circuits or elements) are added to or removed from the block diagram 400. In this embodiment, the number of lookup tables in the configurable logic element 402 is merely exemplary.

In one embodiment, the configurable logic element 406 includes a configurable routing cell or programmable interconnect array 456, six (6) lookup tables 460-470, a programmable mux array 458, and registers 480-490. In one embodiment, registers 480-. Registers 480-. In this embodiment, the number of lookup tables in the configurable logic device 406 is merely exemplary.

In one embodiment, a programmable semiconductor device includes a configurable logic block, a routing connection array, and a configuration memory for performing programmed logic functions according to a user's bit stream. For example, each configurable logic block includes one or more configurable logic elements, where each configurable logic element includes a plurality of look-up tables and registers. In one example, a look-up table is configured to generate one or more output signals from a set of input signals.

The registers coupled to the lookup table are arranged such that one register corresponds to one lookup table. In one example, a first register (e.g., register 430) corresponding to a first lookup table (e.g., lookup table 410) is designated for storing a fixed value to facilitate identification of the programmable integrated circuit device. A second register (e.g., register 434) corresponding to a second lookup table (e.g., lookup table 414) is configured to store the second output signal generated by the second lookup table (e.g., lookup table 414). For example, a fixed value or signature information is read during a bitstream read-back process to verify device identification.

In one embodiment, a third register (e.g., register 432) corresponding to a third lookup table (e.g., lookup table 412) is designated as an embedded signature register to facilitate device identification. A fourth register (e.g., register 436) corresponding to the fourth lookup table (e.g., lookup table 416) is configured to store the fourth output signal generated by the fourth lookup table (e.g., lookup table 416). Alternatively, in another embodiment, a third register (e.g., signature register 432) corresponding to a third lookup table, such as lookup table 412, is designated for storing a fixed value or signature information to facilitate identification of the programmable integrated circuit device. In addition, a fourth register (e.g., register 436) corresponding to a fourth lookup table (e.g., lookup table 416) is designated for storing signature information to facilitate identification of the programmable integrated circuit device.

In one aspect, a fifth register (e.g., register 438) corresponding to a fifth lookup table (e.g., lookup table 418) stores the fifth output signal generated by the fifth lookup table, and a sixth register (e.g., register 440) corresponding to a sixth lookup table (e.g., lookup table 420) stores the sixth output signal generated by the sixth lookup table. A seventh register (e.g., register 442) corresponding to the seventh lookup table (e.g., lookup table 422) stores the seventh output signal generated by the seventh lookup table, and an eighth register (e.g., register 444) corresponding to the eighth lookup table (e.g., lookup table 424) stores the eighth output signal generated by the eighth lookup table. In one example, a plurality of multiplexers in programmable multiplexing array 428 are used to provide internal routing between lookup table 410 and 424 and registers 430 and 444.

Depending on the application, the number of embedded signature registers allocated in a programmable semiconductor device or field programmable gate array may be programmable by the manufacturer. For example, the selected configurable logic block may include at least two embedded signature registers.

FIG. 5 is a block diagram 500 illustrating configurable logic elements (configurable logic slices or logic array blocks) 502 containing signature registers 504 according to one embodiment of the present disclosure. Configurable logic element 502 is similar to configurable logic element 402 except that the embedded signature registers are physically located differently. In one embodiment, the configurable logic element 502 includes a configurable routing cell or programmable interconnect array 426, eight (8) lookup tables 410 & 424, a programmable mux array 428, and registers 432 & 444 & 530 & 534. In one embodiment, registers 530 and 534 are designated or allocated as embedded signature registers and are thus not visible to the end user. The basic concepts of the exemplary embodiments of the present disclosure are not changed even if one or more blocks (circuits or elements) are added to or removed from the block diagram 500. In this embodiment, the number of lookup tables in the configurable logic element 502 is merely exemplary.

In one embodiment, the configurable logic element 504 includes a configurable routing cell or programmable interconnect array 456, six (6) lookup tables 460 and 470, a programmable mux array 458, and registers 480 and 490 and 584. In one embodiment, registers 480-. When the registers 480 & 482 and 584 are used to process fixed values or signature information, the lookup table 460 & 464 has no corresponding register for latching the output. In this embodiment, the number of lookup tables in the configurable logic element 504 is merely exemplary.

Depending on the application, the manufacturer can selectively program the total number of embedded signature registers and the location of the embedded signature registers onto the manufactured field programmable gate array device before shipping to the end user. The advantage of being able to flexibly allocate the required signature registers is that the efficiency of resource allocation can be improved. For example, for some applications, it may not be necessary to specifically set a set of signature registers, so a total number of zero embedded signature registers may be allocated or programmed.

Fig. 6A is a logic block diagram 600 illustrating a recognition device identification process according to one embodiment of the present disclosure. The block diagram 600 includes an exemplary configurable logic element 602, a read-back bitstream 606, a Device identification component 618, and a Predefined Device Identification (PDI) block 628. In one example, the configurable logic element 602 includes four (4) lookup tables 610 and 616, including two (2) embedded signature registers 620 and two (2) regular registers 622. The basic concepts of the exemplary embodiments of the present disclosure are not changed even if one or more blocks (circuits or elements) are added to or removed from the block diagram 600.

In one aspect, the bitstream 606 can be a read-back bitstream initiated by a manufacturer's host for verifying the device or programmable semiconductor device in use. When a bitstream read-back command is initiated, the programmable semiconductor device or field programmable gate array, along with the host controller (if any), begins to generate a read-back bitstream or bitstream 606. In one embodiment, the bitstream 606 includes signature information in predefined physical bit locations (bit locations) or fixed values 608. Signature information or fixed values 608 are retrieved from the embedded signature registers in various configurable logic blocks in the programmable semiconductor device. For example, the bitstream 606 contains signature information or fixed values retrieved from the embedded signature register 620. Although the signature register 620 corresponds to the lookup tables 610 and 612 or is located near the lookup tables 610 and 612 at a physical location, the lookup tables 610 and 612 have no register or flip-flop for latching output in the current configuration.

In one embodiment, the device identification component 618 includes a signature extractor 630, a signature database 632, and a comparator 636. In other embodiments, additional components may be added, such as, but not limited to, a random number decoder, a signature-bit location (signature-bit location) allocator, a clock component, and so forth. In operation, signature extractor 630 retrieves or extracts signature information or fixed values from various physical locations of bitstream 606, as indicated by reference numeral 658. The comparator 636 compares the extracted value from the signature extractor 630 with a predefined or preloaded signature from a signature Database (DB) 632 and generates a comparison result. The pre-defined or pre-loaded signature is a manufacturer signature used to identify the device identification or chip manufacturer. For example, a predefined signature represented by a sequence of numbers is represented by a high cloud semiconductor^TMThe GW1NZ series products were manufactured. The comparison result is then used to reference to a predefined device identification block 628.

In one embodiment, predefined device identification block 628 includes, but is not limited to, one or more of the following sub-blocks: a verification sub-block 650, a manufacturing identification sub-block 652, an unknown device sub-block 654, and other sub-blocks 656. The verified sub-block 650 provides information to verify whether the programmable semiconductor device or field programmable gate array device used is authentic or manufactured by a verified company. Manufacturer identification sub-block 652 is used to report the source of the manufacturer that produced the programmable semiconductor device based on the comparison. The unknown device 654 is used to report the discovered counterfeit device based on the comparison. Depending on the application, in one embodiment, other sub-blocks 656 may be used to verify the identity of the end user based on the comparison. Different applications may generate different reports in response to the comparison.

During operation, a process that can determine the identity of a programmable logic device through a set of specified registers located in a plurality of logic blocks (e.g., embedded signature registers 620) includes receiving a verification bitstream back from the programmable logic device that reflects a fixed value (signature information) and current programming information in the programmable logic device. For example, the validation bitstream is referred to as the read-back bitstream 606. Upon identifying the signature bit positions (e.g., position 608) associated with a set of hidden signature registers embedded in the validation bitstream, the fixed identification value is extracted from the signature bit positions 608 associated with the set of signature registers. The fixed identification value is then compared to a predefined identification value of the programmable logic device to identify the authenticity of the programmable logic device. The signature registers are located in one or more configurable logic blocks. In an exemplary embodiment, the fixed identification value may be decrypted according to a host-defined timestamp, depending on the application. The fixed identification value is decrypted, for example, in response to a random value generated from the initial input bit stream and a system clock. The decryption method depends on the encryption method, the embodiment only provides an exemplary way of encrypting and decrypting by using the system clock, and in other embodiments, encryption and decryption can be performed in other ways to increase the anti-attack effect.

An advantage of using a device identification module (which may be software, hardware, or a combination of software and hardware) is that device verification and device specification identification may be possible.

Fig. 6B is a logic block diagram 660 illustrating a generation process of a fixed value or signature information for identifying device identification according to one embodiment of the present disclosure. Block 660 illustrates an exemplary process of generating a read-back bitstream 680 based on an incoming bitstream 662. When the incoming bitstream 662 arrives at the programmable semiconductor device, pre-signed bit information 666 located at a particular physical bit position within the incoming bitstream 662 is extracted from the bitstream 662, as indicated by reference numeral 664. The combiner 668 combines or collects the pre-signature bit information 666 from the incoming bit stream 662 and forwards the combined pre-signature bit information to the incoming bit block 670. In one embodiment, the pre-signature bit information 666 is also forwarded to a digital generator 672 for generating a random number based on at least a portion of the pre-signature bit information 666. The pre-signature bit information 666 is located at the same physical bit position as the signature information or a fixed value.

In one embodiment, the identification generator 676 generates a set of signature information that is retrieved from various embedded signature registers in various configurable logic blocks in the programmable semiconductor device. In addition, identification generator 676 can also generate signature information in response to the random number generated by digital generator 672 and system clock 674. In one aspect, the digital generator 672 is used to reduce unauthorized data tampering by generating a random number based on at least a portion of the pre-signed bit information.

In this example, the aforementioned signature generator includes the identification generator 676, or includes the number generator 672 and the identification generator 676.

In one embodiment, after generating the signature information, assigner 678 assigns a bit sequence representing the signature information to bit positions 682 of read-back bitstream 680. The read-back bit stream 680 is then forwarded (e.g., during the identification process) to the manufacturer's host (or the user's host) to determine the authenticity of the programmable semiconductor device or field programmable gate array in use. The basic concepts of the exemplary embodiments of the present disclosure are not changed even if one or more blocks (circuits or elements) are added to or removed from block diagram 660.

Fig. 7 is a schematic diagram 700 illustrating a system or computer using one or more programmable semiconductor devices including a set of signature registers according to one embodiment of the present disclosure. Computer system 700 includes a processing unit 701, an interface bus 712, and an Input/Output (Input/Output IO) unit 720. The processing unit 701 includes a processor 702, a main memory 704, a system bus 711, a static storage device 706, a bus control unit 705, input/output elements (devices) 730, and a field programmable gate array 785. The basic concept of the exemplary embodiments of the present disclosure does not change even if one or more blocks (circuits or elements) are added to or removed from fig. 7.

System for controlling a power supplyThe bus 711 is used to transfer information between the various components and the processor 702 for data processing. The processor 702 may be any of a variety of general purpose processors, embedded processors, and microprocessors, for exampleAn embedded processor, Core^TMDuo、Core^TMQuad、Pentium^TMMicroprocessor, Motorola^TM68040、Serial processors or Power PCs^TMA microprocessor.

Main memory 704, which may include multiple levels of cache memory, stores frequently used data and instructions. The main Memory 704 may be a Random Access Memory (RAM), a Magnetic Random Access Memory (MRAM), or a flash Memory. Static memory 706, which may be Read Only Memory (ROM), is coupled to system bus 711 for storing static information and/or instructions. The bus control unit 705 is coupled to the system bus 711 and the interface bus 712, and controls components that can use the buses, such as the main memory 704 or the processor 702. The bus control unit 705 manages communication between the system bus 711 and the interface bus 712. Mass storage memory or Solid State Disk (Solid State Disk) such as a magnetic Disk, optical Disk, hard drive, floppy Disk, cd-rom, or flash memory, is used to store large amounts of data.

In one embodiment, the input/output unit 720 includes a display 721, a keyboard 722, a cursor control device 723, and a low power programmable logic device 725. The display device 721 may be an organic light emitting semiconductor (OLED) display device, a liquid crystal device, a Cathode Ray Tube (Cathode Ray Tube CRT), a touch screen display, or other suitable display device. The display 721 is used to project or display an image (e.g., an image of a graphical reticle). The keyboard 722 may be a conventional alphanumeric input device for communicating information between the computer system 700 and a computer operator. Another type of user input device is cursor control device 723, such as a conventional mouse, touch mouse, trackball, or other type of cursor for communicating between system 700 and a user.

Programmable logic device 725 is coupled to interface bus 712 to provide configurable logic functions to local and remote computers or servers over a wide area network. The programmable logic device 725 and/or the field programmable gate array 785 include one or more device identification modules for verifying the authenticity of the device. In one example, the programmable logic device 725 may be used in a modem or network interface device to facilitate communication between the computer 700 and a network. Computer system 700 may be coupled to a plurality of servers through a network infrastructure, as discussed below.

Fig. 8 is a block diagram 800 illustrating various applications of a programmable semiconductor device that may be used in a cloud environment, containing a signature register capable of recognizing a device identification of a field programmable gate array, according to one embodiment of the present disclosure. Block diagram 800 illustrates a system capable of providing digital processing functions and network communication functions including the programmable integrated circuit device described above, wherein the programmable integrated circuit device includes configurable logic blocks, at least one of which includes a plurality of look-up tables and a plurality of registers in one-to-one correspondence with the plurality of look-up tables, wherein at least one of the registers is configured to store a fixed value for use in identifying the programmable integrated circuit device. In an exemplary embodiment, the system includes an artificial intelligence server 808, a communications network 802, a switching network 804, the Internet 850, and a portable electrical device 815-. In one aspect, a programmable semiconductor device with device identification functionality may be used in one or more of the following environments: artificial intelligence server, portable electrical equipment and switched network. The Network or cloud Network 802 may be a wide Area Network, a Metropolitan Area Network (MAN), a Local Area Network (LAN), a satellite/terrestrial Network, or a combination of wide Area, Metropolitan Area, and Local Area networks. The basic concepts of the exemplary embodiments of the present disclosure are not changed even if one or more blocks (or networks) are added to or removed from the block diagram 800.

The Network 802 includes a plurality of Network nodes (not shown in fig. 8), where each node may include a Mobility Management Entity (MME), a Radio Network Controller (RNC), a Serving Gateway (S-GW), a Packet Data Network Gateway (P-GW), or a home agent to provide various Network functions. Network 802 is coupled to internet 850, artificial intelligence server 808, base station 812, and switching network 804. In one embodiment, the server 808 may include a Machine Learning Computer (MLC) 806.

Switching network 804, which may be referred to as a packet core network, includes cell sites 822 and 826 capable of providing wireless access communication, such as third generation (3)^rdgeneration, 3G), fourth or fifth generation cellular networks. In one example, Switching network 804 comprises an Internet Protocol (IP) and/or Multiprotocol Label Switching (MPLS) based network capable of operating at the Open Systems Interconnection Basic Reference Model (OSI Model) layer for information transfer between clients and network servers. In one embodiment, the switching network 804 is logically coupled 820 with a plurality of users and/or portable devices 816 within a geographic area via a cellular and/or wireless network. The geographic region may refer to a school, city, metropolitan area, country, continent, etc.

The base station 812, also referred to as a cell site, node B, or eNodeB, includes a radio tower that can be coupled to various User Equipments (UEs) and/or Electrical User Equipments (EUEs). The terms "user equipment" and "electrical user equipment" refer to similar portable devices, which are used interchangeably. Such as a user device or a portable electronic device (portable electronic device,PED) may be one or more of the following devices that communicate wirelessly: cellular phone 815, notebook computer 817,816. Tablet computer and819. the handheld device may also be a smart phone, e.g. a mobile phoneA mobile phone,A mobile phone,Cell phones, etc. In one example, the base station 812 facilitates network communications between mobile devices, such as the portable handheld device 815 and 819, over wired and wireless communication networks. The base station 812 may include additional radio towers and other landline switching circuitry.

The Internet 850 is a computing network that uses Transmission Control Protocol/Internet Protocol (TCL/IP) to provide communication between geographically separated devices. In one example, the internet 850 is coupled to a provider server 838 and a satellite network 830 through a satellite receiver 832. In one example, satellite network 830 may provide a number of functions, such as wireless communication and Global Positioning System (GPS). Wireless Application Protocol (WAP) may be used in many areas such as, but not limited to, smart phones 815-.

Exemplary embodiments of the present disclosure include various processing steps, which will be described below. The steps of an embodiment may be embodied in machine or computer executable instructions. The instructions may be used to cause a general-purpose or special-purpose system that is programmed with the instructions to perform the steps of the exemplary embodiments of the present disclosure. Additionally, the steps of exemplary embodiments of the present disclosure may be performed by specific hardware components that contain hardwired logic for performing the steps, or by any combination of programmed computer components and custom hardware components.

Fig. 9 is a flow diagram 900 illustrating a process of identifying a device identification according to one embodiment of the present disclosure. At block 902, a process for enabling verification of an identity of a field programmable gate array in use via a set of designated registers on a plurality of configurable logic blocks includes obtaining a first bit stream. The first bit stream is based on user-defined logic.

At block 904, the first bitstream is forwarded to a field programmable gate array to configure the field programmable gate array. For example, a first bitstream is transmitted from a host computer to a system containing a field programmable gate array over a communication network.

At block 906, a verification command is initiated to the field programmable gate array, asking the field programmable gate array to return a second bit stream or read-back bit stream reflecting current configuration information of the field programmable gate array, the bit stream including a set of fixed identification values or signature information obtained from a set of signature registers. In one aspect, the signature registers are located in various configurable logic blocks and/or configurable logic elements. In one example, register storage values, signature information, or fixed values are read from a plurality of signature registers in various configurable logic elements or configurable logic blocks. In one example, predefined or fixed values are stored and retrieved from a plurality of signature registers in various configurable logic elements. At least a portion of the signature registers in the configurable logic block are hidden from the user for logic configuration.

At block 908, the process can determine or verify the identity of the field programmable gate array in use after a comparison is made between the first bit stream and the second bit stream based on a set of fixed identification values or signature information extracted from the second bit stream or the read-back bit stream. For example, the field programmable gate array or the programmable semiconductor device may be identified as a counterfeit device in response to a mismatch between the predefined field programmable gate array signature and the signature embedded in the second bitstream. The process may also determine a manufacturer and a device model number of the production field programmable gate array in response to a comparison between a predefined field programmable gate array signature and a signature embedded in the read-back bitstream.

While exemplary embodiments of the present disclosure have been shown and described, it will be obvious to those skilled in the art that, based upon the teachings herein, that changes and modifications may be made without departing from exemplary embodiments of the present disclosure and its broader aspects. Therefore, the appended claims are intended to encompass within their scope all such changes and modifications as are within the true spirit and scope of this exemplary embodiment of the disclosure.

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Method and system for providing FPGA device identification by a set of embedded signature registers

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