阅读说明：本技术 基于局部总线的数据采集系统的并行化存储实现方法 (Parallelization storage implementation method of data acquisition system based on local bus ) 是由 黄瀚霆 于 2020-06-01 设计创作，主要内容包括：本发明公开了基于局部总线的数据采集系统的并行化存储实现方法,包括处理器、FPGA、外部存储器,所述处理器通过引出局部总线与所述FPGA直接相连,所述外部存储器通过总线与所述FPGA直接相连,FPGA对局部总线的控制数据流的截获和并行转发,并行存储文件系统包括主存储器、影子存储器、文件管理、垃圾回收、坏块管理、写入均衡。本发明无需构建新型文件系统,采用主存储器和影子存储器结构,只需对原有文件系统和设备底层驱动做微小改动,适用范围广,可移植性强。(The invention discloses a parallelization storage realization method of a data acquisition system based on a local bus, which comprises a processor, an FPGA and an external memory, wherein the processor is directly connected with the FPGA by leading out the local bus, the external memory is directly connected with the FPGA by a bus, the FPGA intercepts and transmits control data streams of the local bus in parallel, and a parallelization storage file system comprises a main memory, a shadow memory, file management, garbage recovery, bad block management and write-in balance. The invention does not need to construct a novel file system, adopts the main memory and shadow memory structure, only needs to slightly change the original file system and the device bottom layer drive, and has wide application range and strong transportability.)

1. The parallelization storage implementation method of the data acquisition system based on the local bus is characterized by comprising the following steps: comprises a processor, an FPGA and an external memory, wherein the processor is directly connected with the FPGA by leading out a local bus, the external memory is directly connected with the FPGA by a bus,

the FPGA intercepts and transmits control data flow of a local bus in parallel, and the parallel storage file system comprises a main memory, a shadow memory, file management, garbage collection, bad block management and write-in balance.

2. The method for implementing parallelized storage of the local bus based data acquisition system of claim 1, wherein: the processor is a CPU (central processing unit), and transmits a data area and a tag area of the file system to the FPGA through the GPCM and the FCM respectively; the FPGA inserts the data cached in the asynchronous FIFO into a corresponding control flow by capturing the control time sequence of the FCM to the Flash so as to realize the parallel Flash write operation; after receiving the FCM reading command, the FPGA forwards all the flashes in parallel through an external memory, intercepts the returned data of the flashes, splices the data and stores the data into an asynchronous FIFO (first in first out) of the FPGA; and reading the complete data stored in the asynchronous FIFO by the processor, thereby completing the parallel reading operation of the Flash.

3. The method for implementing parallelized storage of the local bus based data acquisition system of claim 1, wherein: the processor is a central processing unit PowerPC with a simplified instruction set architecture, and the FPGA inserts a large amount of data cached by the FPGA in SOC development into a corresponding control flow to realize parallel writing in the Flash by capturing the control time sequence of the FCM to the Flash; after receiving the FCM reading command, the FPGA forwards all the flashes in parallel through an external memory, and then intercepts and splices the returned data of the flashes and stores the data into an asynchronous FIFO of the FPGA; and reading the complete data stored in the asynchronous FIFO by the PowerPC, thereby completing the parallel reading operation of the Flash.

4. The method for implementing parallelized storage of the local bus based data acquisition system of claim 3, wherein: the FPGA captures the FCM, and the FCM transmitted by the processor can be captured directly.

5. The method for implementing parallelized storage of the local bus based data acquisition system of claim 1, wherein: the FPGA monitors the local bus by registering a data stream signal in two stages, and judges and divides a data area and a label area of the data stream according to the communication time sequence specification of the local bus; and the FPGA respectively injects the data of the cache area to be stored into the data area of the data stream, and simultaneously forwards the plurality of external memories connected in parallel to finish the quick writing of the data stream.

6. The method for implementing parallelized storage of the local bus based data acquisition system of claim 1, wherein: the number of the external memories is a plurality, the external memories comprise a main memory and a shadow memory, only one memory is used as the main memory, other memories are used as the shadow memories, and the device parameters except the page capacity in the operating system are the same as the main memory parameters; the shadow memory is only used as a data carrier and is directly controlled and uniformly managed by the FPGA; all scan operations of the file system are directed only to main memory.

7. The method for implementing parallelized storage of the local bus based data acquisition system of claim 1, wherein: the file management, garbage collection, bad block management and write balancing are realized in the following way, when the file management, garbage collection and write balancing are carried out by the file system of the processor, the main memory is only required to be scanned and relevant instructions are executed according to the original rule for controlling the single external memory. When the processor manages the bad blocks, the processor needs to communicate with the FPGA by means of GPIO, the FPGA monitors all the memories, when any memory has a hardware error, the FPGA informs the processor, the processor marks the corresponding position into the bad block, simultaneously executes a series of instructions, and finally the FPGA forwards a control data stream sent by the processor in parallel so as to write the bad block information into a BBT (base band table) of a main memory and move data in the bad blocks of the main memory and a shadow memory to a safe position.

Technical Field

The invention relates to the technical field of embedded system engineering, in particular to a parallelization storage implementation method of a data acquisition system based on a local bus.

Background

In recent years, the rapid development and wide application of machine learning technology and wireless communication technology have raised the heat of interconnection of intelligent terminals and everything, and data is important in the artificial intelligence era. Embedded data acquisition systems are favored for their high performance, low power consumption, and low cost. In order to make full use of the powerful computing performance and stable communication interface of the processor, and simultaneously flexibly define a data path and realize an extensible interface, a heterogeneous system consisting of an FPGA and the processor becomes a popular solution.

At present, two main solutions for storage management of an embedded data acquisition system are provided, namely an external memory is directly controlled by a processor and the external memory is directly controlled by an FPGA.

(1) The external memory being directly controlled by the processor

This solution implements management and access operations to the external memory by using the memory control interface provided by the processor, written by the operating system (file system) by calling the underlying driver to the control word of the corresponding interface. The scheme does not need to modify the kernel and the file system of the operating system and generate a memory control time sequence by self, thereby reducing the development difficulty. However, the processor cannot fully utilize the flexible configurable interface of the data acquisition system and the parallelism of the data stream during operation, the memory access speed of the system is reduced, and the operation load of the processor is increased.

(2) External memory controlled directly by FPGA

This solution allows direct access to external memory by the FPGA by building a memory controller within the FPGA. The scheme utilizes the flexibility of the FPGA interface to realize the customized control and access of the memory. However, it is very difficult to construct a memory controller in an FPGA, and how to perform information interaction with a processor is also considered in addition to the most basic control operations of reading, writing, erasing, and the like, and more importantly, it is necessary to verify whether the design is stable, usually, an experienced engineer is required to perform post-simulation on the FPGA engineering, and a copied timing constraint is added to deploy the FPGA in an actual application scenario. The scheme greatly increases the technical difficulty and the development period in the development of the embedded system, which is also the reason why the scheme is not mainly applied.

Disclosure of Invention

In view of the above-mentioned drawbacks and deficiencies of the prior art, it is desirable to provide a parallelized storage implementation method for a local bus based data acquisition system.

According to the technical scheme provided by the embodiment of the application, the method for realizing the parallelization storage of the data acquisition system based on the local bus comprises a processor, an FPGA and an external memory, wherein the processor is directly connected with the FPGA by leading out the local bus, the external memory is directly connected with the FPGA by a bus, the FPGA intercepts and forwards control data streams of the local bus in parallel, and a parallel storage file system comprises a main memory, a shadow memory, file management, garbage recovery, bad block management and write-in balance.

In the invention, the processor is a CPU central processing unit, and the processor transmits a data area and a tag area of a file system to an FPGA through a GPCM and an FCM respectively; the FPGA inserts the data cached in the asynchronous FIFO into a corresponding control flow by capturing the control time sequence of the FCM to the Flash so as to realize the parallel Flash write operation; after receiving the FCM reading command, the FPGA forwards all the flashes in parallel through an external memory, intercepts the returned data of the flashes, splices the data and stores the data into an asynchronous FIFO (first in first out) of the FPGA; and reading the complete data stored in the asynchronous FIFO by the processor, thereby completing the parallel reading operation of the Flash.

In the invention, the processor is a central processing unit PowerPC with a simplified instruction set architecture, and the FPGA inserts a large amount of data cached by the FPGA in SOC development into a corresponding control flow to realize parallel writing in the Flash by capturing the control time sequence of the FCM to the Flash; after receiving the FCM reading command, the FPGA forwards all the flashes in parallel through an external memory, and then intercepts and splices the returned data of the flashes and stores the data into an asynchronous FIFO of the FPGA; and reading the complete data stored in the asynchronous FIFO by the PowerPC, thereby completing the parallel reading operation of the Flash.

In the invention, the FPGA captures the FCM, and the FCM transmitted by the processor can be directly captured and also captured.

In the invention, the FPGA monitors a local bus by registering a data stream signal in two stages, and judges and divides a data area and a label area of a data stream according to the communication time sequence specification of the local bus; and the FPGA respectively injects the data of the cache area to be stored into the data area of the data stream, and simultaneously forwards the plurality of external memories connected in parallel to finish the quick writing of the data stream.

In the invention, the number of the external memories is a plurality, the external memories comprise a main memory and a shadow memory, only one memory is used as the main memory, other memories are used as the shadow memory, and the device parameters except page capacity in the operating system are the same as the main memory parameters; the shadow memory is only used as a data carrier and is directly controlled and uniformly managed by the FPGA; all scan operations of the file system are directed only to main memory.

In the invention, the file management, garbage collection, bad block management and write balancing are realized in the following way, and the processor file system only needs to scan and execute related instructions to the main memory according to the original rule for controlling a single external memory when performing the file management, the garbage collection and the write balancing. When the processor manages the bad blocks, the processor needs to communicate with the FPGA by means of GPIO, the FPGA monitors all the memories, when any memory has a hardware error, the FPGA informs the processor, the processor marks the corresponding position into the bad block, simultaneously executes a series of instructions, and finally the FPGA forwards a control data stream sent by the processor in parallel so as to write the bad block information into a BBT (base band table) of a main memory and move data in the bad blocks of the main memory and a shadow memory to a safe position.

To sum up, the beneficial effect of this application: in the invention, the speed of the processor for reading and writing the external memory is in direct proportion to the number of external memory blocks within the range of not exceeding the upper limit bandwidth of the local bus (the bandwidth of the communication between the processor and the asynchronous FIFO); under the mode that the FPGA serves as a data source, the speed of the processor writing into the external memory is in direct proportion to the number of external memory blocks and is not limited by the bandwidth of a local bus; a memory controller does not need to be built in the FPGA, development time is shortened, a simple, reliable and flexible data path mode is realized, a control mode that a processor serves as a data source to a memory can be realized, and a control mode that the FPGA serves as the data source to the memory can also be realized; the novel file system does not need to be constructed, the main memory and shadow memory structure is adopted, only the original file system and the device bottom layer drive need to be slightly changed, the application range is wide, and the transportability is strong.

Drawings

Other features, objects and advantages of the present application will become more apparent upon reading of the following detailed description of non-limiting embodiments thereof, made with reference to the accompanying drawings in which:

FIG. 1 is a flow chart of the structure of the CPU processor as a data source according to the present invention;

FIG. 2 is a flow chart of the structure of the FPGA of the present invention as a data source;

FIG. 3 is a flow chart of the steps for parallel forwarding of data streams by the main memory and the shadow memory.

Detailed Description

The present application will be described in further detail with reference to the following drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the relevant invention and not restrictive of the invention. It should be noted that, for convenience of description, only the portions related to the present invention are shown in the drawings.

It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict. The present application will be described in detail below with reference to the embodiments with reference to the attached drawings.

As shown in fig. 1, fig. 2, and fig. 3, the method for implementing parallelization storage of a data acquisition system based on a local bus includes a processor, an FPGA, and an external memory, where the processor is directly connected to the FPGA by leading out the local bus, the external memory is directly connected to the FPGA by a bus, the FPGA intercepts and parallelizes control data streams of the local bus, and the parallelization storage file system includes a main memory, a shadow memory, file management, garbage collection, bad block management (part of file system support), and write balancing (part of file system support). The FPGA monitors a local bus by registering a data stream signal in two stages, and judges and divides a data area and a label area (only containing file system information) of the data stream according to the communication time sequence specification of the local bus; and the FPGA respectively injects the data of the cache area to be stored into the data area of the data stream, and simultaneously forwards the plurality of external memories connected in parallel to finish the quick writing of the data stream.

As shown in fig. 1, the processor is a CPU central processing unit, and the processor transmits a data area and a tag area of a file system to the FPGA through a GPCM and an FCM, respectively; the FPGA inserts the data cached in the asynchronous FIFO into a corresponding control flow by capturing the control time sequence of the FCM to the Flash so as to realize the parallel Flash write operation; after receiving the FCM reading command, the FPGA forwards all the flashes in parallel through an external memory, intercepts the returned data of the flashes, splices the data and stores the data into an asynchronous FIFO (first in first out) of the FPGA; and reading the complete data stored in the asynchronous FIFO by the processor, thereby completing the parallel reading operation of the Flash.

As shown in fig. 2, the processor is a central processing unit PowerPC with a reduced instruction set architecture, and the FPGA inserts a large amount of data cached by the FPGA itself in SOC development into a corresponding control flow by capturing a control timing sequence of the FCM to the Flash to implement parallel writing to the Flash; after receiving the FCM reading command, the FPGA forwards all the flashes in parallel through an external memory, and then intercepts and splices the returned data of the flashes and stores the data into an asynchronous FIFO of the FPGA; and reading the complete data stored in the asynchronous FIFO by the PowerPC, thereby completing the parallel reading operation of the Flash. The FPGA captures the FCM, and the FCM transmitted by the processor can be captured directly.

As shown in fig. 3, the number of the external memories is several, the several external memories include a main memory and a shadow memory, only one memory is used as the main memory, the other memories are used as the shadow memory, and the device parameters except the page capacity in the operating system (file system) are all the same as the main memory parameters; the shadow memory is only used as a data carrier and is directly controlled and uniformly managed by the FPGA; all scan operations of the file system are directed only to main memory; since the writing position (page number) of the external memory is determined by the control word of the data stream, and the FPGA changes only the data area of the control data stream, the data contents stored in the memories are different when writing in parallel, but the writing position is the same, and the shadow memory can be regarded as the page capacity extension of the main memory. When the file management, garbage collection and write balancing are carried out by the file system of the processor, only the main memory needs to be scanned and relevant instructions are executed according to the original rule for controlling the single external memory. When the processor manages the bad blocks, the processor needs to communicate with the FPGA by means of GPIO, the FPGA monitors all the memories, when any memory has hardware errors, the FPGA informs the processor, the processor marks the corresponding position into the bad block, simultaneously executes a series of instructions, and finally the FPGA forwards control data flow sent by the processor in parallel so as to write the bad block information into BBT (bad block management report) of the main memory and move the data in the bad blocks of the main memory and the shadow memory to a safe position.