阅读说明：本技术 半导体存储装置以及方法 (Semiconductor memory device and method ) 是由 松并绚也 于 2019-08-08 设计创作，主要内容包括：实施方式提供了一种半导体存储装置,其中能执行适当的读取操作并由此延长了寿命。根据一种实施方式,半导体存储装置包括第一配线、连接至第一配线的第一电阻变化元件、连接至第一电阻变化元件的第一非线性元件、和连接至第一非线性元件的第二配线。在第一电阻变化元件的读取操作中,将第一配线和第二配线之间的电压增加到第一电压,并且在第一配线和第二配线之间的电压增加到第一电压之后,将第一配线和第二配线之间的电压增加到大于第一电压的第二电压。(Embodiments provide a semiconductor memory device in which a proper read operation can be performed and thus a lifetime is extended. According to one embodiment, a semiconductor memory device includes a first wiring, a first resistance change element connected to the first wiring, a first nonlinear element connected to the first resistance change element, and a second wiring connected to the first nonlinear element. In the reading operation of the first resistance change element, the voltage between the first wiring and the second wiring is increased to a first voltage, and after the voltage between the first wiring and the second wiring is increased to the first voltage, the voltage between the first wiring and the second wiring is increased to a second voltage larger than the first voltage.)

1. A semiconductor memory device, comprising:

a first wiring;

a first resistance change element connected to the first wiring;

a first nonlinear element connected to the first resistance change element; and

a second wiring connected to the first nonlinear element, wherein,

the semiconductor memory device is configured such that in a read operation of the first resistance change element,

increasing a voltage applied between the first wiring and the second wiring to a first voltage based on histograms corresponding to a plurality of read threshold voltages of the semiconductor memory device, an

In response to the voltage applied between the first wire and the second wire increasing to the first voltage, the voltage applied between the first wire and the second wire increasing to a second voltage greater than the first voltage based on the histogram.

2. The semiconductor memory device according to claim 1, further comprising:

a third wiring;

a second resistance change element connected to the third wiring;

a second nonlinear element connected to the second resistance change element; and

a fourth wiring connected to the second nonlinear element, wherein,

the semiconductor memory device is configured such that in a read operation of the second resistance change element,

a voltage applied between the third wiring and the fourth wiring is increased to the first voltage, an

Maintaining the voltage applied between the third wire and the fourth wire at a voltage less than the second voltage in response to the voltage applied between the third wire and the fourth wire increasing to the first voltage.

3. A semiconductor memory device, comprising:

a first wiring;

a first resistance change element connected to the first wiring;

a first nonlinear element connected to the first resistance change element;

a second wiring connected to the first nonlinear element; and

a peripheral circuit connected to the first wiring and the second wiring, wherein,

in a read operation of the first resistance change element, the peripheral circuit,

increasing a voltage between the first wiring and the second wiring until a current flowing through the first resistance change element is larger than a first current according to a histogram corresponding to a plurality of read threshold voltages of the semiconductor memory apparatus.

4. The semiconductor memory device according to claim 3,

the first resistance change element includes a magnetoresistive element.

5. The semiconductor memory device according to claim 3,

the first nonlinear element includes a chalcogen element.

6. The semiconductor memory device according to claim 3,

the first nonlinear element includes a metal layer containing at least one of silver (Ag) and copper (Cu), and an insulating layer.

7. The semiconductor memory device according to claim 1,

increasing the voltage applied between the first wire and the second wire to the second voltage in response to determining that the current flowing through the first non-linear element is less than a current threshold.

8. The semiconductor memory device according to claim 7,

the current threshold is predetermined based on a current-voltage characteristic of the first non-linear element.

9. The semiconductor memory device according to claim 2,

each of the first resistance change element and the second resistance change element includes a magnetoresistive element.

10. The semiconductor memory device according to claim 2,

each of the first nonlinear element and the second nonlinear element includes a chalcogen element.

11. The semiconductor memory device according to claim 2,

each of the first and second nonlinear elements includes a metal layer containing at least one of silver (Ag) and copper (Cu), or an insulating layer.

12. The semiconductor memory device according to claim 3,

further, the peripheral circuit may be configured to,

when it is determined that the current flowing through the first resistance change element is greater than the first current, a first signal is output when it is determined that the current flowing through the first resistance change element is less than a second current, and a second signal is output when it is determined that the current flowing through the first resistance change element is greater than the second current.

13. A method, comprising:

selecting a first voltage according to a histogram corresponding to a plurality of read threshold voltages of a plurality of memory cells, each memory cell including a resistance change element and a nonlinear element connected to each other;

applying the first voltage to one of the plurality of memory cells;

comparing a current flowing through the memory cell to a first current threshold;

selectively increasing the first voltage to a second voltage according to the histogram based on the comparison until the current is equal to or greater than the first current threshold; and

outputting a state of data stored in the memory cell based on a comparison of the current to a second current threshold.

Technical Field

Embodiments described herein relate generally to a semiconductor memory device.

Background

A known semiconductor memory device includes a first wiring, a first resistance change element connected to the first wiring, a first nonlinear element connected to the first resistance change element, and a second wiring connected to the first nonlinear element.

Disclosure of Invention

Drawings

Fig. 1 is a schematic block diagram showing the configuration of a part of a semiconductor memory apparatus according to a first embodiment.

Fig. 2 is a schematic circuit diagram showing the configuration of a part of the memory cell array.

Fig. 3 is a schematic perspective view showing the configuration of a part of the memory cell array.

Fig. 4 is a schematic perspective view of the storage unit.

Fig. 5 is a schematic cross-sectional view of a magnetoresistive element.

Fig. 6 is a timing chart showing a write operation according to the first embodiment.

Fig. 7 is a timing chart showing an erasing operation according to the first embodiment.

Fig. 8 is a schematic diagram showing current-voltage characteristics of the magnetoresistive element.

Fig. 9 is a schematic graph showing a current-voltage characteristic of the nonlinear element.

Fig. 10 is a schematic diagram showing a current-voltage characteristic of a memory cell.

Fig. 11 is a schematic graph showing a change in current-voltage characteristics of a memory cell.

Fig. 12 is a histogram showing a reading operation according to the first embodiment.

Fig. 13 is a flowchart showing the read operation.

Fig. 14 is a timing chart showing this read operation.

Fig. 15 is a schematic cross-sectional view of a magnetoresistive element according to a second embodiment.

Fig. 16 is a timing chart showing a write operation according to the second embodiment.

Fig. 17 is a schematic perspective view of a storage unit according to a modification.

Fig. 18 is a timing chart showing a read operation according to a modification.

Fig. 19 is a timing chart showing a read operation according to a modification.

Fig. 20 is a timing chart showing a read operation according to a modification.

Embodiments provide a semiconductor memory device in which a proper read operation can be performed and thus a lifetime is extended.

In summary, according to one embodiment, a semiconductor memory device includes a first wiring, a first resistance change element connected to the first wiring, a first nonlinear element connected to the first resistance change element, and a second wiring connected to the first nonlinear element. In the reading operation of the first resistance change element, a voltage between the first wiring and the second wiring is increased to a first voltage, and after the voltage between the first wiring and the second wiring is increased to the first voltage, the voltage between the first wiring and the second wiring is increased to a second voltage larger than the first voltage.

According to one embodiment, a semiconductor memory device includes a first wiring, a first resistance change element connected to the first wiring, a first nonlinear element connected to the first resistance change element, a second wiring connected to the first nonlinear element, and a peripheral circuit connected to the first wiring and the second wiring. In the read operation of the first resistance change element, the peripheral circuit increases the voltage between the first wiring and the second wiring until a current flowing through the first resistance change element is larger than a first current, and at a predetermined timing after the current flowing through the first resistance change element is larger than the first current, the peripheral circuit outputs a first signal when the current flowing through the first resistance change element is smaller than a second current, and outputs a second signal when the current flowing through the first resistance change element is larger than the second current.