阅读说明：本技术 一种减小FinFET随机静态存储器阈值电压失配的结构 (Structure for reducing threshold voltage mismatch of FinFET random static memory ) 是由 李勇 于 2021-06-28 设计创作，主要内容包括：本发明提供一种减小FinFET随机静态存储器阈值电压失配的结构,分别包括单元A和单元B的第一至第四单元；单元A和单元B分别包括：第一至第三Fin结构；第一至第三Fin结构设有第一栅极；单元B的第一栅极一端通过其第一栅极金属与单元A中靠近其第三Fin结构末端的第一金属连接；第一、第四单元的单元A中的第一、第二Fin结构的末端通过各自的第四金属相互连接；第一、第四单元的单元B中的第三Fin结构的首端通过各自的第三金属相互连接；第一、第四单元的单元B中的第一、第二Fin结构的首端通过各自的第二金属相互连接。本发明将最外层的Fin间距减小2～6nm,将扩大金属栅极端帽层的性能,同时不会牺牲层间介质层间隙填充窗口。(The invention provides a structure for reducing the threshold voltage mismatch of a FinFET random static memory, which comprises first to fourth units of a unit A and a unit B respectively; the unit a and the unit B respectively include: first to third Fin structures; the first to third Fin structures are provided with first grid electrodes; one end of the first grid of the unit B is connected with the first metal close to the tail end of the third Fin structure in the unit A through the first grid metal; the ends of the first and second Fin structures in the unit a of the first and fourth units are connected to each other through respective fourth metals; the head ends of the third Fin structures in the unit B of the first unit and the fourth unit are connected with each other through respective third metals; the head ends of the first and second Fin structures in the unit B of the first and fourth units are connected to each other through the respective second metals. The Fin interval of the outermost layer is reduced by 2-6 nm, the performance of the metal gate terminal cap layer is expanded, and meanwhile, a gap filling window of an interlayer dielectric layer is not sacrificed.)

1. A structure to reduce FinFET sram threshold voltage mismatch, comprising at least:

first to fourth units; the first to fourth units respectively include: unit A and unit B;

wherein the unit A and the unit B respectively comprise: first to third Fin structures; a first grid electrode crossing the first Fin structure, the second Fin structure and the third Fin structure is arranged on the first Fin structure, the second Fin structure and the third Fin structure; a second grid crossing the first Fin structure and the second Fin structure is arranged on the first Fin structure and the second Fin structure; a first metal which spans the first and second Fin structures and is connected with the tail end of the third Fin structure is arranged on the first and second Fin structures; the first metal is positioned between the first grid and the second grid along the longitudinal direction of the first Fin structure and the second Fin structure; the head ends of the first Fin structure and the second Fin structure are connected with each other through a second metal; the head end of the third Fin structure is connected with a third metal; the tail ends of the first Fin structure and the second Fin structure are connected with each other through a fourth metal;

one end of the first grid of the unit A is connected with the first metal close to the tail end of the third Fin structure in the unit B through the first grid metal of the unit A; one end of the first grid of the unit B is connected with the first metal close to the tail end of the third Fin structure in the unit A through the first grid metal of the unit B;

one ends of the second metal in the unit A of the first unit and the second unit are connected with each other; one ends of the second gates in the cell a of the first and second cells are connected to each other through a second gate metal;

the ends of the first and second Fin structures in the unit a of the first and fourth units are connected to each other through the respective fourth metal; the head ends of the third Fin structures in the unit B of the first and fourth units are connected to each other through respective third metals; the head ends of the first and second Fin structures in the unit B of the first and fourth units are connected to each other through the respective second metals.

2. The structure of claim 1, wherein: the ends of the first and second Fin structures in the unit a of the second and third units are connected to each other through the respective fourth metal; the head ends of the third Fin structures in the unit B of the second and third units are connected to each other through respective third metals; the head ends of the first and second Fin structures in the unit B of the second and third units are connected to each other through the respective second metals.

3. The structure of claim 1, wherein: one ends of the second metal in the unit A of the third and fourth units are connected with each other; one ends of the second gates in the cell a of the third and fourth cells are connected to each other through a second gate metal.

4. The structure of claim 1, wherein: the second metal of the first and second cells is connected to a voltage Vss.

5. The structure of claim 1, wherein: the second gate metal is connected to a word line.

6. The structure of claim 1, wherein: the fourth metal in the first to fourth cells connects a bit line.

7. The structure of claim 1, wherein: and the third metal in the first unit and the second unit is connected with a voltage Vdd.

8. The structure of claim 1, wherein: the first and second Fin structures of the cell A in the fourth cell and the first gate thereon form a pass gate.

9. The structure of claim 1, wherein: and the first Fin structure and the second Fin structure of the unit B in the fourth unit and the second grid electrode on the first Fin structure and the second Fin structure form a pull-down tube.

10. The structure of claim 1, wherein: and the distance between the first Fin structure and the second Fin structure in the first unit to the fourth unit is 2-6 nm.

Technical Field

The invention relates to the technical field of semiconductors, in particular to a structure for reducing threshold voltage mismatch of a FinFET random static memory.

Background

The threshold voltage mismatch has a great influence on the static noise margin of the SRAM, and from 65nm to 28nm, the larger the threshold voltage mismatch, the smaller the static noise margin. After the cover cap layer of the FinFET is deposited, metal annealing is carried out, the HK metal is oxidized by the metal annealing, and the K value of the HK metal can be increased, so that the performance of the device is improved; after the metal is annealed, the metal of the HK metal cap layer is crystallized, the work function change of the HK metal cap layer is obviously increased, and the threshold voltage becomes worse in mismatch.

Therefore, a new structure is required to solve the above problems.

Disclosure of Invention

In view of the above-mentioned shortcomings of the prior art, the present invention aims to provide a structure for reducing threshold voltage mismatch of a FinFET random static memory, which is used to solve the problem of how to reduce threshold voltage mismatch of a FinFET random static memory without introducing new problems in the prior art.

To achieve the above and other related objects, the present invention provides a structure for reducing threshold voltage mismatch of FinFET random static memory, comprising at least:

first to fourth units; the first to fourth units respectively include: unit A and unit B;

wherein the unit A and the unit B respectively comprise: first to third Fin structures; a first grid electrode crossing the first Fin structure, the second Fin structure and the third Fin structure is arranged on the first Fin structure, the second Fin structure and the third Fin structure; a second grid crossing the first Fin structure and the second Fin structure is arranged on the first Fin structure and the second Fin structure; a first metal which spans the first and second Fin structures and is connected with the tail end of the third Fin structure is arranged on the first and second Fin structures; the first metal is positioned between the first grid and the second grid along the longitudinal direction of the first Fin structure and the second Fin structure; the head ends of the first Fin structure and the second Fin structure are connected with each other through a second metal; the head end of the third Fin structure is connected with a third metal; the tail ends of the first Fin structure and the second Fin structure are connected with each other through a fourth metal;

one end of the first grid of the unit A is connected with the first metal close to the tail end of the third Fin structure in the unit B through the first grid metal of the unit A; one end of the first grid of the unit B is connected with the first metal close to the tail end of the third Fin structure in the unit A through the first grid metal of the unit B;

one ends of the second metal in the unit A of the first unit and the second unit are connected with each other; one ends of the second gates in the cell a of the first and second cells are connected to each other through a second gate metal;

the ends of the first and second Fin structures in the unit a of the first and fourth units are connected to each other through the respective fourth metal; the head ends of the third Fin structures in the unit B of the first and fourth units are connected to each other through respective third metals; the head ends of the first and second Fin structures in the unit B of the first and fourth units are connected to each other through the respective second metals.

Preferably, the ends of the first and second Fin structures in the unit a of the second and third units are connected to each other through the respective fourth metal; the head ends of the third Fin structures in the unit B of the second and third units are connected to each other through respective third metals; the head ends of the first and second Fin structures in the unit B of the second and third units are connected to each other through the respective second metals.

Preferably, one ends of the second metal in the unit a of the third and fourth units are connected to each other; one ends of the second gates in the cell a of the third and fourth cells are connected to each other through a second gate metal.

Preferably, the second metal of the first and second cells is connected to a voltage Vss.

Preferably, the second gate metal is connected to a word line.

Preferably, the fourth metal in the first to fourth cells connects a bit line.

Preferably, the third metal in the first and second cells is connected to a voltage Vdd.

Preferably, the first and second Fin structures of the cell a in the fourth cell and the first gate thereon constitute a pass gate.

Preferably, the first and second Fin structures of the cell B in the fourth cell and the second gate thereon form a pull-down tube.

Preferably, the distance between the first Fin structure and the second Fin structure in the first unit to the fourth unit is 2-6 nm.

As described above, the structure for reducing the threshold voltage mismatch of the FinFET random static memory of the present invention has the following beneficial effects: the SRAM bit cell with the Fin number of the pull-down tube and the pass gate larger than 1 comprises a single port and a double port, the Fin interval of the outermost layer is reduced by 2-6 nm, the performance of the cap layer of the metal gate terminal is expanded, and meanwhile, the gap filling window of an interlayer dielectric layer is not sacrificed. The shrinkage of the Fin structure outer spacing can lead to slight bridging problems with the pull-down tubes and pass gates, but can be addressed by reducing the extension profile.

Drawings

Fig. 1 shows a layout diagram of a FinFET sram in the present invention.

Detailed Description

The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.

Please refer to fig. 1. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.

The invention provides a structure for reducing the threshold voltage mismatch of a FinFET random static memory, which at least comprises the following components:

first to fourth units; the first to fourth units respectively include: unit A and unit B;

wherein the unit A and the unit B respectively comprise: first to third Fin structures; a first grid electrode crossing the first Fin structure, the second Fin structure and the third Fin structure is arranged on the first Fin structure, the second Fin structure and the third Fin structure; a second grid crossing the first Fin structure and the second Fin structure is arranged on the first Fin structure and the second Fin structure; a first metal which spans the first and second Fin structures and is connected with the tail end of the third Fin structure is arranged on the first and second Fin structures; the first metal is positioned between the first grid and the second grid along the longitudinal direction of the first Fin structure and the second Fin structure; the head ends of the first Fin structure and the second Fin structure are connected with each other through a second metal; the head end of the third Fin structure is connected with a third metal; the tail ends of the first Fin structure and the second Fin structure are connected with each other through a fourth metal;

one end of the first grid of the unit A is connected with the first metal close to the tail end of the third Fin structure in the unit B through the first grid metal of the unit A; one end of the first grid of the unit B is connected with the first metal close to the tail end of the third Fin structure in the unit A through the first grid metal of the unit B;

one ends of the second metal in the unit A of the first unit and the second unit are connected with each other; one ends of the second gates in the cell a of the first and second cells are connected to each other through a second gate metal;

the ends of the first and second Fin structures in the unit a of the first and fourth units are connected to each other through the respective fourth metal; the head ends of the third Fin structures in the unit B of the first and fourth units are connected to each other through respective third metals; the head ends of the first and second Fin structures in the unit B of the first and fourth units are connected to each other through the respective second metals.

As shown in fig. 1, fig. 1 is a layout diagram of a FinFET sram in the present invention. The first to fourth units are four units separated by a dotted line in fig. 1, wherein the first unit is a structure located at the upper right corner of the dotted line in fig. 1; the second unit is a structure positioned at the upper left corner of the dotted line in FIG. 1; the third unit is a structure positioned at the lower left corner of the dotted line in fig. 1; the fourth unit is a structure located at the lower right corner of the dotted line in fig. 1.

Wherein the unit A and the unit B respectively comprise: a first Fin structure 01, a second Fin structure 02, and a third Fin structure 03; a first gate GT1 crossing the first to third Fin structures is arranged on the first to third Fin structures; a second gate GT2 crossing the first Fin structure and the second Fin structure is arranged on the first Fin structure and the second Fin structure; a first metal M1 which spans the first Fin structure and the second Fin structure and is connected with the tail end of the third Fin structure is arranged on the first Fin structure and the second Fin structure; the first metal M1 is located between the first gate GT1 and the second gate GT2 in the longitudinal direction of the first and second Fin structures; the head ends of the first Fin structure and the second Fin structure are connected with each other through a second metal M2; the head end of the third Fin structure 03 is connected with a third metal M3; the ends of the first and second Fin structures are connected to each other by a fourth metal M4.

One end of the first gate GT1 of the cell a is connected to the first metal BM1 near the end of the third Fin structure in the cell B through its first gate metal GM 1; one end of the first gate BGT1 of the cell B is connected to the first metal M1 near the end of the third Fin structure 03 in the cell a through its first gate metal BGM 1;

one ends of the second metal M2 in the unit A of the first and second units are connected with each other; one ends of the second gates in the cell a of the first and second cells are connected to each other through a second gate metal GM 2;

the ends of the first and second Fin structures in the unit a of the first and fourth units are connected to each other by the respective fourth metal M4; the head ends of the third Fin structure 03 in the unit B of the first and fourth units are connected to each other by a respective third metal M3; the head ends of the first and second Fin structures in the unit B of the first and fourth units are connected to each other by the respective second metal M2.

Therefore, as can be seen from fig. 1, the connection manner of the corresponding components in the unit a and the unit B in the first to fourth units is reverse connection.

Further, the ends of the first and second Fin structures in the cell a of the second and third cells of this embodiment are connected to each other through the respective fourth metal M4; the head ends of the third Fin structures in the unit B of the second and third units are connected to each other through respective third metal M3; the head ends of the first and second Fin structures in the unit B of the second and third units are connected to each other by the respective second metal M2.

Further, in the present invention, one ends of the second metal M2 in the cell a of the third and fourth cells of the present embodiment are connected to each other; one ends of the second gates GT2 in the cells a of the third and fourth cells are connected to each other through a second gate metal GM 2.

Further, the second metal of the first and second cells of this embodiment is connected to a voltage Vss.

Further, the second gate metal of the present embodiment is connected to a word line WL. That is, the second gate metal in the first to fourth cells is connected to a word line WL.

Further, the fourth metal in the first to fourth cells of this embodiment is connected to a bit line BL. Further, the third metal in the first and second units of this embodiment is connected to a voltage Vdd.

Further, the first and second Fin structures of the cell a in the fourth cell of the present embodiment and the first gate thereon form a pass gate PG. Further, the first and second Fin structures of the unit B in the fourth unit of this embodiment and the second gate thereon form a pull-down tube PD.

Further, the first and second Fin structures in the first to fourth units of this embodiment have a spacing of 2-6 nm. That is, the first and second Fin structures in the first to fourth units and the unit A and the unit B have a spacing of 2-6 nm.

In summary, the SRAM bit cell with the Fin number of the pull-down tube and the pass gate larger than 1 comprises the single port and the double ports, the Fin distance of the outermost layer is reduced by 2-6 nm, the performance of the cap layer of the metal gate terminal is expanded, and meanwhile, the gap filling window of the interlayer dielectric layer is not sacrificed. The shrinkage of the Fin structure outer spacing can lead to slight bridging problems with the pull-down tubes and pass gates, but can be addressed by reducing the extension profile. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.

The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.