阅读说明：本技术 存储器单元、半导体器件及其形成方法 (Memory cell, semiconductor device and forming method thereof ) 是由 张志宇 林孟汉 杨世海 杨柏峰 林佑明 于 2021-04-30 设计创作，主要内容包括：存储器单元包括：晶体管,包括沿字线延伸的存储器膜；沟道层,沿存储器膜延伸,其中,存储器膜位于沟道层和字线之间；源极线,沿存储器膜延伸,其中,存储器膜位于源极线和字线之间；第一接触层,位于源极线上,其中,第一接触层接触沟道层和存储器膜；位线,沿存储器膜延伸,其中,存储器膜位于位线和字线之间；第二接触层,位于位线上,其中,第二接触层接触沟道层和存储器膜；以及隔离区域,位于源极线和位线之间。本申请的实施例还涉及半导体器件及其形成方法。(The memory cell includes: a transistor including a memory film extending along a word line; a channel layer extending along the memory film, wherein the memory film is located between the channel layer and the word line; a source line extending along the memory film, wherein the memory film is located between the source line and the word line; a first contact layer on the source line, wherein the first contact layer contacts the channel layer and the memory film; a bit line extending along the memory film, wherein the memory film is located between the bit line and the word line; a second contact layer on the bit line, wherein the second contact layer contacts the channel layer and the memory film; and an isolation region between the source line and the bit line. Embodiments of the present application also relate to semiconductor devices and methods of forming the same.)

1. A memory cell, comprising:

a semiconductor substrate; and

a transistor located over the semiconductor substrate, the transistor comprising:

a memory film extending along a word line, wherein the memory film contacts the word line;

a channel layer extending along the memory film, wherein the memory film is located between the channel layer and the word line;

a source line extending along the memory film, wherein the memory film is located between the source line and the word line;

a first contact layer on the source line, wherein the first contact layer contacts the channel layer and the memory film, wherein the first contact layer comprises a first material;

a bit line extending along the memory film, wherein the memory film is located between the bit line and the word line;

a second contact layer on the bit line, wherein the second contact layer contacts the channel layer and the memory film, wherein the second contact layer comprises a first material; and

an isolation region between the source line and the bit line.

2. The memory cell of claim 1, wherein the isolation region contacts the source line and the bit line.

3. The memory cell of claim 1, wherein the first contact layer extends between the source line and the isolation region, and wherein the second contact layer extends between the bit line and the isolation region.

4. The memory cell of claim 1, wherein the channel layer comprises the first material.

5. The memory cell of claim 1, wherein the first material has a higher carrier concentration than the channel layer.

6. The memory cell of claim 1, wherein the first material comprises an oxide.

7. The memory cell of claim 1, wherein the channel layer has a first thickness, the first contact layer has a second thickness, and the second contact layer has a second thickness, wherein the first thickness is different from the second thickness.

8. A semiconductor device, comprising:

a semiconductor substrate;

a first memory cell over the semiconductor substrate, the first memory cell comprising a first transistor, wherein the first transistor comprises:

a gate electrode including a portion of the first word line;

a first portion of ferroelectric material, wherein the first portion of ferroelectric material is located on sidewalls of the first word line; and

a first channel region on a sidewall of the first portion of the ferroelectric material;

a source line, wherein a first portion of the source line provides a first source/drain electrode for the first transistor;

a first contact layer on the source line, wherein the source line is in electrical contact with the first channel region through the first contact layer;

a bit line, wherein a first portion of the bit line provides a second source/drain electrode for the first transistor;

a second contact layer on the bit line, wherein the bit line is in electrical contact with the first channel region through the second contact layer;

a first dielectric material separating the source line and the bit line; and

a second memory cell located above the first memory cell.

9. The semiconductor device of claim 8, wherein the second memory cell comprises a second transistor, wherein the second portion of the source line provides a first source/drain electrode for the second transistor, and wherein the second portion of the bit line provides a second source/drain electrode for the second transistor.

10. A method of forming a semiconductor device, comprising:

patterning a first trench extending through the first conductive line;

depositing a memory film along sidewalls and a bottom surface of the first trench;

depositing an Oxide Semiconductor (OS) layer over the memory film, wherein the oxide semiconductor layer extends along the sidewalls and the bottom surface of the first trench;

depositing a first dielectric material on the oxide semiconductor layer, wherein the first dielectric material fills a remaining portion of the first trench;

patterning a second trench in the first dielectric material and the oxide semiconductor layer, wherein patterning the second trench exposes a sidewall surface of the memory film and a sidewall surface of the oxide semiconductor layer;

depositing a refill layer along sidewalls and a bottom surface of the second trench, wherein the refill layer physically contacts the sidewall surface of the oxide semiconductor layer;

depositing a conductive material on the refill layer, wherein the conductive material fills a remaining portion of the second trench;

patterning a third trench in the conductive material and the refill layer, wherein patterning the third trench exposes the sidewall surface of the memory film and a sidewall surface of the refill layer; and

depositing a second dielectric material in the third trench, wherein the second dielectric material fills the third trench.

Technical Field

Embodiments of the present application relate to memory cells, semiconductor devices, and methods of forming the same.

Background

As an example, semiconductor memory is used in integrated circuits for electronic applications including radios, televisions, cell phones, and personal computing devices. Semiconductor memories include two main categories. One type is volatile memory; the other type is nonvolatile memory. Volatile memory includes Random Access Memory (RAM), which can be further divided into two subcategories: static Random Access Memory (SRAM) and Dynamic Random Access Memory (DRAM). Both SRAM and DRAM are volatile because they lose their stored information when not powered.

On the other hand, the nonvolatile memory may store data thereon. One type of non-volatile semiconductor memory is ferroelectric random access memory (FeRAM or FRAM). Advantages of FeRAM include its fast write/read speed and small size.

Disclosure of Invention

Some embodiments of the present application provide a memory cell comprising: a semiconductor substrate; and a transistor located over the semiconductor substrate, the transistor comprising: a memory film extending along a word line, wherein the memory film contacts the word line; a channel layer extending along the memory film, wherein the memory film is located between the channel layer and the word line; a source line extending along the memory film, wherein the memory film is located between the source line and the word line; a first contact layer on the source line, wherein the first contact layer contacts the channel layer and the memory film, wherein the first contact layer comprises a first material; a bit line extending along the memory film, wherein the memory film is located between the bit line and the word line; a second contact layer on the bit line, wherein the second contact layer contacts the channel layer and the memory film, wherein the second contact layer comprises a first material; and an isolation region between the source line and the bit line.

Other embodiments of the present application provide a semiconductor device, including: a semiconductor substrate; a first memory cell over the semiconductor substrate, the first memory cell comprising a first transistor, wherein the first transistor comprises: a gate electrode including a portion of the first word line; a first portion of ferroelectric material, wherein the first portion of ferroelectric material is located on sidewalls of the first word line; and a first channel region on a sidewall of the first portion of the ferroelectric material; a source line, wherein a first portion of the source line provides a first source/drain electrode for the first transistor; a first contact layer on the source line, wherein the source line is in electrical contact with the first channel region through the first contact layer; a bit line, wherein a first portion of the bit line provides a second source/drain electrode for the first transistor; a second contact layer on the bit line, wherein the bit line is in electrical contact with the first channel region through the second contact layer; a first dielectric material separating the source line and the bit line; and a second memory cell located above the first memory cell.

Still further embodiments of the present application provide a method of forming a semiconductor device, comprising: patterning a first trench extending through the first conductive line; depositing a memory film along sidewalls and a bottom surface of the first trench; depositing an Oxide Semiconductor (OS) layer over the memory film, wherein the oxide semiconductor layer extends along the sidewalls and the bottom surface of the first trench; depositing a first dielectric material on the oxide semiconductor layer, wherein the first dielectric material fills a remaining portion of the first trench; patterning a second trench in the first dielectric material and the oxide semiconductor layer, wherein patterning the second trench exposes a sidewall surface of the memory film and a sidewall surface of the oxide semiconductor layer; depositing a refill layer along sidewalls and a bottom surface of the second trench, wherein the refill layer physically contacts the sidewall surface of the oxide semiconductor layer; depositing a conductive material on the refill layer, wherein the conductive material fills a remaining portion of the second trench; patterning a third trench in the conductive material and the refill layer, wherein patterning the third trench exposes the sidewall surface of the memory film and a sidewall surface of the refill layer; and depositing a second dielectric material in the third trench, wherein the second dielectric material fills the third trench.

Drawings

Various aspects of the invention are best understood from the following detailed description when read with the accompanying drawing figures. It should be noted that, in accordance with standard practice in the industry, various components are not drawn to scale. In fact, the dimensions of the various elements may be arbitrarily increased or decreased for clarity of discussion.

Fig. 1A, 1B, and 1C illustrate perspective, circuit, and top views of a memory array according to some embodiments.

Fig. 2, 3A, 3B, 4, 5, 6, 7, 8, 9, 10, 11, 12A, 12B, 13, 14A, 14B, 15, 16, 17A, 17B, 18A, 18B, 19A, 19B, 20, 21A, 21B, 21C, 22A, 22B, 22C, 23A, 23B, 23C, 24A, 24B, 24C, 25A, 25B, 25C, 26A, 26B, 26C, 27, 28A, 28B, 28C, and 28D illustrate varying views of intermediate steps in the fabrication of memory arrays according to some embodiments.

Fig. 29, 30, 31 and 32 show variant views of an intermediate step in the manufacture of a memory array according to some embodiments.

Fig. 33, 34, 35, and 36 show variant views of an intermediate step in the fabrication of a memory array according to some embodiments.

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to limit the invention. For example, in the following description, forming a first feature over or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. Moreover, the present disclosure may repeat reference numerals and/or characters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Also, spatially relative terms, such as "below …," "below …," "lower," "above …," "upper," and the like, may be used herein for ease of description to describe one element or component's relationship to another (or other) element or component as illustrated. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

Various embodiments provide a 3D memory array having a plurality of vertically stacked memory cells. Each memory cell includes a transistor having a word line region serving as a gate electrode, a bit line region serving as a first source/drain electrode, and a source line region serving as a second source/drain electrode. Each transistor also includes an insulating memory film (e.g., as a gate dielectric) and an Oxide Semiconductor (OS) channel region. In some embodiments, a trench is etched in which the source/drain electrodes of each transistor are formed. In some cases, the etch used for the trench may also etch some of the material of the OS channel region. Etching of the OS channel region can degrade device performance and reduce device efficiency. For example, such etching of the OS material may reduce the contact area between each source/drain electrode and the OS channel region, which may increase the contact resistance between the source/drain electrode and the OS channel region. In some embodiments of the invention, a refill layer of OS material is deposited within the trench prior to forming the source/drain electrodes. The refill layer compensates for possible etching of the OS channel region during trench formation and increases the contact area between the source/drain electrodes and the OS channel region. In some cases, the refill layer may be a different material than the OS channel region, and the refill layer material may be a material that reduces contact resistance between the OS channel region and the source/drain electrodes. In this way, the resistance between the source/drain electrodes and the OS channel region may be increased, which may improve device performance and efficiency.

1A, 1B, and 1C illustrate examples of memory arrays according to some embodiments. FIG. 1A illustrates an example of a portion of a memory array 200 in a three-dimensional view; FIG. 1B shows a circuit diagram of the memory array 200; and figure 1C illustrates a top view (e.g., plan view) of memory array 200 according to some embodiments. The memory array 200 includes a plurality of memory cells 202, which may be arranged in a grid of rows and columns. Memory cells 202 may be further vertically stacked to provide a three-dimensional memory array, thereby increasing device density. The memory array 200 may be disposed in a back end of line (BEOL) of a semiconductor die. For example, the memory array may be disposed in an interconnect layer of a semiconductor die, such as over one or more active devices (e.g., transistors, etc.) formed on a semiconductor substrate.

In some embodiments, memory array 200 is a memory array such as a NOR memory array, a NAND memory array, or the like. Other types of memory arrays are possible. Each memory cell 202 may include a transistor 204 having an insulating memory film 90 as a gate dielectric. The transistor 204 may be, for example, a Thin Film Transistor (TFT) or another type of transistor. In some embodiments, the gate of each transistor 204 is electrically coupled to a respective word line (e.g., conductive line 72), the first source/drain region of each transistor 204 is electrically coupled to a respective bit line (e.g., conductive line 106), and the second source/drain region of each transistor 204 is electrically coupled to a respective source line (e.g., conductive line 108), which electrically couples the second source/drain region to ground. Memory cells 202 in the same horizontal row of memory array 200 may share a common word line (e.g., 72), while memory cells 202 in the same vertical column of memory array 200 may share a common source line (e.g., 108) and a common bit line (e.g., 106).

The memory array 200 includes a plurality of vertically stacked conductive lines 72 (e.g., word lines) with a dielectric layer 52 disposed between adjacent conductive lines 72. The wires 72 extend in a direction parallel to the major surface of the underlying substrate (not explicitly shown in fig. 1A and 1B). The wires 72 may have a stepped configuration such that the lower wire 72 is longer than the upper wire 72 and extends laterally beyond the end points of the upper wire 72. For example, as shown in fig. 1A, a plurality of stacked layers of wires 72 are shown, with the topmost wire 72 being the shortest and the bottommost wire 72 being the longest. The respective lengths of the wires 72 may increase in a direction toward the underlying substrate. In this manner, portions of each of the conductive lines 72 can be accessed from above the memory array 200, and conductive contacts to exposed portions of each of the conductive lines 72 can be made (see, e.g., fig. 28A-28D).

Memory array 200 also includes a plurality of conductive lines 106 (e.g., bit lines) and conductive lines 108 (e.g., source lines). Wires 106 and 108 may each extend in a direction perpendicular to wire 72. Dielectric material 98 is disposed between and isolates adjacent conductive lines 106 and 108. The pairs of conductive lines 106 and 108 and the intersecting conductive line 72 define the boundaries of each memory cell 202, and the dielectric material 102 is disposed between and isolates adjacent pairs of conductive lines 106 and 108. In some embodiments, the wire 108 is electrically coupled to ground. Although fig. 1A shows a particular placement of the wires 106 relative to the wires 108, it should be understood that in other embodiments, the placement of the wires 106 and 108 may be reversed.

As discussed above, the memory array 200 may also include an Oxide Semiconductor (OS) layer 92. OS layer 92 may provide a channel region for transistor 204 of memory cell 202. For example, when an appropriate voltage (e.g., higher than the respective threshold voltage (V) of the corresponding transistor 204) is applied through the corresponding conductor 72_th) The region of OS layer 92 that intersects conductive line 72 may allow current to flow from conductive line 106 to conductive line 108 (e.g., in the direction indicated by arrow 207). Thus, in some cases, the OS layer 92 may be considered a channel layer.

In some embodiments, the refill layer 96 at least partially surrounds the leads 106 and 108. Refill layer 96 may comprise the same material as OS layer 92, or may comprise one or more materials different from the material of OS layer 92. Refill layer 96 may extend between conductive line 106/108 and the surface of OS layer 92. In this manner, refill layer 96 may provide a contact between conductive line 106/108 and the channel region for transistor 204. Thus, in some cases, refill layer 96 may be considered a "contact layer" or "contact interface layer". In some cases, the combination of OS layer 92 and refill layer 96 may provide a channel region for transistor 204. The refill layer 96 is described in more detail below with respect to fig. 23A-23C.

Memory film 90 is disposed between conductive line 72 and OS layer 92, and memory film 90 may provide a gate dielectric for transistor 204. In some embodiments, memory film 90 comprises a ferroelectric material, such as hafnium oxide, hafnium zirconium oxide, silicon doped hafnium oxide, and the like. Thus, memory array 200 may also be referred to as a ferroelectric random access memory (FeRAM) array. Alternatively, the memory film 90 may be a film including two SiO_xSiN between layers_xA multi-layer structure of layers (e.g., an ONO structure), different ferroelectric materials, different types of memory layers (e.g., capable of storing bits), etc.

In embodiments where memory film 90 comprises a ferroelectric material, memory film 90 may be polarized in one of two different directions, and the polarization direction may be changed by applying an appropriate voltage difference across memory film 90 and generating an appropriate electric field. The polarization may be relatively local (e.g., typically contained within each boundary of the memory cell 202), and a continuous region of the memory film 90 may extend across multiple memory cells 202. Depending on the polarization direction of a specific region of the memory film 90, the threshold voltage of the corresponding transistor 204 changes, and a digital value (e.g., 0 or 1) can be stored. For example, when a region of the memory film 90 has a first electrical polarization direction, the corresponding transistor 204 may have a relatively low threshold voltage, and when a region of the memory film 90 has a second electrical polarization direction, the corresponding transistor 204 may have a relatively high threshold voltage. The difference between the two threshold voltages may be referred to as a threshold voltage drift. The larger threshold voltage drift makes it easier (e.g., less prone to errors) to read the digital value stored in the corresponding memory cell 202.

In such embodiments, to perform a write operation on the memory cell 202, a write voltage is applied across a portion of the memory film 90 corresponding to the memory cell 202. The write voltage may be applied, for example, by applying appropriate voltages to corresponding conductive line 72 (e.g., a word line) and corresponding conductive line 106/108 (e.g., a bit line/source line). By applying a write voltage across a portion of the memory film 90, the polarization direction of a region of the memory film 90 can be changed. Thus, the corresponding threshold voltage of the corresponding transistor 204 may also be switched from a low threshold voltage to a high threshold voltage, or vice versa, and a digital value may be stored in the memory cell 202. Because conductive line 72 intersects conductive lines 106 and 108, individual memory cells 202 may be selected for write operations.

In such an embodiment, to perform a read operation on memory cell 202, a read voltage (a voltage between a low threshold voltage and a high threshold voltage) is applied to corresponding conductive line 72 (e.g., a word line). Depending on the polarization direction of the corresponding region of memory film 90, transistor 204 of memory cell 202 may or may not be conductive. Accordingly, conductive line 106 may or may not discharge through conductive line 108 (e.g., a source line coupled to ground), and a digital value stored in memory cell 202 may be determined. Because conductive line 72 intersects conductive lines 106 and 108, individual memory cells 202 may be selected for read operations.

Fig. 1A also shows a reference cross section of a memory array 200 used in subsequent figures. Reference section B-B' is along the longitudinal axis of wire 72 and in a direction, for example, parallel to the direction of current flow of transistor 204. Reference section C-C 'is perpendicular to section B-B' and parallel to the longitudinal axis of wire 72. Reference section C-C extends through lead 106 and/or lead 108. Reference section D-D 'is parallel to reference section C-C' and extends through dielectric material 102. For clarity, the figures that follow refer to these reference sections.

In fig. 2, a substrate 50 is provided. The substrate 50 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., with p-type or n-type dopants) or undoped. Substrate 50 may be a wafer, such as a silicon wafer. Generally, an SOI substrate is a layer of semiconductor material formed on an insulating layer. The insulating layer may be, for example, a Buried Oxide (BOX) layer, a silicon oxide layer, or the like. An insulating layer is provided on a substrate, typically a silicon or glass substrate. Other substrates, such as multilayer or gradient substrates, may also be used. In some embodiments, the semiconductor material of substrate 50 may include silicon; germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium phosphide, and/or gallium indium arsenide phosphide; or a combination thereof.

Fig. 2 also shows circuitry that may be formed over substrate 50. The circuit includes active devices (e.g., transistors) at the top surface of the substrate 50. The transistor may include a gate dielectric layer 203 over the top surface of the substrate 50 and a gate electrode 205 over the gate dielectric layer 203. Source/drain regions 206 are disposed in the substrate 50 on opposite sides of the gate dielectric layer 203 and the gate electrode 205. Gate spacers 208 are formed along sidewalls of the gate dielectric layer 203 that separate the source/drain regions 206 from the gate electrode 205 by an appropriate lateral distance. In some embodiments, the transistor may be a planar Field Effect Transistor (FET), a fin field effect transistor (FinFET), a nano field effect transistor (nanoFET), or the like.

A first ILD 210 surrounds and isolates the source/drain regions 206, the gate dielectric layer 203 and the gate electrode 205, and a second ILD 212 is positioned above the first ILD 210. A source/drain contact 214 extends through the second ILD 212 and the first ILD 210 and is electrically coupled to the source/drain region 206, and a gate contact 216 extends through the second ILD 212 and is electrically coupled to the gate electrode 205. An interconnect structure 220 (comprising one or more stacked dielectric layers 224 and conductive features 222 formed in the one or more dielectric layers 224) is located over the second ILD 212, the source/drain contacts 214 and the gate contacts 216. Although fig. 2 shows two stacked dielectric layers 224, it should be understood that the interconnect structure 220 may include any number of dielectric layers 224 having conductive features 222 disposed therein. Interconnect structure 220 may be electrically connected to gate contact 216 and source/drain contact 214 to form a functional circuit. In some embodiments, the functional circuitry formed by interconnect structure 220 may include logic circuitry, memory circuitry, sense amplifiers, controllers, input/output circuitry, image sensor circuitry, and the like, or combinations thereof. Although fig. 2 discusses transistors formed over substrate 50, other active devices (e.g., diodes, etc.) and/or passive devices (e.g., capacitors, resistors, etc.) may also be formed as part of the functional circuitry.

In fig. 3A and 3B, a multilayer stack 58 is formed over the structure of fig. 2. For simplicity and clarity, the substrate 50, transistors, ILD, and interconnect structures 220 may be omitted from subsequent figures. Although multilayer stack 58 is shown as contacting dielectric layer 224 of interconnect structure 220, any number of intermediate layers may be disposed between substrate 50 and multilayer stack 58. For example, one or more additional interconnect layers including conductive features in insulating layers (e.g., low-k dielectric layers) may be disposed between the substrate 50 and the multilayer stack 58. In some embodiments, the conductive features may be patterned to provide power, ground, and/or signal lines for active devices on the substrate 50 and/or the memory array 200 (see fig. 1A and 1B).

Multilayer stack 58 includes alternating layers of conductive lines 72A-D (collectively referred to as conductive layers 54) and dielectric layers 52A-C (collectively referred to as dielectric layers 52). The conductive layer 54 may be patterned in a subsequent step to define conductive lines 72 (e.g., word lines). Conductive layer 54 may comprise a conductive material such as copper, titanium nitride, tantalum nitride, tungsten, ruthenium, aluminum, combinations thereof, and the like, and dielectric layer 52 may comprise an insulating material such as silicon oxide, silicon nitride, silicon oxynitride, combinations thereof, and the like. Conductive layer 54 and dielectric layer 52 may each be formed using, for example, Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), Physical Vapor Deposition (PVD), plasma enhanced CVD (pecvd), or the like. Although fig. 3A and 3B show a particular number of conductive layers 54 and dielectric layers 52, other embodiments may include a different number of conductive layers 54 and dielectric layers 52.

Fig. 4-12B are views of intermediate stages in fabricating a staircase structure of the memory array 200, according to some embodiments. Fig. 4 to 11 and 12B are shown along a reference section B-B' shown in fig. 1A. Fig. 12A is shown in a three-dimensional view.

In fig. 4, a photoresist 56 is formed over the multilayer stack 58. As discussed above, multilayer stack 58 may include alternating layers of conductive layers 54 (labeled 54A, 54B, 54C, and 54D) and dielectric layers 52 (labeled 52A, 52B, and 52C). The photoresist 56 may be formed by using a spin coating technique.

In fig. 5, photoresist 56 is patterned to expose multilayer stack 58 in region 60 while masking the remaining portions of multilayer stack 58. For example, the topmost layer of multilayer stack 58 (e.g., conductive layer 54D) may be exposed in region 60. The photoresist 56 may be patterned using acceptable photolithographic techniques.

In fig. 6, the exposed portions of multilayer stack 58 in regions 60 are etched using photoresist 56 as a mask. The etching may be any acceptable etching process, such as by wet or dry etching, Reactive Ion Etching (RIE), Neutral Beam Etching (NBE), and the like, or combinations thereof. The etching may be anisotropic. The etch may remove portions of conductive layer 54D and dielectric layer 52C located in region 60 and define opening 61. Because conductive layer 54D and dielectric layer 52C have different material compositions, the etchant used to remove the exposed portions of these layers may be different. In some embodiments, dielectric layer 52C serves as an etch stop layer when etching conductive layer 54D, and conductive layer 54C serves as an etch stop layer when etching dielectric layer 52C. Accordingly, portions of conductive layer 54E and conductive layer 54D may be selectively removed without removing the remaining layers of multilayer stack 58, and opening 61 may be extended to a desired depth. Alternatively, a timed etch process may be used to stop etching openings 61 after openings 61 reach a desired depth. In the resulting structure, conductive layer 54C is exposed in region 60.

In fig. 7, the photoresist 56 is trimmed to expose additional portions of the multilayer stack 58. The photoresist may be trimmed using acceptable photolithography techniques. As a result of trimming, the width of photoresist 56 is reduced and portions of multilayer stack 58 in regions 60 and 62 may be exposed. For example, a top surface of conductive layer 54C may be exposed in region 60, and a top surface of conductive layer 54D may be exposed in region 62.

In fig. 8, the portions of conductive layer 54D, dielectric layer 52C, conductive layer 54C, and dielectric layer 52B that are located in regions 60 and 62 are removed by an acceptable etch process using photoresist 56 as a mask. The etching may be any acceptable etching process, such as by wet or dry etching, Reactive Ion Etching (RIE), Neutral Beam Etching (NBE), and the like, or combinations thereof. The etching may be anisotropic. The etch may extend opening 61 further into multilayer stack 58. Because conductive layers 54D/54C and dielectric layers 52C/52B have different material compositions, the etchant used to remove the exposed portions of these layers may be different. In some embodiments, dielectric layer 52C serves as an etch stop layer when conductive layer 54D is etched; conductive layer 54C serves as an etch stop layer when dielectric layer 52C is etched; dielectric layer 52B acts as an etch stop layer when conductive layer 54C is etched; and conductive layer 54B serves as an etch stop layer when dielectric layer 52B is etched. Accordingly, portions of conductive layer 54D/54C and dielectric layer 52C/52B may be selectively removed without removing the remaining layers of multilayer stack 58, and opening 61 may be extended to a desired depth. Further, during the etching process, the unetched portions of conductive layer 54 and dielectric layer 52 act as masks for the underlying layers, and thus, the previous pattern of conductive layer 54D and dielectric layer 52C (see fig. 7) may be transferred to underlying conductive layer 54C and dielectric layer 52B. In the resulting structure, conductive layer 54B is exposed in region 60, and conductive layer 54C is exposed in region 62.

In fig. 9, the photoresist 56 is trimmed to expose additional portions of the multilayer stack 58. The photoresist may be trimmed using acceptable photolithography techniques. As a result of trimming, the width of photoresist 56 is reduced and portions of multilayer stack 58 in regions 60, 62, and 64 may be exposed. For example, a top surface of conductive layer 54B may be exposed in region 60; the top surface of conductive layer 54C may be exposed in region 62; and the top surface of conductive layer 542D may be exposed in region 64.

In fig. 10, portions of conductive layers 54D, 54C, and 54B located in regions 60, 62, and 64 are removed by an acceptable etch process using photoresist 56 as a mask. The etching may be any acceptable etching process, such as by wet or dry etching, Reactive Ion Etching (RIE), Neutral Beam Etching (NBE), and the like, or combinations thereof. The etching may be anisotropic. The etch may extend opening 61 further into multilayer stack 58. In some embodiments, dielectric layer 52C serves as an etch stop layer when conductive layer 54D is etched; dielectric layer 52B serves as an etch stop layer when conductive layer 54C is etched; and dielectric layer 52A serves as an etch stop layer when conductive layer 54B is etched. Accordingly, portions of conductive layers 54D, 54C, and 54B may be selectively removed without removing the remaining layers of multilayer stack 58, and opening 61 may be extended to a desired depth. Further, during the etching process, each of the dielectric layers 52 serves as a mask for the underlying layers, and thus, the previous pattern of dielectric layers 52C/52B (see fig. 9) may be transferred to the underlying conductive layers 54C/54B. In the resulting structure, dielectric layer 52A is exposed in region 60; exposing dielectric layer 52B in region 62; and dielectric layer 52C is exposed in region 64.

In fig. 11, the photoresist 56 may be removed, such as by an acceptable ashing or wet strip process. Thus, the stepped structure 68 is formed. The stair-step structure comprises a stack of alternating conductive layers 54 and dielectric layers 52. Lower conductive layer 54 is wider and extends laterally beyond upper conductive layer 54, and the width of each of conductive layers 54 increases in a direction toward substrate 50. For example, conductive layer 54A may be longer than conductive layer 54B; conductive layer 54B may be longer than conductive layer 54C; and conductive layer 54C may be longer than conductive layer 54D. Thus, in a subsequent process step, a conductive contact may be made from over the stair-step structure 68 to each of the conductive layers 54.

In fig. 12A and 12B, an inter-metal dielectric (IMD)70 is deposited over multilayer stack 58. IMD 70 may be formed of a dielectric material and may be deposited by any suitable method, such as CVD, plasma enhanced CVD (pecvd), or FCVD. The dielectric material may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron doped phosphosilicate glass (BPSG), Undoped Silicate Glass (USG), and the like. Other insulating materials formed by any acceptable process may be used. IMD 70 extends along the sidewalls of conductive layer 54 and the sidewalls of dielectric layer 52. In addition, IMD 70 may contact the top surface of each of dielectric layers 52.

As further shown in fig. 12A and 12B, a removal process is then applied to IMD 70 to remove excess dielectric material over multilayer stack 58. In some embodiments, a planarization process such as Chemical Mechanical Polishing (CMP), an etch back process, combinations thereof, and the like may be utilized. The planarization process exposes the multilayer stack 58 such that the top surfaces of the multilayer stack 58 and the IMD 70 are flush after the planarization process is complete.

Fig. 13-17B are views of intermediate stages in the manufacture of memory array 200 according to some embodiments. In fig. 13-17B, a multilayer stack 58 is formed, and a groove is formed in the multilayer stack 58, thereby defining a wire 72. Conductive lines 72 may correspond to word lines in memory array 200, and conductive lines 72 may further provide gate electrodes for the resulting transistors of memory array 200. Fig. 17A is shown in a three-dimensional view. Fig. 13 to 16 and 17B are shown along a reference section C-C' shown in fig. 1A.

In fig. 13, a hard mask 80 and photoresist 82 are deposited over multilayer stack 58. The hard mask 80 may comprise, for example, silicon nitride, silicon oxynitride, etc., which may be deposited by CVD, PVD, ALD, PECVD, etc. For example, the photoresist 82 may be formed by using a spin coating technique.

In fig. 14A and 14B, the photoresist 82 is patterned to form trenches 86. The photoresist may be patterned using acceptable photolithography techniques. For example, the photoresist 82 is exposed to light for patterning. After the exposure process, the photoresist 82 may be developed to remove either the exposed or unexposed portions of the photoresist, depending on whether a negative or positive resist is used, to define the pattern of trenches 86.

In fig. 15, the pattern of photoresist 82 is transferred to hard mask 80 using an acceptable etch process, such as by wet or dry etching, Reactive Ion Etching (RIE), Neutral Beam Etching (NBE), or the like, or combinations thereof. The etching may be anisotropic. Thus, trenches 86 are formed that extend through hard mask 80. For example, the photoresist 82 may be removed by an ashing process.

In fig. 16, the pattern of hard mask 80 is transferred to multilayer stack 58 using one or more acceptable etching processes, such as by wet or dry etching, Reactive Ion Etching (RIE), Neutral Beam Etching (NBE), or the like, or combinations thereof. The etching process may be anisotropic. Accordingly, trenches 86 and conductive lines 72 (e.g., word lines) extending through multilayer stack 58 are formed from conductive layer 54. Adjacent wires 72 may be separated from each other by etching trenches 86 through conductive layer 54. Subsequently, in fig. 17A and 17B, the hard mask 80 may then be removed by an acceptable process, such as a wet etch process, a dry etch process, a planarization process, combinations thereof, and the like. Due to the stepped shape of the multilayer stack 58 (see, e.g., fig. 12A), the wires 72 may have varying lengths that increase in a direction toward the substrate 50. For example, the wire 72A may be longer than the wire 72B; the wire 72B may be longer than the wire 72C; and wire 72C may be longer than wire 72D. In some embodiments, the trench 86 may be formed to have a width W1 in the range of about 50nm to about 100nm, although other widths are possible.

Fig. 18A-20 illustrate the formation and patterning of a channel region for transistor 204 (see fig. 1A) in trench 86. Fig. 18A and 19A are shown in three-dimensional views. Fig. 18B, 19B and 20 show cross-sectional views along the reference section C-C' of fig. 1A.

In fig. 18A and 18B, a memory film 90 is conformally deposited in the trench 86. The memory film 90 may be of a material capable of storing bits, such as a material that is capable of switching between two different polarization directions by applying an appropriate voltage difference across the memory film 90. For example, the polarization of the memory film 90 may change due to an electric field caused by applying a voltage difference.

For example, memory film 90 may be a high-k dielectric material, such as a hafnium (Hf) based dielectric material, or the like. In some embodiments, memory film 90 comprises a ferroelectric material, such as hafnium oxide, hafnium zirconium oxide, silicon doped hafnium oxide, and the like. In other embodiments, the memory film 90 may be a film comprising two SiO_xSiN between layers_xA multi-layer structure of layers (e.g., an ONO structure). In still other embodiments, memory film 90 may include different ferroelectric materials or different types of memory materials. The memory film 90 may be deposited by CVD, PVD, ALD, PECVD, etc. to extend along the sidewalls and bottom surfaces of the trench 86. In some embodiments, an annealing step may be performed after the deposition of the memory film 90. In some embodiments, the memory film 90 may be deposited to a thickness in the range of about 5nm to about 15nm, although other thicknesses are possible. In some embodiments, after deposition of memory film 90, trench 86 may have a width W2 in the range of about 40nm to about 70nm, although other widths are possible.

In fig. 19A and 19B, an OS layer 92 is conformally deposited in trench 86 over memory film 90. OS layer 92 comprises a material suitable for providing a channel region for a transistor (e.g., transistor 204, see fig. 1A). In some embodiments, OS layer 92 comprises an indium-containing material, such as indium oxide, indium gallium zinc oxide, indium titanium oxide, indium tungsten oxide, indium tin oxide, or the like, or combinations thereof. In other embodiments, different semiconductor materials than those examples may be used for the OS layer 92. For example, in other embodiments, the OS layer 92 may include zinc oxide or another type of oxide. The OS layer 92 may be deposited by CVD, PVD, ALD, PECVD, etc. OS layer 92 may extend along the sidewalls and bottom surface of trench 86 over memory film 90. In some embodiments, after depositing the OS layer 92, an annealing step (e.g., at a temperature in a range of about 300 ℃ to about 450 ℃) may be performed in an oxygen-related ambient to activate charge carriers of the OS layer 92. In some embodiments, OS layer 92 may be deposited to a thickness in the range of about 1nm to about 15nm, although other thicknesses are possible. In some embodiments, after depositing the OS layer 92, the trench 86 may have a width W3 in the range of about 20nm to about 70nm, although other widths are possible.

In fig. 20, a dielectric material 98 is deposited on the sidewalls and floor of trench 86 and over OS layer 92. Dielectric material 98 may include, for example, silicon oxide, silicon nitride, silicon oxynitride, etc., which may be deposited by CVD, PVD, ALD, PECVD, etc. As shown in fig. 20, a dielectric material 98 may fill the trench 86 and may cover the multilayer stack 58.

In fig. 21A-21C, a removal process is then applied to dielectric material 98, OS layer 92, and memory film 90 to remove excess material over multilayer stack 58. In some embodiments, a planarization process such as Chemical Mechanical Polishing (CMP), a grinding process, an etch back process, combinations thereof, and the like may be utilized. The planarization process may expose the multilayer stack 58 such that the top surface of the multilayer stack 58 is flush after the planarization process is complete. Fig. 21A shows a three-dimensional view, fig. 21B shows a corresponding top view of the structure shown in fig. 21A, and fig. 21C shows a cross-sectional view through the reference section C-C' shown in fig. 1A and 21B.

Fig. 22A-26C illustrate intermediate steps in fabricating conductive lines 106 and 108 (e.g., source lines and bit lines) in memory array 200. Conductive lines 106 and 108 may extend in a direction perpendicular to conductive line 72 so that individual cells of memory array 200 may be selected for read and write operations. Fig. 22A, 23A, 24A, 25A, and 26A show three-dimensional views. Fig. 22B, 23B, 24B, 25B, and 26B show top views. Fig. 22C, 23C and 24C show cross-sectional views along the reference section C-C' shown in fig. 1A and, for example, fig. 22B. FIGS. 25C and 26C show cross-sectional views along reference section D-D' shown in FIG. 1A and, for example, FIG. 25B.

In fig. 22A, 22B and 22C, trenches 100 are patterned through dielectric material 98. Trenches 100 may be disposed between opposing sidewalls of memory film 90 and define areas where conductive lines 106/108 are subsequently formed. In some embodiments, patterning the trench 100 may be performed by a combination of photolithography and etching. For example, photoresist 101 may be deposited over multilayer stack 58, dielectric material 98, OS layer 92, and memory film 90. For example, the photoresist 101 may be formed by using a suitable technique such as a spin coating technique. The photoresist 101 is then patterned to define openings 100. Each of the openings 100 exposes a region of the dielectric material 98 and may expose a region of the OS layer 92. The photoresist may be patterned using acceptable photolithography techniques. For example, the photoresist 101 is exposed to light for patterning. After the exposure process, the photoresist 101 may be developed to remove either the exposed or unexposed portions of the photoresist, depending on whether a negative or positive resist is used, to define the pattern of the openings 100.

The portion of dielectric material 98 exposed by opening 100 may be removed by etching, thereby forming trench 100 in dielectric material 98. The etching may be any acceptable etching process, such as by wet or dry etching, Reactive Ion Etching (RIE), Neutral Beam Etching (NBE), and the like, or combinations thereof. The etching may be anisotropic. In some embodiments, the trench 100 may have a width W4 in the range of about 40nm to about 70nm or a length L1 in the range of about 80nm to about 150nm, although other dimensions are possible. In some embodiments, the trenches 100 are separated by a distance L2 in the range of about 30nm to about 120nm, although other distances are possible. In some embodiments, the trench 100 may have a depth in the range of about 1000nm to about 2000nm, although other depths are possible. After the trench 100 is patterned, the photoresist 101 may be removed by ashing, for example.

The etching may leave a portion of the OS layer 92 within the trench 100 overlying the memory film 90, or the etching may remove the OS layer 92 from the memory film 90 to expose the memory film 90 within the trench 100. For example, fig. 22A shows an embodiment in which after forming the trench 100, a portion of the OS layer 92 remains and covers the sidewalls of the memory film 90. Fig. 22B to 22C show an embodiment in which the OS layer 92 is removed and the sidewall of the memory film 90 is exposed. In some embodiments where portions of OS layer 92 remain on memory film 90 after forming trenches 100, the remaining OS layer 92 may have a thickness in the range of about 0nm to about 15nm, although other thicknesses are possible.

In fig. 23A, 23B and 23C, a refill layer 96 is deposited in the trench 100, according to some embodiments. As shown in fig. 23A, a refill layer 96 may be conformally deposited on the surface of the dielectric material 98, OS layer 92, and/or memory film 90 within the trench 100. Fig. 23A-23C illustrate an embodiment in which OS layer 92 overlying memory film 90 has been removed, and thus refill layer 96 is deposited on the surface of memory film 90 within trench 100. The refill layer 96 may extend along the sidewalls and bottom surface of the trench 100 above the memory film 90. In other embodiments, the refill layer 96 may be deposited on the remaining portions of the OS layer 92 within the trenches 100 overlying the memory film 90. The refill layer 96 may provide an increased contact area between the subsequently formed conductive line 106/108 (see fig. 25A-26C) and the OS layer 92, particularly if the OS layer 92 within the trench 100 is removed. In some embodiments, refill layer 96 may be formed of a material that provides less resistive contact to conductive line 106/108 than the material of OS layer 92. In this manner, the refill layer 96 described herein may reduce resistance and provide improved performance for a transistor (e.g., transistor 204, see fig. 1A).

Refill layer 96 may be deposited using techniques similar to OS layer 92, such as CVD, PVD, ALD, PECVD, and the like. In some embodiments, refill layer 96 may comprise a material that is the same as or similar to the material of OS layer 92. For example, in some embodiments, refill layer 96 comprises an indium-containing material, such as indium oxide, indium gallium zinc oxide, indium titanium oxide, indium tungsten oxide, indium tin oxide, or the like, or combinations thereof. In other embodiments, a different semiconductor material may be used for refill layer 96 than these examples or OS layer 92. For example, in other embodiments, refill layer 96 may comprise zinc oxide or another type of oxide.

In some embodiments, refill layer 96 may be a material having a greater carrier concentration than the material of OS layer 92. In this manner, refill layer 96 may provide a smaller resistive contact between wire 106/108 and OS layer 92. For example, in some embodiments, OS layer 92 may be formed of a material such as indium gallium zinc oxide, indium titanium oxide, indium tungsten oxide, zinc oxide, or indium oxide, and refill layer 96 may be formed of a material having a relatively high carrier concentration such as indium titanium oxide, indium tungsten oxide, zinc oxide, or indium oxide. In some embodiments, the OS layer 92 may have a thickness of about 10¹⁵cm^-3And about 10¹⁷cm^-3And the refill layer 96 may have a carrier concentration of between about 10¹⁹cm^-3And about 10²²cm^-3Carrier concentration in between.

In some embodiments, refill layer 96 may be deposited to a thickness in the range of about 1nm to about 15nm, although other thicknesses are possible. Refill layer 96 may have a thickness that is less than, about equal to, or greater than the thickness of OS layer 92. For example, in some embodiments, refill layer 96 extending over memory film 90 may have a different thickness than OS layer 92 extending over memory film 90. In some embodiments, after depositing the refill layer 96, the trench 100 may have a width W5 in the range of about 20nm to about 70nm or a length L3 in the range of about 50nm to about 80nm, although other dimensions are possible. In some embodiments, after depositing the refill layer 96, the trench 100 may have a depth D1 in the range of about 1000nm to about 2000nm, although other depths are possible. In some embodiments, a planarization process is performed after depositing refill layer 96.

In fig. 24A, 24B, and 24C, the trench 100 is filled with a conductive material 104, according to some embodiments. The conductive line 106/108 is then formed from the conductive material 104 (see fig. 25A to 26C). The conductive material 104 may include one or more materials such as copper, titanium nitride, tantalum nitride, tungsten, ruthenium, aluminum, molybdenum, combinations thereof, and the like, each of which may be formed using, for example, CVD, ALD, PVD, PECVD, and the like. After depositing the conductive material 104, a planarization process may be performed to remove excess portions of the conductive material 104. In some embodiments, the planarization process may also remove excess portions of the refill layer 96. In the resulting structure, the top surfaces of multilayer stack 58, memory film 90, OS layer 92, refill layer 96, and conductive material 104 may be substantially planar (e.g., coplanar within process variations).

In fig. 25A, 25B, and 25C, trenches 120 are patterned in conductive material 104 to form conductive lines 106 and 108, according to some embodiments. Fig. 25C shows a cross-sectional view of line D-D' in fig. 25B. The trench 120 is patterned by patterning the conductive material 104 using a combination of photolithography and etching. For example, a photoresist 119 may be deposited over multilayer stack 58, dielectric material 98, OS layer 92, refill layer 96, memory film 90, and conductive material 104. For example, the photoresist 119 may be formed by using a spin coating technique. The photoresist 119 is patterned to define openings 120. Each of the openings 120 may overlap with a corresponding region of the conductive material 104 and the refill layer 96. The opening 120 does not completely overlap the conductive material 104 and the portion of the conductive material 104 that does not overlap the opening 120 defines the portion of the conductive material 104 that forms the conductive line 106/108. The photoresist 119 may be patterned using acceptable photolithography techniques. For example, the photoresist 119 is exposed to light for patterning. After the exposure process, the photoresist 119 may be developed to remove exposed or unexposed portions of the photoresist 119, depending on whether a negative resist or a positive resist is used, to define the opening 120.

The conductive material 104 and the portions of the refill layer 96 exposed by the openings 120 may be removed by etching to form trenches 120. The etching may be any acceptable etching process, such as by wet or dry etching, Reactive Ion Etching (RIE), Neutral Beam Etching (NBE), and the like, or combinations thereof. The etching may be anisotropic. In this manner, each of the trenches 120 may define a pattern of conductive lines 106 of conductive material 104 and adjacent conductive lines 108 of conductive material 104 separated by the trenches 120. Conductive line 106 may correspond to a bit line in a memory array and conductive line 108 may correspond to a source line in memory array 200. Although fig. 25C shows a cross-sectional view showing only wire 106, the cross-sectional view of wire 108 may be similar. After patterning the trench 120, the photoresist 119 may be removed, for example, by ashing.

In some embodiments, the trench 120 may have a length L4 in the range of about 30nm to about 100nm, although other dimensions are possible. After etching trench 120, the remaining portion of conductive material 104 forming conductive line 106/108 may have a length L5 in the range of about 20nm to about 50nm, although other dimensions are possible. In some cases, the wires 106 and 108 adjacent to the same trench 120 may have different lengths (e.g., length L5). In some embodiments, the length L5 of the conductive line 106/108 may be controlled by controlling the length L4 of the trench 120 (e.g., by controlling the patterned trench 120). In this manner, controlling the dimensions of the trench 120 may control the dimensions of the conductive line 106/108. In addition, controlling the length L4 of the trench 120 may also control the area of contact between the lead 106/108 and the refill layer 96. An exemplary contact area 105 between the conductive line 106 and the refill layer 96 is indicated in fig. 25B. The dimensions of the contact area (e.g., contact area 105) between the conductive line 106/108 and the refill layer 96 are discussed in more detail below with respect to fig. 26A-26C and 27.

In fig. 26A, 26B and 26C, a dielectric material 102 is deposited in the trenches 120 and fills the trenches 120, according to some embodiments. FIG. 26C shows a cross-sectional view of line D-D' in FIG. 26B. The dielectric material 102 may include, for example, silicon oxide, silicon nitride, silicon oxynitride, the like, or combinations thereof. The material of dielectric material 102 may be the same as or different from the material of dielectric material 98. The dielectric material 102 may be deposited using a suitable technique such as CVD, PVD, ALD, PECVD, and the like. Dielectric material 102 may extend along the sidewalls and bottom of trench 120 over memory film 90. After deposition, a planarization process (e.g., CMP, etchback, etc.) may be performed to remove excess portions of the dielectric material 102. In the resulting structure, the top surfaces of multilayer stack 58, memory film 90, conductive lines 106/108, refill layer 96, OS layer 92, and dielectric material 102 may be substantially planar. In this manner, adjacent wires 106 and 108 are separated by an isolation region formed by dielectric material 102. Adjacent conductors 106/108 are separated by a length L4, which length L4 can be controlled by controlling the corresponding length L4 of the trench 120.

An exemplary contact area 105 between the conductive line 106 and the refill layer 96 is shown in fig. 26B. In some cases, forming refill layer 96 between conductive line 106/108 and OS layer 92 may improve the conduction between conductive line 106/108 and OS layer 92, as described herein. For example, in embodiments where OS layer 92 is removed from memory film 90 during etching of trench 100 (see fig. 22A-22C), in the absence of refill layer 96, the contact area between conductive line 106/108 and OS layer 92 would be limited by the thickness of OS layer 92, shown in fig. 26B by exemplary contact region 103. By partially surrounding the conductive line 106/108 with the refill layer 96, the effective contact area between the conductive line 106/108 and the OS layer 92 may be increased, as shown by the contact region 105 in fig. 26B. The area of the contact region 105 may be generally defined by the depth D1, width W5, and length L5 of the conductive line 106/108. In some embodiments, the area of the contact region 105 may be about 1800nm²To about 8500nm²But other contact areas are possible. In some embodiments, the use of refill layer 96 may increase the effective contact area between conductive line 106/108 and OS layer 92 by between about 33% and about 500%, although other percentages are possible. By forming the contact region 105 with a larger area, the contact resistance between the wire 106/108 and the OS layer 92 can be reduced. Furthermore, as previously described, the material of refill layer 96 may be selected to further reduce contact resistance. In some cases, the contact resistance when using refill layer 96 is between about 30% and about 100% of the contact resistance when refill layer 96 is not present.

Because the area of the contact region 105 may be generally defined by the depth D1, the width W5, and the length L5 of the wire 106/108, controlling the dimensions D1, W5, and/or L5 of the wire 106/108 may also control the dimensions of the contact region 105. An example is shown in fig. 27, in which a trench 120 having a length L4 that is smaller than the length L4 of the trench 120 formed for fig. 26A to 26C has been formed (see fig. 25A to 25C). By forming trench 120 to have a smaller length L4, the size of wire 106/108 and the area of contact region 105 may be increased. This is also shown in fig. 27, where the wire 106/108 has a greater length L5 than the wires in fig. 26A-26C. In this manner, a smaller length L4 of trench 120 may result in a larger length L5 of wire 106/108, which correspondingly results in a larger area of contact region 105. For example, forming larger wires 106/108 or larger areas of contact regions 105 may reduce resistance, which may improve device performance, such as by improving power efficiency or reducing heat dissipation.

Turning back to fig. 26A-26C, stacked transistors 204 may be formed in the memory array 200. Each transistor 204 includes a gate electrode (e.g., corresponding to a portion of conductive line 72), a gate dielectric (e.g., corresponding to a portion of memory film 90), a channel region (e.g., corresponding to a portion of OS layer 92 and refill layer 96), and source and drain electrodes (e.g., corresponding to portions of conductive lines 106 and 108). The dielectric material 102 isolates adjacent transistors 204 in the same column and at the same vertical level. The transistors 204 may be arranged in an array of vertically stacked rows and columns.

In fig. 28A, 28B, 28C, and 28D, contacts 110 to the wires 72, 106, and 108 are made. FIG. 28A shows a perspective view of memory array 200; FIG. 28B shows a top view of memory array 200; FIG. 28C shows a cross-sectional view of the device and underlying substrate taken along line 28-28C' of FIG. 28A; and figure 28D shows a cross-sectional view of the device along reference section B-B' of figure 1A. In some embodiments, the stepped shape of the wire 72 may provide a surface on each of the wires 72 for the conductive contacts 110 to engage. Forming contacts 110 may include patterning openings in IMD 70 and dielectric layer 52 to expose portions of conductive layer 54, for example, using a combination of photolithography and etching. A liner (not shown) such as a diffusion barrier layer, an adhesive layer, or the like and a conductive material are formed in the opening. The liner may comprise titanium, titanium nitride, tantalum nitride, and the like. The conductive material may be copper, copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, or the like. A planarization process such as CMP may be performed to remove excess material from the surface of IMD 70. The remaining pad and conductive material form a contact 110 in the opening.

As also shown in the perspective view of fig. 28A, conductive contacts 112 and 114 to the leads 106 and 108, respectively, may also be made. The conductive contacts 110, 112, and 114 may be electrically connected to wires 116A, 116B, and 116C, respectively, which connect the memory array to underlying/overlying circuitry (e.g., control circuitry) and/or signals, power, and ground in the semiconductor die. For example, conductive vias 118 may extend through IMD 70 to electrically connect leads 116C to the underlying circuitry of interconnect structure 220 and active devices on substrate 50 as shown in fig. 28C. Other conductive vias may be formed through IMD 70 to electrically connect leads 116A and 116B to the underlying circuitry of interconnect structure 220. In alternative embodiments, routing and/or power lines to or from the memory array may be provided by interconnect structures formed above the memory array 200 in addition to or in place of the interconnect structures 220. Thus, the memory array 200 may be completed.

Although the embodiments of fig. 2-28B show a particular pattern of conductive lines 106 and 108, other configurations are possible. For example, in these embodiments, the conductive lines 106/108 have a staggered pattern. In some embodiments, the conductive lines 106/108 in the same row of the array are all aligned with each other. Refill layer 96 may be suitably formed on conductive line 106/108 using the techniques described herein.

Fig. 29, 30, 31, and 32 show plan views of intermediate steps in forming the memory array 200, according to some embodiments. The process illustrated in fig. 29-32 is similar to that described for fig. 22A-26C, except that OS layer 92 partially remains on memory film 90 after trench 100 is etched. Such an incomplete etching of the OS layer 92 may result in a trench 100 having a circular shape, an example of which is shown in fig. 29. The memory film 90 is exposed by the trench 100, but the remainder of the OS layer 92 covers a greater portion of the memory film 90 than the trench 100 shown in fig. 22B. In some embodiments, incompletely etching OS layer 92 exposes a larger area of OS layer 92 within the trench, which may increase the contact area between subsequently formed refill layer 96 (see fig. 30) and OS layer 92. In some cases, increasing the contact area between OS layer 92 and refill layer 96 may reduce the resistance. The grooves 100 shown in fig. 22B and 29 are examples, and grooves 100 having other shapes are possible.

In fig. 30, a refill layer 96 is deposited within the trench 100, according to some embodiments. The refill layer 96 may be similar to the refill layer 96 previously described with respect to fig. 23A-23C, and may be formed in a similar manner. In fig. 31, a conductive material 104 is deposited within the trench 100 and on the refill layer 96. The conductive material 104 may be similar to the conductive material 104 previously described with respect to fig. 24A-24C, and may be formed in a similar manner. In fig. 32, trenches are formed in the conductive material 104 and the fill layer 96, and a dielectric material 102 is deposited in the trenches. The trenches may be similar to the trenches 120 previously described with respect to fig. 25A-25C, and may be formed in a similar manner. The dielectric material 102 may be similar to the dielectric material 102 previously described with respect to fig. 26A-26C, and may be formed in a similar manner. In this way, the conductive line 106 and the conductive line 108 are formed. Conductive line 106/108 is in electrical contact with OS layer 92 through refill layer 96, which may reduce contact resistance as previously described.

Fig. 33, 34, 35, and 36 show plan views of intermediate steps in forming the memory array 200, according to some embodiments. The process shown in fig. 33-36 is similar to that described for fig. 22A-26C, except that a refill layer 96 is selectively deposited on the memory film 90. Selective deposition of refill layer 96 in this manner may increase the size of conductive line 106/108 (e.g., length L5) while still providing improved contact resistance between conductive line 106/108 and OS layer 92. Increasing the size of wire 106/108 may improve the conductivity of wire 106/108 and improve device performance.

Fig. 33 shows a plan view after the trench 100 has been formed, similar to the plan view shown in fig. 22B. In fig. 34, a refill layer 96 is deposited within the trench 100, according to some embodiments. As shown in fig. 34, refill layer 96 is formed using a selective deposition process such that it is formed on exposed portions of memory film 90 without forming refill on dielectric material 98Layer 96. In some embodiments, the selectively deposited refill layer 96 is a material such as ITO, IWO, ZnO, In₂O₃Etc., or combinations thereof, but other materials are possible. Refill layer 96 may be formed using a selective deposition process such as selective ALD, CVD, or the like, or other selective deposition process. For example, the refill layer 96 may be formed by passing In (CH) at a temperature of about 200 deg.C₃)₃And H₂O In deposited using ALD₂O₃. This exemplary process deposits refill layer 96 on memory film 90 instead of on dielectric material 98, but other materials or processes are possible. The refill layer 96 may be a material similar to those previously described with respect to fig. 23A-23C, or may be a different material.

In fig. 35, a conductive material 104 is deposited within the trench 100 and on the refill layer 96. The conductive material 104 may be similar to the conductive material 104 previously described with respect to fig. 24A-24C, and may be formed in a similar manner. Because the refill layer 96 does not cover the dielectric material 98, a conductive material 104 is deposited on the portions of the dielectric material 98 within the trenches 100. In fig. 36, trenches are formed in the conductive material 104 and the refill layer 96, and a dielectric material 102 is deposited in the trenches. The trenches may be similar to the trenches 120 previously described with respect to fig. 25A-25C, and may be formed in a similar manner. The dielectric material 102 may be similar to the dielectric material 102 previously described with respect to fig. 26A-26C, and may be formed in a similar manner. In this way, the conductive line 106 and the conductive line 108 are formed. Conductive line 106/108 is in electrical contact with OS layer 92 through refill layer 96, which may reduce contact resistance as previously described.

Various embodiments provide a 3D memory array with vertically stacked memory cells. The memory cells each include a transistor having a memory film, a gate dielectric material, and an oxide semiconductor channel region. The transistors include source/drain electrodes, which are also source lines and bit lines in the memory array. A dielectric material is disposed between and separates adjacent source/drain electrodes. In some embodiments, the etching forms source/drain electrodes thereinA trench for the gate, a refill layer deposited on a surface of the trench to provide improved contact between the source/drain electrodes and the oxide semiconductor channel region. For example, in some cases, the oxide semiconductor channel material is removed during a trench etch process, which may reduce the possible contact area between the oxide semiconductor channel material and the source/drain electrodes. The removed oxide semiconductor channel material may be replaced by depositing refill material within the trench. In addition, the refill material may provide an increased effective contact area between the oxide semiconductor channel material and the source/drain electrodes. By increasing the effective contact area, the contact resistance between the oxide semiconductor channel material and the source/drain electrodes can be reduced. In some embodiments, the refill material may be formed of a material that provides an improved contact, such as a material having a higher carrier concentration than the oxide semiconductor channel material. By reducing the contact resistance in this manner, device performance may be improved. For example, the techniques described herein may allow for improved conduction current (I) of a memory cell_on) Improved power efficiency, and other benefits.

According to an embodiment of the present invention, a memory cell includes: a semiconductor substrate; and a transistor located over the semiconductor substrate, the transistor comprising: a memory film extending along the word line, wherein the memory film contacts the word line; a channel layer extending along the memory film, wherein the memory film is located between the channel layer and the word line; a source line extending along the memory film, wherein the memory film is located between the source line and the word line; a first contact layer on the source line, wherein the first contact layer contacts the channel layer and the memory film, wherein the first contact layer includes a first material; a bit line extending along the memory film, wherein the memory film is located between the bit line and the word line; a second contact layer on the bit line, wherein the second contact layer contacts the channel layer and the memory film, wherein the second contact layer includes the first material; and an isolation region between the source line and the bit line. In an embodiment, an isolation region contacts a source line and a bit line. In an embodiment, a first contact layer extends between the source line and the isolation region, and wherein a second contact layer extends between the bit line and the isolation region. In an embodiment, the channel layer includes a first material. In an embodiment, the first material has a higher carrier concentration than the channel layer. In an embodiment, the first material comprises an oxide. In an embodiment, the channel layer has a first thickness, the first contact layer has a second thickness, and the second contact layer has the second thickness, wherein the first thickness is different from the second thickness.

According to an embodiment of the invention, a device comprises: a semiconductor substrate; a first memory cell over a semiconductor substrate, the first memory cell comprising a first transistor, wherein the first transistor comprises: a gate electrode including a portion of the first word line; a first portion of ferroelectric material, wherein the first portion of ferroelectric material is located on sidewalls of the first word line; and a first channel region on a sidewall of the first portion of ferroelectric material; a source line, wherein a first portion of the source line provides a first source/drain electrode for the first transistor; a first contact layer on the source line, wherein the source line is in electrical contact with the first channel region through the first contact layer; a bit line, wherein a first portion of the bit line provides a second source/drain electrode for the first transistor; a second contact layer on the bit line, wherein the bit line is in electrical contact with the first channel region through the second contact layer; a first dielectric material separating the source line and the bit line; and a second memory cell located above the first memory cell. In an embodiment, the second memory cell comprises a second transistor, wherein the second portion of the source line provides a first source/drain electrode for the second transistor, and wherein the second portion of the bit line provides a second source/drain electrode for the second transistor. In an embodiment, a device comprises: and a second word line positioned below the first word line, wherein the gate electrode of the second transistor includes a portion of the second word line, and wherein the first word line is longer than the second word line. In an embodiment, the first dielectric material physically contacts the first channel region, the first contact layer, and the second contact layer. In an embodiment, the first contact layer and the second contact layer comprise a first material, and wherein the first channel region comprises a second material different from the first material. In an embodiment, a contact area between the source line and the first contact layer is greater than a contact area between the first contact layer and the first channel region. In an embodiment, the first portion of ferroelectric material is in physical contact with the first contact layer and the second contact layer. In an embodiment, the first channel region extends between a portion of the first contact layer and the first portion of the ferroelectric material. In an embodiment, sidewalls of the source lines are free of the first contact layer.

According to an embodiment of the invention, the method comprises: patterning a first trench extending through the first conductive line; depositing a memory film along sidewalls and a bottom surface of the first trench; depositing an Oxide Semiconductor (OS) layer over the memory film, wherein the OS layer extends along sidewalls and a bottom surface of the first trench; depositing a first dielectric material on the OS layer, wherein the first dielectric material fills the remaining portion of the first trench; patterning a second trench in the first dielectric material and the OS layer, wherein the patterned second trench exposes a sidewall surface of the memory film and a sidewall surface of the OS layer; depositing a refill layer along sidewalls and a floor of the second trench, wherein the refill layer physically contacts sidewall surfaces of the OS layer; depositing a conductive material on the refill layer, wherein the conductive material fills the remaining portion of the second trench; patterning a third trench in the conductive material and the refill layer, wherein the patterned third trench exposes a sidewall surface of the memory film and a sidewall surface of the refill layer; and depositing a second dielectric material in the third trench, wherein the second dielectric material fills the third trench. In an embodiment, depositing the refill layer includes performing a selective deposition process that selectively deposits the refill layer on a surface of the memory film and a surface of the OS layer, but not on a surface of the first dielectric material. In an embodiment, the refill layer has a different composition than the OS layer. In an embodiment, the refill layer is deposited to a different thickness than the OS layer.

The foregoing has outlined features of several embodiments so that those skilled in the art may better understand the aspects of the present invention. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.