阅读说明：本技术 存储器器件及其形成方法 (Memory device and method of forming the same ) 是由 吴昭谊 林佑明 杨世海 于 2021-05-26 设计创作，主要内容包括：一种存储器器件包括：衬底、层堆叠及多个复合柱结构。层堆叠设置在衬底上。层堆叠包括交替堆叠的多个导电层及多个介电层。复合柱结构分别穿透过层堆叠。每一个复合柱结构包括介电柱；一对导电柱,穿透过介电柱且通过介电柱的一部分彼此电隔离；沟道层,覆盖介电柱的两侧及所述一对导电柱的两侧；铁电层,设置在沟道层与层堆叠之间；以及缓冲层,设置在沟道层与铁电层之间。(A memory device includes: a substrate, a layer stack, and a plurality of composite pillar structures. The layer stack is disposed on a substrate. The layer stack includes a plurality of conductive layers and a plurality of dielectric layers stacked alternately. The composite post structures are stacked through the transmission layers, respectively. Each composite pillar structure includes a dielectric pillar; a pair of conductive posts penetrating through the dielectric posts and electrically isolated from each other by a portion of the dielectric posts; a channel layer covering both sides of the dielectric pillar and both sides of the pair of conductive pillars; a ferroelectric layer disposed between the channel layer and the layer stack; and a buffer layer disposed between the channel layer and the ferroelectric layer.)

1. A memory device, comprising:

a layer stack disposed on a substrate, wherein the layer stack comprises a plurality of conductive layers and a plurality of dielectric layers alternately stacked;

a plurality of composite post structures respectively penetrating through the layer stack, wherein each composite post structure comprises:

a dielectric column;

a pair of conductive posts penetrating through the dielectric posts and electrically isolated from each other by a portion of the dielectric posts;

a channel layer covering both sides of the dielectric pillar and both sides of the pair of conductive pillars;

a ferroelectric layer disposed between the channel layer and the layer stack; and

a buffer layer disposed between the channel layer and the ferroelectric layer.

2. The memory device of claim 1, wherein the buffer layer comprises a dielectric material having a dielectric constant greater than 5.

3. The memory device of claim 1, wherein the buffer layer comprises at least:

a first dielectric material in contact with the ferroelectric layer; and

a second dielectric material in contact with the channel layer, wherein the first dielectric material and the second dielectric material have different dielectric constants.

4. The memory device of claim 1, wherein the buffer layer is a nitrogen-doped dielectric layer and a nitrogen doping concentration of the buffer layer is graded.

5. The memory device of claim 1, further comprising a plurality of isolation structures respectively penetrating through the layer stack and respectively disposed between the plurality of composite pillar structures to electrically isolate the plurality of composite pillar structures, wherein one of the plurality of composite pillar structures constitutes a memory cell with a corresponding conductive layer at one side of the one of the plurality of composite pillar structures.

6. The memory device according to claim 5, wherein a plurality of memory cells alternately arranged in the Y direction share the same word line, and a plurality of memory cells alternately arranged in the Z direction share the same bit line and the same source line.

7. A memory device, comprising:

a layer stack disposed on a substrate, wherein the layer stack comprises a plurality of conductive layers and a plurality of dielectric layers alternately stacked;

a dielectric post penetrating through the layer stack;

a channel layer surrounding the dielectric pillar;

a ferroelectric layer disposed between the channel layer and the layer stack; and

a buffer layer disposed between the ferroelectric layer and the channel layer.

8. The memory device of claim 7, wherein the ferroelectric layer is embedded between two adjacent dielectric layers and in contact with a corresponding conductive layer.

9. The memory device of claim 7, wherein the ferroelectric layer and the buffer layer are both embedded between two adjacent dielectric layers, and the ferroelectric layer, the buffer layer, and the corresponding conductive layer are at the same level.

10. A method of forming a memory device, comprising:

forming a layer stack on a substrate, wherein the layer stack comprises a plurality of dielectric layers and a plurality of sacrificial layers that are alternately stacked;

forming a trench in the layer stack to penetrate through the layer stack;

lining the ferroelectric layer on the sidewalls of the trench;

forming a buffer layer in the trench to cover the ferroelectric layer;

forming a channel layer in the trench to cover the buffer layer;

filling the trench with a dielectric material to form a dielectric pillar;

forming a pair of conductive posts embedded in the dielectric posts; and

a replacement process is performed to replace the plurality of sacrificial layers with a plurality of conductive layers.

Technical Field

Embodiments of the invention relate to a memory device and a method of forming the same.

Background

The semiconductor Integrated Circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have led to generations of ICs, each of which has smaller and more complex circuits than the previous generation. In the course of IC evolution, the functional density (i.e., the number of interconnected devices per chip area) has generally increased while the geometric size (i.e., the smallest component (or line) that can be produced using a fabrication process) has decreased. Such a scaled-down process generally provides benefits by increasing production efficiency and reducing associated costs.

Such scaling has also increased the complexity of IC processing and fabrication, and similar developments in IC processing and fabrication are required to achieve these advances. For example, three-dimensional (3D) memory devices have been introduced to replace planar memory devices. However, 3D memory devices have not been fully satisfactory in all respects, presenting additional problems that should be addressed.

Disclosure of Invention

An embodiment of the present invention provides a memory device including: a substrate, a layer stack, and a plurality of composite pillar structures. The layer stack is disposed on a substrate. The layer stack includes a plurality of conductive layers and a plurality of dielectric layers stacked alternately. The composite post structures are stacked through the transmission layers, respectively. Each composite pillar structure includes a dielectric pillar; a pair of conductive posts penetrating through the dielectric posts and electrically isolated from each other by a portion of the dielectric posts; a channel layer covering both sides of the dielectric pillar and both sides of the pair of conductive pillars; a ferroelectric layer disposed between the channel layer and the layer stack; and a buffer layer disposed between the channel layer and the ferroelectric layer.

An embodiment of the present invention provides a memory device including: a layer stack disposed on the substrate, wherein the layer stack includes a plurality of conductive layers and a plurality of dielectric layers alternately stacked; a dielectric post penetrating through the stack of layers; a channel layer surrounding the dielectric pillar; a ferroelectric layer disposed between the channel layer and the layer stack; and a buffer layer disposed between the ferroelectric layer and the channel layer.

An embodiment of the present invention provides a method for forming a memory device, including: forming a layer stack on a substrate, wherein the layer stack comprises a plurality of dielectric layers and a plurality of sacrificial layers which are alternately stacked; forming a trench in the layer stack to penetrate through the layer stack; lining the ferroelectric layer on the sidewalls of the trench; forming a buffer layer in the trench to cover the ferroelectric layer; forming a channel layer in the trench to cover the buffer layer; filling the trench with a dielectric material to form a dielectric pillar; forming a pair of conductive posts embedded in the dielectric posts; and performing a replacement process to replace the plurality of sacrificial layers with a plurality of conductive layers.

Drawings

Various aspects of the disclosure are best understood from the following detailed description when read with the accompanying figures. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

Fig. 1 is a cross-sectional view of a substrate according to some embodiments.

Fig. 2A to 10A are top views of a method of forming a three-dimensional (3D) memory device according to a first embodiment.

Fig. 2B to 10B are sectional views along the cross section a-a of fig. 2A to 10A.

Fig. 10C is a plan view along the cross-section B-B of fig. 10B.

Fig. 11A and 11B are plan views of 3D memory devices according to various embodiments.

Figure 12 is a top view of a memory array according to some embodiments.

Fig. 13 is a circuit diagram of the memory array of fig. 12.

Fig. 14A-14D are cross-sectional views of a 3D memory device according to some alternative embodiments.

Fig. 15 to 21A are cross-sectional views of a method of forming a 3D memory device according to a second embodiment.

Fig. 16B is a top view of the 3D memory device of fig. 16A.

Fig. 21B is a top view of the 3D memory device of fig. 21A.

Fig. 22 is a cross-sectional view of a 3D memory device according to a third embodiment.

Fig. 23 is a cross-sectional view of a 3D memory device according to a fourth embodiment.

Fig. 24 is a cross-sectional view of a 3D memory device according to a fifth embodiment.

FIG. 25 illustrates a flow diagram of a method of forming a 3D memory device, according to some embodiments.

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are set forth below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, forming a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. Additionally, the present disclosure may repeat reference numerals and/or letters in the various examples. Such repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Furthermore, for ease of illustration, spatially relative terms such as "below … (beneath)", "below … (below)", "below (lower)", "above … (above)", "above (upper)" etc. may be used herein to describe the relationship of one element or feature to another (other) element or feature illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may have other orientations (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly as well.

Among various non-volatile memories, ferroelectric field effect transistors (fefets) are a promising candidate for high density, low power applications. Fefets have advantages such as non-destructive readout, high program/erase speed, and low power consumption due to their field-driven operation. In addition, fefets are of interest for their high scalability and high complementary metal-oxide-semiconductor (CMOS) compatibility. To make the density higher, 3D vertical structures have been proposed. Recently, 3D vertically stacked ferroelectric structures have been developed, and the memory operation of the 3D vertically stacked ferroelectric structures has been demonstrated. Generally, polysilicon is used as the channel material. However, polysilicon channels face challenges such as low mobility of the very thin polysilicon channel and low dielectric constant of the Interface Layer (IL) between the ferroelectric material and the polysilicon. Since the IL with a low dielectric constant does not match the capacitance of the ferroelectric material, a large voltage is applied across the IL during operation, which may eventually cause the IL to break down, leading to a durability failure. In addition, an IL with a low dielectric constant may further enhance charge trapping, which may lead to threshold voltage shift problems, thereby reducing reliability.

According to one embodiment of the present invention, a FeFET having an oxide semiconductor channel has been proposed. Oxide semiconductor channels are suitable for achieving fast access speeds due to their high mobility and extremely thin body. In practice, however, a thin Interfacial Layer (IL) still exists between the ferroelectric material and the oxide semiconductor channel, so that charge trapping problems occur. Even if no IL is formed between the ferroelectric material and the oxide semiconductor channel, some traps and/or defects that trap charge may be formed at the interface between the ferroelectric material and the oxide semiconductor channel, thereby reducing reliability. Traps and/or defects at the interface between the ferroelectric material and the oxide semiconductor channel may come from unoccupied oxygen vacancies (oxygen vacancies), dangling bonds (dangling bonds), and the like.

According to some embodiments, a three-dimensional (3D) memory device is presented that includes a buffer layer disposed between a ferroelectric layer and a channel layer. The buffer layer having a high dielectric constant can reduce interface charge trapping between the ferroelectric layer and the channel layer to accordingly enhance the switchable performance of the ferroelectric layer, thereby reducing the operating voltage of the 3D memory device and increasing the operating window of the 3D memory device. In this case, the reliability and durability of the 3D memory device are improved accordingly.

Fig. 1 is a cross-sectional view of a substrate according to some embodiments. Fig. 2A to 10A are top views of a method of forming a three-dimensional (3D) memory device according to a first embodiment. Fig. 2B to 10B are sectional views along the cross section a-a of fig. 2A to 10A. The 3D memory device 100 is a 3D memory device having a ferroelectric material and may be, but is not limited to, a ferroelectric field effect transistor (FeFET) memory.

Referring to fig. 1, in front-end-of-line (FEOL) processing of semiconductor fabrication, a plurality of electrical components 104, such as transistors, resistors, capacitors, inductors, diodes, etc., are formed in a device region of a semiconductor substrate 102. For example, the transistors may include fin field effect transistors (finfets), nanostructured transistors (nanostructured transistors), gate-all-around transistors (e.g., nanowires, nanosheets, etc.), planar transistors, and the like. The transistor may be formed by a gate-first process or a gate-last process. The semiconductor substrate 102 may be a bulk substrate (e.g., a doped or undoped silicon substrate) or an active layer of a semiconductor-on-insulator (SOI) substrate. The semiconductor substrate 102 may comprise other semiconductor materials, such as germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, gallium nitride, indium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP; or a combination thereof. Other substrates, such as multilayer substrates or gradient substrates, may also be used. The electrical components 104 may be formed in/on the semiconductor substrate 102 using any suitable formation method known or used in semiconductor manufacturing.

After forming the electrical components 104, interconnect structures are formed over the semiconductor substrate 102 to connect the electrical components 104 to form functional circuits. The interconnect structure may include a plurality of dielectric layers (e.g., 106, 108) and conductive features 105 (e.g., vias, metal lines) formed in the dielectric layers. In some embodiments, the interconnect structure is formed in back-end-of-line (BEOL) processing in semiconductor manufacturing. The formation of interconnect structures is well known in the art and will not be described in detail herein. To avoid confusion and facilitate discussion, in the discussion that follows, the semiconductor substrate 102, the electrical component 104, and the interconnect structures located over the semiconductor substrate 102 are collectively referred to as the underlying structures 101, and details of the underlying structures 101 illustrated in fig. 1 may be omitted in subsequent figures.

Fig. 2A to 10C depict additional processing steps in a BEOL process for forming the 3D memory device 100 according to the first embodiment. Referring now to fig. 2A and 2B, a layer stack 110 is formed over the underlying structure 101. In detail, the layer stack 110 may include a plurality of dielectric layers 112A, 112B, 112C and a plurality of sacrificial layers 114A, 114B alternately stacked on the underlying structure 101. Although only three dielectric layers 112A, 112B, 112C and two sacrificial layers 114A, 114B are illustrated in fig. 2B, embodiments of the present disclosure are not so limited. In other embodiments, the number of dielectric layers and sacrificial layers may be adjusted as desired. For example, the number of dielectric layers may be greater than 4 layers, and the number of sacrificial layers may be greater than 4 layers. Hereinafter, the dielectric layers 112A, 112B, 112C are collectively referred to as the dielectric layer 112, and the sacrificial layers 114A, 114B are collectively referred to as the sacrificial layer 114.

In some embodiments, the dielectric layer 112 may comprise a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), or the like, or combinations thereof. The dielectric layer 112 may be formed by Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), or the like. In some embodiments, the dielectric layers 112 (e.g., 112A, 112B, 112C) are of the same dielectric material, such as silicon oxide. However, embodiments of the present disclosure are not so limited, and in other embodiments, the dielectric layers 112 (e.g., 112A, 112B, 112C) have different dielectric materials.

In some embodiments, the sacrificial layer 114 may comprise a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), the like, or combinations thereof. The sacrificial layer 114 may be formed by CVD, ALD, or the like. In some embodiments, the sacrificial layers 114 (e.g., 114A, 114B) are of the same dielectric material, such as silicon nitride. However, embodiments of the present disclosure are not so limited, and in other embodiments, the sacrificial layers 114 (e.g., 114A, 114B) have different dielectric materials. It should be noted that in the present embodiment, the sacrificial layer 114 and the dielectric layer 112 comprise different dielectric materials with different etch selectivity. For example, sacrificial layer 114 is formed of silicon nitride and dielectric layer 112 is formed of silicon oxide. In this case, the sacrificial layer 114 may be replaced in a subsequent step to form the conductive layer 118 (as shown in fig. 10B).

Next, referring to fig. 3A and 3B, trenches 10 are formed in the layer stack 110 to expose the underlying structure 101. That is, the trench 10 penetrates through the layer stack 110, and the underlying structure 101 is exposed at the bottom of the trench 10. As shown in the top view of fig. 3A, the grooves 10 extend in the Y direction. In addition, the trench 10 exposes the sidewalls of the dielectric layer 112 and the sidewalls of the sacrificial layer 114. Note that in the discussion herein, the sidewalls of layer stack 110 include corresponding sidewalls of all of the constituent layers (e.g., 112 and 114) of the layer stack. For example, the sidewalls of the layer stack 110 exposed to the trench 10 include the sidewalls of the dielectric layer 112 and the sidewalls of the sacrificial layer 114 exposed to the trench 10.

In some embodiments, the trench 10 is formed by an anisotropic etch process (e.g., a plasma etch process). A mask pattern, such as a patterned photoresist, may be formed on the layer stack 110. Then, an anisotropic etching process may be performed by using the mask pattern as an etching mask to form the trench 10. After the anisotropic etching process is completed, the mask pattern (e.g., patterned photoresist) may be removed by a suitable removal process (e.g., ashing or stripping).

Referring to fig. 4A and 4B, the ferroelectric layer 120 is first formed to line or cover the sidewalls of the trench 10. Ferroelectric layer 120 may be of a material that is capable of switching between two different polarization directions by applying an appropriate voltage difference across ferroelectric layer 120. For example, the polarization of ferroelectric layer 120 may change due to the electric field resulting from the application of the voltage difference.

In some embodiments, ferroelectric layer 120 can include ferroelectric materials (e.g., HZO, HSO, HfSiO, HfLaO, HfO doped with La, Y, Si or Ge₂、HfZrO₂、ZrO₂Or HfO₂) And may be formed by Physical Vapor Deposition (PVD), CVD, ALD, and the like. In some alternative embodiments, ferroelectric layer 120 may be a high dielectric constant (high-k) dielectric material, such as a hafnium (Hf) based dielectric material. For example, the ferroelectric material 220 is a compound including hafnium, such as hafnium zirconium oxide (HfZnO), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), hafnium cerium oxide (HfCeO), hafnium oxide (HfO), hafnium gadolinium oxide (HfGdO), hafnium silicon oxide (HfSiO), hafnium zirconium lanthanum oxide (HfZrLaO), hafnium zirconium gadolinium oxide (HfZrGdO), hafnium zirconium yttrium oxide (HfZrYO), hafnium zirconium cerium oxide (HfZrCeO), hafnium zirconium strontium oxide (hfzrsoo), and the like. In addition, the hafnium-containing compound may also be doped with some dopants, such as La, Y, Si, Ge, Ce, Gd, Sr, and the like, or combinations thereof. By doping these dopants in the hafnium-containing compound, an orthorhombic lattice structure (orthorhombic lattice structure) can be realized in the ferroelectric layer 120. In some embodiments, hafnium-containing compounds having an orthorhombic lattice structure have desirable ferroelectric properties to achieve switchable performance of ferroelectric layers in memory devices. Additionally, by including dopants, the orthorhombic lattice structure in the ferroelectric layer 120 may be relatively easily achieved (e.g., at lower temperatures), and the ferroelectric layer 120 may be formed within a relatively low thermal budget of BEOL processes (e.g., at temperatures that do not damage front end of line (FEOL) features, such as electrical components in the underlying structure 101).

In some embodiments, ferroelectric layer 120 is formed by: depositing a ferroelectric material conformally covering the bottom and sidewalls of trench 10 and also covering the upper surface of topmost dielectric layer 112C; and an anisotropic etch process is then carried out to remove the ferroelectric material on the bottom of the trench 10 and on the upper surface of the topmost dielectric layer 112C, as shown in fig. 4B. In this case, the ferroelectric layer 120 may have a rounded or curved top surface adjacent to the topmost dielectric layer 112C. In some embodiments, ferroelectric layer 120 may have a flat top surface, as shown in fig. 4B.

Next, as shown in fig. 4A and 4B, a buffer layer 121 is formed in the trench 10 to cover the ferroelectric layer 120. Buffer layer 121 may comprise a high dielectric constant (high-k) dielectric material that does not trap charge, such as Al₂O₃、TiO₂、ZrO₂、La₂O₃MgO, HfZrO, HfAlO, HfLaO, HfCeO, HfO, HfGdO, HfSiO, and the like, or combinations thereof. The buffer layer 121 may include a high-k dielectric material having a dielectric constant greater than 5 (e.g., k 10 to 30). In some embodiments, the dielectric constant of buffer layer 121 is lower than or equal to the dielectric constant of ferroelectric layer 120. In some alternative embodiments, the dielectric constant of the buffer layer 121 is greater than the dielectric constant of the ferroelectric layer 120. Other materials may be used. In some embodiments, the other material comprises barium titanium oxide (BaTiO)₃) Lead titanium oxide (PbTiO)₃) Lead zirconium oxide (PbZrO)₃) Lithium niobium oxide (LiNbO)₃) Sodium niobium oxide (NaNbO)₃) Niobium potassium oxide (KNbO)₃) Potassium tantalum oxide (KTaO)₃) Bismuth scandium oxide (BiScO)₃) Bismuth iron oxide (BiFeO)₃) Hafnium erbium oxide (Hf)_1-xEr_xO), hafnium lanthanum oxide (Hf)_1-xLa_xO), hafnium yttrium oxide (Hf)_1-xY_xO), hafnium gadolinium oxide (Hf)_1-xGd_xO), hafnium aluminum oxide (Hf)_1-xAl_xO), hafnium titanium oxide (Hf)_1-xTi_xO), hafnium tantalum oxide (Hf)_1-xTa_xO), and the like. However, embodiments of the present disclosure are not so limited, and in other embodiments, other suitable materials that do not trap charge during operation are candidates for the buffer layer 121. In some embodiments, a method of forming buffer layer 121 includes performing a suitable deposition technique, such as CVD, Plasma Enhanced CVD (PECVD), Metal Oxide Chemical Vapor Deposition (MOCVD), ALD, Molecular Beam Deposition (MBD), and the like.

In some alternative embodiments, the buffer layer 121 is a dielectric layer doped with nitrogen, and the nitrogen doping concentration of the buffer layer 121 is graded. Examples of such applications areIn other words, the buffer layer 121 is nitrogen-doped Al₂O₃The layer, and the nitrogen doping concentration of the buffer layer 121 is gradually increased along a direction from the channel layer 122 to the ferroelectric layer 120. On the other hand, the buffer layer 121 may be nitrogen-doped Al₂O₃The layer, and the nitrogen doping concentration of the buffer layer 121 is gradually decreased in a direction from the channel layer 122 to the ferroelectric layer 120. The buffer layer 121 may have a nitrogen doping concentration of less than 15%, for example, 3% to 10%. In some alternative embodiments, when buffer layer 121 is nitrogen-doped Al₂O₃When forming a layer, Al can be deposited by₂O₃Film on the Al₂O₃In-situ doping of nitrogen dopant in the film or deposition of Al₂O₃The film is then subjected to a nitridation treatment to form the buffer layer 121.

In some embodiments, the buffer layer 121 is formed by: depositing a buffer material conformally covering the bottom of trench 10, ferroelectric layer 120, and also covering the upper surface of topmost dielectric layer 112C; and then an anisotropic etch process is carried out to remove the buffer material on the bottom of the trench 10 and on the upper surface of the topmost dielectric layer 112C. In this case, the buffer layer 121 may have a rounded or curved top surface. In some embodiments, the buffer layer 121 may have a flat top surface, as shown in fig. 4B.

Although the buffer layer 121 having a single-layer structure is illustrated in fig. 4B, embodiments of the present disclosure are not limited thereto. In other embodiments, a buffer layer having a double layer structure, a triple layer structure, or a multi-layer structure may be formed on the ferroelectric layer 120, and details will be described in the following paragraphs corresponding to fig. 14A to 14D. In some embodiments, the buffer layer 121 has a thickness of 2nm to 5nm (e.g., 3 nm). Other thickness ranges (e.g., greater than 5nm or 6nm to 10nm) may be applied. In some embodiments, the buffer layer 121 is formed in a fully amorphous state (fully amorphous state). In an alternative embodiment, the buffer layer 121 is formed in a partially crystalline state (partial crystalline state); that is, the buffer layer 121 is formed in a mixed crystalline-amorphous state (mixed crystalline-amorphous state) and has a certain degree of structural order. In still other alternative embodiments, buffer layer 121 is formed in a fully crystalline state (fully crystalline state).

Thereafter, the channel layer 122 is formed in the trench 10 to cover the buffer layer 121. In some embodiments, the channel layer 122 is formed by: depositing a channel material conformally covering the bottom of the trench 10, the sidewalls of the buffer layer 121, and also covering the upper surface of the topmost dielectric layer 112C; and an anisotropic etch process is then carried out to remove the channel material on the bottom of the trench 10 and on the upper surface of the topmost dielectric layer 112C. In this case, the channel layer 122 may have a rounded or curved top surface. In some embodiments, the channel layer 122 may have a planar top surface, as shown in fig. 4B.

In some embodiments, the channel layer 122 may include a metal oxide (or oxide semiconductor), such as Indium Gallium Zinc Oxide (IGZO), formed by a suitable formation method (e.g., PVD, CVD, ALD, etc.). Other suitable materials for ferroelectric layer 120 include zinc oxide (ZnO), indium tungsten oxide (InWO), tungsten oxide (WO), tantalum oxide (TaO), and molybdenum oxide (MoO). In an exemplary embodiment, the dielectric layer 112 is made of SiO₂Formed with a sacrificial layer 114 of SiN and a ferroelectric layer 120 of HfO₂The buffer layer 121 is formed of nitrogen-doped Al₂O₃And the channel layer 122 is formed of IGZO.

It should be noted that the buffer layer 121 is formed between the ferroelectric layer 120 and the channel layer 122 to reduce interface charge trapping, thereby enhancing the reliability of the 3D memory device 100. In this case, as the interface trap density is reduced, the switchable performance of the ferroelectric layer 120 is correspondingly enhanced, thereby reducing the operating voltage of the 3D memory device 100 and increasing the operating window of the 3D memory device 100. In addition, the buffer layer 121 has a high dielectric constant (e.g., k >5), which may improve the endurance of the 3D memory device 100, thereby improving the reliability of the 3D memory device 100.

After the channel layer 122 is formed, a dielectric material is formed to fill in the trench 10. The dielectric material may comprise silicon nitride, silicon oxide, silicon oxynitride, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), and the like, or combinations thereof, and may be formed by suitable deposition methods, such as CVD, ALD, and the like. After the dielectric material is formed, a planarization process (e.g., a Chemical Mechanical Planarization (CMP) process) may be performed to remove excess portions of the dielectric material from the upper surface of the topmost dielectric layer 112C. In this case, the dielectric material forms dielectric pillars 124 in the remaining portions of the trenches 10.

Referring to fig. 5A and 5B, openings 12 and 14 are formed in dielectric pillar 124. The openings 12 and 14 may pass through the dielectric posts 124 to expose the underlying structure 101. As shown in fig. 5A, a portion of dielectric pillar 124 separates opening 12 and opening 14 from each other. In some embodiments, openings 12 and 14 are formed by an anisotropic etch process (e.g., a plasma etch process). A mask pattern, such as a patterned photoresist, may be formed on the layer stack 110. Then, an anisotropic etching process may be performed to form the openings 12 and 14 by using the mask pattern as an etching mask. After the anisotropic etching process is completed, the mask pattern (e.g., patterned photoresist) may be removed by a suitable removal process (e.g., ashing or stripping). In some embodiments, openings 12 and 14 may be formed in the same step or sequentially.

Referring to fig. 6A and 6B, a conductive material is formed to fill in the openings 12 and 14. After forming the conductive material, a planarization process (e.g., a CMP process) may be performed to remove excess portions of the conductive material from the upper surface of the topmost dielectric layer 112C. Thus, the conductive material forms conductive pillars 123 and 125 in the remaining portions of openings 12 and 14, respectively. In some embodiments, the conductive pillars 123 and 125 can be formed of the same source/drain (S/D) material (e.g., W, Ru, Ti, TiN, TaN, etc.). In this case, the conductive pillar 123 may be referred to as a source metal layer and the conductive pillar 125 may be referred to as a drain metal layer, or vice versa.

Referring to fig. 7A and 7B, isolation structures 127 are formed through dielectric pillars 124. Specifically, as shown in fig. 7A, the isolation structure 127 further extends to sever the channel layer 122, defining a memory cell having a pair of source/drain (S/D) regions 123 and 125. That is, one isolation structure 127 is disposed at one side of the pair of S/D regions 123 and 125 (i.e., near the S/D region 123), and another isolation structure 127 is disposed at the other side of the pair of S/D regions 123 and 125 (i.e., near the S/D region 125). From a memory array perspective, isolation structures 127 are disposed between adjacent pairs of S/D regions 123 and 125.

In some embodiments, isolation structures 127 are formed by: etching portions of the dielectric pillars 124 and portions of the channel layer 122 to form openings that expose the underlying structure 101; forming an insulating material in the opening; and performing a planarization process, such as a CMP process, to remove excess portions of the insulating material from the upper surface of the topmost dielectric layer 112C. In some embodiments, the insulating material comprises silicon oxide, silicon nitride, silicon oxynitride, Tetraethylorthosilicate (TEOS) oxide, undoped silicate glass, or doped silicon oxide, such as borophosphosilicate glass (BPSG), Fused Silica Glass (FSG), phosphosilicate glass (PSG), boron-doped silica glass (BSG), low-k dielectric materials, other suitable dielectric materials, or combinations thereof. Exemplary low-k dielectric materials include FSG, carbon-doped silicon oxide,(Applied Materials of Santa Clara, Calif.), Xerogel (Xerogel), Aerogel (Aerogel), amorphous carbon fluoride, Parylene (Parylene), benzocyclobutene (BCB), SiLKTM (Dow Chemical, Midland, Mich.), polyimide, other low-k dielectric Materials, or combinations thereof. Herein, the low-k dielectric material used in the isolation structure 127 between adjacent memory cells can reduce crosstalk or coupling interference between adjacent memory cells, thereby improving the performance and reliability of the 3D memory device 100.

After forming isolation structures 127 between adjacent memory cells, sacrificial layer 114 is subsequently replaced with conductive layer 118 by a replacement process, which will be described in detail in fig. 8A-10A and 8B-10B.

Referring to fig. 8A and 8B, a slit 16 is formed in the layer stack 110. In the illustrated embodiment, the slit 16 penetrates through the layer stack 110 and exposes the underlying structure 101. In another embodiment, the slits 16 extend through some layers of the layer stack 110 but not all layers. For example, the slots 16 may extend through all of the sacrificial layers 114 and expose the bottommost dielectric layer 112A. In some embodiments, the slits 16 may be formed by using acceptable photolithography and etching techniques, such as using an etch process that is selective to the layer stack 110 (e.g., the material of the dielectric layer 112 and the material of the sacrificial layer 114 are etched at a faster rate than the material of the underlying structure 101). The etch may be any acceptable etch process and may be similar in some embodiments to the etch used to form the trench 10 discussed with respect to fig. 3A and 3B.

In some embodiments, the slit 16 is disposed beside the ferroelectric layer 120 (or the trench 10) and extends along the Y direction in the top view of fig. 8A. However, embodiments of the present disclosure are not limited thereto, and in other embodiments, the slit 16 may extend along the X direction in a top view. In addition, the width 16w of the slit 16 may be smaller than the width 10w of the trench 10 to save horizontal chip area. Although the shape of the slit 16 illustrated in the top view of fig. 8A is a linear shape, embodiments of the present disclosure are not limited thereto. In an alternative embodiment, the shape of the slit 16 in top view may be a plurality of dots or islands spaced apart from each other and distributed between adjacent memory cells. Herein, the shape and position of the slits are not limited thereto as long as the slits can be used for a subsequent replacement process.

Referring to fig. 9A and 9B, the sacrificial layer 114 is removed to form a plurality of gaps 18 between the dielectric layers 112. In some embodiments, the method for removing the sacrificial layer 114 includes a wet etching process or an isotropic etching process. Since the underlying structure 101, the dielectric layer 112, and the ferroelectric layer 120 may have sufficient etch selectivity relative to the sacrificial layer 114, the sacrificial layer 114 may be selectively removed during such a wet etch process or an isotropic etch process. As shown in fig. 9B, after removing the sacrificial layer 114, the front gap 18 exposes the surface of the dielectric layer 112 and the surface of the ferroelectric layer 120. In addition, since the composite structure 129 composed of the ferroelectric layer 120, the buffer layer 121, the channel layer 122, the dielectric pillars 124 and the S/D regions 123, 125 is connected to the dielectric layer 112, the composite structure 129 can provide support for the dielectric layer 112 and prevent the dielectric layer 112 from collapsing after the sacrificial layer 114 is removed. In addition, the peripheral region surrounding the array region with the memory array also has portions of the sacrificial layer 114 that are not removed by the replacement process. Thus, in addition to the composite structure 129, portions of the sacrificial layer 114 in the peripheral region also provide further support to prevent collapse of the dielectric layer 112 in the array region.

Referring to fig. 10A and 10B, a plurality of conductive layers 118 (including 118A, 118B) are formed in the gaps 18 between adjacent dielectric layers 112 to implement the 3D memory device 100. In some embodiments, conductive layer 118 is formed by: depositing a conductive material to fill in the gap 18, covering the upper surface of the topmost dielectric layer 112C and covering the sidewalls of the slot 16; and a portion of the conductive material covering the upper surface of the topmost dielectric layer 112C and the sidewalls of the slots 16 is removed. The remaining portion of the conductive material fills into the gap 18 to form a conductive layer 118. The conductive material may include copper, tungsten, cobalt, aluminum, tungsten nitride, ruthenium, silver, gold, rhodium, molybdenum, nickel, cadmium, zinc, alloys thereof, combinations thereof, and the like, and may be formed by suitable deposition methods (e.g., CVD, PVD, ALD, plating, and the like). In some alternative embodiments, a barrier layer may be formed between the conductive layer 118 and the adjacent dielectric layer 112 to prevent the metal element of the conductive layer 118 from diffusing into the adjacent dielectric layer 112. The barrier layer may also provide the function of increasing adhesion between the conductive layer 118 and the adjacent dielectric layer 112, and may be referred to as a glue layer in some examples. The barrier layer may comprise a metal nitride such as titanium nitride, tantalum nitride, molybdenum nitride, zirconium nitride, hafnium nitride, and the like. In some other embodiments, the barrier layer and the conductive layer 118 are of different conductive materials. For example, conductive layer 118 is made of tungsten and the barrier layer is made of titanium nitride.

FIG. 10C illustrates a plan view along the cross-section B-B of FIG. 10B. As shown in fig. 10C, the memory cell 140 of the 3D memory device 100 is depicted by the dashed box in fig. 10C. The 3D memory device 100 may include a plurality of such memory cells. In detail, the memory cell 140 includes a pair of conductive pillars 123 and 125, a channel layer 122, a buffer layer 121, a ferroelectric layer 120, and a conductive layer 118. The channel layer 122 is disposed on the same side of the conductive pillars 123 and 125. The buffer layer 121 is disposed on the channel layer 122. The ferroelectric layer 120 is disposed between the buffer layer 121 and the conductive layer 118. In this embodiment, the conductive layer 118 may be referred to as a control gate (hereinafter referred to as the control gate 118), and the conductive pillars 123 and 125 may be referred to as S/D regions (hereinafter referred to as the S/D regions 123 and 125). Since ferroelectric layer 120 is disposed between control gate 118 and S/D regions 123 and 125, memory cell 140 may be referred to as a ferroelectric field effect transistor (FeFET) memory cell.

In some embodiments, memory cell 140 can be programmed (e.g., written to and/or read from) by control gate 118 and S/D regions 123 and 125 of the transistor of memory cell 140.

To perform a write operation on a particular memory cell (e.g., memory cell 140), a write voltage is applied to a portion of ferroelectric layer 120 corresponding to memory cell 140. For example, the write voltage may be applied by applying a first voltage to the control gate 118 of the memory cell 140 and a second voltage to the S/D regions 123 and 125. The voltage difference between the first voltage and the second voltage sets (set) the polarization direction of the ferroelectric layer 120. According to the polarization direction of ferroelectric layer 120, threshold voltage V of corresponding transistor of memory cell 140_TCan be controlled from a low threshold voltage V_LSwitching to a high threshold voltage V_HOr vice versa. Threshold voltage value (V) of transistor_LOr V_H) May be used to indicate either a "0" or a "1" bit stored in the memory cell.

To perform a read operation on memory cell 140, a read voltage is applied to the transistor (e.g., between control gate 118 and S/D region 123), which is between the low threshold voltage V_LAnd a high threshold voltage V_HThe voltage in between. The transistor of the memory cell 140 may or may not be turned on according to a polarization direction of the ferroelectric layer 120 (or a threshold voltage of the transistor). Thus, when a voltage is applied, for example, at the S/D region 123, current may pass or may passFlows between the S/D region 123 and the S/D region 125 without passing through the channel layer 122. Thus, the current may be detected to determine the digital bits (digital bits) stored in the memory cells.

Fig. 11A and 11B are plan views of 3D memory devices according to various embodiments.

Referring to fig. 11A, the 3D memory device 200 is similar to the 3D memory device 100 of fig. 10C, but the isolation structure 227 of the 3D memory device 200 is further extended to cut off the buffer layer 121 so that the isolation structure 227 may be in contact with the ferroelectric layer 120. In this case, the isolation structure 227 of the 3D memory device 200 may provide better isolation between adjacent memory cells.

Referring to fig. 11B, the 3D memory device 300 is similar to the 3D memory device 100 of fig. 10C, but the isolation structure 327 of the 3D memory device 300 is further extended to cut off the buffer layer 121 and the ferroelectric layer 120, so that the isolation structure 327 may be in contact with the conductive layer 118A. In this case, isolation structure 327 of 3D memory device 300 may provide better isolation between adjacent memory cells.

FIG. 12 depicts an example of a portion of a memory array 400 according to some embodiments. Fig. 13 is a circuit diagram of the memory array 400 of fig. 12. In some embodiments, the memory array 400 is a NOR (NOR) memory array or architecture. In the following embodiments, a NOR memory array is exemplified, but the embodiments of the present disclosure are not limited thereto.

Referring to fig. 12, the memory array 400 includes a plurality of memory cells 140, and the plurality of memory cells 140 may be arranged in a grid of rows and columns. To avoid clutter, the other memory cells, except memory cell 140, are not marked with dashed boxes. In some embodiments, memory cells 140 in different columns may be arranged in a staggered configuration, as shown in FIG. 12. However, embodiments of the present disclosure are not limited thereto, and in other embodiments, the memory cells 140 in different columns may be arranged in the same or aligned configuration. In addition, the components and configuration of the memory unit 140 are described in detail in the above embodiments, and therefore are not described herein again.

In the top view of fig. 12, the conductive layers 118 and the composite structures 129 extend along the Y direction and are alternately arranged along the X direction. The composite structures 129 in the same column may include a plurality of composite post structures separated from each other by the spacer structures 127. In some embodiments, each of the composite pillar structures includes a pair of conductive pillars 123 and 125. Memory array 400 also includes a plurality of source lines 130 and a plurality of bit lines 132 disposed over memory cells 140. In the top view of FIG. 12, the source lines 130 and bit lines 132 extend along the X direction and are alternately arranged along the Y direction. In detail, one of the source lines 130 is electrically connected to the corresponding conductive pillar 123 in the odd or even column, and one of the bit lines 132 is electrically connected to the corresponding conductive pillar 125 in the even or odd column.

From the perspective of the circuit diagram of fig. 13, each memory cell 140 may include a transistor having a ferroelectric layer 120 and a buffer layer 121 (as shown in fig. 12). In some embodiments, the conductive layer 118 in each memory cell 140 shown in fig. 12 may be used as the word line WL shown in fig. 13. The word lines WL are arranged along the Z direction. Each word line WL connects the gate terminals G of two columns of memory cells 140 adjacent in the lateral direction in the same XY plane. On the other hand, memory cells 140 in the same horizontal row of memory array 400 may share a common word line. In some embodiments, the word line WL is electrically connected to the electrical component 104 (e.g., the S/D region of the transistor) in the FEOL through the conductive feature 105 in the interconnect structure of the underlying structure 101 (fig. 1). In this case, the electrical component 104 may control the switching of the gate terminal G. In addition, the conductive pillar 123 in each memory cell 140 shown in fig. 12 is connected to the source terminal S of the memory cell 140 stacked along the vertical direction Z, as shown in fig. 13. Similarly, the conductive pillar 125 in each memory cell 140 shown in fig. 12 is connected to the drain terminal D of the memory cell 140 stacked along the vertical direction Z, as shown in fig. 13. That is, the source terminals S of the stacked memory cells 140 are connected together by the conductive pillars 123, and the drain terminals D of the stacked memory cells 140 are connected together by the conductive pillars 125. In other words, memory cells 140 in the same vertical column of memory array 400 may share a common source line and a common bit line such that the channels of memory cells 140 in the same vertical column of memory array 400 are connected in parallel. Accordingly, stacked memory cells 140 in the same vertical column may be considered connected by a NOR configuration, and the 3D memory array 400 may be referred to as a 3D NOR memory array.

Fig. 14A-14D are cross-sectional views of a 3D memory device according to some alternative embodiments.

Referring to fig. 14A, a 3D memory device 500 is similar to the 3D memory device 100 of fig. 10B, but the buffer layer 121 in fig. 10B is replaced with a buffer layer 521 having a double-layer structure. Specifically, the buffer layer 521 includes a first dielectric material 521a in contact with the ferroelectric layer 120 and a second dielectric material 521b in contact with the channel layer 122. In some embodiments, the first dielectric material 521a and the second dielectric material 521b have different dielectric constants. In the present embodiment, the first dielectric material 521a is nitrogen-doped Al having a first nitrogen doping concentration₂O₃Layer, second dielectric material 521b being nitrogen doped Al having a second nitrogen doping concentration₂O₃And the first nitrogen doping concentration is less than the second nitrogen doping concentration. The first nitrogen doping concentration may be in a range of 0% to 5%, and the second nitrogen doping concentration may be in a range of 5% to 7%. For example, the first dielectric material 521a is Al doped with nitrogen at a concentration of 4%₂O₃Layer, and the second dielectric material 521b is Al with a nitrogen doping concentration of 6%₂O₃And (3) a layer. In addition, the first dielectric material 521a may be undoped Al with a nitrogen doping concentration of 0%₂O₃Layer or intrinsic Al₂O₃Layer, and the second dielectric material 521b may be Al with a nitrogen doping concentration of 5%₂O₃And (3) a layer. In some alternative embodiments, the first dielectric material 521a may be ZrO₂Layer, and the second dielectric material 521b may be TiO₂And (3) a layer.

Referring to fig. 14B, the 3D memory device 500a is similar to the 3D memory device 500 of fig. 14A, but the first dielectric material 521a and the second dielectric material 521B in fig. 14A are exchanged with each other to form the buffer layer 521' of fig. 14B. That is, the buffer layer 521' includes the second dielectric material 521b in contact with the ferroelectric layer 120 and the first dielectric material 521a in contact with the channel layer 122. The materials and configurations of the first dielectric material 521a and the second dielectric material 521b are described in detail in the above embodiments, and therefore, are not described herein again.

Referring to fig. 14C, the 3D memory device 600 is similar to the 3D memory device 100 of fig. 10B, but the buffer layer 121 in fig. 10B is replaced with a buffer layer 621 having a triple-layer structure. Specifically, the buffer layer 621 includes a first dielectric material 621a in contact with the ferroelectric layer 120, a third dielectric material 621c in contact with the channel layer 122, and a second dielectric material 621b between the first dielectric material 621a and the third dielectric material 621 c. In some embodiments, the first dielectric material 621a, the second dielectric material 621b and the third dielectric material 621c have different dielectric constants. In the present embodiment, the first dielectric material 621a is nitrogen-doped Al having a first nitrogen doping concentration₂O₃Layer, second dielectric material 621b is nitrogen doped Al having a second nitrogen doping concentration₂O₃Layer, the third dielectric material 621c is nitrogen-doped Al having a third nitrogen doping concentration₂O₃And a layer, wherein the first nitrogen doping concentration is less than the second nitrogen doping concentration, and the second nitrogen doping concentration is less than the third nitrogen doping concentration. The first nitrogen doping concentration may be in a range of 0% to 5%, the second nitrogen doping concentration may be in a range of 5% to 7%, and the third nitrogen doping concentration may be in a range of 7% to 10%. For example, the first dielectric material 621a is undoped Al with a nitrogen doping concentration of 0%₂O₃Layer or intrinsic Al₂O₃Layer of the second dielectric material 621b Al with a nitrogen doping concentration of 5%₂O₃Layer, and the third dielectric material 621c is Al with a nitrogen doping concentration of 10%₂O₃And (3) a layer. In some alternative embodiments, the first dielectric material 621a may be Al₂O₃Layer, second dielectric material 621b may be ZrO₂Layer, and the third dielectric material 621c may be TiO₂And (3) a layer.

Referring to fig. 14D, the 3D memory device 600a is similar to the 3D memory device 600 of fig. 14C, but the first and third dielectric materials 621a and 621C in fig. 14C are exchanged with each other to form the buffer layer 621' of fig. 14D. That is, the buffer layer 621' includes a third dielectric material 621c in contact with the ferroelectric layer 120, a first dielectric material 621a in contact with the channel layer 122, and a second dielectric material 621b between the first dielectric material 621a and the third dielectric material 621 c. The materials and configurations of the first dielectric material 621a, the second dielectric material 621b and the third dielectric material 621c are described in detail in the above embodiments, and therefore, are not described in detail herein.

Fig. 15 to 21A are cross-sectional views of a method of forming a 3D memory device according to a second embodiment. Fig. 16B is a top view of the 3D memory device of fig. 16A. Fig. 21B is a plan view along the cross-section C-C of fig. 21A. In some embodiments, the 3D memory device is a NAND (NAND) memory device or the like. In the following embodiments, a NAND memory device is exemplified, but the embodiments of the present disclosure are not limited thereto.

Referring to fig. 15, a layer stack 210 is formed over the underlying structure 101. The materials and configurations of underlying structure 101 are described in detail in the above embodiments and, thus, are not described in detail herein. In detail, the layer stack 210 may include a plurality of dielectric layers 212A, 212B, 212C, 212D and a plurality of sacrificial layers 214A, 214B, 214C alternately stacked on the underlying structure 101. Although only four dielectric layers 212A, 212B, 212C, 212D and three sacrificial layers 214A, 214B, 214C are illustrated in fig. 15, embodiments of the present disclosure are not so limited. In other embodiments, the number of dielectric layers and sacrificial layers may be adjusted as desired. For example, the number of dielectric layers may be 8, 16, 32, or more than 32, and the number of sacrificial layers may be 8, 16, 32, or more than 32. Hereinafter, the dielectric layers 212A, 212B, 212C, 212D are collectively referred to as the dielectric layer 212, and the sacrificial layers 214A, 214B, 214C are collectively referred to as the sacrificial layers 214. The materials and formation methods of the dielectric layer 212 and the sacrificial layer 214 are similar to those of the dielectric layer 112 and the sacrificial layer 114, and are described in detail in the above embodiments, and thus are not repeated herein.

Referring to fig. 16A and 16B, an opening 20 is formed in the layer stack 210 to expose the underlying structure 101. That is, the opening 20 penetrates through the layer stack 210, and the underlying structure 101 is exposed at the bottom of the opening 20. In addition, the opening 20 exposes the sidewall of the dielectric layer 212 and the sidewall of the sacrificial layer 214. Note that although only one opening 20 is illustrated in fig. 16A and 16B, embodiments of the present disclosure are not limited thereto. In other embodiments, one or more openings may be formed through the layer stack 210. Further, the shape of the opening 20 is not limited to a circular shape. That is, the shape of the opening 20 may be elliptical, rectangular, polygonal, or a combination thereof.

Referring to fig. 17, a ferroelectric material 220 is formed to conformally cover the bottom and sidewalls of the opening 20, and also cover the upper surface of the topmost dielectric layer 212D. Ferroelectric material 220 may have a material that is capable of switching between two different polarization directions by applying an appropriate voltage difference across ferroelectric material 220. For example, the polarization of ferroelectric material 220 may change due to the electric field resulting from the application of the voltage difference.

In some embodiments, ferroelectric material 220 can include HZO, HSO, HfSiO, HfLaO, HfO doped with La, Y, Si or Ge₂、HfZrO₂、ZrO₂Or HfO₂And may be formed by PVD, CVD, ALD, etc. In some alternative embodiments, the ferroelectric material 220 may be a high-k dielectric material, such as a hafnium (Hf) -based dielectric material. For example, the ferroelectric material 220 is a compound including hafnium, such as hafnium zirconium oxide (HfZnO), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), hafnium cerium oxide (HfCeO), hafnium oxide (HfO), hafnium gadolinium oxide (HfGdO), hafnium silicon oxide (HfSiO), hafnium zirconium lanthanum oxide (HfZrLaO), hafnium zirconium gadolinium oxide (HfZrGdO), hafnium zirconium yttrium oxide (HfZrYO), hafnium zirconium cerium oxide (HfZrCeO), hafnium zirconium strontium oxide (hfzrsoo), and the like. In addition, the hafnium-containing compound may also be doped with some dopants, such as La, Y, Si, Ge, Ce, Gd, Sr, and the like, or combinations thereof. By doping these dopants in the hafnium containing compound, an orthorhombic lattice structure can be achieved in the ferroelectric material 220. In some embodiments, hafnium-containing compounds having an orthorhombic lattice structure have desirable ferroelectric properties to achieve switchable performance of ferroelectric layers in memory devices. Additionally, by including dopants, the orthorhombic lattice structure in the ferroelectric material 220 may be relatively easily achieved (e.g., at lower temperatures), and the ferroelectric material 220 may be formed within a relatively low thermal budget of the BEOL process (e.g., at temperatures that do not damage front end of line (FEOL) features, such as electrical components in the underlying structure 101Below).

Referring to fig. 18A and 18B, an anisotropic etch process is performed to remove the ferroelectric material 220 on the bottom of the opening 20 and on the upper surface of the topmost dielectric layer 212D. In this case, the ferroelectric layer 220a is formed to cover the sidewalls of the opening 20, and the ferroelectric layer 220a may have a flat top surface 220t1, as shown in fig. 18A. In some alternative embodiments, the ferroelectric layer 220B may have a rounded or curved top surface 220t2 adjacent to the topmost dielectric layer 212D, as shown in fig. 18B.

The following process will be described by taking the structure of fig. 18A as an example. Referring to fig. 19, a buffer layer 221 is formed in the opening 20 to cover the ferroelectric layer 220 a. The material and the forming method of the buffer layer 221 are similar to those of the buffer layer 121, and are described in detail in the above embodiments, and thus are not described again herein. In addition, the buffer layer 221 may include a single layer structure (as shown in fig. 19), a double layer structure (as shown in fig. 14A and 14B), a triple layer structure (as shown in fig. 14C and 14D), or a multi-layer structure.

Referring to fig. 20, a channel layer 222 is formed in the opening 20 to cover the buffer layer 121 and also cover the bottom of the opening 20. Next, dielectric pillars 224 are formed on the channel layer 222 in the openings 20. In some embodiments, the channel layer 222 and the dielectric pillars 224 are formed by: depositing a channel material conformally covering the bottom of the opening 20, the sidewalls of the buffer layer 221, and also covering the upper surface of the topmost dielectric layer 212D; filling a dielectric material in the opening 20; a planarization process, such as a CMP process, is performed to remove excess portions of the dielectric material and excess portions of the channel material from the upper surface of the topmost dielectric layer 212D. In this case, the channel layer 222 is U-shaped in the cross-sectional view of fig. 20 to wrap the sidewalls and bottom surface of the dielectric pillar 224. The materials of the channel layer 222 and the dielectric pillars 224 are similar to those of the channel layer 122 and the dielectric pillars 124, and are described in detail in the above embodiments, and thus are not repeated herein. That is, overlying structures on the underlying structure 101 may be embedded in interconnect structures of the BEOL. In this embodiment, the channel layer 222 may be disposed between any two metal lines in the interconnect structure. For example, the bottom 222b of the channel layer 222 may be disposed on or connected to the metal n (Mn) in the interconnect structure, and the top 222t of the channel layer 222 may be disposed below or connected to the metal n +1(Mn +1) in the interconnect structure.

Referring to fig. 21A and 21B, the steps of replacing the sacrificial layer 214 with the conductive layer 218 (as shown in fig. 20) by a replacement process have been described in detail in fig. 8A to 10A and 8B to 10B, and thus are not described again herein. After the replacement process is performed, the conductive layer 218 (including 218A, 218B, 218C) is formed in the gaps between adjacent dielectric layers 212 to implement the 3D memory device 700. In particular, the 3D memory device 700 may include a layer stack 210 ' disposed on the underlying structure 101, a dielectric pillar 224 penetrating through the layer stack 210 ', a channel layer 222 wrapping the dielectric pillar 224, a ferroelectric layer 220a disposed between the channel layer 222 and the layer stack 210 ', and a buffer layer 221 disposed between the ferroelectric layer 220a and the channel layer 222. In the top view of fig. 21B, the channel layer 222 wraps (e.g., surrounds) the dielectric pillar 224, the buffer layer 221 wraps the channel layer 222, the ferroelectric layer 220a wraps the buffer layer 221, and the conductive layer 218 wraps the ferroelectric layer 220 a.

As shown in fig. 21A, the dashed box in fig. 21A depicts memory cell 740 of 3D memory device 700. The 3D memory device 700 may include a plurality of such memory cells. In detail, the memory cell 740 includes a channel layer 222, a buffer layer 221, a ferroelectric layer 220a, and a conductive layer 218. The buffer layer 221 is disposed between the channel layer 222 and the ferroelectric layer 220 a. The ferroelectric layer 220a is disposed between the buffer layer 221 and the conductive layer 218. In this embodiment, the conductive layer 218 may be referred to as a control gate (hereinafter referred to as the control gate 218). The channel layer 222 has a top 222t and a bottom 222b opposite the top 222 t. The top 222t of the channel layer 222 may be electrically connected to a bit line, and the bottom 222b of the channel layer 222 may be electrically connected to a source line, or vice versa. That is, overlying structures on the underlying structure 101 may be embedded in interconnect structures of the BEOL. In this embodiment, the channel layer 222 may be disposed between any two metal lines in the interconnect structure. For example, the bottom 222b of the channel layer 222 may be disposed on or connected to the metal n (Mn) in the interconnect structure, and the top 222t of the channel layer 222 may be disposed below or connected to the metal n +1(Mn +1) in the interconnect structure. Since ferroelectric layer 220a is disposed between control gate 218 and channel layer 222, memory cell 740 may be referred to as a ferroelectric field effect transistor (FeFET) memory cell.

In some embodiments, the memory cell 740 may be programmed (e.g., written to and/or read from) by the control gate 218 and the channel layer 222 of the transistor of the memory cell 740.

To perform a write operation for a particular memory cell (e.g., memory cell 740), a write voltage is applied to a portion of ferroelectric layer 220a corresponding to memory cell 740. For example, the write voltage may be applied by applying a first voltage to the control gate 218 of the memory cell 740 and a second voltage to a bit line connected to the top 222t of the channel layer 222 and a source line connected to the bottom 222b of the channel layer 222. The voltage difference between the first voltage and the second voltage sets the polarization direction of the ferroelectric layer 220 a. According to the polarization direction of ferroelectric layer 220a, the threshold voltage V of the corresponding transistor of memory cell 740_TCan be controlled from a low threshold voltage V_LSwitching to a high threshold voltage V_HOr vice versa. Threshold voltage value (V) of transistor_LOr V_H) May be used to indicate either a "0" or a "1" bit stored in the memory cell.

To perform a read operation on memory cell 740, a read voltage is applied to the transistor (e.g., between control gate 218 and a source line connected to bottom 222b of channel layer 222), which is between a low threshold voltage V_LAnd a high threshold voltage V_HThe voltage in between. The transistor of the memory cell 740 may or may not be turned on according to a polarization direction of the ferroelectric layer 220a (or a threshold voltage of the transistor). Accordingly, when a voltage is applied, current may or may not flow through the channel layer 222. Thus, the current may be detected to determine the digital bit stored in the memory cell.

Fig. 22 is a cross-sectional view of a 3D memory device according to a third embodiment.

Referring to fig. 22, a 3D memory device 800 is similar to the 3D memory device 700 of fig. 21A, but the U-shaped channel layers 222 in fig. 21A are replaced with a pair of individual channel layers 322 respectively located on sidewalls of the dielectric pillars 224. In some embodiments, the channel layer 322 is formed by: depositing a channel material conformally covering the bottom of the opening 20, the sidewalls of the buffer layer 221, and also covering the upper surface of the topmost dielectric layer 212D; and an anisotropic etch process is then carried out to remove the channel material on the bottom of the opening 20 and on the upper surface of the topmost dielectric layer 212D. The material of the channel layer 322 is similar to that of the channel layer 222, and is described in detail in the above embodiments, and thus is not described herein again. After forming the channel layer 322, dielectric pillars 224 and/or other isolation structures are formed in the openings to electrically isolate the channel layer 322a from the channel layer 322 b. Since the continuous channel layer 222 of fig. 22 is divided into two separate independent channel layers 322a and 322b, the number of memory cells in the 3D memory device 800 is twice the number of memory cells of the 3D memory device 700. Dashed boxes 840A and 840B in fig. 22 illustrate two memory cells formed in a region corresponding to the memory cell 740 in fig. 21A.

Fig. 23 is a cross-sectional view of a 3D memory device according to a fourth embodiment.

Referring to fig. 23, a 3D memory device 900 is similar to the 3D memory device 800 of fig. 22, but the continuous ferroelectric layer 220A of fig. 22 is replaced with a plurality of ferroelectric layers or a plurality of ferroelectric segments 320A, 320B and 320C (collectively referred to as ferroelectric layers 320). The ferroelectric layers 320 are respectively embedded between the adjacent dielectric layers 212 and are in contact with the corresponding conductive layers 218. In some embodiments, one of the ferroelectric layers 320 and the corresponding conductive layer 218 are at substantially the same level. Herein, when elements are described as being "at substantially the same level," the elements are formed at substantially the same height in the same layer or have the same location embedded by the same layer. In some embodiments, the tops of the elements at substantially the same level are substantially coplanar. For example, as shown in fig. 23, the ferroelectric layer 320A and the corresponding conductive layer 218A have the same height in the same layer, and the top surface or the bottom surface of the ferroelectric layer 320A is substantially coplanar with the top surface or the bottom surface of the corresponding conductive layer 218A.

It should be noted that in an embodiment, the separate and individual ferroelectric layers 320 are capable of reducing crosstalk or coupling interference between adjacent memory cells, thereby increasing performance and reliability of the 3D memory device 900.

In some embodiments, ferroelectric layer 320 is formed by adding additional processing steps to the foregoing process steps illustrated in fig. 15-19. In detail, portions of the sacrificial layer 214 in fig. 16A are etched laterally through the openings 20 such that a plurality of spaces are formed between adjacent dielectric layers 212. In this case, the sidewalls of the sacrificial layer 214 are recessed, and the sidewalls of the sacrificial layer 214 are not aligned with the sidewalls of the dielectric layer 212. Next, a ferroelectric material is formed to fill in the space between the adjacent dielectric layers 212. In some embodiments, the ferroelectric material not only fills the spaces between adjacent dielectric layers 212, but also covers the sidewalls of the dielectric layers 212, the upper surface of the topmost dielectric layer 212D, and the bottom of the opening 20. Thereafter, excess portions of the ferroelectric material covering the sidewalls of the dielectric layer 212, the upper surface of the topmost dielectric layer 212D, and the bottom of the opening 20 are removed to form separate and independent ferroelectric layers 320, respectively. Then, a buffer layer 221 is formed to cover the dielectric layer 212 and the ferroelectric layer 320, as shown in fig. 23.

Although the channel layer 322 illustrated in fig. 23 is I-shaped along the sidewalls of the dielectric pillars 224, embodiments of the present disclosure are not limited thereto. In other embodiments, the channel layer of fig. 23 may be U-shaped to wrap around the sidewalls and bottom of the dielectric posts 224, as shown in fig. 21A. In addition, a separate and independent ferroelectric layer 320 may be applicable to the architecture of the 3D memory device 100 illustrated in fig. 10B. In addition, the buffer layer 221 having the single-layer structure of fig. 23 may be replaced with an alternative buffer layer having a double-layer structure (as shown in fig. 14A and 14B), a triple-layer structure (as shown in fig. 14C and 14D), or a multi-layer structure.

Fig. 24 is a cross-sectional view of a 3D memory device according to a fifth embodiment.

Referring to fig. 24, a 3D memory device 1000 is similar to the 3D memory device 900 of fig. 23, but the continuous buffer layer 221 in fig. 23 is replaced with a plurality of buffer layers or buffer segments 321A, 321B, and 321C (collectively referred to as buffer layers 321). The buffer layers 321 are respectively embedded between the adjacent dielectric layers 212 and are in contact with the corresponding ferroelectric layers 320. In some embodiments, one of the buffer layers 321 and the corresponding conductive layer 218 and ferroelectric layer 320 are at substantially the same level. That is, as shown in fig. 24, the buffer layer 321A, the corresponding ferroelectric layer 320A and the corresponding conductive layer 218A have the same height in the same layer, and the top surface or the bottom surface of the buffer layer 321A, the top surface or the bottom surface of the corresponding ferroelectric layer 320A and the top surface or the bottom surface of the corresponding conductive layer 218A are substantially coplanar.

The process steps of the buffer layer 321 are similar to those of the ferroelectric layer 320, and are described in detail in the above embodiments, and thus are not described herein again. After the buffer layer 321 is formed, the channel layer 322 is formed to cover the dielectric layer 212 and the buffer layer 321, as shown in fig. 24. Although the channel layer 322 illustrated in fig. 24 is I-shaped along the sidewalls of the dielectric pillars 224, embodiments of the present disclosure are not limited thereto. In other embodiments, the channel layer of fig. 24 may be U-shaped to wrap around the sidewalls and bottom of the dielectric posts 224, as shown in fig. 21A. In addition, the separate and independent ferroelectric layer 320 and the buffer layer 321 may be suitable for the architecture of the 3D memory device 100 illustrated in fig. 10B. In addition, the buffer layer 321 having the single-layer structure of fig. 24 may be replaced with an alternative buffer layer having a double-layer structure (as shown in fig. 14A and 14B), a triple-layer structure (as shown in fig. 14C and 14D), or a multi-layer structure.

FIG. 25 depicts a flowchart 1200 of a method of forming a 3D memory device according to some embodiments. While the disclosed method 1200 is illustrated and described herein as a series of acts or events, it will be appreciated that the illustrated ordering of such acts or events are not to be interpreted in a limiting sense. For example, some acts may occur in different orders and/or concurrently with other acts or events apart from those illustrated and/or described herein. In addition, not all illustrated acts may be required to implement one or more aspects or embodiments described herein. Further, one or more of the acts depicted herein may be performed in one or more separate acts and/or phases. Fig. 25 may illustrate some embodiments of the method disclosed in fig. 2A-10B.

Referring to fig. 25, at block 1210, a layer stack is formed on a substrate, wherein the layer stack includes a plurality of dielectric layers and a plurality of sacrificial layers that are alternately stacked. Fig. 2A and 2B illustrate top and cross-sectional views corresponding to some embodiments corresponding to block 1210.

At block 1220, a trench is formed in the layer stack to penetrate through the layer stack. Fig. 3A and 3B illustrate top and cross-sectional views corresponding to some embodiments corresponding to block 1220.

At block 1230, a ferroelectric layer is formed to line the sidewalls of the trench. At block 1240, a buffer layer is formed in the trench to cover the ferroelectric layer. At block 1250, a channel layer is formed in the trench to cover the buffer layer. At block 1260, the trench is filled with a dielectric material to form a dielectric pillar. Fig. 4A and 4B illustrate top and cross-sectional views corresponding to some embodiments corresponding to blocks 1230 through 1260.

At block 1270, a pair of conductive posts embedded in the dielectric posts is formed. Fig. 5A-6A and 5B-6B illustrate top and cross-sectional views corresponding to some embodiments corresponding to block 1270.

At block 1280, a replacement process is performed to replace the plurality of sacrificial layers with a plurality of conductive layers. Fig. 8A-10A and 8B-10B illustrate top and cross-sectional views corresponding to some embodiments corresponding to block 1280.

According to an embodiment, a memory device includes a substrate, a layer stack, and a plurality of composite pillar structures. The layer stack is disposed on the substrate. The layer stack includes a plurality of conductive layers and a plurality of dielectric layers that are alternately stacked. The composite post structures penetrate through the layer stacks, respectively. Each composite pillar structure includes a dielectric pillar; a pair of conductive posts penetrating through the dielectric posts and electrically isolated from each other by a portion of the dielectric posts; a channel layer covering both sides of the dielectric pillar and both sides of the pair of conductive pillars; a ferroelectric layer disposed between the channel layer and the layer stack; and a buffer layer disposed between the channel layer and the ferroelectric layer.

In some embodiments, the buffer layer comprises a dielectric material having a dielectric constant greater than 5. In some embodiments, the buffer layer comprises a single layer structure, a double layer structure, a triple layer structure, or a multi-layer structure. In some embodiments, the buffer layer comprises at least: a first dielectric material in contact with the ferroelectric layer; and a second dielectric material in contact with the channel layer, wherein the first dielectric material and the second dielectric material have different dielectric constants. In some embodiments, the buffer layer is a nitrogen-doped dielectric layer, and the nitrogen doping concentration of the buffer layer is graded. In some embodiments, the nitrogen doping concentration of the buffer layer gradually increases along a direction from the ferroelectric layer to the channel layer. In some embodiments, the nitrogen doping concentration of the buffer layer gradually decreases in a direction from the ferroelectric layer to the channel layer. In some embodiments, the memory device further comprises a plurality of isolation structures respectively penetrating through the layer stack and respectively disposed between the plurality of composite pillar structures to electrically isolate the plurality of composite pillar structures, wherein one of the plurality of composite pillar structures and a corresponding conductive layer at one side of the one of the plurality of composite pillar structures constitute a memory cell. In some embodiments, a plurality of memory cells alternately arranged in the Y direction share the same word line, and a plurality of memory cells alternately arranged in the Z direction share the same bit line and the same source line.

According to an embodiment, a memory device includes: a layer stack disposed on a substrate, wherein the layer stack comprises a plurality of conductive layers and a plurality of dielectric layers alternately stacked; a dielectric post penetrating through the layer stack; a channel layer surrounding the dielectric pillar; a ferroelectric layer disposed between the channel layer and the layer stack; and a buffer layer disposed between the ferroelectric layer and the channel layer.

In some embodiments, the channel layer also extends to cover the bottom surface of the dielectric pillar such that the channel layer is U-shaped in cross-section. In some embodiments, the ferroelectric layer is embedded between two adjacent dielectric layers and in contact with the corresponding conductive layer. In some embodiments, the ferroelectric layer and the buffer layer are both embedded between two adjacent dielectric layers, and the ferroelectric layer, the buffer layer and the corresponding conductive layer are at the same level. In some embodiments, the buffer layer comprises at least: a first dielectric material in contact with the ferroelectric layer; and a second dielectric material in contact with the channel layer, wherein the first dielectric material and the second dielectric material have different dielectric constants.

According to an embodiment, a method of forming a memory device includes: forming a layer stack on a substrate, wherein the layer stack comprises a plurality of dielectric layers and a plurality of sacrificial layers that are alternately stacked; forming a trench in the layer stack to penetrate through the layer stack; lining the ferroelectric layer on the sidewalls of the trench; forming a buffer layer in the trench to cover the ferroelectric layer; forming a channel layer in the trench to cover the buffer layer; filling the trench with a dielectric material to form a dielectric pillar; forming a pair of conductive posts embedded in the dielectric posts; and performing a replacement process to replace the plurality of sacrificial layers with a plurality of conductive layers.

In some embodiments, the plurality of dielectric layers and the plurality of sacrificial layers comprise materials having different etch selectivities. In some embodiments, the forming the pair of conductive pillars comprises: forming a first opening and a second opening in the dielectric pillar spaced apart from each other, wherein the first opening and the second opening expose a portion of the substrate; and filling the first opening and the second opening with a conductive material. In some embodiments, the method further comprises: forming a plurality of isolation structures in the dielectric pillar, wherein the plurality of isolation structures extend to sever the channel layer to contact the buffer layer. In some embodiments, the method further comprises: forming a plurality of isolation structures in the dielectric pillars, wherein the plurality of isolation structures extend to sever the channel layer and the buffer layer to contact the ferroelectric layer. In some embodiments, the method further comprises: forming a plurality of isolation structures in the dielectric pillars, wherein the plurality of isolation structures extend to sever the channel layer, the buffer layer, and the ferroelectric layer to contact corresponding ones of the plurality of conductive layers.

The foregoing has outlined features of several embodiments so that those skilled in the art may better understand the various aspects of the disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.