阅读说明：本技术 一种结合鳍式电晶管与soi电晶管的器件结构及制造方法 (Device structure combining fin type transistor and SOI transistor and manufacturing method ) 是由 郑智仁 翁文寅 于 2020-03-24 设计创作，主要内容包括：本发明提供一种结合鳍式电晶管与SOI电晶管的器件结构及制造方法,基底和位于基底上的氧化层；位于氧化层上的薄层硅,位于薄层硅上的多个硅的凸起结构；形成于多个硅的凸起结构表面以及多个硅的凸起结构之间的所述薄层硅上的一层氧化物,覆盖在氧化物表面并填充在多个硅的凸起结构之间的栅极金属层。本发明将传统的鳍式电晶管结构与SOI电晶管相互融合,形成的器件结构的栅极硅凸起结构外覆盖了一层氧化物,在栅极硅凸起之间也存在氧化物,并且栅极硅凸起结构之间的下方并没有完全将硅薄层去除,形成了漏电流的通道,因此在原有的栅极硅凸起结构中形成漏电流的同时,在栅极硅凸起结构之间的底部也同时形成漏电流,进而极大地提高了漏电流。(The invention provides a device structure combining a fin type transistor and an SOI transistor and a manufacturing method thereof, wherein the device structure comprises a substrate and an oxide layer positioned on the substrate; a thin layer of silicon on the oxide layer, a plurality of silicon raised structures on the thin layer of silicon; and a layer of oxide formed on the thin layer of silicon between the plurality of silicon raised structures and the plurality of silicon raised structures, and a gate metal layer covering the oxide surface and filling the plurality of silicon raised structures. According to the invention, the traditional fin type transistor structure and the SOI transistor are fused with each other, a layer of oxide covers the grid silicon bulge structure of the formed device structure, the oxide also exists between the grid silicon bulges, and the silicon thin layer is not completely removed below the grid silicon bulge structures, so that a leakage current channel is formed, and the leakage current is formed at the bottom between the grid silicon bulge structures while the leakage current is formed in the original grid silicon bulge structures, so that the leakage current is greatly improved.)

1. A device structure combining a fin-type transistor and an SOI transistor, the device structure comprising:

a substrate and an oxide layer on the substrate;

the thin silicon layer is positioned on the oxidation layer, and a plurality of silicon protruding structures are positioned on the thin silicon layer;

and the layer of oxide is formed on the surfaces of the plurality of silicon raised structures and the thin layer of silicon between the plurality of silicon raised structures, and the gate metal layer covers the surfaces of the oxide and is filled between the plurality of silicon raised structures.

2. The device structure of claim 1, wherein the fin-type transistor is integrated with an SOI transistor, and wherein: the oxide layer on the substrate is silicon dioxide.

3. The device structure of claim 1, wherein the fin-type transistor is integrated with an SOI transistor, and wherein: the thin silicon layer on the oxide layer is monocrystalline silicon.

4. The device structure of claim 1, wherein the fin-type transistor is integrated with an SOI transistor, and wherein: and the material of the silicon convex structure in the plurality of silicon convex structures positioned on the thin silicon layer is monocrystalline silicon.

5. The device structure of claim 1, wherein the fin-type transistor is integrated with an SOI transistor, and wherein: the oxide formed on the surfaces of the plurality of silicon raised structures and the thin layer of silicon between the plurality of silicon raised structures is a high performance oxide.

6. The device structure of claim 1, wherein the fin-type transistor is integrated with an SOI transistor, and wherein: the height of the plurality of silicon raised structures is 40 nm.

7. The device structure of claim 1, wherein the fin-type transistor is integrated with an SOI transistor, and wherein: the gate metal layer material comprises TiN and TaN.

8. The device structure of claim 1, wherein the fin-type transistor is integrated with an SOI transistor, and wherein: the thickness of the oxide layer is 100 nm.

9. The device structure of claim 1, wherein the fin-type transistor is integrated with an SOI transistor, and wherein: the thickness of the thin layer of silicon is 30 nm.

10. The device structure of claim 1, wherein the fin-type transistor is integrated with an SOI transistor, and wherein: the oxide thickness was 10 angstroms.

11. The method of fabricating a device structure incorporating a fin-type transistor and an SOI transistor according to any one of claims 1 to 10, wherein: the method comprises the following steps:

providing a silicon substrate, and forming an oxide layer on the silicon substrate;

depositing a silicon layer on the oxide layer;

etching the silicon layer to form a plurality of silicon protruding structures, and stopping etching until the distance between the silicon layer between the formed silicon protruding structures and the oxide layer is 30nm to form a thin silicon layer between the silicon protruding structures;

depositing a layer of oxide on the plurality of silicon raised structures and the thin silicon among the silicon raised structures;

and fifthly, depositing a grid metal layer on the surface of the oxide, wherein the grid metal layer is filled among the plurality of silicon protruding structures.

Technical Field

The invention relates to the field of semiconductor manufacturing, in particular to a device structure combining a fin type transistor and an SOI transistor and a manufacturing method thereof.

Background

Disclosure of Invention

In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a device structure and a manufacturing method for combining a fin-type transistor and an SOI transistor, so as to solve the problems that the process for manufacturing a FinFET structure is complicated and the leakage current cannot be effectively increased in the prior art.

To achieve the above and other related objects, the present invention provides a device structure combining a fin transistor and an SOI transistor, the device structure at least comprising: a substrate and an oxide layer on the substrate;

the thin silicon layer is positioned on the oxidation layer, and a plurality of silicon protruding structures are positioned on the thin silicon layer;

and the layer of oxide is formed on the surfaces of the plurality of silicon raised structures and the thin layer of silicon between the plurality of silicon raised structures, and the gate metal layer covers the surfaces of the oxide and is filled between the plurality of silicon raised structures.

Preferably, the oxide layer on the substrate is silicon dioxide.

Preferably, the thin layer of silicon on the oxide layer is monocrystalline silicon.

Preferably, the material of the silicon protruding structures in the plurality of silicon protruding structures on the thin layer of silicon is monocrystalline silicon.

Preferably, the oxide formed on the surface of the plurality of silicon raised structures and the thin layer of silicon between the plurality of silicon raised structures is a high performance oxide.

Preferably, the height of the plurality of silicon bump structures is 40 nm.

Preferably, the gate metal layer material comprises TiN and TaN.

Preferably, the thickness of the oxide layer is 100 nm.

Preferably, the thickness of the thin layer of silicon is 30 nm.

Preferably, the oxide is 10 angstroms thick.

The invention also provides a manufacturing method of the device structure combining the fin type transistor and the SOI transistor, which comprises the following steps:

providing a silicon substrate, and forming an oxide layer on the silicon substrate;

depositing a silicon layer on the oxide layer;

etching the silicon layer to form a plurality of silicon protruding structures, and stopping etching until the distance between the silicon layer between the formed silicon protruding structures and the oxide layer is 30nm to form a thin silicon layer between the silicon protruding structures;

depositing a layer of oxide on the plurality of silicon raised structures and the thin silicon among the silicon raised structures;

and fifthly, depositing a grid metal layer on the surface of the oxide, wherein the grid metal layer is filled among the plurality of silicon protruding structures.

As described above, the device structure and the manufacturing method of the invention combining the fin transistor and the SOI transistor have the following advantages: according to the invention, the traditional fin type transistor structure and the SOI transistor are fused with each other to form a new device structure, a layer of oxide covers the grid silicon bulge structure of the device structure, the oxide also exists between the grid silicon bulges, and the silicon thin layer is not completely removed below the grid silicon bulge structures to form a leakage current channel, so that the leakage current is formed at the bottom between the grid silicon bulge structures while the leakage current is formed in the original grid silicon bulge structure, and the leakage current is further greatly improved.

Drawings

FIGS. 1a and 1b are schematic diagrams of an in-process FinFET structure in the prior art;

FIG. 2 shows an SEM image of a FinFET structure in a conventional process;

fig. 3 is a cross-sectional view of a device structure incorporating a fin transistor and an SOI transistor according to the present invention;

fig. 4 is a schematic flow diagram illustrating the leakage current in the device structure of the present invention.

Detailed Description

The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.

Please refer to fig. 3 to 4. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.

The invention provides a device structure combining a fin-type transistor and an SOI transistor, and as shown in FIG. 3, FIG. 3 is a cross-sectional view of the device structure combining the fin-type transistor and the SOI transistor. The device structure at least comprises: a substrate and an oxide layer on the substrate; that is, the oxide layer 02 is disposed on the substrate 01 in fig. 3, and further, the oxide layer 02 is silicon dioxide. The oxide layer 02 is a Silicon-On-Insulator (SOI) layer, which is Silicon On an insulating substrate, i.e., a buried oxide layer is introduced between the top Silicon and the backing substrate.

The thin silicon layer is positioned on the oxidation layer, and a plurality of silicon protruding structures are positioned on the thin silicon layer; further, the thin layer of silicon on the oxide layer is monocrystalline silicon. The invention still further provides that the raised structure material of silicon in the plurality of raised structures of silicon on the thin layer of silicon is monocrystalline silicon. In this embodiment, the thickness of the oxide layer is 100 nm.

And the layer of oxide is formed on the surfaces of the plurality of silicon raised structures and the thin layer of silicon between the plurality of silicon raised structures, and the gate metal layer covers the surfaces of the oxide and is filled between the plurality of silicon raised structures. Further, the oxide formed on the surface of the plurality of silicon raised structures and the thin layer of silicon between the plurality of silicon raised structures is a high performance oxide. Further, the height of the plurality of silicon protruding structures is 40 nm. Still further, the gate metal layer material comprises TiN and TaN. In the embodiment, the thickness of the thin layer of silicon is 30 nm. Further, the oxide thickness was 10 angstroms.

The invention also provides a manufacturing method of the device structure combining the fin type transistor and the SOI transistor, which comprises the following steps:

providing a silicon substrate, and forming an oxide layer on the silicon substrate; referring to fig. 3, fig. 3 is a cross-sectional view of a device structure incorporating a fin transistor and an SOI transistor according to the present invention. An oxide layer 02 is formed on the silicon substrate 01, in this embodiment, the oxide layer 02 is formed by a deposition method, and further, the oxide layer 02 formed in this step is silicon dioxide, and the thickness of the silicon dioxide is 100 nm. The oxide layer 02 is a Silicon-On-Insulator (SOI) layer, which is Silicon On an insulating substrate, i.e., a buried oxide layer is introduced between the top Silicon and the backing substrate.

Depositing a silicon layer on the oxide layer; in this embodiment, this step deposits a layer of the silicon layer on the oxide layer (silicon dioxide) 02, and in this embodiment, the silicon layer is monocrystalline silicon.

Etching the silicon layer to form a plurality of silicon protruding structures, and stopping etching until the distance between the silicon layer between the formed silicon protruding structures and the oxide layer is 30nm to form a thin silicon layer between the silicon protruding structures; that is, as shown in fig. 3, the plurality of silicon protruding structures 03 formed after etching stop etching until the remaining thickness of the silicon layer on the oxide layer 02 is 30nm, and the thin silicon layer 003 is formed.

Depositing a layer of oxide on the plurality of silicon raised structures and the thin silicon among the silicon raised structures; the oxide 04 covers the outer surfaces of the plurality of silicon raised structures 03 and the upper surface of the thin layer of silicon 003 covering the space between the plurality of silicon raised structures 03. The oxide 04 is a high performance oxide.

And fifthly, depositing a grid metal layer on the surface of the oxide, wherein the grid metal layer is filled among the plurality of silicon protruding structures. As shown in fig. 3, this step covers a layer of gate metal layer 05 on the oxide 04, and further, the gate metal layer 05 contains TiN and TaN, and the gate metal layer 05 fills in between the silicon raised structures 03 while covering the oxide 04.

As shown in fig. 4, fig. 4 is a schematic flow diagram illustrating the leakage current in the device structure of the present invention. Leakage current is formed in the original grid silicon protruding structures, and meanwhile leakage current channels are formed at the bottoms between the grid silicon protruding structures.

In summary, the conventional fin-type transistor structure and the SOI transistor are fused with each other to form a new device structure, a layer of oxide covers the gate silicon bump structure of the device structure, the oxide exists between the gate silicon bumps, and the silicon thin layer is not completely removed below the gate silicon bump structures to form a leakage current channel, so that the leakage current is formed at the bottom between the gate silicon bump structures while the leakage current is formed in the original gate silicon bump structures, and the leakage current is greatly improved. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.

The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.