阅读说明：本技术 一种叠层片式高通滤波器 (Laminated high-pass filter ) 是由 卓群飞 梁启新 付迎华 简丽勇 马龙 刘月泳 于 2020-03-12 设计创作，主要内容包括：一种叠层片式高通滤波器,包括基体、设置在基体外侧的输入端P1、输出端P2、接地端P3和接地端P4以及设置在基体内部的电路层,所述的基体内部的电路层呈叠层结构,所述的电路层包括有七层,本发明的有益效果是：本发明以LTCC(低温共烧陶瓷)技术为基础,采用集总参数模型设计实现叠层片式高通滤波器的特殊电性能要求；本发明有效实现了高通滤波器的特性,且具有低损耗、高抑制、高可靠性、低成本和适合于大规模的生产等优点,另外还适应了新的电子元件集成化、小型化的发展趋势。(The invention discloses a laminated high-pass filter, which comprises a base body, an input end P1, an output end P2, a grounding end P3, a grounding end P4 and a circuit layer arranged in the base body, wherein the input end P1, the output end P2, the grounding end P3 and the grounding end P4 are arranged outside the base body, the circuit layer in the base body is of a laminated structure, and the circuit layer comprises seven layers, and the laminated high-pass filter has the advantages that: the invention is based on LTCC (low temperature co-fired ceramic) technology, and adopts lumped parameter model design to realize the special electrical property requirement of the laminated high-pass filter; the invention effectively realizes the characteristics of the high-pass filter, has the advantages of low loss, high inhibition, high reliability, low cost, suitability for large-scale production and the like, and is also suitable for the development trend of integration and miniaturization of new electronic elements.)

1. The laminated high-pass filter is characterized by comprising a base body, an input end P1, an output end P2, a grounding end P3, a grounding end P4 and a circuit layer, wherein the input end P1, the output end P2, the grounding end P3 and the grounding end P4 are arranged on the outer side of the base body, the circuit layer is arranged inside the base body, the circuit layer inside the base body is of a laminated structure, and the circuit layer comprises seven layers:

a first layer, wherein a first layer of first metal patterns 1a, a first layer of second metal patterns 1b and a first layer of third metal patterns 1c are printed on a ceramic dielectric substrate;

a second layer, on which a second layer of first metal patterns 2a, a second layer of second metal patterns 2b, a second layer of third metal patterns 2c and a second layer of fourth metal patterns 2d are printed, wherein the second layer of first metal patterns 2a is connected with the input end P1; the second-layer fourth metal pattern 2d is connected to the output terminal P2;

a third layer, wherein metal patterns are printed on the ceramic dielectric substrate, and the third layer of the first substrate 3a, the third layer of the second substrate 3b, the third layer of the third substrate 3c and the third layer of the fourth substrate 3d are respectively arranged on the ceramic dielectric substrate, the third layer of the first substrate 3a and the third layer of the second substrate 3b form a third layer of the first inductor, and the third layer of the third substrate 3c and the third layer of the fourth substrate 3d form a third layer of the second inductor; wherein the third layer of the first substrate 3a and the second layer of the first metal pattern 2a form a high-pass filter first capacitor C1; the third layer of the second substrate 3b, the second layer of the second metal pattern 2b and the first layer of the first metal pattern 1a jointly form a third capacitor C3 of the high-pass filter; the third layer of the third substrate 3C and the second layer of the third metal pattern 2C jointly form a high-pass filter fifth capacitor C5; the third layer of the fourth substrate 3d, the second layer of the fourth metal pattern 2d and the first layer of the third metal pattern 1C jointly form a seventh capacitor C7 of the high-pass filter;

a fourth layer, printing a fourth layer of first metal patterns 4a, a fourth layer of second metal patterns 4b and a fourth layer of third metal patterns 4c on the ceramic dielectric substrate, wherein the fourth layer of first metal patterns 4a is connected with the third layer of second substrate 3b through a fourth layer of first dot columns v1 a; the fourth layer of second metal pattern 4b is connected with the first layer of second metal pattern 1b through a fourth layer of second dot column v1b to form a high-pass filter fourth capacitor C4; the fourth layer third metal pattern 4c is connected to the third layer fourth substrate 3d through the fourth layer third dot column v1 c;

a fifth layer, wherein a fifth layer first metal pattern 5a, a fifth layer second metal pattern 5b and a fifth layer third metal pattern 5c are printed on the ceramic dielectric substrate; the fifth layer first metal pattern 5a is connected with the fourth layer first metal pattern 4a through a dot column to form a high-pass filter first inductor L1; the fifth layer second metal pattern 5b is connected with the fourth layer second metal pattern 4b through a dot column to form a high-pass filter second inductor L2; the fifth-layer third metal pattern 5c is connected with the fourth-layer third metal pattern 4c through a dot column to form a third inductor L3 of the high-pass filter;

a sixth layer, wherein a sixth layer of first metal patterns 6a and a sixth layer of second metal patterns 6b are printed on the ceramic dielectric substrate; the sixth-layer first metal pattern 6a is connected to the fifth-layer first metal pattern 5a through a sixth-layer first dot column v2a, and the sixth-layer second metal pattern 6b is connected to the fifth-layer third metal pattern 5c through a sixth-layer second dot column v2 c;

a seventh layer, printing a seventh layer of first metal patterns 7 on the ceramic dielectric substrate; the seventh layer of first metal pattern 7 and the sixth layer of first metal pattern 6a form a high-pass filter second capacitor C2; the seventh layer first metal pattern 7 and the seventh layer first dot column v2b are connected to the fifth layer second metal pattern 5 b; the seventh layer first metal pattern 7 and the sixth layer second metal pattern 6b constitute a sixth high-pass filter capacitor C6.

Technical Field

The invention discloses a novel miniaturized laminated high-pass filter which is suitable for 5G mobile communication base station equipment.

Background

Low Temperature Co-fired Ceramic (LTCC) is a high density packaging technology with a wide application range, and its excellent electronic, mechanical and thermal characteristics have become the first choice for future electronic element integration and modularization, and is generally applied in multi-layer Chip circuit modularization (MICMI) design. The radio frequency microwave elements and modules designed and produced on the basis of the LTCC technology comprise a balun filter, a multiplexer, a duplexer, an antenna, a coupler, a balun, a receiving front-end module, an antenna switch module and the like. In addition to advantages in cost and integrated packaging, there are many advantages in terms of wiring line width and pitch, low impedance metallization, design versatility, and high frequency performance. As modern electronic devices are increasingly miniaturized and high-frequency, they have been widely used for miniaturized electronic devices.

In the field of mobile communications, communication products have more and more functions, and available spectrum resources are particularly important, and filters of various frequency bands are required to separate different signals. In the design of communication products, discrete low-pass filters can be adopted to process input signals of different frequency bands, and the chip type high-pass filter manufactured by adopting the LTCC technology has the advantages of high reliability, low insertion loss, high selectivity, small volume, light weight, easiness in integration, low cost and the like, and is suitable for large-scale production, so that the application is very wide.

Disclosure of Invention

The invention provides a novel miniaturized laminated high-pass filter, which adopts a lumped parameter design structure and is formed by adding a transmission zero outside a high-pass filter prototype. The high-pass filter provided by the invention is formed by adopting an LTCC technology and then co-firing at a low temperature of about 900 ℃.

The technical scheme adopted by the invention for solving the technical problems is as follows: the utility model provides a novel miniaturized stromatolite formula high pass filter, includes the base member, sets up input P1, output P2, earthing terminal P3 and earthing terminal P4 and set up the circuit layer in the base member outside the base member, the inside circuit layer of base member be laminated structure, the circuit layer including seven layers, seven layer structures are as follows:

a first layer, wherein a first layer of first metal patterns 1a, a first layer of second metal patterns 1b and a first layer of third metal patterns 1c are printed on a ceramic dielectric substrate;

a second layer, on which a second layer of first metal pattern 2a, a second layer of second metal pattern 2b, a second layer of third metal pattern 2c and a second layer of fourth metal pattern 2d are printed, wherein the second layer of first metal pattern 2a is connected with an input end P1 to form an input port of the high-pass filter; the second layer of fourth metal pattern 2d is connected with the output end P2 to form a filter output port;

a third layer, wherein metal patterns are printed on the ceramic dielectric substrate, and the third layer of the first substrate 3a, the third layer of the second substrate 3b, the third layer of the third substrate 3c and the third layer of the fourth substrate 3d are respectively arranged on the ceramic dielectric substrate, the third layer of the first substrate 3a and the third layer of the second substrate 3b form a third layer of the first inductor, and the third layer of the third substrate 3c and the third layer of the fourth substrate 3d form a third layer of the second inductor; wherein the third layer of the first substrate 3a and the second layer of the first metal pattern 2a form a high-pass filter first capacitor C1; the third layer of the second substrate 3b, the second layer of the second metal pattern 2b and the first layer of the first metal pattern 1a jointly form a third capacitor C3 of the high-pass filter; the third layer of the third substrate 3C and the second layer of the third metal pattern 2C jointly form a high-pass filter fifth capacitor C5; the third layer of the fourth substrate 3d, the second layer of the fourth metal pattern 2d and the first layer of the third metal pattern 1C jointly form a seventh capacitor C7 of the high-pass filter;

a fourth layer, printing a fourth layer of first metal patterns 4a, a fourth layer of second metal patterns 4b and a fourth layer of third metal patterns 4c on the ceramic dielectric substrate, wherein the fourth layer of first metal patterns 4a is connected with the third layer of second substrate 3b through a fourth layer of first dot columns v1 a; the fourth layer of second metal pattern 4b is connected with the first layer of second metal pattern 1b through a fourth layer of second dot column v1b to form a high-pass filter fourth capacitor C4; the fourth layer third metal pattern 4c is connected to the third layer fourth substrate 3d through the fourth layer third dot column v1 c;

a fifth layer, wherein a fifth layer first metal pattern 5a, a fifth layer second metal pattern 5b and a fifth layer third metal pattern 5c are printed on the ceramic dielectric substrate; the fifth layer first metal pattern 5a is connected with the fourth layer first metal pattern 4a through a dot column to form a high-pass filter first inductor L1; the fifth layer second metal pattern 5b is connected with the fourth layer second metal pattern 4b through a dot column to form a high-pass filter second inductor L2; the fifth-layer third metal pattern 5c is connected to the fourth-layer third metal pattern 4c through a dot column, so that a high-pass filter third inductor L3 is formed.

A sixth layer, wherein a sixth layer of first metal patterns 6a and a sixth layer of second metal patterns 6b are printed on the ceramic dielectric substrate; the sixth-layer first metal pattern 6a is connected to the fifth-layer first metal pattern 5a through a sixth-layer first dot column v2a, and the sixth-layer second metal pattern 6b is connected to the fifth-layer third metal pattern 5c through a sixth-layer second dot column v2 c;

a seventh layer, printing a seventh layer of first metal patterns 7 on the ceramic dielectric substrate; the seventh layer of first metal pattern 7 and the sixth layer of first metal pattern 6a form a high-pass filter second capacitor C2; the seventh layer first metal pattern 7 and the seventh layer first dot column v2b are connected to the fifth layer second metal pattern 5 b; the seventh layer first metal pattern 7 and the sixth layer second metal pattern 6b constitute a sixth high-pass filter capacitor C6.

The invention has the beneficial effects that: the invention is based on LTCC (low temperature co-fired ceramic) technology, and adopts lumped parameter model design to realize the special electrical property requirement of the laminated high-pass filter; the invention effectively realizes the characteristics of the high-pass filter, has the advantages of low loss, high inhibition, high reliability, low cost, suitability for large-scale production and the like, and is also suitable for the development trend of integration and miniaturization of new electronic elements.

The invention will be further described with reference to the accompanying drawings and specific embodiments.

Drawings

FIG. 1 is a schematic diagram of an equivalent circuit of a novel stacked-layer high-pass filter according to the present invention;

FIG. 2 is a perspective view of the novel stacked high-pass filter according to the present invention;

FIG. 3 is a schematic diagram of the internal structure of the novel stacked-layer high-pass filter according to the present invention;

FIG. 4 is a schematic diagram of a first layer circuit plan structure according to the present invention;

FIG. 5 is a schematic diagram of a second layer circuit structure according to the present invention;

FIG. 6 is a schematic diagram of a third layer circuit plan structure according to the present invention;

FIG. 7 is a schematic view of a point-pillar connection plane between the third layer and the fourth layer according to the present invention;

FIG. 8 is a schematic diagram of a fourth layer circuit plan structure according to the present invention;

FIG. 9 is a schematic circuit plan view of a fifth layer according to the present invention;

FIG. 10 is a schematic view of a point-pillar connection between the fifth layer and the sixth layer according to the present invention;

FIG. 11 is a schematic diagram of a sixth layer circuit plan structure according to the present invention;

fig. 12 is a schematic diagram of a seventh layer circuit plane structure according to the present invention.

Detailed Description

Please refer to fig. 1, which is an equivalent circuit diagram of a stacked-layer high-pass filter. Signals enter the port and are output from the port II, the high-pass filter is composed of a first inductor (L1), a second inductor (L2), a third inductor (L3), a first capacitor (C1), a third capacitor (C3), a fifth capacitor (C5) and a seventh capacitor (C7), the first inductor (L1) and the second capacitor (C2) form series resonance to form a first transmission zero in a stop band of the high-pass filter, the second inductor (L2) and the fourth capacitor (C4) form series resonance to form a second transmission zero in the stop band of the high-pass filter, the third inductor (L3) and the sixth capacitor (C6) form series resonance to form a third transmission zero in the stop band of the high-pass filter, and stop band attenuation of the high-pass filter is effectively improved.

Fig. 2 is an external structure of the stacked-chip high-pass filter, in which P1 is a signal input terminal, P2 is a signal output terminal, and P3 and P4 are ground ports, respectively.

The internal structure of the laminated high-pass filter is shown in fig. 3, and fig. 4-12 are exploded views of layers, the circuit structures are distributed in the ceramic substrate, and the circuit structure has a total of 7 layers:

a first layer, as shown in fig. 4, a first layer of first metal patterns (1a), a first layer of second metal patterns (1b) and a first layer of third metal patterns (1c) are printed on a ceramic dielectric substrate;

a second layer, as shown in fig. 5, on which a second layer of first metal patterns (2a), a second layer of second metal patterns (2b), a second layer of third metal patterns (2c) and a second layer of fourth metal patterns (2d) are printed, wherein the second layer of first metal patterns (2a) is connected with the input end (P1); the second layer fourth metal pattern (2d) is connected with the output terminal (P2);

a third layer, as shown in fig. 6, metal patterns are printed on the ceramic dielectric substrate, which are respectively a third layer of first substrate (3a), a third layer of second substrate (3b), a third layer of third substrate (3c) and a third layer of fourth substrate (3d), wherein the third layer of first substrate (3a) and the third layer of second substrate (3b) form a third layer of first inductor, and the third layer of third substrate (3c) and the third layer of fourth substrate (3d) form a third layer of second inductor; wherein the third layer of the first substrate (3a) and the second layer of the first metal pattern (2a) form a high-pass filter first capacitor (C1); the third layer of the second substrate (3b), the second layer of the second metal pattern (2b) and the first layer of the first metal pattern (1a) jointly form a third capacitor (C3) of the high-pass filter; the third layer of third substrate (3C) and the second layer of third metal pattern (2C) jointly form a high-pass filter fifth capacitor (C5); the third layer of the fourth substrate (3d), the second layer of the fourth metal pattern (2d) and the first layer of the third metal pattern (1C) jointly form a seventh capacitor (C7) of the high-pass filter;

a fourth layer, as shown in fig. 7 and 8, a fourth layer of first metal patterns (4a), a fourth layer of second metal patterns (4b) and a fourth layer of third metal patterns (4c) are printed on the ceramic dielectric substrate, and the fourth layer of first metal patterns (4a) is connected with the third layer of second substrate (3b) through fourth layer of first dot columns (v1 a); the fourth layer of second metal pattern (4b) is connected with the first layer of second metal pattern (1b) through a fourth layer of second point column (v1b) to form a high-pass filter fourth capacitor (C4); the fourth layer of the third metal pattern (4c) is connected with the third layer of the fourth substrate (3d) through a fourth layer of the third dot columns (v1 c);

a fifth layer, as shown in fig. 9, a fifth layer of first metal patterns (5a), a fifth layer of second metal patterns (5b) and a fifth layer of third metal patterns (5c) are printed on the ceramic dielectric substrate; the fifth layer first metal pattern (5a) is connected with the fourth layer first metal pattern (4a) through a dot column to form a first inductor (L1) of the high-pass filter; the fifth layer second metal pattern (5b) is connected with the fourth layer second metal pattern (4b) through a dot column to form a high-pass filter second inductor (L2); the fifth layer third metal pattern (5c) is connected with the fourth layer third metal pattern (4c) through a dot column to form a third inductor (L3) of the high-pass filter;

a sixth layer, as shown in fig. 10 and 11, printing a sixth layer of the first metal pattern (6a) and a sixth layer of the second metal pattern (6b) on the ceramic dielectric substrate; the sixth layer first metal pattern (6a) is connected with the fifth layer first metal pattern (5a) through a sixth layer first dot column (v2a), and the sixth layer second metal pattern (6b) is connected with the fifth layer third metal pattern (5c) through a sixth layer second dot column (v2 c);

a seventh layer, as shown in fig. 12, printing a seventh layer of the first metal pattern (7) on the ceramic dielectric substrate; the seventh layer of first metal pattern (7) and the sixth layer of first metal pattern (6a) form a high-pass filter second capacitor (C2); the seventh layer first metal pattern (7) is connected with the fifth layer second metal pattern (5b) through a seventh layer first dot column (v2 b); the seventh layer first metal pattern (7) and the sixth layer second metal pattern (6b) form a sixth capacitor (C6) of the high-pass filter.