阅读说明：本技术 使用固件的存储器装置策略执行 (Memory device policy enforcement using firmware ) 是由 G·卡列洛 J·S·帕里 于 2019-12-27 设计创作，主要内容包括：本申请涉及使用固件的存储器装置策略执行。一种存储器装置可包括非易失性存储器单元阵列和经配置以控制对所述非易失性存储器单元阵列的存取的存储器控制器。所述存储器控制器可包含经配置以控制存储器装置性能来执行存储器装置策略的固件。所述存储器控制器可包含经配置以存储指示所述存储器装置策略的数据的至少一个硬件寄存器。所述固件可经配置以读取指示所述存储器装置策略的所述数据并通过控制存储器装置性能来执行所述存储器装置策略。(The application relates to memory device policy enforcement using firmware. A memory device may include an array of non-volatile memory cells and a memory controller configured to control access to the array of non-volatile memory cells. The memory controller may include firmware configured to control memory device performance to execute memory device policies. The memory controller may include at least one hardware register configured to store data indicative of the memory device policy. The firmware may be configured to read the data indicative of the memory device policy and to execute the memory device policy by controlling memory device performance.)

1. A memory device, comprising:

an array of non-volatile memory cells; and

a memory controller configured to control access to the array of non-volatile memory cells, the memory controller including firmware configured to control memory device performance to execute memory device policies, the memory controller including:

at least one hardware register configured to store data indicative of the memory device policy; and is

The firmware is configured to read the data indicative of the memory device policy and to execute the memory device policy by controlling memory device performance.

2. The memory device of claim 1, wherein controlling memory device performance includes throttling performance of the memory device.

3. The memory device of claim 2, wherein the memory device includes a serial interface and throttling performance includes controlling a number of channels used for serial communication through the serial interface of the memory device.

4. The memory device of claim 2, wherein throttling performance includes limiting data transfer speed.

5. The memory device of claim 2, wherein throttling performance includes limiting an amount of data transferred over a period of time.

6. The memory device of claim 1, wherein controlling memory device performance includes performing a system reset of the memory device.

7. The memory device of claim 1, wherein controlling memory device performance includes entering a write protect mode of the memory device.

8. The memory device of claim 1, wherein controlling memory device performance includes simulating a hardware failure of the memory device.

9. The memory device of claim 1, wherein the firmware is configured to read data indicative of the memory device policy during idle time when data is not being transferred.

10. The memory device of claim 1, wherein the firmware is configured to read the data indicative of the memory device policy during Error Correction Code (ECC) processing when performance is affected by high activity.

11. A system, comprising:

a host controller configured to serially communicate with a memory device using a minimum of two channels; and

the memory device includes an array of non-volatile memory cells; and

a memory controller configured to communicate with the host controller and control access to the array of non-volatile memory cells using the at least two channels, the memory controller including firmware configured to control memory device performance to execute memory device policies,

the memory controller includes:

at least one hardware register configured to store data indicative of the memory device policy; and is

The firmware is configured to read the data indicative of the memory device policy and to execute the memory device policy by controlling memory device performance, wherein controlling memory device performance includes at least one of:

controlling a number of channels of the at least two channels to be used for serial communication;

limiting a data transfer speed;

limiting an amount of data transferred over a period of time;

performing a system reset of the memory device;

entering a write-protect mode of the memory device; or

Simulating a hardware failure in the memory device.

12. The system of claim 11, wherein the system includes a phone, and the phone includes the host controller and the memory controller.

13. The system of claim 11, wherein the memory controller is configured for sending a request to a permission grant server for a different permission to change a memory device performance and receiving data indicative of the permission, updating the at least one hardware register to update the memory device policy based on the received data indicative of the permission, and executing the updated memory device policy by controlling a memory device performance.

14. The system of claim 11, wherein the firmware is configured to read the data indicative of the memory device policy during at least one of:

idle time when data is not transferred, or

Error Correction Code (ECC) processing while data requires additional Low Density Parity Check (LDPC) correction loops and the processor of the memory controller is waiting for results.

15. A method, comprising:

executing a memory device policy using firmware within a memory controller of a memory device, comprising:

storing data indicative of a memory device policy within at least one hardware register in the memory controller;

reading the data indicative of the memory device policy; and

controlling memory device performance to enforce the memory device policy.

16. The method of claim 15, wherein controlling memory device performance includes throttling performance of the memory device.

17. The method of claim 16, wherein throttling performance includes controlling a number of channels used for serial communication over a serial interface of the memory device.

18. The method of claim 16, wherein throttling performance comprises limiting data transfer speed.

19. The method of claim 16, wherein throttling performance comprises limiting an amount of data transferred over a period of time.

20. The method of claim 15, wherein controlling memory device performance includes performing a system reset of the memory device.

21. The method of claim 15, wherein controlling memory device performance includes entering a write protect mode of the memory device.

22. The method of claim 15, wherein controlling memory device performance includes simulating a hardware failure in the memory device.

23. A method, comprising:

executing a memory device policy using firmware within a memory controller of a memory device, comprising:

storing data indicative of a memory device policy within at least one hardware register in the memory controller;

reading the data indicative of the memory device policy; and

controlling memory device performance to execute the memory device policy, wherein controlling memory device performance includes at least one of:

controlling a number of channels used by a serial interface of the memory device,

limiting the data transfer rate, an

The amount of data over a period of time is limited.

24. The method of claim 23, further comprising reading the data indicative of the memory device policy during idle time when data is not being transferred.

25. The method of claim 23, further comprising reading the data indicative of the memory device policy during Error Correction Code (ECC) processing when the memory device performance is affected by high activity.

Technical Field

The present application relates to memory devices, and in particular, to memory device policy enforcement using firmware.

Background

Memory devices are typically provided as internal semiconductor integrated circuits in computers or other electronic devices. There are many different types of memory, including volatile and non-volatile memory. Volatile memory requires power to maintain its data and includes Random Access Memory (RAM), Dynamic Random Access Memory (DRAM), or Synchronous Dynamic Random Access Memory (SDRAM), among others. Non-volatile memory can retain stored data when not powered and includes flash memory, Read Only Memory (ROM), electrically erasable programmable ROM (eeprom), static ram (sram), erasable programmable ROM (eprom), resistance variable memory, such as Phase Change Random Access Memory (PCRAM), Resistive Random Access Memory (RRAM), Magnetoresistive Random Access Memory (MRAM), or storage class (e.g., memristor) memory, among others.

Flash memory is used as non-volatile memory for a wide range of electronic applications. Flash memory devices typically include one or more groups of single transistor floating gate or charge well memory cells that allow for high memory density, high reliability, and low power consumption. Two common types of flash memory array architectures include NAND and NOR architectures, named in the logical form in which each's basic memory cell configuration is arranged. The memory cells of a memory array are typically arranged in a matrix. In an example, the gate of each floating gate memory cell in a row of the array is coupled to an access line (e.g., a word line). In the NOR architecture, the drain of each memory cell in a column of the array is coupled to a data line (e.g., a bit line). In a NAND architecture, the drains of each memory cell in a string of the array are coupled together in series, source to drain, between a source line and a bit line. The word lines coupled to the gates of each group of unselected memory cells are driven at a specified pass voltage (e.g., Vpass) to cause each group of unselected memory cells to operate as pass transistors (e.g., pass current in a manner that is unrestricted by their stored data values).

Each flash memory cell in a NOR or NAND architecture semiconductor memory array can be programmed individually or collectively to one or several programmed states. For example, a Single Level Cell (SLC) may represent one of two programmed states (e.g., 1 or 0), representing one bit of data. However, flash memory cells can also represent one of more than two programmed states, allowing higher density memory to be fabricated without increasing the number of memory cells, as each cell can represent more than one binary digit (e.g., more than one bit). Such cells may be referred to as multi-state memory cells, multi-bit cells, or multi-level cells (MLCs). In some examples, an MLC may refer to a memory cell that may store two bits of data per cell (e.g., one of four programmed states), a three-level cell (TLC) may refer to a memory cell that may store three bits of data per cell (e.g., one of eight programmed states), and a four-level cell (QLC) may store four bits of data per cell. MLC is used herein in its broadest context to refer to any memory cell that can store more than one bit of data per cell (i.e., can represent more than two programmed states).

A conventional memory array is a two-dimensional (2D) structure disposed on a surface of a semiconductor substrate. To increase memory capacity and reduce cost for a given area, the size of individual memory cells has been reduced. However, there are technical limitations to the size reduction of individual memory cells, and thus, the memory density of 2D memory arrays. In response, three-dimensional (3D) memory structures, such as 3D NAND architecture semiconductor memory devices, are being developed to further increase memory density and reduce memory cost.

The memory arrays or devices may be combined together to form the storage capacity of a memory system, such as Solid State Drives (SSDs), Universal Flash Storage (UFS) devices, multi-media card (MMC) solid state memory devices, and embedded MMC (emmc) devices. These devices are particularly useful as the main storage device for computers, which is superior to conventional hard disk drives having moving parts in terms of, for example, performance, size, weight, durability, operating temperature range, and power consumption. For example, these devices may have reduced seek times, latency, or other electromechanical delays associated with the disk drive. These devices may also use non-volatile flash memory cells to eliminate internal battery power requirements, thus allowing the drive to be more versatile and compact.

These solid state devices may include a number of memory devices, including a number of dies or Logical Units (LUNs). Each die may include a number of memory arrays and peripheral circuitry thereon, and the memory arrays may include a number of blocks of memory cells organized into a number of physical pages. The solid state device may receive commands from the host in conjunction with memory operations, such as read or write operations to transfer data (e.g., user data and associated integrity data, such as error data and address data, etc.) between the memory device and the host, or erase operations to erase data from the memory device.

Disclosure of Invention

In one aspect, the present application relates to a memory device comprising: an array of non-volatile memory cells; and a memory controller configured to control access to the array of non-volatile memory cells, the memory controller including firmware configured to control memory device performance to execute a memory device policy, the memory controller including: at least one hardware register configured to store data indicative of the memory device policy; and the firmware is configured to read the data indicative of the memory device policy and to execute the memory device policy by controlling memory device performance.

In another aspect, the present application relates to a system comprising: a host controller configured to serially communicate with a memory device using a minimum of two channels; and the memory device includes an array of non-volatile memory cells; and a memory controller configured to communicate with the host controller using the at least two channels and to control access to the array of non-volatile memory cells, the memory controller including firmware configured to control memory device performance to execute memory device policies, the memory controller including: at least one hardware register configured to store data indicative of the memory device policy; and the firmware is configured to read the data indicative of the memory device policy and execute the memory device policy by controlling memory device performance, wherein controlling memory device performance includes at least one of: controlling a number of channels of the at least two channels to be used for serial communication; limiting a data transfer speed; limiting an amount of data transferred over a period of time; performing a system reset of the memory device; entering a write-protect mode of the memory device; or to simulate a hardware failure in the memory device.

In another aspect, the present application relates to a method comprising: executing a memory device policy using firmware within a memory controller of a memory device, comprising: storing data indicative of a memory device policy within at least one hardware register in the memory controller; reading the data indicative of the memory device policy; and controlling memory device performance to enforce the memory device policy.

In yet another aspect, the present application relates to a method comprising: executing a memory device policy using firmware within a memory controller of a memory device, comprising: storing data indicative of a memory device policy within at least one hardware register in the memory controller; reading the data indicative of the memory device policy; and controlling memory device performance to execute the memory device policy, wherein controlling memory device performance includes at least one of: controlling the number of channels used by a serial interface of the memory device, limiting data transfer speed, and limiting the amount of data over a period of time.

Drawings

Various embodiments are illustrated by way of example in the figures of the accompanying drawings. Such embodiments are illustrative, and are not intended to be exhaustive or exclusive embodiments of the present subject matter.

Figure 1 shows a diagram of an example of a UFS system.

FIG. 2 shows an example block diagram of a memory device including a memory controller and a memory array.

FIG. 3 illustrates an example block diagram of a memory controller.

FIG. 4 shows an example of an environment including a host device and a managed memory device.

FIG. 5 illustrates an example block diagram of a memory device.

FIG. 6 shows an example schematic of a 3D NAND architecture semiconductor memory array.

FIG. 7 shows another example schematic of a 3D NAND architecture semiconductor memory array.

FIG. 8 shows another example schematic of a portion of a 3D NAND architecture semiconductor memory array.

FIG. 9 illustrates, by way of example and not limitation, an embodiment of a method for providing a memory device policy to a memory device for the memory device to execute.

Fig. 10 illustrates, by way of example and not limitation, an embodiment of a process performed by a memory device and an OEM license server.

FIG. 11 illustrates some non-limiting example licensing models and corresponding memory device policies.

FIG. 12 illustrates, by way of example and not limitation, a block diagram of a system including a host and a memory device configured to execute memory device policies.

Fig. 13 illustrates a block diagram of an example machine on which any one or more of the techniques (e.g., methods) discussed herein may be executed.

Detailed Description

Some mobile electronic devices, such as smart phones, tablet computers, etc., can be broken down into several major components: a processor (e.g., a Central Processing Unit (CPU) or other main processor); a Graphics Processing Unit (GPU); memory (e.g., Random Access Memory (RAM), such as dynamic RAM (dram), mobile or low power DDR RAM, etc.); a storage device (e.g., a non-volatile memory (NVM) device such as flash memory, Read Only Memory (ROM), Solid State Drive (SSD), or other memory device, etc.); and a user interface (e.g., a display, a touch screen, a keyboard, one or more buttons, etc.). Different electronic devices have different storage requirements.

Software (e.g., programs), instructions, an Operating System (OS), and other data are stored on the storage device and loaded into memory for use by the processor. Memory (e.g., DRAM) is typically faster but volatile, and thus is a different type of storage than storage devices (e.g., SSD) that are suitable for long term storage, including long term storage when in an "off condition. Programs, instructions or data in use by a user or mobile electronic device are typically loaded into memory for use by the processor.

In contrast, embedded MMC (MC eM) devices are attached to a circuit board and are considered components of host devices with read speeds comparable to those of serial ATA (SATA) -based SSD devices.

In response, the storage device has been transferred from parallel to a serial communication interface. Universal Flash Storage (UFS) devices, including controllers and firmware, communicate with host devices using a Low Voltage Differential Signaling (LVDS) serial interface with dedicated read/write paths, further advancing higher read/write speeds. UFS devices may be used with mobile devices or other electronic devices as discussed above.

The inventors of the present invention have recognized that it is particularly desirable to provide different performance affecting features to a device at different price points, and that firmware within a memory device may be used to implement memory device policies by controlling memory device performance. A memory device may include an array of non-volatile memory cells and a memory controller configured to access the array of non-volatile memory cells. The memory controller may include firmware configured to control memory device performance to execute memory device policies. The memory controller may include at least one hardware register configured to store data indicative of a memory device policy. The firmware may be configured to read data indicative of a memory device policy and to execute the memory device policy by controlling memory device performance. Thus, by way of example and not limitation, a permission at a first price point may indicate a first memory device policy that provides a first device performance level using a set of device features, and a permission at a second price point may indicate a second memory device policy that provides a second device performance level using a different set of device features. The enforcement of memory device policies will be discussed in more detail below after an overview of a system including memory devices.

Figure 1 shows a diagram of an example of a UFS system 100. UFS system 100 is shown to contain a UFS host 101 and a UFS device 102. UFS host 1010 contains application 103 that wishes to read or write data to UFS device 102. An application 103 on the UFS host 101 uses a UFS driver 104, and the UFS driver 104 manages a UFS host controller 105 using a set of registers through a UFS host controller interface. UFS host controller 105 communicates with UFS interconnect 107 of UFS device 102 using UFS interconnect 106. The UFS interconnect includes a physical layer and provides basic transport capabilities. The physical layer may be a differential duplex PHY comprising TX and RX pairs. PHY refers to circuitry for implementing physical layer functions and connects link layer devices (commonly known by the acronym MAC for media access control) to the physical medium. UFS interconnect 107 communicates with components of UFS device 102. UFS device 102 includes, among other things, a device-level manager 108 that provides device-level features (e.g., power management). The descriptor 109 stores configuration related information. The storage 110 may be segmented into a plurality of Logical Units (LUs) 0-N (111, 112, 113) that handle read/write and other storage related commands. For example, a 16GB UFS device may be configured with 4 LUs per 4 GB.

While the disclosure herein may be described with respect to UFSs, one of ordinary skill in the art having the benefit of this disclosure will recognize that the disclosed improvements may also be applied to emmcs and other interfaces between a storage device and a host.

FIG. 2 shows an example block diagram of a memory device 202 including a memory controller 215 and a memory array 210 having a plurality of memory cells 214, and a host 201 external to the memory device 202. One or more physical interfaces may be used to transfer data between the memory device 202 and the host 201. By way of example and not limitation, the physical interface may include a Serial Advanced Technology Attachment (SATA) interface, a peripheral component interconnect express (PCIe) interface, a Universal Serial Bus (USB) interface, M-PHY for UFS, 8-bit parallel, eMMC, or one or more other physical connectors or interfaces. Host 201 may include a host system such as a personal computer, digital camera, mobile electronic device, memory card reader, or one or more other electronic devices external to memory device 202.

Memory controller 215 may receive instructions from host 201 and may communicate with memory array 210 to transfer (e.g., write or erase) data to one or more memory cells 214 in memory array 210 or to transfer (e.g., read) data from the memory cells 214. Memory controller 215 may include circuitry or firmware, among other things. For example, the memory controller 215 may include one or more memory control units, circuits, or components configured to control access within the memory array 210 and provide a translation layer between the host 201 and the memory device 202. Memory controller 215 may include one or more input/output (I/O) circuits, lines, or interfaces to transfer data to or from memory array 210.

Fig. 3 illustrates an example block diagram of a memory controller 315, such as memory controller 215 shown in fig. 2. The memory controller 315 is shown to contain a memory management component 316 and a memory controller component 317. Memory management component 316 may include, among other things, circuitry or firmware, such as a number of components or integrated circuits associated with various memory management functions, including wear leveling (e.g., garbage collection or reclamation), error detection or correction, block de-registration, or one or more other memory management functions. The memory management component 316 can parse or format host commands (e.g., commands received from a host) into device commands (e.g., commands associated with operation of a memory array, etc.), or generate device commands for the memory controller component 317 or one or more other components of the memory device (e.g., to implement various memory management functions).

Memory management component 316 may include a management table 318 configured to hold various information associated with one or more components of a memory device, such as various information associated with a memory array or one or more memory cells coupled to memory controller 315. For example, the management table 318 may include information regarding a block age, a block erase count, an error history, or one or more error counts (e.g., a write operation error count, a read bit error count, a read operation error count, an erase error count, etc.) of one or more blocks of memory cells coupled to the memory controller 315. In some examples, a bit error may be referred to as an uncorrectable bit error if the number of errors in the one or more error counts detected is above a threshold. The management table 318 may hold, among other things, a count of correctable or uncorrectable bit errors.

The memory management component 316 may include a Redundant Array of Independent Disks (RAID) unit 319 (the term "disk" is a continuation of previous implementations where disk drives have been used and does not require that the RAID unit 319 include physical disks). The RAID unit 319 may provide data reliability through redundant memory operations and redundant memory storage, among other things.

The memory management component 316 may include protected memory functions, such as a Replay Protected Memory Block (RPMB) function 320. For example, RPMB provides a means for host system 201 to store data to a particular memory region in an authenticated and playback protected manner by device 202. To provide the RPMB, the programming authentication key information is first provided to the UFS device memory. The authentication key is used to sign read and write accesses made to the replay protected memory region with a Message Authentication Code (MAC). RPMB enables secure storage of sensitive data such as Digital Rights Management (DRM) keys. The RPMB cannot be accessed by normal means but is instead accessed using a specific set of commands and using a secure protocol. The RPMB is authenticated using the security key.

The memory management component 316 may include UFS messaging 321. Messages convey information between the UFS host and the device. The message may contain a UFS Protocol Information Unit (UPIU), which is a defined data structure containing several sequentially addressed bytes arranged as individual information fields. There are different types of UPIU. All UPIU structures contain a common header area at the beginning (lowest address) of the data structure. The remaining fields of the structure vary depending on the type of UPIU.

Memory management component 316 may include a performance throttle 322 that provides device-side control of data transfer speed. A storage device, such as a NAND device, may have one or more indicators that trigger performance throttling to prevent damage to the storage device, and to prevent errors in reading values from the storage device, and so forth. For example, high temperatures (ambient or device temperature) may affect the reliability of the memory device and may result in increased power consumption due to increased transistor leakage at high temperatures. The memory device may have the ability to throttle performance to reduce self-heating to help control device temperature and avoid excessive power consumption. For example, circuitry and/or firmware within a controller of a memory device may respond to a temperature sensor output (internal or external environmental sensor) indicating a crossing of a temperature threshold by setting an over temperature exception register and throttling performance. In other examples, circuitry and/or firmware may set a performance throttling exception event register and throttle performance. Throttling may mean accessing fewer NAND memory cells at the same time, accessing NAND memory cells (e.g., pages) at reduced NAND interface speed, and so forth. As described in more detail below, various embodiments may implement memory device policies using performance throttling to adjust memory device performance.

Memory controller component 317 may include, among other things, the following circuitry or components: configured to control memory operations associated with writing data to one or more memory cells of a memory device coupled to memory controller 315, reading data from one or more memory cells of a memory device coupled to memory controller 315, or erasing one or more memory cells of a memory device coupled to memory controller 315. The memory operation may be based on a host command (e.g., associated with wear leveling, error detection or correction, etc.), such as received from a host or generated internally by the memory management component 316 or the memory controller component 317. The memory controller component 317 may include an Error Correction Code (ECC) component 323, which ECC component 323 may include, among other things, an ECC engine or other circuitry configured to detect or correct errors associated with writing data to or reading data from one or more memory cells of a memory device coupled to the memory controller 315. The memory controller 315 may be configured to efficiently detect and recover from error phenomena (e.g., bit errors, operational errors, etc.) associated with various operations or data storage, while maintaining the integrity of data transferred between the host and the memory devices, or maintaining the integrity of stored data (e.g., using redundant RAID storage in the RAID units 319, etc.), and may remove (e.g., log out) failed memory resources (e.g., memory units, memory arrays, pages, blocks, etc.) from future errors.

FIG. 4 shows an example of an environment 424 that includes a host device 401 and a managed memory device 402 that are configured to communicate with each other via a communication interface. Thus, as described herein, actions attributed to host device 401 are outside of those of managed memory device 402, as shown, even when managed memory device 402 is a package within host device 401. Thus, in some examples, managed memory device 402 may be included as part of host 401, or managed memory device 402 may be a separate component external to host device 401. The host device 401 or managed memory device 402 may be included in a variety of products, such as, by way of example and not limitation, a mobile communication device 425, an automobile 426, an appliance 427, or other internet of things (IoT) devices (e.g., sensors, motors or actuators, drones, etc.) that support processing, communication, or control of the product.

The managed memory device 402 includes a memory controller 415 and a memory array 410 that includes, for example, a number of individual memory devices (e.g., each memory device is a stack of three-dimensional (3D) NAND dies). Thus, managed memory device 402 includes memory controller 415 and one or more memory devices. In examples without managed memory device 402, memory controller 415 or its equivalent may be part of host device 401 and external to the package that includes the one or more memory devices of memory array 410. In 3D architecture semiconductor memory technology, vertical structures are stacked, increasing the number of layers, physical pages, and thus the density of a given memory device (e.g., storage device).

In an example, managed memory device 402 may be a discrete memory or storage component of host device 401. In other examples, managed memory device 402 may be part of an integrated circuit (e.g., a system on a chip (SoC), etc.) that is stacked or otherwise included with one or more other components of host device 401.

Data may be communicated between the managed memory device 402 and one or more other components of the host device 401 using one or more communication interfaces, such as a Serial Advanced Technology Attachment (SATA) interface, a peripheral component interconnect express (PCIe) interface, a Universal Serial Bus (USB) interface, a Universal Flash Storage (UFS) interface, an eMMC^TMAn interface, or one or more other connectors or interfaces. The host device 401 may include a host system, an electronic device, a processor, control circuitry, or a memory card reader. In some examples, host device 401 may be a machine having some or all of the components discussed with reference to the machine of fig. 4. Data may be transferred between managed memory device 402 and other components via an I/O bus.

The memory controller 415 may receive instructions from processing circuitry (e.g., a processor) of the host device 401 and may communicate with the memory array 410 to transfer (e.g., write or erase) data to or from one or more of the memory devices and associated memory cells, planes, sub-blocks, or pages of the memory array 410. Memory controller 415 may include, among other things, circuitry or firmware, including one or more components or integrated circuits. For example, the memory controller 415 may include one or more circuits, control circuitry, or components configured to control access within the memory array 410 and provide a translation layer between the host device 401 and the memory devices of the memory array 410. The memory controller 415 may include one or more input/output (I/O) circuits, lines, or interfaces to transfer data to or from the memory array 410. The memory controller 415 may include a memory manager 416 and an array controller 417. The array controller 417 may include, among other things, circuitry or components configured to control memory operations associated with: writing data to one or more memory cells of a memory device in the memory array 410, reading data from one or more memory cells of a memory device in the memory array 410, or erasing one or more memory cells of a memory device in the memory array 410. The memory operation may be based on a host command (e.g., associated with wear leveling, error detection or correction, etc.), such as received from processing circuitry of the host device 401 or generated internally by the memory manager 416.

In operation, data is typically written to or read from the NAND managed memory device 402 in pages and erased in blocks. However, one or more memory operations (e.g., read, write, erase, etc.) may be performed on larger or smaller groups of memory cells as desired. The data transfer size of the NAND managed memory device 402 is commonly referred to as a page, while the data transfer size of the host is commonly referred to as a sector.

The array controller 417 may include an Error Correction Code (ECC) component 423, which ECC component 423 may include, among other things, an ECC engine or other circuitry configured to detect or correct errors associated with: data is written to or read from one or more memory cells of a memory device coupled to memory controller 415. The memory manager 416 may comprise, among other things, circuitry or firmware, such as a number of components or integrated circuits associated with various memory management functions. For purposes of this description, example memory operations and management functions will be described in the context of a NAND memory. Those skilled in the art will recognize that other forms of non-volatile memory may have similar memory operation or management functions. Such NAND management functions include wear leveling (e.g., garbage collection or reclamation), error detection (e.g., Bit Error Rate (BER) monitoring) or correction, block de-registration, or one or more other memory management functions. The memory manager 416 may parse or format host commands (e.g., commands received from processing circuitry of the host device 401) into device commands (e.g., commands associated with operation of a memory array, etc.), or generate device commands for the array controller 417 or one or more other components of the managed memory device 424 (e.g., to achieve various memory management functions). In an example, some of these operations may be implemented in the memory control unit of each memory device in the memory array 120.

The memory array 410 may include one or more memory devices. An individual memory device may include a number of memory cells arranged, for example, in a number of devices, planes, sub-blocks, or pages. As one example, a 48GB TLC NAND memory device may include 18,592 bytes (16,384+2208 bytes) of data per page, 1536 pages per block, 548 blocks per plane, and four or more planes per device. As another example, a 32GB MLC memory device, storing two bits of data per cell (i.e., four programmable states), may include 18,592 bytes per page (16,384+2208 bytes) of data, 1024 pages per block, 548 blocks per plane, and four planes per device, but the required write time is half and the encoding/erasing (P/E) cycle is twice as compared to a corresponding TLC memory device. Other examples may include other numbers or arrangements. In some examples, the memory device or portions thereof may be selectively operated in SLC mode or in a desired MLC mode (e.g., TLC, QLC, etc.).

Different types of memory devices may provide different page sizes, or may require different amounts of metadata associated therewith. For example, different memory device types may have different bit error rates, which may result in a different amount of metadata being required to ensure the integrity of a data page (e.g., a memory device with a higher bit error rate may require more bytes of error correction code data than a memory device with a lower bit error rate). As an example, multi-level cell (MLC) NAND flash memory devices may have a higher bit error rate than corresponding single-level cell (SLC) NAND flash memory devices. Thus, MLC devices may require more bytes of metadata for error data than corresponding SLC devices.

Fig. 5 shows an example block diagram of a memory device 502, the memory device 502 including a memory array 510 having a plurality of memory cells 514 and one or more circuits or components that provide communication with or perform one or more memory operations on the memory array 510. Memory device 502 may include a row decoder 528, a column decoder 529, sense amplifiers 530, page buffers 531, selectors 532, input/output (I/O) circuits 533, and a memory control unit 515. Memory cells 514 of memory array 510 may be arranged in rows, columns, pages, and blocks, and may be accessed using, for example, access lines 534, data lines 535, or one or more select gates, etc.

Memory control unit 515 may control memory operations of memory device 502 according to one or more signals or instructions received over control lines 536, including, for example, one or more clock signals or control signals indicating a desired operation (e.g., write, read, erase, etc.), or address signals (a0-AX) received over address lines 537. One or more devices external to the memory device 502 can control the value of a control signal on a control line 536 or an address signal on an address line 537. Examples of devices external to memory device 502 may include, but are not limited to, a host, a memory controller, a processor, or one or more circuits or components not shown in fig. 5.

Memory device 502 can transfer (e.g., write or erase) data to or from one or more of memory cells 514 using access lines 534 and data lines 535. As described above, row decoder 528 and column decoder 529 can receive and decode address signals (A0-AX) from address lines 537, can determine which memory cell 514 will be accessed, and can provide signals to one or more of access lines 534 (e.g., one or more of a plurality of word lines (WL 0-WLm)) or data lines 535 (e.g., one or more of a plurality of bit lines (BL 0-BLn)).

Memory device 502 can include sensing circuitry, such as sense amplifier 530, configured to determine (e.g., read) a value of data on memory cell 514, or to determine a value of data to be written to memory cell 514, using data line 535. For example, in a selected string of memory cells, one or more of the sense amplifiers 530 may read a logic level in the selected memory cell in response to a read current flowing in the memory array through the selected string to the data line 535.

One or more devices external to memory device 502 may communicate with memory device 502 using I/O lines (DQ0-DQN)538, address lines 537(A0-AX), or control lines 536. Input/output (I/O) circuitry 533 may transfer values of data into or out of memory device 502, e.g., into or out of page buffer 531 or memory array 510, using I/O lines 538, according to control lines 536 and address lines 537, for example. The page buffer 531 may store data received from one or more devices external to the memory device 502 before the data is programmed into the relevant portion of the memory array 510, or may store data read from the memory array 510 before the data is transmitted to one or more devices external to the memory device 502.

Column decoder 529 can receive and decode address signals (A0-AX) into one or more column address signals (CSEL 1-CSELn). A selector 532 (e.g., a selection circuit) may receive the column select signal and select data in page buffer 531 representing a value of data to be read from memory cell 514 or programmed into memory cell 514. Selected data may be transferred between page buffer 531 and I/O circuitry 533 using data lines 539.

The memory control unit 515 may receive positive and negative power supply signals, such as a supply voltage (Vcc)540 and a negative power supply (Vss)541 (e.g., ground potential), from an external source or power supply (e.g., an internal or external battery, an AC-DC converter, etc.). In some examples, memory control unit 515 may include regulator 542 to provide a positive or negative power supply signal internally.

In three-dimensional (3D) architecture semiconductor memory technology, vertical structures are stacked, increasing the number of layers, physical pages, and thus the density of memory devices, such as the storage devices described above.

FIG. 6 shows an example schematic of a 3D NAND architecture semiconductor memory array 610 including a plurality of strings of memory cells, each string including 32-layer (TIER0-TIER31) charge storage transistors stacked source-to-drain in the Z-direction from a source-side Select Gate (SGS) to a drain-side Select Gate (SGD). Each memory cell string in a 3D memory array may be arranged as a data line (e.g., a Bit Line (BL)) along the Y-direction and as a physical page (P0-P15) along the X-direction. Within a physical page (e.g., P0), each level represents a row of memory cells and each string of memory cells represents a column. A block of memory cells may include a number of physical pages (e.g., 128, 384, etc.). In other examples, each memory cell string may include more or fewer levels (e.g., 8, 16, 64, 128, etc.) as desired, as well as one or more additional levels of semiconductor material (e.g., select gates, data lines, etc.) above or below the charge storage transistors.

Each memory cell in the memory array 610 includes a control gate coupled to (e.g., electrically connected or otherwise operably connected to) an access line (e.g., a word line) that collectively couples the control gates across a particular level or portion of a level, as desired. A particular level in the 3D memory array, and thus a particular memory cell in a string, may be accessed or controlled using a respective access line. For example, the memory device 610 includes a first level of semiconductor material 643 (e.g., polysilicon, etc.) coupling the control gates of each memory cell in the TIER31, and a second level of semiconductor material 644 coupling the source side Select Gates (SGS) of the array. Similar levels of metal or semiconductor material may couple each level of control gates. A particular string of memory cells in the array can be accessed, selected, or controlled using a combination of Bit Lines (BL) and select gates, etc., and a particular memory cell at one or more levels in a particular string can be accessed, selected, or controlled using one or more access lines (e.g., word lines).

FIG. 7 shows a 3D NAND architecture semiconductor memory array 710, which includes organizing into blocks (e.g., block a 745A, block B745B, etc.) and sub-blocks (e.g., sub-block a)₀745A₀Subblock A_n745A_nsub-Block B₀745B₀Sub-block 745_n301B_nEtc.). Memory array 710 represents a portion of a greater number of similar structures than are typically found in a block, device, or other unit of a memory device.

Each memory cell string includes several levels of charge storage transistors (e.g., floating gate transistors, charge trapping structures, etc.) stacked in a source-to-drain manner in the Z-direction between a source line (SRC) or source-side Select Gate (SGS) and a drain-side Select Gate (SGD). Each memory cell string in a 3D memory array may be arranged as a data line (e.g., Bit Line (BL) BL0-BL2) along the X-direction and as a physical page along the Y-direction.

Within a physical page, each level represents a row of memory cells and each string of memory cells represents a column. A sub-block may include one or more physical pages. A block may include a number of sub-blocks (or physical pages) (e.g., 128, 256, 384, etc.). The illustrated memory device, provided for purposes of description, includes two blocks, each block having two sub-blocks, each sub-block having a single physical page, where each physical page has three strings of memory cells, and each string has 8 levels of memory cells. In a practical device, the memory array 300 will typically include a much larger number of blocks, sub-blocks, physical pages, strings of memory cells, and/or tiers. For example, each memory cell string may include a selected number of levels (e.g., 16, 32, 64, 128, etc.) as well as one or more additional levels of semiconductor material (e.g., select gates, data lines, etc.) above or below the charge storage transistors, as desired. As an example, a 48GB TLC NAND memory device may include 18,592 bytes (B) of data per page (16,384+2208 bytes), 1536 pages per block, 548 blocks per plane, and 4 or more planes per device.

Each memory cell in the memory array 710 includes a Control Gate (CG) coupled to (e.g., electrically connected or otherwise operably connected to) an access line (e.g., Word Line (WL)) that commonly couples the Control Gate (CG) across a particular level or portion of a level, as desired. A particular level in the 3D memory array 710, and therefore a particular memory cell in a string, may be accessed or controlled using a respective access line. Various select lines may be used to access groups of select gates.

FIG. 8 shows an example schematic of a portion of a 3D NAND architecture semiconductor memory array 810 including a plurality of memory cells 814 arranged in a two-dimensional array of strings (e.g., first string 846, second string 847, third string 848, and fourth string 849) and levels (e.g., TIER0-TIER7850, 851, 852, 853, 854, 855, 856, 857), and sense amplifiers 830. For example, the memory array 810 may show an example schematic of a portion of a physical page of memory cells of a 3D NAND architecture semiconductor memory device. Each memory cell string is coupled to a source line (SRC) using a respective source-side Select Gate (SGS) (e.g., first SGS858, second SGS 859, third SGS 860, or fourth SGS 861) and to a respective data line (e.g., first, second, third, or fourth bit lines (BL0-BL3)862, 863, 864, 865) using a respective drain-side Select Gate (SGD) (e.g., first SGD 866, second SGD 867, third SGD 868, or fourth SGD 869). Although shown in the example of FIG. 9 as having 8 levels (TIER0-TIER 7912-926, e.g., using Word Lines (WL) WL0-WL7) and 4 data lines (BL0-BL 3928-934), other examples may include memory cell strings having more or fewer levels (e.g., 16, 32, 64, etc.) or data lines, as desired.

In a NAND architecture semiconductor memory array, such as the example memory array 900, the state of a selected memory cell can be accessed by sensing a change in current or voltage associated with a particular data line containing the selected memory cell. The memory array 900 may be accessed using one or more drivers (e.g., by control circuitry, one or more processors, digital logic, etc.). In an example, depending on the type of desired operation to be performed on a particular memory cell or set of memory cells, one or more drivers may activate the particular memory cell or set of memory cells by driving a particular potential to one or more data lines (e.g., bit lines BL0-BL3), access lines (e.g., word lines WL0-WL7), or select gates.

To program or write data to the memory cells, a program voltage (Vpgm) (e.g., one or more program pulses, etc.) may be applied to the selected word line (e.g., WL4), and thus to the control gate of each memory cell coupled to the selected word line (e.g., the first, second, third, or fourth control gates 870, 871, 872, 873 of the memory cell coupled to WL 4). The programming pulses may begin, for example, at or near 15V, and in some instances may increase in magnitude during the application of each programming pulse. While a programming voltage is applied to the selected word line, potentials such as ground potential (e.g., Vss) may be applied to the data lines (e.g., bit lines) and the substrate (and thus the channel between the source and drain) of the memory cell targeted for programming, resulting in charge transfer (e.g., direct injection or Fowler-Nordheim (FN) tunneling, etc.) from the channel to the floating gate of the targeted memory cell.

In contrast, a pass voltage (Vpass) may be applied to one or more word lines having memory cells that are not targeted for programming, or an inhibit voltage (e.g., Vcc) may be applied to data lines (e.g., bit lines) having memory cells that are not targeted for programming, for example, to inhibit charge transfer from the channel to the floating gates of these non-targeted memory cells. The pass voltage may vary, for example, depending on the proximity of the applied pass voltage to the word line that is the target of programming. The inhibit voltage may include a supply voltage (Vcc) relative to a ground potential (e.g., Vss), such as a voltage from an external source or supply (e.g., a battery, an AC/DC converter, etc.).

As an example, if a programming voltage (e.g., 15V or higher) is applied to a particular word line, such as WL4, a pass voltage of 10V may be applied to one or more other word lines, such as WL3, WL5, etc., to inhibit programming of non-target memory cells, or to maintain the value stored on these memory cells that are not the programming target. As the distance between the applied programming voltage and the non-target memory cells increases, the pass voltage required to inhibit programming of the non-target memory cells may decrease. For example, in the case of applying a program voltage of 15V to WL4, a pass voltage of 10V may be applied to WL3 and WL5, a pass voltage of 8V may be applied to WL2 and WL6, a pass voltage of 7V may be applied to WL1 and WL7, and the like. In other examples, the pass voltage or number of word lines, etc. may be higher or lower, or more or less.

Sense amplifier 830 coupled to one or more of the data lines (e.g., first, second, third, or fourth bit lines (BL0-BL3)862, 863, 864, 865) can detect the state of each memory cell in the respective data line by sensing a voltage or current on the particular data line.

Between the application of one or more programming pulses (e.g., Vpgm), a verify operation can be performed to determine whether the selected memory cell has reached its intended programmed state. If the selected memory cell has reached its intended programmed state, it can be inhibited from further programming. Additional programming pulses may be applied if the selected memory cell has not reached its intended programmed state. If the selected memory cells have not reached their intended programmed state after a certain number of programming pulses (e.g., a maximum number), the selected memory cells, or strings, blocks, or pages associated with these selected memory cells, may be marked as defective.

To erase a memory cell or group of memory cells (e.g., erase is typically performed in blocks), an erase voltage (Vers) (e.g., typically Vpgm) may be applied (e.g., using one or more bit lines, select gates, etc.) to the substrate (and thus the channel between the source and drain) of the memory cell targeted for erase while the word line of the targeted memory cell is held at a potential such as ground potential (e.g., Vss), resulting in a charge transfer (e.g., direct injection or fowler-nordheim (FN) tunneling, etc.) from the floating gate to the channel of the targeted memory cell.

After providing an overview of a system including a memory device, a more detailed discussion regarding using firmware to execute memory device policies is provided below. For example, using firmware to execute memory device policies enables a device to enable different performance-affecting features with which it may be easy to switch a memory device from a low-performance memory device to a high-performance memory device, the high-performance memory device enabling the different performance-affecting features. The firmware may detect and control memory policies when configured by an OEM or end user using non-volatile settings (e.g., descriptor registers or fuses).

Various embodiments of the present subject matter use firmware monitoring of hardware usage to perform licensed contracts or other settings. It is desirable to cover a product that has different market segments of the same hardware and firmware settings changed. Thus, by way of example and not limitation, a single product may be inventoried to deliver a single or dual channel product using only firmware setting changes. Multiple Stock Keeping Units (SKUs) may be derived and price point models may be developed with various throughput or bandwidth selection schemes or serializer/deserializer (SERDES) speed and width selection schemes for the same hardware product.

In an example embodiment, an OEM of a memory device may provide upgrades to an end user of the device by purchasing keys or licenses directly from the OEM. In the example where the device is a telephone sold by a wireless telephone company, the telephone company may pay a lower price for low performance telephones so that they can be sold on a cheaper basis. The OEM may then sell the upgrade to end customers willing to pay for additional device functionality.

FIG. 9 illustrates, by way of example and not limitation, an embodiment of a method for providing a memory device with a memory device policy for the memory device to execute the memory device policy (e.g., using memory device performance that affects features of execution, such as number of channels used for serial communication, data transfer limitations, etc.). At 974, the OEM server or other license granting system may receive a request from the user using the memory device to grant different memory device performance (e.g., an increase or decrease in performance of the memory device). The request may relate to a payment or an increased royalty to enable one or more performance-affecting features, and may also relate to a refund or a reduced royalty to disable one or more performance-affecting features. At 975, an Original Equipment Manufacturer (OEM) server or other license granting system may provide data indicative of the requested license (e.g., key) to the memory device. The memory device may store keys or other data indicating permissions in dedicated hardware registers within the memory device. The memory device may query the register to determine the memory device policy (e.g., the rights granted by the permission), and then execute the memory device policy reflected in the permission.

Fig. 10 illustrates by way of example, and not limitation, an embodiment of a process performed by the memory device 1076 and the OEM license server (or other license granting system) 1077. At 1078, the user may request permission to change (e.g., enhance or reduce) the performance of the memory device through the memory device 1078. At 1079, the OEM license server 1077 may receive a request for a license to change the performance of the memory device. The server may request payment for the change or provide a refund for the change. At 1080, the permission granting system is configured to send data indicative of the requested permission to the memory device. At 1081, the memory device may receive data indicating the permission changes and then update the dedicated hardware registers to store data indicating the valid memory device policy. At 1083, the hardware registers are read using firmware within the memory device, and then at 1084, the memory device policy is executed.

One example of a characteristic that affects performance is the number of lanes used to serially transfer data. The discussion below uses control of the number of channels used as an example to control memory device performance to execute memory device policies. This concept can be applied to other performance affecting features of a memory device.

Modern electronic devices and managed memory have controllers to take high speed serial data received at the serial interface and convert them to a much wider parallel interface for sending to other chips or memory. Serial interfaces are typically plugged into links involving multiple high-speed lanes. UFS devices that conform to the current standard may support two channels. However, additional high speed channels may be supported in future devices. Each channel may contain a differential pair for transmitting and receiving data. Using fewer channels generally corresponds to a cheaper and lower power device. Cut-through using available high-speed channels has been performed using automated hardware solutions and standards. Current UFS controllers cannot configure the number of available channels (one or two) due to power latency and speed constraints. Firmware can be used to modify PHY attributes and declare support for only one channel, but an automatic "channel discovery" procedure implemented at the hardware level will allow the device to enable and use the second channel.

Various embodiments of the present subject matter address the auto channel discovery procedure by querying dedicated hardware registers using firmware to check whether to use the second channel, checking internal settings, and executing a preferred policy. The enforcement policy involves only using the channel authorized by the interrogated special-purpose hardware register. Additionally or alternatively, the execution policy may relate to resetting the system, entering a write-protect mode, throttling performance, and/or the like. Additionally or alternatively, some example embodiments may integrate data throughput to perform limited throughput in a limited time. By way of example and not limitation, the storage device may be used to perform a daily 1GB of data allocation at high bandwidth, after which the device may reduce the bandwidth of the daily extra data to above 1 GB. Additionally or alternatively, some example embodiments may use firmware to simulate hardware failures such that the hardware cannot use the channel. An example of a hardware fault is a temperature outside of a boundary condition, which may trigger the device to reduce the heat generated by reducing the communication speed. The PHY settings may be changed to downgrade unauthorized channels so that the hardware cannot use the channels, but remains through. Querying the dedicated hardware register to check whether use of the second channel can be performed during idle time. To defeat the circumvention scheme where the host only enables the second channel during its performance peak request, a check for a MEDIA error recovery stream (where performance has been affected and the CPU may stop waiting for Error Correction Code (ECC) processing, such as a Low Density Parity Check (LDPC) engine to complete soft correction) may be added. The data may require additional LDPC correction loops and the processor of the memory controller may be waiting for the results. Some example embodiments may limit access periodically and reduce performance by using a watchdog timer or by periodically checking channel execution.

FIG. 11 illustrates some non-limiting example licensing models and corresponding memory device policies. The illustrated table contains three permission models (e.g., permission model A, B, C) that correspond to three modes for controlling memory device performance (e.g., limiting channel count; limiting speed; and limiting number of bytes per day). It should be noted that other memory device performance controls may be implemented, and also that some permissions may implement a combination of at least two memory device performance controls. Each licensing model may be associated with a number of permitted channels available for serial communication. For example, permit a is shown for only channel 1, while permits B and C are shown for both channels 1 and 2. Further, each licensing model may be associated with a permitted UFS speed (G4 and/or G3). To enforce the memory device policy, each licensing model may check for authorization (e.g., a key or license) at a determined time or occasion. For example, licensing model a limits the channel count to one channel and may check the authorization of power on the memory device in case the auto channel discovery program automatically uses both channels. Licensing model B limits speed to G3 and may, by way of example and not limitation, periodically check for authorization using a watchdog timer. The licensing model C limits the amount of data (e.g., number of bytes) over a period of time (e.g., one day) and may use a total byte counter to determine when the amount of data is exceeded. After exceeding different levels of data usage, various embodiments may change other performance affecting characteristics of the memory device. By way of example and not limitation, the number of lanes may be reduced after a first threshold of data usage per day, and then the speed may be further limited after a second threshold of data usage per day.

FIG. 12 illustrates, by way of example and not limitation, a block diagram of a system including a host 1201 and a memory device 1202 configured to execute memory device policies. The host and memory device may include the other features previously described. The illustrated host 1201 includes a host controller 1205 with a serializer/deserializer (SERDES), and the illustrated memory device 1202 includes a memory controller 1215 with a SERDES. The SERDES in both the host 1201 and the memory device 1202 are configured with two differential pairs corresponding to two serial communication channels (channel 1 and channel 2) between the SERDES. The memory controller 1215 may include a memory management component 1216. Memory management component 1216 uses PHY settings 1286 to control transfer capabilities, and PHY settings 1286 may include at least one dedicated hardware register configured to store information indicative of memory device policies, such as licensed memory device performance characteristics. Firmware 1285 within memory management component 1216 may query the registers to determine the memory device policy and execute the policy by controlling memory device performance via performance throttling 1287. Memory management component 1216 may include a watchdog timer 1288 for controlling when a memory device queries registers to authenticate memory device policies. Performance throttling may include controlling the number of channels used for serial communication according to a memory device policy. Additionally or alternatively, performance throttling may include controlling (e.g., limiting or increasing) a data transfer speed of the serial communication in accordance with a memory device policy. Additionally or alternatively, performance throttling may include controlling an amount of data allowed to be transferred over a period of time (e.g., hours, days, weeks, or months) in accordance with a memory device policy. Counter 1289 may be used to track data transfers. Additionally or alternatively, performance throttling may include a system reset and/or entering a write-protect mode if a device policy is violated. Additionally or alternatively, performance throttling may include simulating a hardware failure (e.g., a high temperature condition that triggers the memory device to throttle performance to reduce self-heating).

Fig. 13 illustrates a block diagram of an example machine 1300 above which any one or more of the techniques (e.g., methods) discussed herein may be performed. In alternative embodiments, the machine 1300 may act as a standalone device or may be connected (e.g., networked) to other machines. In a networked deployment, the machine 1300 may operate in the capacity of a server machine, a client machine, or both server-client network environments. In an example, the machine 1300 may act as a peer machine in a peer-to-peer (P2P) (or other distributed) network environment. The machine 1300 may be a Personal Computer (PC), a tablet PC, a set-top box (STB), a Personal Digital Assistant (PDA), a mobile telephone, a web appliance, an IoT device, an automotive system, or any machine capable of executing instructions (sequential or otherwise) that specify actions to be taken by that machine. Further, while only a single machine is illustrated, the term "machine" shall also be taken to include any collection of machines that individually or jointly execute one or more sets of instructions to perform any one or more of the methodologies discussed herein (e.g., cloud computing, software as a service (SaaS), other computer cluster configurations).

Embodiments and examples as described herein may include, or may operate with, logic, components, devices, packages, or mechanisms. A circuit system is a collection (e.g., set) of circuits implemented in a tangible entity that includes hardware (e.g., simple circuits, gates, logic, etc.). The circuitry membership may be flexible over time and underlying hardware changes. The circuitry includes components that, when operated, may perform particular tasks either individually or in combination. In an example, the hardware of the circuitry may be designed, unchangeably, to carry out a particular operation (e.g., hardwired). In an example, the hardware of the circuitry may include variably connected physical components (e.g., execution units, transistors, simple circuits, etc.), including computer-readable media physically modified (e.g., magnetically, electrically, movably placed of a constant aggregate particle, etc.) to encode instructions for a particular operation. When physical components are connected, the underlying electrical characteristics of the hardware formation change, for example, from an insulator to a conductor or vice versa. The instructions enable the participating hardware (e.g., execution units or loading mechanisms) to create, via the variable connections, circuitry components in the hardware to perform portions of particular tasks when in operation. Thus, the computer readable medium is communicatively coupled to other components of the circuitry when the device is operating. In an example, any of the physical components may be used in more than one component in more than one circuitry. For example, in operation, an execution unit may be used for a first circuit of a first circuitry at one point in time and reused by a second circuit in the first circuitry, or reused by a third circuit in the second circuitry at a different time.

A machine (e.g., computer system) 1300 (e.g., host device 105, managed memory device 110, etc.) may include a hardware processor 1302 (e.g., a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), a hardware processor core, or any combination thereof, such as memory controller 115, etc.), a main memory 1304, and a static memory 1306, some or all of which may communicate with each other via an interconnection link (e.g., bus) 1308. The machine 1300 may further include a display unit 1310, an alphanumeric input device 1312 (e.g., a keyboard), and a User Interface (UI) navigation device 1314 (e.g., a mouse). In an example, the display unit 1310, input device 1312, and UI navigation device 1314 may be touch screen displays. The machine 1300 may additionally include a storage device (e.g., a drive unit), a signal generation device 1318 (e.g., a speaker), a network interface device 1320, one or more sensors 1316 such as a Global Positioning System (GPS) sensor, compass, accelerometer, or other sensor. The machine 1300 may include an output controller 1328, such as a serial (e.g., Universal Serial Bus (USB), parallel, or other wired or wireless (e.g., Infrared (IR), Near Field Communication (NFC), etc.) connection to communicate or control one or more peripheral devices (e.g., printer, card reader, etc.).

The machine-readable medium 1322 may include a storage device 1321 on which is stored one or more sets of data structures or instructions 1324 (e.g., software) embodying or utilized by any one or more of the techniques or functions described herein. The instructions 1324 may also reside, completely or at least partially, within the main memory 1304, within static memory 1306, or within the hardware processor 1302 during execution thereof by the machine 1300. In an example, one or any combination of hardware processor 1302, main memory 1304, static memory 1306, or storage 1321 may constitute machine-readable medium 1322. While the machine-readable medium 1322 is shown to be a single medium, the term "machine-readable medium" can include a single medium or multiple media (e.g., a centralized or distributed database, or associated caches and servers) that are configured to store the one or more instructions 1324. The term "machine-readable medium" may include any transitory or non-transitory medium that is capable of storing, encoding or carrying transitory or non-transitory instructions for execution by the machine 1300 and that cause the machine 1300 to perform any one or more of the techniques of this disclosure, or that is capable of storing, encoding or carrying data structures used by or associated with such instructions. Non-limiting examples of machine-readable media may include solid-state memory and optical and magnetic media. In an example, a centralized machine-readable medium includes a machine-readable medium having a plurality of particles with an invariant (e.g., static) mass. Thus, the centralized machine-readable medium is a non-transitory propagating signal. Specific examples of a centralized machine-readable medium may include: non-volatile memory, such as semiconductor memory devices (e.g., electrically programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM)) and flash memory devices; magnetic disks, such as internal hard disks and removable disks; magneto-optical disks; and CD-ROM and DVD-ROM disks.

Instructions 1324 (e.g., software, programs, an Operating System (OS), etc.) or other data are stored on the storage device 1321 and may be accessed by the memory 1304 for use by the processor 1302. The memory 1304 (e.g., DRAM) is typically faster but volatile, and thus is a different type of storage than the storage 1321 (e.g., SSD), which storage 1321 is suitable for long term storage, including long term storage when in an "off" condition. Instructions 1324 or data in use by a user or the machine 1300 are typically loaded into memory 1304 for use by the processor 1302. When the memory 1304 is full, virtual space from the storage 1321 may be allocated to replenish the memory 1304; however, because storage 1321 is typically slower than memory 1304, and write speeds are typically at least twice slower than read speeds, the use of virtual memory can greatly reduce the user experience due to storage latency (compared to memory 1304, such as DRAM). Furthermore, the use of storage 1321 for virtual memory may greatly reduce the usable lifespan of storage 1321.

In contrast to virtual memory, virtual memory compression (e.g.,kernel feature "ZRAM") uses portions of memory as compressed blocks to avoid paging to storage 1321. Paging occurs in the compressed block until such data must be written to storage 1321. Virtual memory compression increases the available size of memory 1304 while reducing wear on storage 1321.

Storage devices optimized for mobile electronic devices or mobile storage traditionally include MMC solid state storage devices (e.g., microampere full digital (microSD)^TM) Card, etc.). MMC devices include several parallel interfaces (e.g., 8-bit parallel interfaces) with a host device, often separate components that are removable from the host device. In contrast, eMMC^TMThe device is attached to a circuit board and considered as a component of a host device with a read speed comparable to that of a serial ATA based device^TMSSD device (serial Advanced Technology (AT) attached, or SATA). However, the demand for mobile device performance continues to increase in order to fully enable virtual or augmented reality devices, take advantage of ever increasing network speeds, and the like. In response to this need, the storage device has been shifted from parallel to serial communication interface. Universal Flash Storage (UFS) devices, including controllers and firmware, communicate with host devices using a Low Voltage Differential Signaling (LVDS) serial interface with dedicated read/write paths, further advancing higher read/write speeds.

The instructions 1324 may further be transmitted or received over a communication network 1326 using a transmission medium via the network interface device 1320 utilizing any one of a number of transport protocols (e.g., frame relay, Internet Protocol (IP), Transmission Control Protocol (TCP), User Datagram Protocol (UDP), hypertext transfer protocol (HTTP), etc.). Example communication networks may include a Local Area Network (LAN), a Wide Area Network (WAN), a packet data network (e.g., the Internet), a mobile telephone network (e.g., a cellular network), a Plain Old Telephone (POT)S) network and wireless data network (e.g., referred to asOf the Institute of Electrical and Electronics Engineers (IEEE)802.11 series of standards, known asIEEE 802.16 series of standards), IEEE 802.15.4 series of standards, peer-to-peer (P2P) networks, and others. In an example, the network interface device 1320 may include one or more physical jacks (e.g., ethernet, coaxial, or telephone jacks) or one or more antennas to connect to the communications network 1326. In an example, the network interface device 1320 may include multiple antennas to wirelessly communicate using at least one of single-input multiple-output (SIMO), multiple-input multiple-output (MIMO), or multiple-input single-output (MISO) techniques. The term "transmission medium" shall be taken to include any intangible medium that is capable of storing, encoding or carrying instructions for execution by the machine, and includes digital or analog communications signals or other intangible medium to facilitate communication of such software.

The foregoing detailed description is intended to be illustrative, and not restrictive. The scope of the disclosure should, therefore, be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.