阅读说明：本技术 少管脚存储器的控制系统、fpga芯片和存储系统 (Control system, FPGA chip and storage system of few-pin memory ) 是由 汤博先 刘烈 于 2020-03-31 设计创作，主要内容包括：本发明公开了一种少管脚存储器的控制系统、FPGA芯片和存储系统,用于实现用户层与少管脚存储器的相互通信。所述控制系统包括控制器和接口模块,所述控制器分别与用户层模块和所述接口模块连接,所述接口模块与所述少管脚存储器连接；所述控制器,用于获取所述用户层模块发送的命令和地址,并将所述命令和地址进行处理后发送至所述接口模块；所述接口模块,用于根据所述数据命令和进行时钟域转换,并将经过所述时钟域转换后的所述命令和地址发送至所述少管脚存储器。本发明还公开了一种包括上述控制系统的FPGA芯片和存储系统。(The invention discloses a control system, an FPGA chip and a storage system of a few-pin memory, which are used for realizing the mutual communication between a user layer and the few-pin memory. The control system comprises a controller and an interface module, wherein the controller is respectively connected with a user layer module and the interface module, and the interface module is connected with the few-pin memory; the controller is used for acquiring the command and the address sent by the user layer module, processing the command and the address and sending the processed command and address to the interface module; and the interface module is used for performing clock domain conversion according to the data command and sending the command and the address converted by the clock domain to the few-pin memory. The invention also discloses an FPGA chip and a storage system comprising the control system.)

1. The control system of the few-pin memory is characterized by comprising a controller and an interface module, wherein the controller is respectively connected with a user layer module and the interface module, and the interface module is connected with the few-pin memory;

the controller is used for acquiring the command and the address sent by the user layer module, processing the command and the address and sending the processed command and address to the interface module;

the interface module is used for performing clock domain conversion on the command and the address sent by the controller and sending the command and the address subjected to the clock domain conversion to the few-pin memory.

2. The system for controlling a pin-less memory of claim 1,

the controller is used for acquiring the write data command, the address and the write data information sent by the user layer module, processing the write data command, the address and the write data information and sending the processed write data command, address and write data information to the interface module;

the interface module is configured to perform clock domain conversion on the write data command, the address and the write data information after the write data command is cached, and send the write data command, the address and the write data information after the clock domain conversion to the less-pin memory.

3. The system for controlling a pin-less memory of claim 2,

the controller is used for acquiring the data reading command sent by the user layer module, processing the data reading command and sending the processed data reading command to the interface module;

the interface module is used for performing clock domain conversion on the read data command and then transmitting the read data command to the less-pin memory, receiving a read data indicating signal transmitted by the less-pin memory after transmitting the read data command subjected to clock domain conversion to the less-pin memory, selecting corresponding read data from data transmitted by the less-pin memory according to the read data indicating signal, generating a read effective signal corresponding to the corresponding read data, and transmitting the corresponding read data and the read effective signal to the controller;

and the controller is used for feeding back the corresponding read data to the user layer module according to the read valid signal after receiving the read valid signal and the corresponding read data sent by the interface module.

4. The control system of a few pin memory of claim 3, wherein the controller comprises a command module and a write data module;

the command module is used for receiving a write data command and an address sent by the user layer module, converting the address into an address corresponding to the at least pipe pin memory, recombining the converted address and the write data command and sending the recombined address and the write data command to the interface module;

the write data module is used for receiving write data information sent by the user layer module, wherein the write data information comprises a write data enable signal, a write mask signal and write data; and obtaining a write enable signal according to the write data enable signal and the write mask signal, and sending the write enable signal and the write data to the interface module.

5. The control system of a few-pin memory of claim 4, wherein the controller further comprises a read data module;

the command module is used for acquiring a data reading command sent by the user layer module and sending the data reading command to the interface module;

and the read data module is used for receiving the corresponding read data fed back by the interface module when the read valid signal fed back by the interface module is detected, and sending the read valid signal and the corresponding read data to the user layer module.

6. The system for controlling a pipe less memory of claim 5, wherein the interface module comprises a control path module, a data path module, and an I/O logic module;

the control path module is used for receiving a write data command and an address sent by the controller during write data, obtaining a delay parameter according to the write data command, sending the delay parameter to the data path module, analyzing the write data command into a command code according to a low-pin memory protocol, combining the command code with the address to form a first address command code, and sending the first address command code to the I/O logic module;

the data path module is used for caching the write data according to the delay parameter and sending the write data to the I/O logic module;

the I/O logic module is configured to convert the write data and the first address command code into a clock domain corresponding to the at least one pin memory and then send the clock domain to the at least one pin memory.

7. The system for controlling a pin-less memory of claim 6,

the control path module is used for acquiring the read data command when reading data, resolving the read data command into a command code according to a few-pin memory protocol, combining the command code with the address into a second address command code, and sending the second address command code to the few-pin memory through the I/O logic module;

the I/O logic module is used for receiving a reading indication signal sent by the less-pin memory according to the second address command code and sending the reading indication signal to the control channel module;

the control path module is configured to control the control path module to select corresponding read data from the data sent by the few-pin memory according to the read data indication signal sent by the few-pin memory, generate the read valid signal, and send the read valid signal to the controller.

8. The control system of a pin-less memory of claim 7, wherein the first address command code is sent with the write data sharing DQ lines when a parallel command mode is used.

9. The control system for a pin-less memory of claim 8, wherein when a serial command mode is used, the first address command code is transmitted by an stb line alone, and the write data is transmitted by the DQ line.

10. The system for controlling a pin-less memory of claim 9, wherein the first address naming code is sent prior to the write data.

11. The control system of the few pin memory of any one of claims 4-10,

the command module is used for determining whether a write command queue is full after receiving a write request signal sent by the user layer module, and sending a write busy response signal to the user layer module if the write command queue is full; if the write command queue is not full, receiving the write data command sent by the user layer module; the read busy response signal is used for receiving a read request signal sent by the user layer module, determining whether a read command queue is full, and if the read command queue is full, sending a read busy response signal to the user layer module; and if the read command queue is not full, receiving the read data command sent by the user layer module.

12. The system for controlling a pipe less memory of any one of claims 4-10, wherein said interface module further comprises said initialization module

The initialization module is used for initializing the few-pin memory according to a few-pin memory protocol standard after being powered on, and the initialization comprises resetting and read-write calibration.

13. An FPGA chip comprising the control system of the low pin count memory of any one of claims 1-12.

14. A memory system comprising a user plane module, a few pin memory and the FPGA chip of claim 13, the user plane module and the few pin memory being separately connected to the FPGA chip.

Technical Field

The invention relates to the technical field of memories, in particular to a control system, an FPGA chip and a storage system of a few-pin memory.

Background

The IP core is a module provided by a certain party in the form of a logic unit or a chip design. Designers can design the logic of an application specific integrated circuit or a field programmable gate array on the basis of an IP core so as to shorten the design period and improve the design quality and efficiency.

A few-pin Memory (RPC Memory) adopts a DRAM process and technology as a new DRAM device. Compared with the current mainstream DDR3 memory, the low-pin memory adopts the same technology and process, but only uses about half of IO pins, so the chip area of the low-pin memory is smaller and has higher competitiveness. Therefore, low pin count memories are an ideal choice for many portable mobile products with large cache capacity and high bandwidth requirements. In portable mobile devices with increasingly complex functionality, fewer I/O interfaces means less area, power consumption and cost. Therefore, the memory with less pins has incomparable advantages in application scenes of fewer I/O interfaces, low cost control, small area of a memory chip, low power consumption and high-speed transmission. Based on the market demand and the storage characteristics of the few-pin memory, an implementation method of an interface circuit is urgently needed to implement the mutual communication between the user layer and the few-pin memory.

Disclosure of Invention

The embodiment of the invention provides a control system, an FPGA chip and a storage system of a few-pin memory, which can realize the mutual communication between a user layer and the few-pin memory.

The invention provides a control system of a few-pin memory, which comprises a controller and an interface module, wherein the controller is respectively connected with a user layer module and the interface module;

the controller is used for acquiring the command and the address sent by the user layer module, processing the command and the address and sending the processed command and address to the interface module;

and the interface module is used for performing clock domain conversion according to the data command and sending the command and the address converted by the clock domain to the few-pin memory.

Optionally, the controller is configured to acquire a write data command, an address, and write data information sent by the user layer module, process the write data command, the address, and the write data information, and send the processed write data command, address, and write data information to the interface module;

the interface module is configured to perform clock domain conversion on the write data command, the address and the write data information after the write data command is cached, and send the write data command, the address and the write data information after the clock domain conversion to the less-pin memory.

Optionally, the controller is configured to acquire a read data command sent by the user layer module, process the read data command, and send the processed read data command to the interface module;

the interface module is used for performing clock domain conversion on the read data command and then transmitting the read data command to the less-pin memory, receiving a read data indicating signal transmitted by the less-pin memory after transmitting the read data command subjected to clock domain conversion to the less-pin memory, selecting corresponding read data from data transmitted by the less-pin memory according to the read data indicating signal, generating a read effective signal corresponding to the corresponding read data, and transmitting the corresponding read data and the read effective signal to the controller;

and the controller is used for feeding back the corresponding read data to the user layer module according to the read valid signal after receiving the read valid signal and the corresponding read data sent by the interface module.

Optionally, the controller comprises a command module and a write data module;

the command module is used for receiving a write data command and an address sent by the user layer module, converting the address into an address corresponding to the at least pipe pin memory, recombining the converted address and the write data command and sending the recombined address and the write data command to the interface module;

the write data module is used for receiving write data information sent by the user layer module, wherein the write data information comprises a write data enable signal, a write mask signal and write data; and obtaining a write enable signal according to the write data enable signal and the write mask signal, and sending the write enable signal and the write data to the interface module.

Optionally, the controller further comprises a data reading module;

the command module is used for acquiring a data reading command sent by the user layer module and sending the data reading command to the interface module;

and the read data module is used for receiving the corresponding read data fed back by the interface module when the read valid signal fed back by the interface module is detected, and sending the read valid signal and the corresponding read data to the user layer module.

Optionally, the interface module includes a control path module, a data path module and an I/O logic module;

the control path module is used for receiving a write data command and an address sent by the controller during write data, obtaining a delay parameter according to the write data command, sending the delay parameter to the data path module, analyzing the write data command into a command code according to a low-pin memory protocol, combining the command code with the address to form a first address command code, and sending the first address command code to the I/O logic module;

the data path module is used for caching the write data according to the delay parameter and sending the write data to the I/O logic module;

the I/O logic module is configured to convert the write data and the first address command code into a clock domain corresponding to the at least one pin memory and then send the clock domain to the at least one pin memory.

The control path module is used for acquiring the read data command when reading data, resolving the read data command into a command code according to a few-pin memory protocol, combining the command code with the address into a second address command code, and sending the second address command code to the few-pin memory through the I/O logic module;

the I/O logic module is used for receiving a reading indication signal sent by the less-pin memory according to the second address command code and sending the reading indication signal to the control channel module;

the control path module is configured to control the control path module to select corresponding read data from the data sent by the few-pin memory according to the read data indication signal sent by the few-pin memory, generate the read valid signal, and send the read valid signal to the controller.

Optionally, when a parallel command mode is used, the first address command code is sent with the write data sharing a DQ line. When the serial command mode is used, the first address command code is transmitted by the stb line alone, and the write data is transmitted with the DQ line. The first address naming code is transmitted prior to the write data.

The command module is used for determining whether a write command queue is full after receiving a write request signal sent by the user layer module, and sending a write busy response signal to the user layer module if the write command queue is full; if the write command queue is not full, receiving the write data command sent by the user layer module; the read busy response signal is used for receiving a read request signal sent by the user layer module, determining whether a read command queue is full, and if the read command queue is full, sending a read busy response signal to the user layer module; and if the read command queue is not full, receiving the read data command sent by the user layer module.

Optionally, the initialization module is configured to initialize the small-pin memory according to a protocol standard of the small-pin memory after power on, where the initialization includes resetting and read-write calibration.

Optionally, the command module is configured to map the address to a Bank address, a Row address, and a Column address corresponding to the stub memory.

A second aspect of the present invention provides an FPGA chip comprising the control system of the pin-less memory according to the first aspect.

A third aspect of the present invention provides a storage system, which includes a user layer module, a few-pin memory, and the FPGA chip of the first aspect, where the user layer module and the few-pin memory are respectively connected to the FPGA chip.

In the above scheme, the user layer module communicates with the minority carrier memory through the control system, the control system includes a controller and an interface module, the controller is used for receiving commands from the user layer module and providing signals meeting the requirements of time sequence and sequence to the interface of the minority carrier memory through the interface module, thereby realizing the operation of the minority carrier memory through the interface module.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the description of the embodiments of the present invention will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to these drawings without inventive labor.

FIG. 1 is a diagram of a control system connected to a user plane module and a few-pin memory according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of a control system according to an embodiment of the present invention;

FIG. 3 is a schematic diagram illustrating interaction between a user layer module and a few-pin memory via a control system according to an embodiment of the present invention;

FIG. 4 is a diagram illustrating a write timing sequence with a burst length of 4 for a user layer module according to an embodiment of the present invention;

FIG. 5 is a diagram illustrating a write timing sequence of a SMIF memory with a burst length of 4 in an embodiment of the present invention;

fig. 6 is a schematic diagram of a reading sequence with a burst length of a user layer module of 4 in the embodiment of the present invention;

fig. 7 is a schematic view of a read timing of a few-pin memory when the burst length of the user layer module is 4 according to an embodiment of the present invention;

FIG. 8 is a schematic diagram of the connection between the FPGA chip and the user layer module and the pin-less memory according to the embodiment of the present invention;

fig. 9 is a schematic structural diagram of a storage system in an embodiment of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

Referring to fig. 1, fig. 1 is a schematic diagram illustrating a connection between a control system 20 of an under-chassis memory and a user layer module 10 and an under-chassis memory 30 according to an embodiment of the present invention, where the control system 20 includes a controller 201 and an interface module 202, the controller 201 is connected to the user layer module 10 and the interface module 202, respectively, and the interface module 202 is connected to the under-chassis memory 30; the controller 201 is configured to obtain a command and an address sent by the user layer module 10, process the command and the address, and send the processed command and address to the interface module 202; for example, the controller 201 is configured to convert an address sent by the user layer module 10 into an address corresponding to the low-pin memory 30, and send the address to the user layer module 202, for example, the controller 201 is configured to split or reassemble a command sent by the user layer module 10, so as to obtain a corresponding instruction according to the protocol of the low-pin memory and the command conversion, such as an instruction of activating, precharging, writing or reading, and send the converted instruction to the interface module 202. The interface module 202 is used for converting the clock domain of the command sent by the controller 201, converting the low-speed clock domain into the high-speed clock domain to generate the required signals of the pin-less memory 30, and sending the command and address converted by the clock domain to at least the pin-less memory 30, so as to convert the command and address sent by the controller into the read-write rate required by the pin-less memory. It can be understood that, in the above solution, the user layer module 10 communicates with the minority memory 30 through the control system 20, and the controller 201 of the control system 20 is configured to receive a command from the user layer module 10 and provide a signal meeting timing and sequence requirements to the interface of the minority memory 30 through the interface module 201, so as to implement 30 operations on the minority memory and implement communication and control between the user layer and the minority memory 30. The commands include a write data command and a write data command, and other commands for controlling the low pin count memory, such as a reset command, which is not an example here. That is, the control of the pin-less memory 30 includes the process of writing data and reading data, and the user layer module 10 can send a read data command and a write data command to the controller 201 to implement the process of writing data or reading data from the pin-less memory 30, which will be described below.

In the process of writing data, the user layer module 10 may send a write data command, an address and write data information to the controller 201, where the write data information includes write data to be written, a write mask signal and a write data enable signal, and the controller 201 is configured to obtain the write data command, the address and the write data information sent by the user layer module 10, process the write data command, the address and the write data information, and send the processed write data command, address and write data information to the interface module 202; the interface module 202 is configured to perform clock domain conversion on the write data command, the address and the write data information after performing cache processing on the write data information according to the write data command, and send the write data command, the address and the write data information after the clock domain conversion to at least the pin memory 30. In this embodiment, the user layer module 10 may cause the user layer module 10 to write data from the pin-less memory 30 by sending a write data command, address, and write data information to the control system.

In the process of reading data, the controller 201 is configured to obtain a data reading command sent by the user layer module 10, process the data reading command, and send the processed data reading command to the interface module 202; the interface module 202 is configured to perform clock domain conversion on the read data command, send the read data command to the at least pin memory 30, receive a read data indication signal sent by the less pin memory 30 after sending the read data command subjected to clock domain conversion to the at least pin memory 30, select corresponding read data from data sent by the less pin memory 30 according to the read data indication signal, generate a read valid signal corresponding to the corresponding read data, and send the corresponding read data and the read valid signal to the controller 201; the controller 201 is configured to, after receiving the read valid signal and the corresponding read data sent by the interface module 202, feed back the corresponding read data to the user layer module 10 according to the read valid signal. It can be seen that in the present embodiment, the user layer module can control the system 10 to enable the user layer module 10 to read data from the pin-less memory 30.

In the above scheme, the user layer module communicates with the minority carrier memory through the control system, the control system includes a controller and an interface module, the controller is used for receiving commands from the user layer module and providing signals meeting the requirements of time sequence and sequence to the interface of the minority carrier memory through the interface module, thereby realizing the operation of the minority carrier memory through the interface module.

Referring to fig. 2, optionally, the controller 201 includes a command module 2011 and a write data module 2012; the command module 2011 is configured to receive a write data command and an address sent by the user layer module 10, and convert the address into an address corresponding to at least the pin memory 30, and specifically, the command module 2011 is configured to map the address into a Bank address, a Row address, and a Column address corresponding to the pin-less memory 30. The converted address and the write data command are split or reassembled according to the least pipe protocol and sent to the interface module 202. The write data module 2012 is configured to receive write data information sent by the user layer module 10, where the write data information includes a write data enable signal, a write mask signal, and write data, obtain the write enable signal according to the write data enable signal and the write mask signal, and send the write enable signal and the write data to the interface module 202. That is, the write data module 211 mainly functions to receive and store a write data enable signal, write data information, and a write mask signal sent by a user, perform logic calculation on the write data enable signal and the write mask signal to obtain a write enable signal, provide write data for the interface module 202 according to currently stored write data and a write command received by the controller 201, a configured burst length, and the like, and transmit the write enable signal to the interface module 202. For the few-pin memory with the depth of M and the width of N, the stored data of each address from 0 to M corresponds to a mask signal with the bit number of N bits, and each bit of the mask signal corresponds to each bit of the stored data of the corresponding address, and is used for masking the bit of the stored data that does not rewrite the value of the corresponding register or the bit of the value that needs to rewrite the corresponding register. If the mask is high effective, namely the bit with 1 mask is masked and the value of the corresponding bit register is not rewritten; similarly, if the mask is active low, the bits with a mask of 0 will be masked without overwriting the value of the corresponding bit register. The memory also has a write enable signal with a single bit wide for controlling whether the few-pin memory can write data. Since the write enable signal is single-bit, and binary is represented as 0 or 1, for example, the write enable signal is active low, i.e., the memory can write data when the write enable signal is 0; the write enable signal is active high, i.e., the low pin memory can write data when the write enable signal is 1. Before performing logic operation with a mask signal of multiple bits, firstly, a write enable signal is expanded to a write enable signal with the same bit width as the mask signal, and then the expanded write enable signal is subjected to logic operation with the mask signal to obtain a write enable signal with the same bit width as the mask signal. Specifically, if the mask signal and the write enable signal are both high-effective, the multi-bit mask signal is first bit-inverted, and then bit-and-operated with the expanded write enable signal, respectively, to obtain an expanded write enable signal with the same bit width as the write data and the mask signal.

Optionally, the controller 201 further includes a read data module 2013; the command module 2011 is configured to obtain a read data command sent by the user layer module 10, and send the read data command to the interface module 202; the read data module 2013 is configured to receive corresponding read data fed back by the interface module 202 when detecting a read valid signal fed back by the interface module 202, and send the read valid signal and the corresponding read data to the user layer module 10.

Optionally, interface module 202 includes a control path module 2021, a data path module 2022, and an I/O logic module 2023; the control path module 2021 is configured to receive a write data command and an address sent by the controller 201 during writing data, obtain a delay parameter according to the write data command, send the delay parameter to the data path module 2022, analyze the write data command into a command code according to a low pin memory protocol, combine the command code with the address into a first address command code, and send the first address command code to the I/O logic module 2023; the data path module 2022 is configured to perform cache processing on the write data according to the delay parameter, and send the write data to the I/O logic module 2023; I/O logic module 2023 for converting the write data, write data command and address to at least the clock domain corresponding to pin memory 30 and then transmitting to at least pin memory 30. Wherein, when the parallel command mode is used, the first address command code shares a DQ line with the write data, and a command address code is issued ahead of data. When the serial command mode is used, the first address command code is transmitted by the stb line alone, and the write data is transmitted with the DQ line. It is easy to see that, in the scheme, the command is firstly sent through the DQ line and then data is sent, and the DQ line is shared, in the long burst mode, a command usually transmits larger data, and at the moment, the efficiency loss caused by sending the command address is reduced through the scheme.

Optionally, the control path module 2022 is configured to, when reading data, obtain a read data command, analyze the read data command into a command code according to a pin-less memory protocol, combine the command code with the address into a second address command code, and send the second address command code to the pin-less memory 30 through the I/O logic module 2023; the I/O logic module 2023 is configured to receive a read indication signal sent by the stub memory 30 according to the second address command code, and send the read indication signal to the control path module 2022; the control path module 2022 is configured to control the control path module to select corresponding read data from the data sent by the few-pin memory 30 according to the read data indication signal sent by the few-pin memory, generate the read valid signal, and send the read valid signal to the controller, so that the last user layer module 10 can read data from the few-pin memory 30.

Optionally, the command module is configured to determine whether a write command queue is full after receiving a write request signal sent by the user layer module, and send a write busy response signal to the user layer module if the write command queue is full; if the write command queue is not full, receiving the write data command sent by the user layer module; the read busy response signal is used for receiving a read request signal sent by the user layer module, determining whether a read command queue is full, and if the read command queue is full, sending a read busy response signal to the user layer module; and if the read command queue is not full, receiving the read data command sent by the user layer module. In the scheme, the normal reading and writing process is ensured by designing the writing command queue and the reading command queue to optimize the reading and writing sequence.

In addition, the interface module further comprises an initialization module, wherein the initialization module is used for initializing the few-pin memory 30 according to the protocol standard of the few-pin memory 30 after being powered on, and the initialization comprises the processes of resetting, reading and writing calibration and the like, so that the subsequent normal data reading operation or data writing operation can be conveniently carried out.

Referring to fig. 3-7, a related timing diagram during the process of reading and writing data by the user layer module is described below, fig. 3 is an interactive schematic diagram of the user layer module 10 and the under pin memory 30 through the control system 20, as shown in fig. 3, when writing data, the user layer module 10 sends a clock signal (e.g., a reference clock, a high speed clock), a reset signal, write data information (e.g., write data valid, write data end, write data command, etc.) and an address signal to the control system 20, the control system 20 sends a serial signal, a clock signal, a differential signal, a chip select signal, a reset signal to the under pin memory 30, when reading data, the under pin memory 30 sends a data signal (read data, etc.) and a data indication signal (e.g., read data indication signal) to the control system 20, the control system 20 receives data according to the data indication, and sends read data and read data valid signals to user design module 10, which user design module 10 performs a read data operation upon receiving the read data valid signals. Fig. 4 is a schematic diagram of a write timing sequence with a burst length of 4 for the user layer module 10, where clk is a clock signal, addr is an address signal, cmd is a write command signal, cmd _ en is a command valid signal, cmd _ rdy indicates that a signal can be sent, and when the signal is at a high level, it indicates that a command can be sent. wr _ data is write data, data _ mask is a write mask signal, wr _ data _ en is a write data valid signal, wr _ data _ end is a write data end signal, and wr _ rdy represents a write data ready signal, and when high, it is stated that data can be written. FIG. 5 is a schematic diagram of the write timing of the low pin count memory with the burst length of the user layer module of 4, including rpc _ clk signal, rpc _ dqs signal, rpc _ dq signal, rpc _ cs _ n signal and rpc _ stb signal, where the write timing relationship of the signals is shown in FIG. 5 and is not described herein.

Fig. 6 is a schematic diagram of a read sequence of burst length 4 of the user layer module 10, where clk is a clock signal, cmd is a command signal, cmd _ en is a command valid signal, cmd _ rdy indicates that a signal can be sent, when the signal is at a high level, a command can be sent, rd _ data _ valid is a read valid signal, and rd _ data is read data. Correspondingly, fig. 7 is a schematic view of a read timing of the minority memory with a burst length of the user layer module of 4, including rpc _ clk signal, rpc _ dqs signal, rpc _ dq signal, rpc _ cs _ n signal and rpc _ stb signal, where the read timing relationship of the signals is as shown in fig. 7 and is not described herein.

It should be noted that, the timing diagrams of fig. 4 to fig. 7 are only described herein with the burst length of the user layer module 10 being 4, the burst modes 1 to 64 corresponding to the low pin memory are adjustable, and fig. 4 to fig. 7 are only illustrated with the burst length 4, which is not limited herein, and when there are other burst lengths, there are different timing relationships, which are not necessarily described herein.

As shown in fig. 8, an embodiment of the present invention further provides an FPGA chip 100, where the FPGA chip includes the control system 20 of the low pin memory described in the foregoing embodiment, and the FPGA chip 100 is connected to the user layer module 10 and the low pin memory 30, respectively. It should be noted that the FPGA chip 100 is used to implement the mutual communication between the user layer module 10 and the under pin memory 30, for example, the process of the user layer module 10 writing data or reading data from the under pin memory 30, and the details of the communication between the FPGA chip and the user layer module 10 and the under pin memory 30 can be seen from the description of the above embodiments, which will not be described herein. As shown in fig. 9, an embodiment of the present invention further provides a storage system, which includes a user layer module 10, an under-pin memory 30, and the FPGA chip 100 described in the foregoing embodiment, where the user layer module and the under-pin memory are respectively connected to the FPGA chip. It should be noted that the FPGA chip 100 is used to implement the mutual communication between the user layer module 10 and the few-pin memory 30, for example, the process of the user layer module 10 writing data or reading data from the few-pin memory 30, and details of the communication between the FPGA chip 100 and the user layer module 10 and the few-pin memory 30 can be seen from the description of the above embodiments, which is also not described herein.

It will be apparent to those skilled in the art that, for convenience and brevity of description, only the above-mentioned division of the functional units and modules is illustrated, and in practical applications, the above-mentioned function distribution may be performed by different functional units and modules according to needs, that is, the internal structure of the apparatus is divided into different functional units or modules to perform all or part of the above-mentioned functions.

The above-mentioned embodiments are only used for illustrating the technical solutions of the present invention, and not for limiting the same; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present invention, and are intended to be included within the scope of the present invention.