阅读说明：本技术 存储器装置 (Memory device ) 是由 姜慧如 林仲德 于 2021-06-15 设计创作，主要内容包括：一种存储器装置包括至少一多元存储器单元。每一个存储器单元包括N个子位元单元的并联连接。N是大于1的整数。N个子位元单元中的每一者包括相应的晶体管和相应的电容的串联连接。第一子位元单元包括具有电容值C的第一电容,并且每一个第i子位元单元包括具有电容值2～(i-1)×C的第i电容。可以存储具有2～(N)个数值的多元位元。还提供了包括多个多元逻辑单元的装置网络。多个多元逻辑单元中的每一者包括N个子位元单元的并联连接。每一个子位元单元包括相应的晶体管和相应的电容的串联连接,电容具有2的幂次的电容值比率。(A memory device includes at least one multi-element memory cell. Each memory cell includes a parallel connection of N sub-bit cells. N is an integer greater than 1. Each of the N sub-bitcells includes a series connection of a respective transistor and a respective capacitor. The first sub-bit cell includes a first capacitor having a capacitance value C, and each of the ith sub-bit cells includes a second capacitor having a capacitance value 2 i‑1 Ith capacitance of x C. Can store a file having 2 N Multiple bits of individual values. A device network including a plurality of multivariate logic units is also provided. Each of the plurality of multi-element logic cells includes a parallel connection of N sub-bit cells. Each sub-bit cell comprising a string of a respective transistor and a respective capacitorIn series, the capacitance has a ratio of capacitance values to a power of 2.)

1. A memory device comprising at least one multi-element memory cell, wherein each of said multi-element memory cells comprises a parallel connection of N sub-bit cells, wherein:

n is an integer greater than 1;

each of the N sub-bitcells includes a series connection of a respective one of a transistor and a respective one of a capacitor;

a first sub-bit unit including a first capacitor having a capacitance value C; and

each ith sub-bit cell includes an ith capacitor having a capacitance of 2^i-1×(1+2^-N-1) X C to 2^i-1×(1-2^-N-1) And each i is greater than 1 and not greater than N in a range of x C.

Technical Field

The present disclosure relates to a memory device, in particular a memory device comprising at least one multi-element memory cell.

Background

A multi-bit cell refers to a cell that can have more than two states. Multiple bit cells can be used to provide high device density while reducing the complexity of the support circuitry required to support the operation of the memory array or logic circuitry. The multiple bit cell can operate beyond the limit of a binary bit cell, and can provide high-speed computing power by inherently simplifying data processing operations.

Disclosure of Invention

The present disclosure provides a memory device. The memory device includes at least one multi-element memory cell, wherein each of the multi-element memory cells includes a parallel connection of N sub-bit cells. N is an integer greater than 1. Each of the N sub-bitcells includes a series connection of a respective transistor and a respective capacitor. The first sub-bit cell unit comprises a first capacitor, and the first capacitor has a capacitance value C. Each ith sub-bit cell includes an ith capacitor having a capacitance value of 2^i-1×(1+2^-N-1) X C to 2^i-1×(1-2^-N-1) In the range of × C, each i is greater than 1 and not greater than N.

The present disclosure provides a network of devices. The device network includes a plurality of multi-element logic cells, wherein each of the multi-element logic cells includes a parallel connection of N sub-bit cells. N is an integer greater than 1. Each of the N sub-bitcells includes a series connection of a respective transistor and a respective capacitor. The first sub-bit cell unit comprises a first capacitor, and the first capacitor has a capacitance value C. Each ith sub-bit cell includes an ith capacitor having a capacitance value of 2^i-1×(1+2^-N-1) X C to 2^i-1×(1-2^-N-1) In the range of × C, i is greater than 1 and not greater than N. A first multi-element logic unit selected from the multi-element logic units comprises an output node which is electrically connected to an output node or an input node of a second multi-element logic unit selected from the multi-element logic units.

The present disclosure provides a method of forming a multi-element memory cell. The method for forming a multi-cell memory cell includes depositing N number of layer stack units over a substrate, where N is an integer greater than 1, and each layer stack unit selected from the N number of layer stack units includes an isolation dielectric layer, a gate electrode layer, a gate dielectric layer, a semiconductor channel layer, a dielectric spacer layer, a capacitance dielectric layer, and a ground electrode layer; etching a plurality of trenches through the N layer stack units; laterally etching a plurality of patterned portions of each dielectric spacer layer, wherein a plurality of lateral recesses are formed adjacent to a plurality of dielectric spacer plates, the dielectric spacer plates being a plurality of remaining portions of the dielectric spacer layers; depositing a semiconductor material or a conductive material in the lateral recess, wherein a composite layer is formed on each of the semiconductor channel layers to provide a respective transistor, the composite layer comprising a dielectric spacer plate, a source region and a drain region; and forming a bit line on each group of drain regions above or below each other, wherein a parallel connection of N sub-bitcells is formed, wherein each of the N sub-bitcells comprises a series connection of a respective transistor and a respective capacitor, the capacitor comprising a source region of the respective transistor, a patterned portion of the respective capacitor dielectric layer, and a patterned portion of the respective ground electrode layer.

Drawings

The disclosed embodiments can be understood in more detail by reading the following detailed description and examples, in conjunction with the accompanying drawings. It is noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

FIG. 1 is a circuit diagram of a first exemplary multi-cell memory array including a row of multi-cell memory cells according to an embodiment of the disclosure.

FIG. 2 is a circuit diagram of a second exemplary multi-cell memory array including two rows of multi-cell memory cells according to an embodiment of the present disclosure.

Fig. 3A is a vertical cross-sectional view of an exemplary structure for forming an array of multi-cell memory cells after forming a multi-level stack of cells over a layer of dielectric material having metal interconnect structures formed therein, in accordance with an embodiment of the present disclosure.

Fig. 3B is a top view of the exemplary structure of fig. 3A.

Fig. 4A is a vertical cross-sectional view of an exemplary structure after forming a line trench in accordance with an embodiment of the present disclosure.

Fig. 4B is a top view of the exemplary structure of fig. 4A.

Fig. 5A is a vertical cross-sectional view of an exemplary structure after forming a dielectric trench fill structure in accordance with an embodiment of the present disclosure.

Fig. 5B is a top view of the exemplary structure of fig. 5A.

Fig. 6A is a vertical cross-sectional view of an exemplary structure after forming a dielectric pillar structure in accordance with an embodiment of the present disclosure.

Fig. 6B is a top view of the exemplary structure of fig. 6A.

Fig. 7A is a vertical cross-sectional view of an example structure after forming a source-side lateral recess and a drain-side lateral recess, according to an embodiment of the present disclosure.

Fig. 7B is a top view of the exemplary structure of fig. 7A.

Fig. 7C is a horizontal sectional view taken along the plane C-C' of fig. 7A.

Fig. 8A is a vertical cross-sectional view of an exemplary structure after forming source and drain regions in accordance with an embodiment of the present disclosure.

Fig. 8B is a top view of the exemplary structure of fig. 8A.

Fig. 8C is a horizontal sectional view along the plane C-C' of fig. 8A.

Figure 9A is a vertical cross-sectional view of an example structure after forming an isolation pillar structure, in accordance with an embodiment of the present disclosure

Fig. 9B is a top view of the exemplary structure of fig. 9A.

Fig. 9C is a horizontal sectional view taken along the plane C-C' of fig. 9A.

Fig. 10A is a vertical cross-sectional view of an exemplary structure after removal of drain side isolation pillar structures and formation of drain side pillar cavities, in accordance with an embodiment of the present disclosure.

Fig. 10B is a top view of the exemplary structure of fig. 10A.

Fig. 10C is a horizontal sectional view taken along the plane C-C' of fig. 10A.

Figure 11A is a vertical cross-sectional view of an exemplary structure after forming a gate level lateral recess and a ground level lateral recess, in accordance with an embodiment of the present disclosure.

Fig. 11B is a top view of the exemplary structure of fig. 11A.

Fig. 11C is a horizontal sectional view taken along the plane C-C' of fig. 11A.

FIG. 11D is a horizontal cross-sectional view taken along plane D-D' of FIG. 11A.

Figure 12A is a vertical cross-sectional view of an exemplary structure after forming gate insulating spacers and ground insulating spacers, in accordance with an embodiment of the present disclosure.

Fig. 12B is a top view of the exemplary structure of fig. 12A.

Fig. 12C is a horizontal sectional view taken along the plane C-C' of fig. 12A.

Fig. 12D is a horizontal cross-sectional view along plane D-D' of fig. 12A.

FIG. 13A is a vertical cross-sectional view of an exemplary structure after forming bit lines according to an embodiment of the disclosure.

Fig. 13B is a top view of the exemplary structure of fig. 13A.

Fig. 13C is a horizontal sectional view taken along the plane C-C' of fig. 13A.

Fig. 13D is a horizontal cross-sectional view along plane D-D' of fig. 13A.

Fig. 13E is a horizontal cross-sectional view taken along plane E-E' of fig. 13A.

Fig. 14 is a circuit schematic of a first exemplary network of devices during programming according to an embodiment of the disclosure.

Fig. 15 is a circuit schematic of a first exemplary device network during sensing according to an embodiment of the disclosure.

Fig. 16 is a circuit schematic of a second exemplary network of devices according to an embodiment of the present disclosure.

Fig. 17 is a flowchart illustrating operations for forming structures of the present disclosure, in accordance with an embodiment of the present disclosure.

Wherein the reference numerals are as follows:

100: multi-element memory array and multi-element memory array

101: multi-element memory cell

BL _ 1: first bit line

BL _ 2: second bit line

BL _ 3: third bit line

101_ 1: first multi-element memory cell

101_ 2: second multi-element memory cell

101_ 3: third multi-element memory cell

WL _ 1: first word line

WL _ 2: second word line

WL _ N: the Nth word line

200: second exemplary Multi-element memory array

700: substrate

720: semiconductor device with a plurality of semiconductor chips

760: dielectric material layer

780: metal interconnection structure

788: global bit line

20: isolation dielectric layer

30: gate electrode layer

40: gate dielectric layer

50: semiconductor channel layer

60L: dielectric spacer layer

80: capacitor dielectric layer

90: ground electrode layer

81: first capacitor dielectric layer

82: second capacitor dielectric layer

83: third capacitor dielectric layer

79: line trench

hd 1: first horizontal direction

hd 2: second horizontal direction

78: dielectric trench filling structure

76: dielectric pillar structure

77: columnar cavity

C-C': plane surface

60: dielectric spacer plate

61: source side lateral recess

63: drain side lateral recess

62: source region

64: drain region

72: source side isolation pillar structure

74: drain side isolation pillar structure

33: grid quasi-position transverse recess

93: lateral recess of ground level

32: gate insulating spacer

92: ground insulating spacer

84: bit line

10: sub-bit cell

D-D': plane surface

E-E': plane surface

301: multiple element logic unit

301_ 1: first multi-element logic unit

301_ 2: second multi-element logic unit

BL: bit line

301_ 1: first multi-element logic unit

301_ 2: first multi-element logic unit

301_ 3: first multi-element logic unit

301_ 4: first multi-element logic unit

301_ 5: first multi-element logic unit

301_ 6: first multi-element logic unit

401: second multi-element logic unit

1710-1750: operation of

Detailed Description

The present disclosure provides many different embodiments, or examples, for implementing different features of the disclosure. The following disclosure describes specific embodiments of various components and arrangements thereof to simplify the description. Of course, these specific examples are not intended to be limiting. For example, if the disclosure recites a first feature formed on or above a second feature, that embodiment may include that the first feature is in direct contact with the second feature, embodiments may also include that additional features are formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the same reference numbers and/or designations may be reused in various embodiments of the disclosure below. These iterations are for simplicity and clarity and are not intended to limit the particular relationship between the various embodiments and/or configurations discussed.

Furthermore, it is used in terms of spatial correlation. Such as "below" …, below "lower" upper "and similar terms, are used for convenience in describing the relationship of one element or feature to another element(s) or feature(s) in the figures. These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. In addition, the device may be turned to a different orientation (rotated 90 degrees or at other orientations), and the spatially relative terms used herein should be interpreted accordingly. Unless explicitly stated otherwise, each element having the same reference numeral is assumed to have the same material composition and to have a thickness within the same thickness range.

The present disclosure is directed generally to semiconductor devices and, in particular, to memory devices including at least one multi-element memory cell, device networks including a plurality of multi-element logic cells, and methods of making the same. In contrast to binary devices or binary memory cells, a multi-device or multi-cell refers to a device or cell having more than two discrete states (multi-cells). The multi-element device includes a ternary device (ternary device) that may have three states, a quaternary device (quaternary device) that may have four states, a quinary device (quinary device) that may have five states, a senary device (sensory device) that may have six states, and the like. The same manufacturing process may be used to form the memory device or device nets of the present disclosure, and the variation in electrical routing (electrical wiring) achieved by the layout change in the metal interconnect structure may be sufficient to switch between the manufacture of the memory device and the manufacture of the device nets. A memory device comprising at least one multi-element memory cell can be used for storing multi-element bits having 2N possible storage values, e.g. 0 to 2^N-a value in the range of 1. Each of the multiple logic cells may produce 2N possible output values in a digital mode of operation, or may produce infinite output values in an analog mode of operation,and connections may be configured in a network to provide non-synaptic network computing (non-synaptic network computing). Various embodiments of the present disclosure are discussed in detail below.

Fig. 1 is a circuit diagram of a first exemplary multi-cell memory array 100 including a row (column) of multi-cell memory cells in accordance with an embodiment of the present disclosure. The first exemplary multi-cell memory array 100 includes a row of multi-cell memory cells 101. Each of the plurality of memory cells 101 may be numbered with a positive integer. For example, the multi-cell memory unit 101 may include a first multi-cell memory unit 101_1 attached (attached) to a first bit line BL _1, a second multi-cell memory unit 101_2 attached to a second bit line BL _2, a third multi-cell memory unit 101_3 attached to a third bit line BL _3, and the like. Each bit line is a programming voltage supply line for programming (programming) a corresponding multi-cell memory cell 101.

N word lines are connected to each of the plurality of memory cells 101. Generally, the number N is a positive integer greater than 1, such as 2, 3, 4, 5, 6, and the like. In other words, a plurality of word lines are connected to each of the plurality of memory cells 101. For any given programming voltage applied to the bit line (which is the programming voltage supply line), each multi-cell memory cell 101 may be programmed to 2^NOne of the states. The N word lines may be shared among the multi-cell memory cells 101 within the first exemplary multi-cell memory array 100. The N word lines may be numbered with positive integers. For example, the N word lines may include a first word line WL _1, a second word line WL _2, and so on to an nth word line WL _ N.

According to an embodiment of the present disclosure, each multi-element memory cell 101 includes a parallel connection of N sub-bit cells. A sub-bit cell is a cell that forms a component of a multi-bit cell. The combination of N sub-bitcells provides a single multi-bit memory cell 101 over its parallel electrical connection between electrical ground and the corresponding bitline. Each of the N sub-bitcells includes a series connection of a respective transistor and a respective capacitor. The gate electrode of each transistor is electrically connected (i.e., electrically shorted) to a respective one of the N word lines. Specifically, for each integer i from 1 to N, the gate electrode of the ith transistor in each multi-element memory cell 101 is electrically connected to the ith word line WL _ i.

In addition, each capacitor in a sub-bit cell has a corresponding capacitance value that is approximately twice as high as the capacitance value of another capacitor in another sub-bit cell (powers of two times). Ideally, the first sub-bit cell includes a first capacitor having a capacitance value C, and each of the ith sub-bit cells includes a second capacitor having a capacitance value 2ⁱAnd the ith capacitance of multiplied by C, wherein each i is larger than 1 and not larger than N. However, no physical device can be manufactured with infinite precision. For manufacturing purposes, each ith sub-bit cell includes a capacitor having a capacitance of 2^i-1×(1+2^-N-1) X C to 2^i-1×(1-2^-N-1) An ith capacitance in the range of x C, each i being greater than 1 and not greater than N. The total capacitance of each multi-element memory cell 101 (i.e., the sum of all capacitance values of the N capacitors) is targeted to be (2)^N-1) times C. The total cumulative variation (total cumulative variation) of the sum of all capacitance values of the N capacitances does not exceed (2)^N-2)/2^N+1Multiplied by C, i.e. (1/2-1/2)^N) Multiplied by C and thus less than 1/2 multiplied by C. By limiting the total error (total error) in the total capacitance value of each of the plurality of bitcells 101 to (2)^N-1-1/2+1/2^N) Multiply by C to (2)^N-1+1/2-1/2^N) Multiplied by C, the maximum total charge that can be stored in each of the plurality of bitcells 101 is V _ prog (which is the programming voltage) multiplied by (2)^N-1) Multiplied by C.

The sense circuit attached to the bit line of each multi-element memory cell 101 may be configured for less than (2)^N-1-1/2+1/2^N)/(2^N-1) the detected charge distribution state "0" multiplied by V _ prog by C for the voltage at j × (2)^N-1-1/2+1/2^N)/(2^N-1). times.V _ prog.xC to (2)^N-1+1/2-1/2^N) Detected charge distribution state "j" in the range of x V _ prog x C, each positive integer j being less than 2^N. Therefore, the error of the total capacitance value of each multi-element memory cell 101 is limited to be less than(2^N-2)/2^N+1 times C to ensure identification (discern) of 2 of each multi-element memory cell 101^NThe sense circuit for each state operates normally without introducing capacitance deviation (capacitance deviation) in the individual sub-bit cells of the multi-cell memory cell 101.

Generally, each multi-bit memory cell 101 can be programmed by draining (drain) all charge from each capacitor in the sub-bit cell, by applying a programming voltage V _ prog to the bit line of the corresponding multi-bit memory cell 101, and by using a binary number as an input value for each word line of the multi-bit memory cell 101. For example, if programming at 0 to 2^N-1 state "j", the number "j" is converted into a binary number. The first digit (digit 1) of the binary number from the right corresponds to the state of the first word line WL _1, the second digit (digit 2) of the binary number from the right corresponds to the state of the second word line WL _2, and for each integer p up to N, the p-th digit (digit 2) of the binary number from the right^p-1Digit) of the corresponding p-th word line WL _ p. If the state of the pth word line WL _ p is 1, a turn-on voltage is applied to the gate electrode of the pth transistor connected to the pth word line WL _ p. The charge of the p-th capacitor is V _ prog × 2^p-1And (4) x C. If the state of the pth word line WL _ p is 0, a turn-off voltage is applied to the gate electrode of the pth transistor connected to the pth word line WL _ p. The charge stored in the p-th capacitor remains zero.

Generally, each of the capacitors of the N sub-bitcells in the multi-bitcell memory cell 101 includes a first node connected to electrical ground and a second node connected to the source region of the respective transistor within the respective one of the N sub-bitcells. The parallel connection of the N sub-bitcells within each multi-cell memory cell 101 may be between the corresponding bitline and electrical ground.

In one embodiment, the multi-cell memory array 100 may include a plurality of bit lines that may be arranged in rows from side to side. In this embodiment, the plurality of multi-cell memory cells 101 may be arranged as a row of multi-cell memory cells arranged along the repetition direction of the bit line. Generally speaking, a single multi-element memory cell 101 may be attached to a bit line as shown in FIG. 1, or multiple multi-element memory cells 101 may be attached to a bit line as shown in the second exemplary multi-element memory array 200 shown in FIG. 2.

Fig. 2 is a circuit diagram of a second exemplary multi-cell memory array including two rows of multi-cell memory cells according to an embodiment of the present disclosure. Referring to fig. 2, a column of multi-cell memory cells 101 is attached to each bit line in the second exemplary multi-cell memory array 200. The second exemplary multi-cell memory array 200 shows bit line switches that connect or disconnect each bit line to or from a programming voltage supply circuit or sensing circuit (not shown) configured to measure the total amount of charge stored in the capacitance of the corresponding multi-cell memory cell 101. An output capacitor for sensing the charged state of the multi-element memory cell 101 may be attached to each bit line.

Referring collectively to fig. 1 and 2, a multi-cell memory device may include at least one multi-cell memory cell 101. The multi-cell memory device may include a column of multi-cell memory cells 101 as shown in fig. 2. Each of the plurality of memory cells 101 in the same row is connected to a corresponding bit line. In one embodiment, as shown in fig. 1 and 2, the at least one multi-cell memory cell 101 may include at least one row of multi-cell memory cells 101. In this embodiment, each of the plurality of memory cells 101 in the same row share the same set of word lines, and each word line in the same set of word lines is connected to a respective gate electrode in each of the plurality of memory cells 101 in a respective row of the plurality of memory cells. Thus, the multi-cell memory array of the present disclosure is scalable along the bit line direction and along the word line direction.

The multi-element memory cell 101 described above may be fabricated using a series of fabrication operations that will be described below. In addition, the electrical routing in the metal interconnect structure may be suitably modified using a series of manufacturing operations to be described below to form a multi-element logic cell that is electrically routed to form a device network.

Fig. 3A is a vertical cross-sectional view of an exemplary structure for forming a multi-cell memory cell array after forming a multi-layer stacked cell over a layer of dielectric material having a metal interconnect structure formed therein, in accordance with an embodiment of the present disclosure. Fig. 3B is a top view of the exemplary structure of fig. 3A. Referring to fig. 3A and 3B, exemplary structures for forming an array of a multi-element memory cell or device network are shown. The exemplary structure includes a substrate 700, which may be a semiconductor substrate, such as a monocrystalline silicon substrate. A semiconductor device 720, such as a field effect transistor, may be formed on the substrate 700. The semiconductor device 720 may include a peripheral circuit (peripheral circuit) for operating a multi-element memory cell to be formed later, or may include a logic circuit for supporting the operation of a device network to be formed later. A metal interconnect structure 780 formed within the dielectric material layer 760 may be formed over the semiconductor device 720. The metal interconnect structure 780 may be electrically connected to the semiconductor device 720 and may electrically connect nodes of a subset of the semiconductor device 720 to nodes of a subsequently to-be-formed multi-cell memory cell or a device network of multi-cell logic cells. For example, metal interconnect 780 may include global bit lines (global bit lines) 788, global bit lines 788 to be connected to respective subsets of bit lines to be subsequently formed.

According to an embodiment of the present disclosure, a multi-layered stacked unit (20, 30, 40, 50, 60L, 80, 90) may be formed over the dielectric material layer 760. The total number of layer stack cells (20, 30, 40, 50, 60L, 80, 90) may be N, the total number of sub-bitcells within a multi-cell memory cell 101 as described above. Generally, N is an integer greater than 1, and each of the layer stack units selected from the N layer stack units includes, from bottom to top or from top to bottom, an isolation dielectric layer 20, a gate electrode layer 30, a gate dielectric layer 40, a semiconductor channel layer 50, a dielectric spacer layer 60L, a capacitance dielectric layer 80, and a ground electrode layer 90. Although the present disclosure is described using embodiments in which three-layer stacked units (20, 30, 40, 50, 60L, 80, 90) are used, embodiments in which two-layer stacked units, four-layer stacked units, five-layer stacked units, or six-layer stacked units, or more, are used are expressly contemplated herein.

Each isolation dielectric layer 20 may provide inter-level isolation between a vertically adjacent pair of sub-bit cells of each subsequently formed multi-bit memory cell. Each isolation dielectric layer 20 comprises a dielectric material such as silicon nitride, a dielectric metal oxide, or a stack thereof. Each isolation dielectric layer 20 comprises a dielectric material such as silicon nitride, a dielectric metal oxide, or a stack thereof. For example, each isolation dielectric layer 20 may comprise silicon nitride and may be deposited by chemical vapor deposition. The thickness of each isolation dielectric layer 20 may be in the range of 10nm to 200nm, although lesser and greater thicknesses may also be used.

Each gate electrode layer 30 comprises a conductive material that can be isotropically etched with respect to the isolation dielectric layer 20, the gate dielectric layer 40, the semiconductor channel layer 50, and each of the capacitor dielectric layers 80. For example, each gate electrode layer 30 may include a metal material, such as an elemental metal (e.g., tungsten, ruthenium, cobalt, titanium, tantalum, etc.), a metal nitride material (e.g., titanium nitride (TiN), tantalum nitride (TaN), and/or tungsten nitride (WN)), or a heavily doped semiconductor material (e.g., doped polysilicon). Other suitable materials are contemplated within the scope of this disclosure. The thickness of each gate electrode layer 30 may be in the range of 10nm to 200nm, although lesser and greater thicknesses may also be used.

Each gate dielectric layer 40 includes a gate dielectric material. The gate dielectric material may be different from the material of the dielectric spacer layer 60L. Specifically, the gate dielectric material of the gate dielectric layer 40 may be resistant to an isotropic etch process for subsequent lateral recessing of the dielectric spacer layer 60L. For example, the gate dielectric layer 40 may include a metal oxide material having a dielectric constant greater than 7.9, i.e., a high-k metal oxide material. The thickness of the gate dielectric layer 40 may be in the range of 1nm to 10nm, although lesser and greater thicknesses may also be used.

Each semiconductor channel layer 50 includes a semiconductor material that provides a low leakage current level. A metal oxide semiconductor material may be used for the semiconductor channel layer 50 to minimize leakage current therethrough. For example, the semiconductor channel layer 50 may include a dielectric oxide semiconductor material, such as Indium Gallium Zinc Oxide (IGZO), doped zinc oxide, doped indium oxide, or doped cadmium oxide. Other suitable materials are contemplated within the scope of this disclosure. The thickness of each semiconductor channel layer 50 may be in the range of 5nm to 50nm, although lesser and greater thicknesses may also be used.

Each dielectric spacer layer 60L comprises a dielectric material that can be selectively isotropically etched with respect to the materials of the isolation dielectric layer 20, the gate electrode layer 30, the gate dielectric layer 40, the semiconductor channel layer 50, the capacitance dielectric layer 80, and the ground electrode layer 90. For example, the dielectric spacer layer 60L may comprise undoped silicate glass, doped silicate glass, organosilicate glass, or a porous dielectric material (porous dielectric material). Other suitable materials are contemplated within the scope of this disclosure. In one embodiment, the dielectric spacer layer 60L may comprise borosilicate glass or organosilicate glass, which may provide an etch rate at least ten times higher than that of undoped silicate glass, which may be subsequently used as a dielectric fill material. The thickness of each dielectric spacer layer 60L may be in the range of 10nm to 200nm, although lesser and greater thicknesses may also be used.

The capacitance dielectric layer 80 differs in composition, thickness, or composition and thickness across the layer stack unit (20, 30, 40, 50, 60L, 80, 90). Specifically, the dielectric constant to thickness ratio (constant-to-thickness ratio) of each capacitive dielectric layer 80 may be an integer power of 2 of the dielectric constant to thickness ratio of any other capacitive dielectric layer 80. Capacitance dielectric layer 80 may include a first capacitance dielectric layer 81 for providing capacitance of a first sub-bitcell unit of multi-cell memory cell 101, a second capacitance dielectric layer 82 for providing capacitance of a second sub-bitcell unit of multi-cell memory cell 101, and a third capacitance dielectric layer 83 for providing capacitance of a third sub-bitcell unit of multi-cell memory cell 101.

Generally, N capacitive dielectric layers 80 may be provided. In one embodiment, first capacitive dielectric layer 81 may have ε₁/t₁First dielectric constant to thickness ratio (wherein ε₁Is the first dielectric constant of the first capacitor dielectric layer, and t₁Is a first thickness of the first capacitor dielectric layer) and each kth capacitor dielectric layer 80 has epsilon_k/t_kThe k-th dielectric constant to thickness ratio of (2)^k-1×(1+2^-N-1) X C to 2^k-1×(1-2^-N-1) Each integer k is greater than 1 and not greater than N, where ε_kIs the k dielectric constant, t, of the k capacitor dielectric layer_kIs the kth thickness of the kth capacitor dielectric layer 80. The limitation of the dielectric constant to thickness ratio ensures that the sensing circuit can identify 2 of each multi-element memory cell 101 during a sensing operation^NA state without error.

In one embodiment, at least two of the capacitive dielectric layers 80 may comprise, or may consist essentially of, different capacitive dielectric materials. Various capacitor dielectric layers 80 that may be used for the capacitor dielectric layer 80 include, but are not limited to, silicon oxide (having a dielectric constant of 3.9), silicon nitride (having a dielectric constant of 7.9), aluminum oxide (having a dielectric constant in the range of 9.3 to 11.6 depending on crystal orientation), tantalum pentoxide (having a dielectric constant of about 25), hafnium oxide (having a dielectric constant of about 23), lanthanum oxide (having a dielectric constant of about 27), titanium oxide (having a dielectric constant in the range of 67 to 85), and strontium titanate (having a dielectric constant of about 240). The thickness and dielectric constant of the capacitive dielectric layer 80 can be selected such that the dielectric constant to thickness ratio of the capacitive dielectric layer 80 has a corresponding value that provides a geometric sequence of powers of 2, i.e., 1, 2, 4, 8, etc.

Each ground electrode layer 90 comprises a conductive material that can be isotropically etched with respect to the isolation dielectric layer 20, the gate electrode layer 30, the gate dielectric layer 40, the semiconductor channel layer 50, and each capacitance dielectric layer 80. For example, each ground electrode layer 90 may include a metal material, such as an elemental metal (e.g., tungsten, ruthenium, cobalt, titanium, tantalum, etc.), a metal nitride material (e.g., titanium nitride (TiN), tantalum nitride (TaN), and/or tungsten nitride (WN)), or a heavily doped semiconductor material (e.g., doped polysilicon). Other suitable materials are contemplated within the scope of this disclosure. The material of the ground electrode layer 90 may be the same as or different from that of the gate electrode layer 30. The thickness of each ground electrode layer 90 may be in the range of 10nm to 200nm, although lesser and greater thicknesses may also be used.

The isolation dielectric layer 20 may be disposed at the bottom of the layer stack unit (20, 30, 40, 50, 60L, 80, 90). Another isolation dielectric layer 20 may be provided at the bottom of the layer stack unit (20, 30, 40, 50, 60L, 80, 90). In addition, a suitable etch stop layer (not shown) or planarization stop layer (not shown) may be formed over the layer stack unit (20, 30, 40, 50, 60L, 80, 90) to facilitate a subsequent etching process and/or a subsequent planarization process, such as a chemical mechanical planarization process.

Fig. 4A is a vertical cross-sectional view of an example structure after forming a line trench, according to an embodiment of the present disclosure. Fig. 4B is a top view of the exemplary structure of fig. 4A. Referring to fig. 4A and 4B, a photoresist layer may be applied over the layer stack unit (20, 30, 40, 50, 60L, 80, 90) and may be lithographically patterned to form elongated openings extending laterally along a first horizontal direction hd1 and laterally spaced along a second horizontal direction hd2 perpendicular to the first horizontal direction hd 1. The line pattern in the photoresist layer may be transferred through the layer stack unit (20, 30, 40, 50, 60L, 80, 90) by performing an anisotropic etch process that sequentially etches through each layer within the layer stack unit (20, 30, 40, 50, 60L, 80, 90). The top surface of the underlying metal interconnect structure 780 (e.g., the top surface of global bit line 788) may serve as an etch stop structure. The line groove 79 may be formed through the layer stack unit (20, 30, 40, 50, 60L, 80, 90). Thus, the layer stack unit (20, 30, 40, 50, 60L, 80, 90) provided in the process operation of fig. 3A and 3B is divided into a plurality of layer stack units (20, 30, 40, 50, 60L, 80, 90) laterally spaced by the line trenches 79. The photoresist layer may be subsequently removed by ashing.

In general, the trench formed between an adjacent pair of stacked cells (20, 30, 40, 50, 60L, 80, 90) may have a uniform width or may have a laterally undulating width. Although the present disclosure is described using an embodiment in which the trenches are line trenches 79 having a corresponding uniform width throughout, embodiments in which the trenches have a laterally undulating width, or embodiments having a uniform width with sidewalls having a lateral wiggle (lateral wiggle), are expressly contemplated herein.

The width of each line trench 79 along the second horizontal direction hd2 may be in the range of 30nm to 300nm, although smaller and larger widths may also be used. The width of each layer stack unit (20, 30, 40, 50, 60L, 80, 90) between an adjacent pair of line trenches 79 may be in the range of 30nm to 600nm, although smaller and larger widths may also be used.

Fig. 5A is a vertical cross-sectional view of an exemplary structure after forming a dielectric trench fill structure in accordance with an embodiment of the present disclosure. Fig. 5B is a top view of the exemplary structure of fig. 5A. Referring to fig. 5A and 5B, a first dielectric fill material may be deposited in the line trenches 79. The first dielectric fill material may be a dielectric material that is different from the dielectric material of the dielectric spacer layer 60L. For example, the first dielectric fill material may comprise undoped silicate glass, silicon nitride, silicon carbon nitride (SiCN), or a dielectric metal oxide (e.g., aluminum oxide). Other suitable materials are contemplated within the scope of this disclosure. Excess portions of the first dielectric fill material may be removed from above a horizontal plane including a topmost surface of the layer stack unit (20, 30, 40, 50, 60L, 80, 90). The remaining portion of the first dielectric fill material filling the line trenches 79 comprises the dielectric trench fill structures 78.

Fig. 6A is a vertical cross-sectional view of an exemplary structure after forming a dielectric pillar structure in accordance with an embodiment of the present disclosure. Fig. 6B is a top view of the exemplary structure of fig. 6A. Referring to fig. 6A and 6B, a photoresist layer (not shown) may be applied over the exemplary structure and may be lithographically patterned to form a discrete two-dimensional array of openings covering the dielectric trench fill structure 78, or a plurality of line-like openings extending laterally along the second horizontal direction hd 2. An anisotropic etch process may be performed to etch unmasked portions of the dielectric trench fill structure 78 without etching the material of the layer stack units (20, 30, 40, 50, 60L, 80, 90). A two-dimensional array of columnar cavities 77 may be formed within the volume of the line trench 79 that is not masked by the patterned photoresist layer. Each of the cylindrical chambers 77 may have a rectangular horizontal cross-sectional area. The photoresist layer may be subsequently removed by ashing.

The remaining portion of dielectric trench fill structure 78 comprises a two-dimensional array of dielectric pillar structures 76. Generally, a two-dimensional array of dielectric pillar structures 76 may be formed in the line trenches 79 by depositing and patterning a first dielectric fill material in the line trenches 79.

Fig. 7A is a vertical cross-sectional view of an exemplary structure after forming a source-side lateral recess and a drain-side lateral recess in accordance with an embodiment of the present disclosure. Fig. 7B is a top view of the exemplary structure of fig. 7A. Fig. 7C is a horizontal sectional view taken along the plane C-C' of fig. 7A. Referring to fig. 7A-7C, an isotropic etch process may be performed to laterally etch the physically exposed portions of the dielectric spacer layer 60L selective to the dielectric pillar structures 76, the isolation dielectric layer 20, the gate electrode layer 30, the gate dielectric layer 40, the semiconductor channel layer 50, the capacitance dielectric layer 80, and the ground electrode layer 90. For example, if the dielectric spacer layer 60L comprises a silicon oxide material, such as borosilicate glass, undoped silicate glass, or organosilicate glass, a wet etch process using hydrofluoric acid may be used to laterally recess the dielectric spacer layer 60L. In other words, the patterned portion of the dielectric spacer layer 60L formed in the process operations of fig. 3A and 3B is laterally recessed to form lateral recesses (61, 63).

The lateral recesses (61, 63) may be formed in a volume of material from which the dielectric spacer layer 60L is etched. The lateral recess distance may be in the range of 10nm to 200nm, although smaller and larger lateral recess distances may also be used. After the isotropic etching process, each remaining portion of the dielectric spacer layer 60L is referred to herein as a dielectric spacer plate (dielectric spacer plate) 60. Each lateral recess (61, 63) may be laterally bounded by a straight vertical sidewall segment and a pair of concave vertical sidewall segments (i.e., vertical sidewall segments having a concave horizontal cross-sectional profile) of the dielectric spacer plate 60. The lateral recesses (61, 63) include a source side lateral recess 61, in which a source region is to be subsequently formed, and a drain side lateral recess 63, in which a drain region is to be subsequently formed. Lateral recesses (61, 63) are formed adjacent to the dielectric spacer plate 60, the dielectric spacer plate 60 being the remaining portion of the corresponding dielectric spacer layer 60L after the isotropic etch process. In one embodiment, the pair of source-side lateral recesses 61 and the pair of drain-side lateral recesses 63 may alternate along the second horizontal direction hd 2.

Fig. 8A is a vertical cross-sectional view of an exemplary structure after forming source and drain regions, according to an embodiment of the present disclosure. Fig. 8B is a top view of the exemplary structure of fig. 8A. Fig. 8C is a horizontal sectional view along the plane C-C' of fig. 8A. Referring to fig. 8A-8C, source/drain material may be deposited in the lateral recesses to form source and drain regions 62 and 64. The source/drain material may comprise a heavily doped semiconductor material, such as doped polysilicon, a doped silicon germanium alloy, or a doped III-V compound semiconductor material. The dopant concentration in the doped semiconductor material may be 5.0 x 10¹⁹/cm³To 2.0X 10²¹/cm³Although smaller and larger dopant concentrations may also be used. Alternatively or additionally, the source/drain material may comprise a metal material, such as a conductive metal nitride material (e.g., titanium nitride (TiN), tantalum nitride (TaN), and/or tungsten nitride (WN)) and/or a metal (e.g., tungsten (W), titanium (Ti), or ruthenium (Ru)). Other suitable materials are contemplated within the scope of this disclosure. A pair of source regions 62 may be formed around each first subset of the pillar shaped cavities 77 and a pair of drain regions 64 may be formed around each second subset of the pillar shaped cavities 77. The source region 62 and the drain region 64 may be symmetrically formed during this process operation and may be subsequently distinguished depending on whether a bitline is formed thereon or whether an insulating pillar structure is formed thereon.

Each combination of the dielectric spacer plate 60, the source region 62, and the drain region 64 constitutes a composite layer (60, 62, 64). Each composite layer (60, 62, 64) is formed between and contacts a respective semiconductor channel layer 50 and a respective capacitive dielectric layer 80. The source and drain regions 62, 64 of each transistor are laterally spaced by a respective dielectric spacer plate 60 and contact a respective portion of the semiconductor channel layer 50. Each capacitive dielectric layer 80 contacts a respective composite layer (60, 62, 64). Each semiconductor channel layer 50 extends laterally along the first horizontal direction hd 1.

Fig. 9A is a vertical cross-sectional view of an example structure after forming an isolation pillar structure, according to an embodiment of the present disclosure. Fig. 9B is a top view of the exemplary structure of fig. 9A. Fig. 9C is a horizontal sectional view taken along the plane C-C' of fig. 9A. Referring to fig. 9A through 9C, a second dielectric fill material may be deposited in the pillar cavity 77. Excess portions of the second dielectric fill material may be removed from over a topmost surface of the layer stack unit (20, 30, 40, 50, 60, 62, 64, 80, 90) by a planarization process, such as a Chemical Mechanical Planarization (CMP) process. The remaining portion of the second dielectric fill material includes a two-dimensional array of isolation pillar structures (72, 74). After forming the composite layer (60, 62, 64), a second dielectric fill material can be deposited in the pillar cavity 77 between an adjacent pair of dielectric pillar structures 76.

The isolation pillar structures (72, 74) include drain-side isolation pillar structures 74, which are a first subset of the isolation pillar structures (72, 74) in contact with a respective subset of the drain regions 64. Further, the isolation pillar structures (72, 74) include a source side isolation pillar structure 72 that is a second subset of the isolation pillar structures (72, 74) that is in contact with a corresponding subset of the source regions 62. The second dielectric fill material of the isolation pillar structures (72, 74) may be different from the first dielectric fill material of the dielectric pillar structures 76. In one embodiment, the second dielectric fill material may be a dielectric material that is selectively removed relative to the first dielectric fill material. For example, the first dielectric fill material may comprise undoped silicate glass and the second dielectric fill material may comprise doped silicate glass or organosilicate glass. Other suitable materials are contemplated within the scope of this disclosure. In another example, the first dielectric fill material may comprise silicon carbonitride, silicon nitride, or a dielectric metal oxide, and the second dielectric fill material may comprise a silicon oxide-based material, such as undoped silicate glass, doped silicate glass, or organosilicate glass.

Fig. 10A is a vertical cross-sectional view of an example structure after removal of drain side isolation pillar structures and formation of drain side pillar cavities, in accordance with an embodiment of the present disclosure. Fig. 10B is a top view of the exemplary structure of fig. 10A. Fig. 10C is a horizontal sectional view taken along the plane C-C' of fig. 10A. Referring to fig. 10A through 10C, a photoresist layer may be applied and patterned to mask the source side isolation pillar structure 72, but not the drain side isolation pillar structure 74. An anisotropic etch process may be performed to remove the drain side isolation pillar structure 74 without removing the source side isolation pillar structure 72, the dielectric pillar structure 76, or the layer stack unit (20, 30, 40, 50, 60, 62, 64, 80, 90). The drain side isolation pillar structure 74 may be removed by an anisotropic etch process, and the pillar cavity 77 may be formed with a volume from which the drain side isolation pillar structure 74 is removed. The drain regions 64 may be physically exposed to a respective one of the columnar cavities 77. Generally, a first subset of the isolation pillar structures (72, 74) that are in contact with the drain region 64 (e.g., the drain side isolation pillar structures 74) may be removed, while a second subset of the isolation pillar structures (72, 74) that are in contact with the source region 62 (e.g., the source side isolation pillar structures 72) are not removed. The photoresist layer may be subsequently removed by ashing.

Fig. 11A is a vertical cross-sectional view of an exemplary structure after forming a gate-level lateral recess (gate-level lateral recess) and a ground-level lateral recess (ground-level lateral recess), in accordance with an embodiment of the present disclosure. Fig. 11B is a top view of the exemplary structure of fig. 11A. FIG. 11C is a horizontal cross-sectional view taken along plane C-C' of FIG. 11A. FIG. 11D is a horizontal cross-sectional view taken along plane D-D' of FIG. 11A. Referring to fig. 11A to 11D, each of the gate electrode layers 30 and each of the ground electrode layers 90 may be laterally recessed around the pillar-shaped cavities 77 by performing an isotropic etching process. The isotropic etch process causes the material of each of the gate electrode layer 30 and the ground electrode layer 90 to be selectively recessed laterally with respect to the material of the dielectric pillar structures 76, the isolation dielectric 20, the gate dielectric 40, the semiconductor channel layer 50, the source region 62, the drain region 64, and the capacitor dielectric 80. The chemistry of the isotropic etch process may be selected based on the materials of the gate electrode layer 30 and the ground electrode layer 90. In one embodiment, the lateral recesses (33, 93) may be formed using a metal wet etch process selective to dielectric and semiconductor materials.

The lateral recess (33, 93) includes a gate level lateral recess 33 formed by laterally recessing the gate electrode layer 30 and a ground level lateral recess 93 formed by laterally recessing the ground electrode layer 90. The lateral etch distance of the isotropic etch process may be in the range of 10nm to 200nm, such as 20nm to 100nm, although smaller and larger lateral etch distances may also be used.

Figure 12A is a vertical cross-sectional view of an example structure after forming gate insulating spacers and ground insulating spacers, according to an embodiment of the present disclosure. Fig. 12B is a top view of the exemplary structure of fig. 12A. Fig. 12C is a horizontal cross-sectional view taken along plane C-C' of fig. 12A. Figure 12D is a horizontal cross-sectional view taken along plane D-D' of figure 12A. Referring to fig. 12A-12D, an insulating spacer material may be conformably deposited in the columnar cavities 77 and the lateral recesses (33, 93) by a conformant deposition process, such as a Low Pressure Chemical Vapor Deposition (LPCVD) process. An anisotropic etch process may be performed to etch portions of the insulating spacer material deposited in the pillar cavities 77. The remaining portion of the dielectric fill material filling the lateral recess (33, 93) comprises an insulating spacer (32, 92). The insulating spacers (32, 92) include a gate insulating spacer 32 filling the gate level lateral recess 33 and a ground insulating spacer 92 filling the ground level lateral recess 93. Gate insulating spacers 32 may be formed on the sidewalls of the recess of the gate electrode layer 30 around the columnar cavity 77, and ground insulating spacers 92 are formed on the sidewalls of the recess of the ground electrode layer 90 around the columnar cavity 77. In one embodiment, the physically exposed sidewalls of the insulating spacers (32, 92) may be vertically coincident with sidewalls of the isolation dielectric layer 20, the gate dielectric layer 40, the semiconductor channel layer 50, the drain region 64, the capacitance dielectric layer 80, and the ground electrode layer 90.

Fig. 13A is a vertical cross-sectional view of an exemplary structure after forming bit lines according to an embodiment of the present disclosure. Fig. 13B is a top view of the exemplary structure of fig. 13A. FIG. 13C is a horizontal cross-sectional view taken along plane C-C' of FIG. 13A. Figure 13D is a horizontal cross-sectional view taken along plane D-D' of figure 13A. Fig. 13E is a horizontal cross-sectional view taken along plane E-E' of fig. 13A. Referring to fig. 13A to 13E, a conductive material may be deposited in the pillar shaped cavity 77, and an unnecessary portion of the conductive material may be removed from the outside of the pillar shaped cavity 77 by a planarization process using an etch back process or a chemical mechanical planarization process. Each remaining portion of the conductive material filling the pillar cavity 77 includes a bit line 84 that contacts a corresponding subset of the drain regions 64. Each bit line 84 can be formed on a corresponding set of drain regions 64 above or below each other.

A parallel connection of N sub-bitcells 10 may be formed on each side of the bitline 84. Each of the N sub-bitcells 10 comprises a series connection of a respective transistor and a respective capacitance comprising the source region 62 of the respective transistor, a patterned portion of the respective capacitance dielectric layer 80 provided in the process operation of fig. 3A and 3B, and a patterned portion of the respective ground electrode layer 90 provided in the process operation of fig. 3A and 3B. The gate electrode layers 30 may be individually electrically biased (electrically biased) with corresponding word line voltages and may be used as word lines as shown in fig. 1 and 2.

Referring collectively to fig. 1-13E, and in accordance with an embodiment of the present disclosure, a memory device is provided that includes at least one multi-element memory cell 101. Each of the at least one multi-element memory cells 101 comprises a parallel connection of N sub-bit cells 10. N is an integer greater than 1, and N sub-bit cells 1Each of 0 comprises a series connection of a respective transistor (30, 40, 50, 62, 64) and a respective capacitance (62, 80, 90). The first sub-bit cell includes a first capacitor having a capacitance value C, and each of the ith sub-bit cells includes a second capacitor having a capacitance value at 2^i-1×(1+2^-N-1) X C to 2^i-1×(1-2^-N-1) An ith capacitance in the range of x C, each i being greater than 1 and not greater than N.

In one embodiment, each capacitor (62, 80, 90) of the N sub-bitcells 10 includes a first node connected to electrical ground (including the ground electrode layer 90), and a second node connected to the source region 62 of a respective transistor (30, 40, 50, 62, 64) within a respective one of the N sub-bitcells 10. In one embodiment, the parallel connection of the N sub-bitcells 10 within each of the at least one multi-cell memory cell 101 is between the corresponding bitline 84 and electrical ground, which is electrically connected to each of the ground electrode layers 90.

In one embodiment, the parallel connection of the N sub-bitcells 10 may include a vertical stack of a corresponding set of N capacitors (62, 80, 90) located over the substrate 700 and over a metal interconnect structure 780 formed within the dielectric material layer 760 and a vertical stack of a corresponding set of N transistors interleaved (interconnect) with the vertical stack of the corresponding set of N capacitors along the vertical direction.

In one embodiment, each of the N sub-bit cells 10 is connected in parallel including a respective bit line 84, the bit line 84 contacting the drain region 64 of a respective set of N transistors (30, 40, 50, 62, 64) and extending vertically through the vertical stack of the respective set of N capacitors (62, 80, 90) and through the vertical stack of the respective set of N transistors (30, 40, 50, 62, 64).

In one embodiment, each transistor within the vertical stack of a respective set of N transistors (30, 40, 50, 62, 64) includes a respective semiconductor channel layer 50 and a respective composite layer (60, 62, 64) extending along a horizontal direction, the composite layer (60, 62, 64) including a dielectric spacer plate 60, and source and drain regions 62, 64, the source and drain regions 62, 64 being laterally spaced by the dielectric spacer plate 60 and contacting a respective portion of the semiconductor channel layer 50.

In one embodiment, each capacitance (62, 80, 90) within the respective set of N capacitances (62, 80, 90) includes a respective capacitance dielectric layer 80 in contact with a respective composite layer (60, 62, 64), and a respective ground electrode layer 90 in contact with the respective capacitance dielectric layer 80, the ground electrode layer 90 including a first node of the respective capacitance (62, 80, 90). Source regions 62 within the same sub-bit cell 10 include second nodes of respective capacitances (62, 80, 90).

In one embodiment, at least two of the capacitive dielectric layers 80 within a respective set of the vertical stacks (62, 80, 90) of N capacitors comprise different capacitive dielectric materials. In one embodiment, each of the capacitance dielectric layers 80 within the vertical stack of the corresponding set of N capacitances (62, 80, 90) has the same area, and the first capacitance dielectric layer 81 within the corresponding set of N capacitances (62, 80, 90) includes a first permittivity to thickness ratio ε₁/t₁(wherein ε₁Is the first dielectric constant of the first capacitor dielectric layer 81, and t₁Is a first thickness of the first capacitor dielectric layer 81) and each kth capacitor dielectric layer in a corresponding set of N capacitors (62, 80, 90) includes a kth dielectric constant to thickness ratio epsilon_k/t_k(wherein ε_kIs the kth dielectric constant of the kth capacitor dielectric layer, and t_kIs the k-th thickness of the k-th capacitance dielectric layer), the k-th dielectric constant to thickness ratio epsilon_k/t_kIn 2^k-1×(1+2^-N-1) X C to 2^k-1×(1-2^-N-1) In the range of × C, each integer k is greater than 1 and not greater than N.

In embodiments in which one or more of the capacitive dielectric layers 80 are etched in parallel (capacitive etch) during the formation of the lateral recesses (33, 93), the capacitive dielectric layers 80 may have different areas. In this embodiment, the first capacitor dielectric layer 81 within a corresponding set of N capacitors (62, 80, 90) includes a first capacitance value ε₁A₁/t₁And each kth capacitive dielectric layer within a respective set of N capacitors (62, 80, 90) includesK-th capacitance value epsilon_kA_k/t_kK-th capacitance value ε_kA_k/t_kIn 2^k-1×(1+2^-N-1) X C to 2^k-1×(1-2^-N-1) In the range of × C, each integer k is greater than 1 and not greater than N. A1 is the area of the first capacitive dielectric layer 81, and A_kIs the area of the k-th capacitor dielectric layer, each k being in the range of 2 to N.

In one embodiment, each ground electrode layer 90 extends laterally along a horizontal direction (e.g., the first horizontal direction hd1), each gate electrode (including the gate electrode layer 30) within the vertical stack of the corresponding set of N transistors (30, 40, 50, 62, 64) extends laterally along the horizontal direction, and each source region 62 within the vertical stack of the corresponding set of N transistors (30, 40, 50, 62, 64) is electrically floating (electrically floating) when the corresponding set of N transistors (30, 40, 50, 62, 64) is turned off.

Referring to fig. 14, a circuit schematic of a first exemplary network of devices is shown, according to an embodiment of the present disclosure. The first exemplary device network includes two multivariate logic units 301 configured for multivariate addition operations (multivariate addition operations). The structure of each multi-cell logic cell 301 may be the same as the multi-cell memory cell 101 described in fig. 1, 2, and 13A-13E. In the example shown here, the first and second multi-element logic cells 301_1 and 301_2 are connected to a common bit line to provide an adder (adder). Although the adder is shown as an example of a network of devices providing logical operations, embodiments are explicitly contemplated herein in which other logical operations may be performed. Generally speaking, multi-element logic cells may be electrically wired differently to provide a network of devices configured for computational, multi-element logic operation, or analog mode operation.

The first exemplary device network of FIG. 14 can be organized by draining all charge in the capacitor by grounding the bit line, by applying a signal to the word line corresponding to the binary bit value of the two binary numbers to be added, and by applying a programming voltage V _ prog to the bit line through the bit line switch. Each of the plurality of logic cellsThe programming operation of 301 may be the same as that of the multi-cell memory cell 101 described above. For example, the gate electrode of each sub-bit cell of the first capacitor having a capacitance C is biased at a voltage corresponding to the last digit of the binary numbers to be added (the "1" digit), and has a capacitance of 2^kThe k electrode of each sub-bit cell of the k capacitor of x C is biased at the "k number of bits from the last bit" (i.e., 2) corresponding to the binary number to be added^kNumber of bits). The binary value applied to the kth sub-bitcell cell is 2 out of the stored values in the multi-bitcell logic^kIs weighted because the capacitance of the kth sub-bit cell is 2 of the capacitance of the first sub-bit cell^kAnd (4) doubling. Thus, each input voltage Vin to the kth gate (measured as either "0" or "1") is at 2 for the stored value in the multi-element logic cell involved^kWeighted by the factor of (c). The effective weight w of each binary input value applied to the kth gate is represented by w_k＝2^kXvin, where Vin is 0 or 1. The stored value in each of the multi-element logic units 301 is represented by Σ w of all values of index k_kAll values of k are given, i.e. in the range of 1 to N.

Referring to fig. 15, the gate of a sense amplifier or another multi-element logic cell may be connected to a bit line BL, so that the bit line BL may serve as an output node of a device network including two multi-element logic cells 301. The sense amplifier may include an output capacitance into which a portion (fraction) of the charge may be transferred during a sensing operation. The capacitance may be part of a gate electrode of a next stage (next stage) multi-element logic cell if another multi-element logic cell is connected to an output node of the multi-element logic cell.

During sensing or during applying an input voltage to the next stage of the multi-cell logic unit, the bit line switch is turned off (turn off), so that the bit line BL is electrically floating. All gate electrodes of the multi-cell logic cells connected to the bit line can be turned on and charge is transferred to the output capacitor or word line of the next level of multi-cell logic cells. The total charge stored in two multi-element logic cells is multiplied by V _ prog by CMultiplication by (all values of index k at the first multi-element logic unit [ Sigma ] w_k) And (all values of k at the index of the second multi-element logic unit ∑ w_k) The sum of) is given. The charge accumulated on the output capacitance after all gate electrodes of the two multi-element logic units 301 are turned on is given by the total charge stored in the two multi-element logic units multiplied by the capacitance value of the output capacitance divided by the sum of the output capacitance and the capacitance values of all capacitances of the two multi-element logic units 301. In other words, after all gate electrodes of the two multi-element logic cells 301 are turned on, the charge accumulated on the output capacitance is given by the total charge stored in the two multi-element logic cells multiplied by a factor F by: f ═ C _ output/(C _ output +2 × (2)^N+1-1) × C), where C _ output is the capacitance value of the output capacitor.

Referring to fig. 16, a circuit schematic of a second exemplary network of devices is shown, according to an embodiment of the present disclosure. In this configuration, the device network includes a first multi-element logic cell (301_1, 301_2, …, 301_6) whose output node is an input node of a second multi-element logic cell 401.

In general, the multi-element logic cells (302, 401) may be connected at the same stage (stage) as shown in fig. 14 and 15, or may be connected across multiple stages as shown in fig. 16.

Referring to fig. 3A-16, and in accordance with an embodiment of the present disclosure, a device network comprising a plurality of multivariate logic cells is provided. Each of the plurality of multi-element logic cells includes a parallel connection of N sub-bitcells (which may be implemented as the N sub-bitcells 10 shown in fig. 13A-13E). N is an integer greater than 1. Each of the N sub-bitcells includes a series connection of a respective transistor and a respective capacitor. The first sub-bit cell includes a first capacitor having a capacitance value C, and each of the ith sub-bit cells includes a second capacitor having a capacitance value at 2^i-1×(1+2^-N-1) X C to 2^i-1×(1-2^-N-1) An ith capacitance in the range of x C, each i being greater than 1 and not greater than N. A first multi-element logic unit selected from the plurality of multi-element logic units comprises an output node which is electrically connected with the plurality of multi-element logic unitsThe output node or the input node of the selected second multi-element logic cell.

In one embodiment, as shown in fig. 14 and 15, the output node of the first multi-element logic cell 301_1 is electrically connected to the output node of the second multi-element logic cell 301_2, and the device network further comprises a bit line switch connected to the output node of the first multi-element logic cell 301_1 and the output node 301_2 of the second multi-element logic cell, and configured to apply a programming voltage V _ prog during programming of the state of each of the first multi-element logic cell 301_1 and the second multi-element logic cell 301_ 2. The device network may include a sense amplifier connected to the output node of the first multi-element logic cell 301_1 and to the output node of the second multi-element logic cell 301_ 1.

In one embodiment, as shown in FIG. 16, the output node of the first multi-element logic unit 301_1 is electrically connected to the input node of the second multi-element logic unit 401. In this embodiment, the network of devices further comprises at least one further multi-element logic unit (301_2, 301_3, …, 301_6) having an output node connected to at least one further input node of the second multi-element logic unit 401.

Each parallel connection of the N sub-bit cells may comprise: a respective set of N-capacitor vertical stacks (62, 80, 90) over the substrate 700 and over a metal interconnect structure 780 formed within the dielectric material layer 760, and a respective set of N-transistor vertical stacks (30, 40, 50, 62, 64) interleaved with the respective set of N-capacitor vertical stacks (62, 80, 90). Each of the N sub-bitcells is connected in parallel including a respective bitline 84, the bitline 84 contacting the drain region 64 of a respective set of N transistors (30, 40, 50, 62, 64) and extending vertically through the vertical stack of the respective set of N capacitors (62, 80, 90) and through the vertical stack of the respective set of N transistors (30, 40, 50, 62, 64).

Referring to fig. 17, a flow chart illustrates process operations for forming the disclosed structure. Referring to operation 1710 and fig. 3A and 3B, N number of layer stack units (20, 30, 40, 50, 60L, 80, 90) are formed over a substrate 700. N is an integer greater than 1, and each layer stack unit (20, 30, 40, 50, 60L, 80, 90) selected from the N layer stack units (20, 30, 40, 50, 60L, 80, 90) includes an isolation dielectric layer 20, a gate electrode layer 30, a gate dielectric layer 40, a semiconductor channel layer 50, a dielectric spacer layer 60L, a capacitance dielectric layer 80, and a ground electrode layer 90. Referring to operation 1720 and fig. 4A and 4B, a trench (e.g., a line trench 79) is formed through the N layer stack units (20, 30, 40, 50, 60L, 80, 90). The process operations of fig. 5A-6B may optionally be performed if multiple multi-element memory cells 101 are formed or multiple multi-element logic cells (301, 401) are formed.

Referring to operation 1730 and FIGS. 7A-7C, the patterned portion of each dielectric spacer 60L is laterally etched. Lateral recesses (61, 63) are formed adjacent to the dielectric spacer plate 60, the dielectric spacer plate 60 being the remaining part of the dielectric spacer layer 60L. Referring to operation 1740 and fig. 8A-8C, a semiconductor material or a conductive material is deposited in the lateral recess (61, 63). A composite layer (60, 62, 64) including a dielectric spacer plate 60, a source region 62, and a drain region 64 is formed over each of the semiconductor channel layers 50 to provide a respective transistor (30, 40, 50, 60, 62, 64). The process operations of fig. 9A-12D may optionally be performed if multiple multi-element memory cells 101 are formed or multiple multi-element logic cells (301, 401) are formed.

Referring to operation 1750 and FIGS. 13A-13E, bit lines 84 may be formed on each set of drain regions 64 above or below each other. Forming a parallel connection of N sub-bit cells. Each of the N sub-bit cells comprises a series connection of a respective transistor (30, 40, 50, 60, 62, 64) and a respective capacitor (62, 80, 90), the respective capacitor comprising a source region 62 of the respective transistor (30, 40, 50, 60, 62, 64), a patterned portion of a respective capacitor dielectric layer 80, and a patterned portion of a respective ground electrode layer 90.

Various embodiments of the present disclosure may be used to fabricate and operate memory devices that include at least one multi-element memory cell, and/or device networks that include multiple multi-element logic cells. Various configurations of the device of the present disclosure may be derived from each other through the addition of structural units and through the variation of electrical routing, which may be achieved by changing the layout of the metal interconnect structure 780 formed within the dielectric material layer 760.

In one exemplary aspect, the present disclosure is directed to a memory device. The memory device comprises at least one multi-element memory unit. Each of the plurality of memory cells includes a parallel connection of N sub-bit cells. N is an integer greater than 1. Each of the N sub-bit cells includes a series connection of a respective transistor and a respective capacitor. The first sub-bit cell unit comprises a first capacitor, and the first capacitor has a capacitance value C. Each ith sub-bit cell includes an ith capacitor having a capacitance value of 2^i-1×(1+2^-N-1) X C to 2^i-1×(1-2^-N-1) In the range of × C, each i is greater than 1 and not greater than N.

In some embodiments, each of the capacitors of the N sub-bit cells includes a first node connected to electrical ground and a second node connected to a source region of a respective transistor within a respective one of the N sub-bit cells.

In some embodiments, the parallel connection of the N sub-bit cells within each of the plurality of memory cells is between the corresponding bit line and electrical ground.

In some embodiments, the plurality of memory cells includes at least one column of the plurality of memory cells, wherein each of the plurality of memory cells in the same column is connected to a respective bit line.

In some embodiments, the multi-cell memory cells include at least one row of multi-cell memory cells. Each of the plurality of memory cells in the same row shares a plurality of word lines of the same group. Each word line in the same group of word lines is connected to a respective gate electrode in each of the plurality of memory cells in a respective row of the plurality of memory cells.

In some embodiments, each of the N sub-bitcells is connected in parallel including a corresponding set of N capacitors and a corresponding set of N transistors. A corresponding set of N capacitors is positioned over the substrate and over a plurality of metal interconnect structures formed within the plurality of layers of dielectric material. The vertical stacks of a respective set of N transistors are interleaved with the vertical stacks of a respective set of N capacitors.

In some embodiments, each of the N sub-bitcells is connected in parallel including a respective bit line that contacts the plurality of drain regions of the respective set of N transistors and extends vertically through the vertical stack of the respective set of N capacitors and through the vertical stack of the respective set of N transistors.

In some embodiments, each transistor within the respective set of vertical stacks of N transistors includes a respective semiconductor channel layer and a respective composite layer. The respective semiconductor channel layers extend in a horizontal direction. The corresponding composite layer comprises dielectric spacer plates, and source and drain regions. The source and drain regions are laterally spaced apart by the dielectric spacer plate and contact respective portions of the semiconductor channel layer.

In some embodiments, each capacitor within a vertical stack of a set of N capacitors includes a respective capacitor dielectric layer and a respective ground electrode layer. The respective capacitor dielectric layers are in contact with the respective composite layers. The respective ground electrode layer is in contact with the respective capacitance dielectric layer and includes a first node of the respective capacitance. The source regions within the same sub-bit cell include the second nodes of the respective capacitances.

In some embodiments, at least two of the capacitive dielectric layers within the respective set of vertical stacks of N capacitors comprise different capacitive dielectric materials.

In some embodiments, each of the capacitive dielectric layers within the vertical stack of a respective set of N capacitors has the same area. A first capacitor dielectric layer within the corresponding set of N capacitors includes a first dielectric constant to thickness ratio epsilon₁/t₁. Each of the k-th capacitor dielectric layers in the corresponding set of N capacitors includes a k-th dielectric constant to thickness ratio ε_k/t_kK dielectric constant to thickness ratio ε_k/t_kIn 2^k-1×(1+2^-N-1) X C to 2^k-1×(1-2^-N-1) In the range of × C, each integer k is greater than 1 and not greater than N.

In some embodiments, the respective ground electrode layers extend laterally along a horizontal direction. Each gate electrode within the vertical stack of a respective set of N transistors extends laterally along the horizontal direction. Each source region within the vertical stack of the respective set of N transistors is electrically floating when the respective set of N transistors is turned off.

In another exemplary aspect, the present disclosure is directed to a network of devices. The device network includes a plurality of multivariate logic units. Each of the plurality of logic cells includes a parallel connection of N sub-bitcells. N is an integer greater than 1. Each of the N sub-bit cells includes a series connection of a respective transistor and a respective capacitor. The first sub-bit cell unit comprises a first capacitor, and the first capacitor has a capacitance value C. Each ith sub-bit cell includes an ith capacitor having a capacitance value of 2^i-1×(1+2^-N-1) X C to 2^i-1×(1-2^-N-1) In the range of × C, i is greater than 1 and not greater than N. A first multi-element logic unit selected from the multi-element logic units comprises an output node which is electrically connected to an output node or an input node of a second multi-element logic unit selected from the multi-element logic units.

In some embodiments, the output node of the first multi-element logic unit is electrically connected to the output node of the second multi-element logic unit. The device network further includes a bit line switch connected to an output node of the first multi-element logic cell and an output node of the second multi-element logic cell, and the bit line switch is configured to apply a programming voltage during programming of a state of each of the first multi-element logic cell and the second multi-element logic cell. The device network also includes a sense amplifier connected to the output node of the first multi-element logic cell.

In some embodiments, the output node of the first multi-element logic unit is electrically connected to the input node of the second multi-element logic unit. The device network further includes at least another multi-element logic unit having an output node connected to at least another input node of the second multi-element logic unit.

In some embodiments, each of the N sub-bitcells is connected in parallel including a corresponding set of N capacitors and a corresponding set of N transistors. A corresponding set of N capacitors is positioned over the substrate and over a plurality of metal interconnect structures formed within the plurality of layers of dielectric material. The vertical stacks of a respective set of N transistors are interleaved with the vertical stacks of a respective set of N capacitors. Each of the N sub-bitcells is connected in parallel including a respective bit line contacting the plurality of drain regions of a respective set of N transistors and extending vertically through the vertical stack of the respective set of N capacitors and through the vertical stack of the respective set of N transistors.

In yet another exemplary aspect, the present disclosure is directed to a method of forming a multi-element memory cell. A method of forming a multi-cell memory cell includes depositing N number of layer stack units over a substrate, where N is an integer greater than 1, and each layer stack unit selected from the N number of layer stack units includes an isolation dielectric layer, a gate electrode layer, a gate dielectric layer, a semiconductor channel layer, a dielectric spacer layer, a capacitance dielectric layer, and a ground electrode layer; etching a plurality of trenches through the N layer stack units; laterally etching a plurality of patterned portions of each dielectric spacer layer, wherein a plurality of lateral recesses are formed adjacent to a plurality of dielectric spacer plates, the dielectric spacer plates being a plurality of remaining portions of the dielectric spacer layers; depositing a semiconductor material or a conductive material in the lateral recess, wherein a composite layer is formed on each of the semiconductor channel layers to provide a corresponding transistor, the composite layer comprising a dielectric spacer plate, a source region and a drain region; and forming a bit line on each group of drain regions above or below each other, wherein a parallel connection of N sub-bit cells is formed, wherein each of the N sub-bit cells comprises a series connection of a respective transistor and a respective capacitor, the capacitor comprising a source region of the respective transistor, a patterned portion of a respective capacitor dielectric layer, and a patterned portion of a respective ground electrode layer.

In some embodiments, the first capacitive dielectric layer within the N number of layer-stacked units comprises a first dielectric constant to thickness ratio epsilon₁/t₁. Each of the k-th capacitor dielectric layers in the N layer-stacked units includes a k-th dielectric constant to thickness ratio epsilon_k/t_kK dielectric constant to thickness ratio ε_k/t_kIn 2^k-1×(1+2^-N-1) X C to 2^k-1×(1-2^-N-1) In the range of × C, each integer k is greater than 1 and not greater than N.

In some embodiments, the method of forming a memory cell further comprises depositing and patterning a first dielectric fill material in the trench, wherein a two-dimensional array of a plurality of dielectric pillar structures is formed within the trench, and after forming the two-dimensional array of dielectric pillar structures, performing a lateral etch on the patterned portion of the dielectric spacer layer; and depositing a second dielectric fill material in the plurality of cavities between adjacent pairs of dielectric pillar structures after forming the composite layer, wherein a two-dimensional array of a plurality of isolation pillar structures is formed.

In some embodiments, the method of forming a memory cell further comprises removing a first subset of the isolation pillar structures that contact the drain region without removing a second subset of the isolation pillar structures that contact the source region, wherein the plurality of pillar cavities are formed in a volume from which the first subset of the isolation pillar structures are removed; laterally recessing each of the gate electrode layers and each of the ground electrode layers around the columnar cavity; depositing and anisotropically etching an insulating spacer material, wherein a plurality of insulating spacers are formed on a plurality of recessed sidewalls of the gate electrode layer and the ground electrode layer around the columnar cavity; and depositing a conductive material in the columnar cavity, wherein a plurality of bit lines are formed, the bit lines contacting respective subsets of the drain regions.

The foregoing outlines features of many embodiments so that those skilled in the art may better understand the present disclosure in various aspects. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the invention as set forth in the appended claims. Various changes, substitutions, or alterations to the disclosure may be made without departing from the spirit and scope of the disclosure.