阅读说明：本技术 互补金属氧化物半导体器件 (CMOS device ) 是由 金钟明 于 2019-06-24 设计创作，主要内容包括：本发明提供一种互补金属氧化物半导体器件,所述互补金属氧化物半导体(CMOS)器件包括：高电阻率基板；第一CMOS结构,设置在所述高电阻率基板的第一区域中；以及第二CMOS结构,与所述第一CMOS结构的半导体类型相同,并且设置在所述高电阻率基板的与所述第一区域分开的第二区域中。所述高电阻率基板设置在所述第一CMOS结构和所述第二CMOS结构之间,以将所述第一CMOS结构与所述第二CMOS结构分开。(The present invention provides a Complementary Metal Oxide Semiconductor (CMOS) device comprising: a high resistivity substrate; a first CMOS structure disposed in a first region of the high resistivity substrate; and a second CMOS structure of the same semiconductor type as the first CMOS structure and disposed in a second region of the high-resistivity substrate that is separate from the first region. The high resistivity substrate is disposed between the first and second CMOS structures to separate the first and second CMOS structures.)

1. A complementary metal oxide semiconductor device comprising:

a high resistivity substrate;

a first complementary metal oxide semiconductor structure disposed in a first region of the high resistivity substrate; and

a second complementary metal oxide semiconductor structure of the same semiconductor type as the first complementary metal oxide semiconductor structure and disposed in a second region of the high resistivity substrate separate from the first region,

wherein the high resistivity substrate is disposed between the first and second CMOS structures to separate the first and second CMOS structures.

2. The CMOS device of claim 1, wherein each of said first and second CMOS structures is a triple well structure.

3. The CMOS device of claim 1, wherein said first CMOS structure comprises a first low resistivity layer, a first deep N-well layer, and a first P-well layer stacked as a first triple well structure.

4. The CMOS device of claim 1, wherein said second CMOS structure comprises a second low resistivity layer, a second deep N-well layer, and a second P-well layer stacked as a second triple well structure.

5. The CMOS device of claim 2, wherein said first CMOS structure comprises:

a first low resistivity layer stacked in the first region of the high resistivity substrate;

a first deep N-well layer disposed on and surrounded by the first low-resistivity layer;

a first P-well layer disposed on and surrounded by the first deep N-well layer; and

a first source region, a first drain region, and a first gate region disposed in the first P-well layer to form a source, a drain, and a gate, respectively, of the first CMOS structure.

6. The CMOS device of claim 5, wherein said second CMOS structure comprises:

a second low resistivity layer stacked in the second region of the high resistivity substrate;

a second deep N-well layer disposed on and surrounded by the second low-resistivity layer;

a second P-well layer disposed on and surrounded by the second deep N-well layer; and

a second source region, a second drain region, and a second gate region disposed in the second P-well layer to form a source, a drain, and a gate, respectively, of the second CMOS structure.

7. The complementary metal oxide semiconductor device of claim 6, wherein a resistivity value of the high-resistivity substrate is greater than both a resistivity value of the first low-resistivity layer and a resistivity value of the second low-resistivity layer.

8. The complementary metal oxide semiconductor device of claim 6, wherein a thickness of a region of the high-resistivity substrate between the first and second complementary metal oxide semiconductor structures is thicker than both a thickness of the first low-resistivity layer and a thickness of the second low-resistivity layer, and the thickness of the high-resistivity substrate is thinner than both a total thickness of the first low-resistivity layer and the first deep Nwell layer and a total thickness of the second low-resistivity layer and the second deep Nwell layer.

9. A complementary metal oxide semiconductor device comprising:

a high resistivity substrate;

a first complementary metal oxide semiconductor structure of a first triple well structure disposed in a first region of the high resistivity substrate; and

a second complementary metal oxide semiconductor structure of a second triple well structure disposed in a second region of the high resistivity substrate separate from the first region,

wherein the high resistivity substrate is disposed between the first triple well structure and the second triple well structure to separate the first triple well structure from the second triple well structure.

10. The cmos device of claim 9, wherein the first cmos structure is the same semiconductor type as the second cmos structure.

11. The cmos device of claim 9, wherein said first triple well structure of said first cmos structure comprises a stacked first low resistivity layer, a first deep nwell layer, and a first pwell layer.

12. The cmos device of claim 9, wherein said second triple well structure of said second cmos structure comprises a stacked second low resistivity layer, a second deep nwell layer, and a second pwell layer.

13. The cmos device of claim 10, wherein said first cmos structure comprises:

a first low resistivity layer stacked in the first region of the high resistivity substrate;

a first deep N-well layer disposed on and surrounded by the first low-resistivity layer;

a first P-well layer disposed on and surrounded by the first deep N-well layer; and

a first source region, a first drain region, and a first gate region disposed in the first P-well layer to form a source, a drain, and a gate, respectively, of the first CMOS structure.

14. The cmos device of claim 13, wherein said second cmos structure comprises:

a second low resistivity layer stacked in the second region of the high resistivity substrate;

a second deep N-well layer disposed on and surrounded by the second low-resistivity layer;

a second P-well layer disposed on and surrounded by the second deep N-well layer; and

a second source region, a second drain region, and a second gate region disposed in the second P-well layer to form a source, a drain, and a gate, respectively, of the second CMOS structure.

15. The complementary metal oxide semiconductor device of claim 14, wherein a resistivity value of the high-resistivity substrate is greater than both a resistivity value of the first low-resistivity layer and a resistivity value of the second low-resistivity layer.

16. The complementary metal oxide semiconductor device of claim 14, wherein a thickness of a region of the high-resistivity substrate between the first and second complementary metal oxide semiconductor structures is thicker than both a thickness of the first low-resistivity layer and a thickness of the second low-resistivity layer, and the thickness of the high-resistivity substrate is thinner than both a total thickness of the first low-resistivity layer and the first deep nwell layer and a total thickness of the second low-resistivity layer and the second deep nwell layer.

17. A complementary metal oxide semiconductor device comprising:

a substrate;

a first complementary metal oxide semiconductor structure disposed in the substrate and including a first layer; and

a second complementary metal oxide semiconductor structure disposed in the substrate and including a second layer separated from the first layer by a portion of the substrate disposed between the first layer and the second layer, the portion of the substrate having a higher resistivity than both the resistivity of the first layer and the resistivity of the second layer.

18. The cmos device of claim 17, wherein the portion of the substrate disposed between the first layer and the second layer has a thickness greater than a thickness of a portion of the substrate other than the portion of the substrate disposed between the first layer and the second layer.

Technical Field

The following description relates to a layout structure of a Complementary Metal Oxide Semiconductor (CMOS) transistor with improved insertion loss.

Background

Recently developed mobile Wi-Fi modules are configured to perform 2.4GHz/5GHz dual band Multiple Input Multiple Output (MIMO) communication, and miniaturization and integrated design of the Wi-Fi modules are required to adapt to mobile devices.

Furthermore, there is a need for a front-end integrated circuit (FEIC) including a Power Amplifier (PA), an internal coupler, a Radio Frequency (RF) switch, and a Low Noise Amplifier (LNA) in one chip. For this reason, a front-end circuit configured as two chips by separating conventional transmission and reception has recently been configured as a single chip using a single chip process.

In the case where the front-end integrated circuit (FEIC) is formed as a single chip as described above, although a Silicon-on-Insulator (SOI) process may be used to maximize the characteristics of the radio frequency switch embedded therein, it is very difficult to design a power amplifier when the SOI process is used. Thus, the transmitter and receiver may be configured as a single chip using a BiCMOS process.

However, the switching loss of the BiCMOS process is greater than that of the SOI process, which directly affects the reception performance of the receiver and the output power of the transmitter. Therefore, in order to solve such a problem, a structure capable of reducing the switching loss is required.

Disclosure of Invention

This summary is provided to introduce a selection of concepts in a simplified form that are further described below in the detailed description. This summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.

In one general aspect, a CMOS device includes: a high resistivity substrate; a first CMOS structure disposed in a first region of the high resistivity substrate; and a second CMOS structure of the same semiconductor type as the first CMOS structure and disposed in a second region of the high-resistivity substrate that is separate from the first region. The high resistivity substrate is disposed between the first and second CMOS structures to separate the first and second CMOS structures.

Each of the first and second CMOS structures may be a triple well structure.

The first CMOS structure may include a first low resistivity layer, a first deep N-well layer, and a first P-well layer stacked as a first triple well structure.

The second CMOS structure may include a second low resistivity layer, a second deep N-well layer, and a second P-well layer stacked as a second triple well structure.

The first CMOS structure may include: a first low resistivity layer stacked in the first region of the high resistivity substrate; a first deep N-well layer disposed on and surrounded by the first low-resistivity layer; a first P-well layer disposed on and surrounded by the first deep N-well layer; and a first source region, a first drain region, and a first gate region disposed in the first pwell layer to form a source, a drain, and a gate of the first CMOS structure, respectively.

The second CMOS structure may include: a second low resistivity layer stacked in the second region of the high resistivity substrate; a second deep N-well layer disposed on and surrounded by the second low-resistivity layer; a second P-well layer disposed on and surrounded by the second deep N-well layer; and a second source region, a second drain region, and a second gate region disposed in the second pwell layer to form a source, a drain, and a gate of the second CMOS structure, respectively.

The high-resistivity substrate may have a resistivity value greater than both a resistivity value of the first low-resistivity layer and a resistivity value of the second low-resistivity layer.

A thickness of a region of the high-resistivity substrate between the first CMOS structure and the second CMOS structure may be thicker than both a thickness of the first low-resistivity layer and a thickness of the second low-resistivity layer, and may be thinner than both a total thickness of the first low-resistivity layer and the first deep N-well layer and a total thickness of the second low-resistivity layer and the second deep N-well layer.

In another general aspect, a CMOS device includes: a high resistivity substrate; a first CMOS structure of a first triple-well structure disposed in a first region of the high-resistivity substrate; and a second CMOS structure of a second triple well structure disposed in a second region of the high resistivity substrate separate from the first region. The high resistivity substrate is disposed between the first triple well structure and the second triple well structure to separate the first triple well structure from the second triple well structure.

The first CMOS structure may be of the same semiconductor type as the second CMOS structure.

The first triple well structure of the first CMOS structure may include a first low resistivity layer, a first deep N-well layer, and a first P-well layer stacked.

The second triple well structure of the second CMOS structure may include a second low resistivity layer, a second deep N-well layer, and a second P-well layer stacked.

The first CMOS structure may include: a first low resistivity layer stacked in the first region of the high resistivity substrate; a first deep N-well layer disposed on and surrounded by the first low-resistivity layer; a first P-well layer disposed on and surrounded by the first deep N-well layer; and a first source region, a first drain region, and a first gate region disposed in the first pwell layer to form a source, a drain, and a gate of the first CMOS structure, respectively.

The second CMOS structure may include: a second low resistivity layer stacked in the second region of the high resistivity substrate; a second deep N-well layer disposed on and surrounded by the second low-resistivity layer; a second P-well layer disposed on and surrounded by the second deep N-well layer; and a second source region, a second drain region, and a second gate region disposed in the second pwell layer to form a source, a drain, and a gate of the second CMOS structure, respectively.

The high-resistivity substrate may have a resistivity value greater than both a resistivity value of the first low-resistivity layer and a resistivity value of the second low-resistivity layer.

A thickness of a region of the high-resistivity substrate between the first CMOS structure and the second CMOS structure may be thicker than both a thickness of the first low-resistivity layer and a thickness of the second low-resistivity layer, and may be thinner than both a total thickness of the first low-resistivity layer and the first deep N-well layer and a total thickness of the second low-resistivity layer and the second deep N-well layer.

A Complementary Metal Oxide Semiconductor (CMOS) device comprising: a substrate; a first CMOS structure disposed in the substrate and including a first layer; and a second CMOS structure disposed in the substrate and including a second layer separated from the first layer by a portion of the substrate disposed between the first layer and the second layer, the portion of the substrate having a higher resistivity than both the first layer and the second layer.

The thickness of the portion of the substrate disposed between the first layer and the second layer may be greater than the thickness of a portion of the substrate other than the portion of the substrate disposed between the first layer and the second layer.

Other features and aspects will be apparent from the following detailed description and the accompanying drawings.

Drawings

Fig. 1 is a sectional view showing a layout structure of a Complementary Metal Oxide Semiconductor (CMOS) transistor according to an example.

Fig. 2 is a sectional view showing a layout structure of a CMOS transistor according to an example.

Fig. 3 is a circuit diagram of a CMOS transistor according to an example.

Fig. 4 is a diagram illustrating a thickness of a high resistivity substrate according to an example.

Fig. 5 is a graph showing insertion loss characteristics of a switching circuit to which a CMOS transistor is applied according to an example.

Fig. 6 is a diagram showing an application of a CMOS transistor according to an example.

Like reference numerals refer to like elements throughout the drawings and the detailed description. The figures may not be drawn to scale and the relative sizes, proportions and depictions of the elements in the figures may be exaggerated for clarity, illustration and convenience.

Detailed Description

The following detailed description is provided to assist the reader in obtaining a thorough understanding of the methods, devices, and/or systems described herein. However, various modifications, variations, and equivalents of the methods, apparatus, and/or systems described herein will be apparent to those skilled in the art upon review of the present disclosure. For example, the order of operations described herein is merely an example and is not limited to those set forth herein, but rather, variations may be made in addition to operations which must occur in a particular order, as will be apparent upon understanding the disclosure of the present application. In addition, descriptions of features known in the art may be omitted for the sake of clarity and conciseness.

The features described herein may be embodied in different forms and should not be construed as limited to the examples described herein. Rather, the examples described herein are provided merely to illustrate some of the many possible ways to implement the methods, devices, and/or systems described herein that will be apparent after understanding the disclosure of the present application.

Here, it is noted that the use of the term "may" with respect to an example or embodiment (e.g., with respect to what the example or embodiment may include or implement) means that there is at least one example or embodiment that includes or implements such a feature, and all examples and embodiments are not limited thereto.

Throughout the specification, when an element such as a layer, region or substrate is described as being "on," connected to "or" coupled to "another element, it may be directly on," connected to or directly coupled to the other element or one or more other elements may be present therebetween. In contrast, when an element is referred to as being "directly on," "directly connected to" or "directly coupled to" another element, there may be no intervening elements present.

As used herein, the term "and/or" includes any one of the associated listed items as well as any combination of any two or more.

Although terms such as "first", "second", and "third" may be used herein to describe various elements, components, regions, layers or sections, these elements, components, regions, layers or sections should not be limited by these terms. Rather, these terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section referred to in the examples described herein could be termed a second element, component, region, layer or section without departing from the teachings of the examples.

Spatially relative terms (such as "above … …", "above", "below … …" and "below") may be used herein to describe one element's relationship to another element as illustrated in the figures for ease of description. Such spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "above" or "over" relative to another element would then be "below" or "beneath" the other element. Thus, the term "above … …" includes both an orientation of "above … …" and "below … …" depending on the spatial orientation of the device. The device may also be otherwise oriented (e.g., rotated 90 degrees or at other orientations) and the spatially relative terms used herein interpreted accordingly.

The terminology used herein is for the purpose of describing various examples only and is not intended to be limiting of the disclosure. The singular is intended to include the plural unless the context clearly dictates otherwise. The terms "comprises," "comprising," and "having" specify the presence of stated features, quantities, operations, elements, components, and/or combinations thereof, but do not preclude the presence or addition of one or more other features, quantities, operations, components, elements, and/or combinations thereof.

Variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, may be produced. Accordingly, the examples described herein are not limited to the particular shapes shown in the drawings, but include changes in shapes that occur during manufacturing.

The features of the examples described herein may be combined in various ways that will be apparent after understanding the disclosure of the present application. Further, while the examples described herein have various configurations, other configurations are possible as will be apparent after understanding the disclosure of the present application.

Hereinafter, examples will be described in detail with reference to the accompanying drawings.

Fig. 1 is a sectional view showing a layout structure of a Complementary Metal Oxide Semiconductor (CMOS) transistor according to an example.

Referring to fig. 1, the layout structure of the CMOS transistor includes at least two CMOS structures, for example, a first CMOS structure 120 and a second CMOS structure 130, in the layout structure of the CMOS transistor including a plurality of CMOS structures.

The layout structure of the CMOS transistors may include a high resistivity substrate 110, a first CMOS structure 120, and a second CMOS structure 130.

The high-resistivity substrate 110 includes a high-resistivity region.

The first CMOS structure 120 may be formed in the first region a1 of the upper portion of the high-resistivity substrate 110 among the plurality of CMOS structures, and formed as a first triple well structure 120-TW having three well layers.

The second CMOS structure 130 may be formed in the second region a2 of the upper portion of the high resistivity substrate 110 among the plurality of CMOS structures. The second region a2 is separated from the first region a 1. The second CMOS structure 130 may be formed as a second triple well structure 130-TW having three well layers.

The high-resistivity substrate 110 may be formed between the first CMOS structure 120 and the second CMOS structure 130 to separate the first CMOS structure 120 and the second CMOS structure 130 from each other. The high-resistivity substrate 110 may be formed between the first triple-well structure 120-TW and the second triple-well structure 130-TW to separate the first triple-well structure 120-TW and the second triple-well structure 130-TW.

In fig. 1, S1, G1, and D1 are a first source region, a first gate region, and a first drain region, respectively, of the first CMOS structure 120 corresponding to a first transistor, and S2, G2, and D2 are a second source region, a second gate region, and a second drain region, respectively, of the second CMOS structure 130 corresponding to a second transistor.

Unnecessary redundant description may be omitted for components having the same reference numerals and the same functions for each drawing, and differences for each drawing may be construed.

Fig. 2 is a sectional view showing a layout structure of a CMOS transistor according to an example.

Referring to fig. 2, the first triple well structure 120-TW of the first CMOS structure 120 may include a first low resistivity layer 121, a first deep N-well layer 122, and a first P-well layer 123 stacked.

The first low-resistivity layer 121 may have a well structure stacked in the first region a1 of the upper portion of the high-resistivity substrate 110 among the plurality of CMOS structures. The resistivity value of the first low resistivity layer 121 may be relatively smaller than that of the high resistivity substrate 110. For example, the first low resistivity layer 121 may have a resistivity value of 50 ohm-meter (Ω · m).

The first deep N-well layer 122 may be formed on an upper portion of the first low-resistivity layer 121, and may have a well structure surrounded by the first low-resistivity layer 121. For example, the first deep N-well layer 122 is an N-type doped region. The well structure of the first deep N-well layer 122 has a well shape as a whole by forming N-type doped columns (N-type doped columns) vertically on both sides after N-type doping is horizontally performed. This is one example of forming a well structure, and the formation of the first deep N-well layer 122 is not limited to this method.

The first P-well layer 123 may be formed on an upper portion of the first deep N-well layer 122, and may have a well structure surrounded by the first deep N-well layer 122. For example, the first P-well layer 123 is a P-type doped region that is a body region of the CMOS structure.

Each of the first low-resistivity layer 121, the first deep N-well layer 122, and the first P-well layer 123 is formed as a well structure and sequentially stacked to finally form a triple well structure.

A first source region SA1, a first drain region DA1, and a first gate region GA1, which respectively form a source, a drain, and a gate of the first CMOS structure 120, may be formed on an upper portion of the first P-well layer 123.

For example, the high-resistivity substrate 110 has a resistivity value greater than that of the first low-resistivity layer 121. For example, the high resistivity substrate 110 may be 1 kiloohm-meter (K Ω · m).

The second triple well structure 130-TW of the second CMOS structure 130 may include a second low resistivity layer 131, a second deep N-well layer 132, and a second P-well layer 133 stacked.

The second low-resistivity layer 131 may have a well structure stacked in the second region a2 of the upper portion of the high-resistivity substrate 110 among the plurality of CMOS structures. The second low resistivity layer 131 may have a resistivity value relatively smaller than that of the high resistivity substrate 110. For example, the second low resistivity layer 131 may have a resistivity value of 50 ohm-meters (Ω · m).

The second deep N-well layer 132 may be formed on an upper portion of the second low-resistivity layer 131, and may have a well structure surrounded by the second low-resistivity layer 131. For example, the second deep N-well layer 132 is an N-type doped region. By forming the N-type doped columns vertically on both sides after the N-type doping is performed horizontally, the well structure of the second deep N-well layer 132 has a well shape as a whole. This is one example of forming a well structure, and the formation of the second deep N-well layer 132 is not limited to this method.

The second P-well layer 133 may be formed on an upper portion of the second deep N-well layer 132, and may have a well structure surrounded by the second deep N-well layer 132. For example, the second pwell layer 133 is a P-type doped region that is a body region of the CMOS structure.

Each of the second low-resistivity layer 131, the second deep N-well layer 132, and the second P-well layer 133 is formed as a well structure and sequentially stacked to finally form a triple well structure.

A second source region SA2, a second drain region DA2, and a second gate region GA2, which respectively form a source, a drain, and a gate of the second CMOS structure 130, may be formed on an upper portion of the second pwell layer 133.

For example, the high-resistivity substrate 110 has a resistivity value greater than that of the second low-resistivity layer 131.

Referring to fig. 1 and 2, a CMOS transistor using a BiCMOS process including a high-resistivity substrate 110 and a first low-resistivity layer 121 and a high-resistivity substrate 110 and a second low-resistivity layer 131 may be mainly formed as an N-type MOS.

In a BiCMOS process, there is a process of improving performance using a high-resistivity substrate 110. When such a process is used, most of the area of the high-resistivity substrate 110 is a high-resistivity area, and the first and second CMOS structures 120 and 130, which can be used as switches, respectively include first and second low- resistivity layers 121 and 131 having a low-resistivity area formed on the high-resistivity substrate 110, and transistor terminals of the first and second CMOS structures 120 and 130 are formed on the first and second low- resistivity layers 121 and 131, respectively.

Further, referring to fig. 1 and 2, since a signal leaks through a P-well layer when the P-well layer in which a terminal region is formed is shared and noise can also enter and exit through the P-well layer, adjacent first and second CMOS structures 120 and 130 of the CMOS structure do not generally share the P-well layer, so that a transistor for an RF signal can be formed as a triple-well structure including a deep N-well layer and a low-resistivity layer that surround the P-well layer in two layers.

In a CMOS transistor having a triple well structure, the deep N-well layer of the triple well structure may also reduce signal leakage and noise ingress and egress, but there may still be limitations on the reduction capability. That is, the transistor circuit of the CMOS structure of the triple well structure still causes signal leakage.

To further prevent such signal leakage and improve insertion loss, the first and second CMOS structures 120 and 130 independently include first and second low resistivity layers 121 and 131, respectively, and the high-resistivity substrate 110 is placed between the first and second low resistivity layers 121 and 131, and thus the low resistivity layers of the transistors arranged in a group may be separated from each other, and accordingly, interference between the transistors arranged in a group or stack may be reduced, and insertion loss may be reduced.

To prevent the PN junction between the first deep N-well layer 122 and the first P-well layer 123 from being turned on, the operating voltage VDD may be connected to the first deep N-well layer 122 and the ground potential may be connected to the first P-well layer 123.

To prevent the PN junction between the second deep N-well layer 132 and the second P-well layer 133 from being turned on, the operating voltage VDD may be connected to the second deep N-well layer 132 and the ground potential may be connected to the second P-well layer 133.

Fig. 3 is a circuit diagram of a CMOS transistor according to an example.

Referring to fig. 3, the transistors of the first CMOS structure 120 and the transistors of the second CMOS structure 130 are physically separated from each other by the high-resistivity substrate 110, and thus interference therebetween may be reduced by the high-resistivity substrate 110, thereby improving insertion loss.

Fig. 4 is a diagram illustrating a thickness of a high resistivity substrate according to an example.

Referring to fig. 4, a thickness DT1 of the high-resistivity substrate 110 in a region between the first low-resistivity layer 121 and the second low-resistivity layer 131 may be thinner than a thickness DT2 of the first low-resistivity layer 121, the same as a thickness DT2 of the first low-resistivity layer 121, or thicker than a thickness DT2 of the first low-resistivity layer 121. For example, when the thickness DT1 of the high-resistivity substrate 110 is thicker than the thickness DT2 of the first low-resistivity layer 121, the interference cancellation performance between the first CMOS structure 120 and the second CMOS structure 130 may be further improved by the high-resistivity substrate 110.

For example, the thickness DT1 of the high-resistivity substrate 110 may be thinner than the total thickness DT3 of the first low-resistivity layer 121 and the first deep nwell layer 122.

For example, the thickness DT1 of the high-resistivity substrate 110 may be thicker than the thickness of the second low-resistivity layer 131 (e.g., may also be DT 2).

For example, the thickness DT1 of the high-resistivity substrate 110 may be thinner than the total thickness of the second low-resistivity layer 131 and the second deep nwell layer 132.

Although not shown in the drawings, the thickness DT1 of the high-resistivity substrate 110 in the high-resistivity region disposed between the first low-resistivity layer 121 and the second low-resistivity layer 131 may be thinner than, the same as, or thicker than the thickness of the high-resistivity substrate 110 in the region other than between the first low-resistivity layer 121 and the second low-resistivity layer 131. However, for example, when the thickness DT1 is thicker than in the region other than between the first low resistivity layer 121 and the second low resistivity layer 131, the interference cancellation performance between the first CMOS structure 120 and the second CMOS structure 130 may be further improved by the high resistivity substrate 110.

Fig. 5 is a graph showing insertion loss characteristics of a switching circuit to which a CMOS transistor is applied according to an example.

In fig. 5, G10 is a graph showing insertion loss characteristics of a switching circuit to which a conventional CMOS transistor is applied, and G20 is a graph showing insertion loss characteristics of a switching circuit to which a CMOS transistor according to the example described herein is applied.

Referring to G10 and G20, it can be seen that the insertion loss characteristics of the switching circuit to which the CMOS transistor according to the example is applied are improved compared to the insertion loss characteristics of the switching circuit to which the conventional CMOS transistor is applied.

Fig. 6 is a diagram showing an application of a CMOS transistor according to an example.

Referring to fig. 6, a CMOS transistor is applied to a radio frequency switch included in a front end circuit (or module).

The radio frequency switch shown in fig. 6 may include: for example, a first series switch SE1 connected between the antenna ANT and the first port P1, a second series switch SE2 connected between the antenna ANT and the second port P2, a third series switch SE3 connected between the antenna ANT and the third port P3, a first shunt switch SH1 connected between the first port P1 and ground, a second shunt switch SH2 connected between the second port P2 and ground, and a third shunt switch SH3 connected between the third port P3 and ground.

A transistor of a CMOS structure may be applied to each of the first series switch SE1, the second series switch SE2, the third series switch SE3, and the first shunt switch SH1, the second shunt switch SH2, and the third shunt switch SH 3.

As described above, in a CMOS transistor by a BiCMOS process in which a high-resistivity region is disposed between two CMOS transistors adjacent to each other in a plurality of stacked or grouped CMOS transistors, the high-resistivity region and the low-resistivity region are separated from each other, insertion loss can be improved by reducing interference between the CMOS transistors.

While the disclosure includes specific examples, it will be apparent upon an understanding of the disclosure of the present application that various changes in form and detail may be made in these examples without departing from the spirit and scope of the claims and their equivalents. The examples described herein are to be considered in a descriptive sense only and not for purposes of limitation. The description of features or aspects in each example will be considered applicable to similar features or aspects in other examples. Suitable results may be obtained if the described techniques are performed in a different order and/or if components in the described systems, architectures, devices, or circuits are combined in a different manner and/or replaced or supplemented by other components or their equivalents. Therefore, the scope of the present disclosure is defined not by the detailed description but by the claims and their equivalents, and all modifications within the scope of the claims and their equivalents are to be construed as being included in the present disclosure.